Unclassified Technical Note PR-TN-2005/00406

Date of issue: May 2009

MOS Model 20
Level 2002.2

A.C.T. Aarts, A. Tajic, and S.J. Sque

Unclassified Technical Note
c

NXP Semiconductors 2009

May 2009 MOS Model 20, Level 2002.2 Unclassified Technical Note PR-TN-2005/00406

Corresponding author: S.J. Sque, stephen.sque@nxp.com

c NXP Semiconductors 2009
All rights are reserved. Reproduction in whole or in part is
prohibited without the written consent of the copyright owner.

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c NXP Semiconductors 2009

Unclassified Technical Note PR-TN-2005/00406 MOS Model 20, Level 2002.2 May 2009

Unclassified Technical Note: PR-TN-2005/00406

Title: MOS Model 20
Level 2002.2

Author(s): A.C.T. Aarts, A. Tajic, and S.J. Sque

Part of project: Compact Modelling

Customer: NXP Semiconductors

Keywords: circuit simulation, compact modelling, DMOS, LDMOS, high voltage
MOS, extended drain MOS, MOS Model 20, power integrated circuits

Abstract: The model description for the compact high-voltage MOS transistor
model called MOS Model 20 (MM20) is presented. MM20 has been
developed for circuit simulation of power integrated circuits. MM20
describes the electrical behaviour of a high-voltage MOS device, like
a Lateral Double-diffused MOS (LDMOS) device or an extended-drain
MOSFET. The model combines the MOSFET operation of the channel
region with that of the drift region of such high-voltage devices.
Since MM20 is a surface-potential–based model, it gives an accurate de-
scription in all operation regimes, ranging from sub-threshold to above
threshold, in both the linear and saturation regime. MM20 includes
strong inversion, depletion, and accumulation, in both the channel re-
gion and the drift region of the device. In addition to the previous
MM20 model (level = 2001), in this MM20 model (level = 2002), quasi-
saturation is included, an effect which is typical for high-voltage LD-
MOS devices.
The objective of this report is to present the full definition of MM20,
level = 2002, including the model parameter set, the temperature and
geometrical scaling rules, and all the implemented model equations for
the currents, charges, and noise sources. The parameter extraction strat-
egy is briefly explained.

c NXP Semiconductors 2009 iii

level 2002. May 2005 : Introduction of MOS Model 20. This update includes some practical changes. level 2002. Release of version 2002. test version. March 2008 : Update of documentation of MOS Model 20.May 2009 MOS Model 20. and improved avalanche-current modelling. January 2004 : Update of documentation of MOS Model 20.2 Unclassified Technical Note PR-TN-2005/00406 Preface and History of Model and Documentation Preface The first version of the compact LDMOS model. This update includes some practical changes. This update includes velocity saturation in the drift region. level 2002. February 2007 : Update of MOS Model 20. level 2002. This update includes a section on the parameter extraction strategy. This update corrects minor errors related to self-heating and temperature scaling. iv c NXP Semiconductors 2009 . May 2009 : Update of documentation of MOS Model 20. MOS Model 20. and the clip-low values of m and of λD . History of Documentation August 2003 : First documentation of MOS Model 20. level 2001. March 2008 : Update of MOS Model 20. Several minor bugs fixed in version 2002. and the implementation of the noise transfer function. which includes self-heating. August 2006 : Update of documentation of MOS Model 20. level 2002. the clip-low values of m and of λD . Future changes and additions to the model have been documented by extending or changing the documentation in this report. August 2006 : Update of MOS Model 20. level 2001.2. according to the model formulation of January 2004. March 2007 : Update of documentation of MOS Model 20. test version.2 and corrects minor errors. January 2004 : Update of MOS Model 20. omits the source-drain interchange for the DC current description. This update includes some practical changes. level 2002. level 2001. like the pinch-off voltage Voxp0 .2 of the model. test version. became available in October 2003. level 2002. October 2004 : Introduction of MOS Model 20. May 2005 : Introduction of MOS Model 20. level 2001. level 2001. This update. History of Model October 2003 : Release of MOS Model 20. like the clip-low values of W and WD . test version. Level 2002. level 2002. like the pinch-off voltage Voxp0 . This update takes into account the contribution of both the channel and drift regions to the weak-avalanche current. October 2004 : Introduction of MOS Model 20. This update details aspects new to version 2002. This update includes velocity saturation in the drift region. level 2001. level 2002. for instance.

. . . . . . . . . .Unclassified Technical Note PR-TN-2005/00406 MOS Model 20. 24 3. . . . . . .1 List of Numerical Constants . . . . . . . . . . . . . . . . . . .4 Postprocessing . . . . . .2 Internal Electrical Quantities and Variables . . . . .2 List of Physical Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Self-Heating . . . . . . . . . . . . .3. . .4 Noise Equations . . . .1 Input Variables and Quantities . . . . . . . . . . . . . . . .4. . . . . . . .3. . . 42 c NXP Semiconductors 2009 v . . 12 3. . . . . . . . . 28 4. . . . . . . . . .2 Default and Clipping Values of Geometrical Model Parameters . . . .2. . . . . . . . . . 41 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3. . . . . . . . . . . . .1 Structural Elements of MOS Model 20 . . . . . . . . . . . . . . . . . . 5 2. . . . . . . . . . . . . . . . . . 40 4. . . . . . 41 4. . . . . . . . . . . .5. . . . . . . . .3 Temperature Scaling .3 Geometry and Temperature Scaling . . . . . . .1 List of Electrical Model Parameters . . . . . . . . . . . . . . .2 Structure of this Report . 29 4. . . . . . . . . . . . . . 11 3. . . . . . . . . .3 Embedding Procedure of MOS Model 20 in a Circuit Simulator . . . 21 3. . . . . . . . .2 Geometrical Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4. . . . . . . . . 3 1. . . . . . . . . . . . . . . . . . . . .1 Internal Parameters . . . . . 12 3. . . . . . . . . . . .5. . . . 11 3. . . . . . . . . . . . . . . .1.1 External Electrical Quantities and Variables . . . 35 4. . . .1. . . . . . . . . 27 3. . . . .2. . . . . . . . . . . . . . . . .2 Clipping of Actual Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 List of Circuit Simulator Variables . . . . . 11 3. .2 Model Equations . . . . . . . . . .2. . . . . 11 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3. . . . 16 3. . . . . . .1 MULT Scaling . . . . . 26 3. . . . . . . . .3 Usage .1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2002. .1 Equivalent Circuit . . . . . . . . . . . . . . .2 May 2009 Contents 1 Introduction 1 1. . . . . . . . . . . .3. . . . .3 Electrical Model . .5. . . . . . . .3 Charge Equations . .1 List of Geometrical Model Parameters . . . . . . . . . . . . . . . . . . . . . 21 3. . . . 27 4 Implemented Equations 28 4. . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Embedding 5 2. .2 Current Equations . . . . . . 6 2. . . . . . . . . .2 Default and Clipping Values of Electrical Model Parameters . . . . . . . . . . . . . . . . 7 3 Nomenclature 11 3. . . 41 4. . . . . . . . . . . . . . . . .

. . . . . .2 Extraction of Miniset Parameters (including Temperature Scaling) . 49 6 Pstar-Specific Items 50 6. . . . . . . . .2 Unclassified Technical Note PR-TN-2005/00406 5 Parameter Extraction Strategy 44 5. . . . . 44 5. . . . . . . . . . . . . . . . . . . . . 46 5. . . . . . . . . . . . . . . . Level 2002. . . . . . . . . . . . . . . . . . . . . . . . .May 2009 MOS Model 20.3 Extraction of Maxiset Parameters . . 50 6. . . . . . . . . . . . . . . . . . .2 DC Operating Point Output . .1 Measurements . . . . . . .1 Syntax . . . . . . . . . . . . . . 51 References 53 A Auxiliary Functions 55 vi c NXP Semiconductors 2009 . . . . . . . . . . . . . . . . . . .

2 May 2009 1 Introduction MOS Model 20 (MM20) is a compact MOSFET model intended for analogue circuit simulation in high-voltage MOS technologies. depletion. MOS Model 20 has especially been developed to improve the convergence behaviour during circuit simulation. and weak avalanche (or impact ionization). by having the voltage at the transition (node Di) from the channel region to the drift region calculated inside the model itself. described by MOS Model 20.e. they should be covered by separate models. level 1101 [4]. and noise-power spectral densities. MOS Model 20 only provides a model for the intrinsic MOSFET behaviour of the region under the thin gate oxide of a high-voltage MOS device. static feedback. accumulation. As such. junction leakage currents. interconnect capacitances. several im- portant physical effects have been included in the model: mobility reduction. drain-induced barrier lowering.and gate/drain over- lap regions. velocity saturation. The equations describing these quantities are based on surface-potential formulations. channel length modulation. as well as the gate/source. for very high-voltage MOS transistors with an additional thick field oxide. and parasitic bipolar transistors are not included. MOS Model 20 is aimed as a successor of the combination of MOS Model 9 (MM9) [1] for the channel region in series with MOS Model 31 (MM31) [1] for the drift region under the thin gate oxide. and inversion in both the channel region and the drift region). see Figure 1. MOS Model 20 describes the electrical behaviour of the region under the thin gate oxide of a high-voltage MOS device. Additionally. like in Figure 3. MOS Model 20 gives a complete description of all transistor-action–related quantities: nodal cur- rents. The surface potential as a function of the terminal voltages is obtained by the explicit expression as derived in Ref. resulting in equations valid over all operation regimes (i. The model is based on the Silicon-on-Insulator (SOI)-LDMOS model developed by the University of Southampton [2].Unclassified Technical Note PR-TN-2005/00406 MOS Model 20. Furthermore. MOS Model c NXP Semiconductors 2009 1 . see Figure 2. nodal charges. It thus combines the MOSFET operation of the channel region with that of the drift region under the thin gate oxide in a high- voltage MOS device. Junction charges. like a Lateral Double-diffused MOS (LDMOS) device or an extended-drain MOSFET. For instance. Level 2002. G 0000000000000000000 1111111111111111111 channel region drift region 000 111 00000 11111 00 1111 00 11 00 11 00 1111111111 00000000 1111111111111111111 0000000000000000000 0 1 00 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 D 11 B 000 111 000 111 S 111 000000 111 000 111 000 11100 11 000 111 0 1 00 11 00 1100 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 000 111 000 111 000 11100 11 000 111 0 1 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 000 11100 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 +000 111 0 1 00 11 00 1100 11 00 11 00 11 00 11 00 11 00 11 000 11100 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 n+ 11 n 000 111 p+ Di p−well n− 1111111111111111111111111111111111 0000000000000000000000000000000000 Figure 1: The region under the thin gate oxide of an n-channel LDMOS device. an additional diode model for this pn-junction has to be added. to describe the electrical behaviour due to the pn-junction between the backgate (B) and drain (D). [3] and used in MOS Model 11 (MM11). in macro models of various high-voltage MOS devices.

Level 2002. G B S 00 D Figure 2: Macro model for an LDMOS transistor. * 00 00 %6 ' +: Figure 3: Macro model for an SOI-LDMOS transistor with a thick field oxide. 2 c NXP Semiconductors 2009 . self-heating of the device. is now included via a thermal network as of version 2002. MOS Model 40 (MM40) [1] has been used to model the part of the drift region underneath the thick oxide.2 of the model.2 Unclassified Technical Note PR-TN-2005/00406 20 can be used in series with a separate model for the drift region under the thick field oxide.May 2009 MOS Model 20. Finally. which may significantly affect the electrical behaviour. In the case of the SOI-LDMOS transistor in Figure 3.

the actual parameters for an arbitrary transistor are obtained by applying the temperature and geometry scaling rules. This maxiset consists of the transistor dimensions. is denoted as the set of actual parameters. this procedure is called preprocessing. Thus. Since most of these actual parameters scale with temperature. and temperature of the device. c NXP Semiconductors 2009 3 . Since a DMOS transistor is an asymmetric device. and since self-heating is significant for high- voltage devices. These scaling rules thus describe the dependencies of the actual parameters on the drift-region length. from which the actual parameters for an arbitrary temperature are obtained by applying the temperature scaling rules. in order to prevent numerical difficulties in the preprocessing procedure.1 Structural Elements of MOS Model 20 The structure of MOS Model 20 is the same as the structure of MOS Model 9 and MOS Model 11.2.and p-channel devices. is denoted as the miniset. The set of electrical parameters at a reference temperature including the tem- perature scaling parameters and reference temperature itself. usually called the maxiset. The pre-specified clipping ranges for the actual parameters are taken as those in the electrical model parameter list in Section 3. device width. as they occur in the equations for the various electrical quantities. These temperature scaling rules thus describe the dependencies of the actual parameters on the temperature of the device. • Clipping: To prevent the scaling rules from generating actual parameters that are outside a physically realistic range or that create numerical difficulties (such as division by zero). Furthermore. This clipping of actual pa- rameters is done after the preprocessing. This structure can be divided into: • Model embedding: It is convenient to use one single model for both n. Since the application of the scaling rules is done only once. no source-drain interchange is applied in case the external voltage mapped onto an n-channel transistor is negative.2 May 2009 1. each of them can be determined by electrical measurements over a range of temperatures. in MOS Model 20.1. the model parameters of both the electrical and geometrical model may also be clipped to a pre-specified range. For this reason. • Current equations: These are all expressions needed to obtain the DC nodal currents as a function of the bias conditions. the electrical parameters for certain device dimen- sions at a reference temperature. prior to the actual electrical simulation. the DC currents and charges are calculated by use of the externally applied volt- ages mapped onto an equivalent n-channel transistor. They can be separated into equations for the channel current and the avalanche current.1.e. and all temperature. • Preprocessing: The complete set of all the parameters. The pre-specified clipping ranges for both the electrical and geometrical model parameters are taken as those in the geometrical model parameter list in Section 3. Level 2002. they form the input for the so-called geometrical model. the reference temperature itself. Together. i. the process as a whole is characterized by an enlarged set of parameters. the actual parameters may be clipped to a pre-specified range.Unclassified Technical Note PR-TN-2005/00406 MOS Model 20.and geometry scaling parameters. This miniset forms the input for the so-called electrical model. Since most of the electrical parameters also scale with geometry.3. From the maxiset parameters. any p-channel device and its bias conditions are mapped onto those of an equivalent n-channel transistor. This clipping of model parameters is done before the preprocessing. This mapping comprises a number of sign changes.

current fluctuations in the gate current are induced as well. which are referred to as induced gate noise. the nomenclature is explained. Finally the operating point output parameters are described. Level 2002. which create fluctuations in the channel current.2 Unclassified Technical Note PR-TN-2005/00406 • Charge equations: These are all the equations that are used to calculate both the intrinsic and extrinsic charge quantities. 1. the procedure of embedding MOS Model 20 in a circuit simulator is outlined. 4 c NXP Semiconductors 2009 .2 Structure of this Report After this introductory section. They can be separated into equations for the channel-region charges and the drift-region charges. Owing to the capacitive coupling between the gate and channel region. which are assigned to the nodes. while in Section 4 the implemented equations are listed.May 2009 MOS Model 20. • Noise equations: The total noise output of a transistor consists of a thermal noise and a flicker noise part. Next.

Since a DMOS transistor is an asymmetric device. currents. This is accomplished by mapping a p-channel device with its bias conditions and parameter set onto an equivalent n-channel device with appropriately changed bias conditions (i. It is con- venient to use one single model for both types of transistor instead of two separate models.2 May 2009 2 Embedding In high-voltage technologies. Variable Program Units Description Name 1 VeD VDE V Potential applied to the drain node 2 VeG VGE V Potential applied to the gate node 3 VeS VSE V Potential applied to the source node 4 VeB VBE V Potential applied to the bulk node 5 IeD IDE A DC current into the drain 6 Ie G IGE A DC current into the gate 7 IeS ISE A DC current into the source 8 Ie B IBE A DC current into the bulk 9 QeD QDE C Charge in the device attributed to the drain node 10 QeG QGE C Charge in the device attributed to the gate node 11 QeS QSE C Charge in the device attributed to the source node 12 QeB QBE C Charge in the device attributed to the bulk node 13 SeD SDE A2 s Spectral density of the noise current into the drain 14 SeG SGE A2 s Spectral density of the noise current into the gate 15 SeS SSE A2 s Spectral density of the noise current into the source 16 SeDG SDGE A2 s Cross spectral density between the drain and the gate noise currents 17 SeGS SGSE A2 s Cross spectral density between the gate and the source noise currents 18 SeSD SSDE A2 s Cross spectral density between the source and the drain noise currents c NXP Semiconductors 2009 5 . The total transformation procedure is explained in detail in Section 2. In this way. Thus.1 External Electrical Quantities and Variables No. the DC currents and charges are calculated by use of the externally applied voltages mapped onto an equivalent n-channel transistor.3. no source-drain interchange is applied in case the external voltage mapped onto an n-channel transistor is negative. the same equations are used for both n. both n.Unclassified Technical Note PR-TN-2005/00406 MOS Model 20. 2. we let the electrons and holes have the same electrical behaviour. and charges) and parameters. Level 2002. in MOS Model 20.and p-type transistors. In MOS Model 20. As a result. both types of transistor can be treated as an n-channel transistor.and p-channel LDMOS transistors are supported. voltages.e.

May 2009 MOS Model 20. 2. ieD D e  b Ve e = Ie + dQD iD  D D dt SeD  ieG G e  b Ve e = Ie + dQG iG  G G dt SeG  ieS S dQSe  b Ve iSe = IeS +  S dt SeS  ieB B e  b Ve e = Ie + dQB iB B B dt Figure 4: Definition of the external electrical quantities and variables. Variable Program Units Description Name 1 VDS VDS V Drain-to-source voltage applied to the equivalent n-MOST 2 VGS VGS V Gate-to-source voltage applied to the equivalent n-MOST 3 VSB VSB V Source-to-bulk voltage applied to the equivalent n-MOST 4 IDS IDS A DC current through the channel flowing from drain to source 5 IAVL IAVL A DC current flowing from drain to bulk due to the weak-avalanche effect 6 QD QD C Intrinsic charge in the equivalent n-MOST attributed to the drain node 7 QG QG C Intrinsic charge in the equivalent n-MOST attributed to the gate node 8 QS QS C Intrinsic charge in the equivalent n-MOST attributed to the source node 9 QB QB C Intrinsic charge in the equivalent n-MOST attributed to the bulk node 6 c NXP Semiconductors 2009 .2 Internal Electrical Quantities and Variables No. Level 2002.2 Unclassified Technical Note PR-TN-2005/00406 The definitions of the external electrical variables are illustrated in Figure 4.

5. calculate the modified voltages VDS . VeG . Change from branch current to nodal currents. source. and noise-power spectral densities – using the MOS Model 20 equations and the corresponding voltages. and VSB . establishing the external current output quan- tities. From here onwards. 2.3) should be followed. the following procedure (illustrated in detail in Figure 2. gate. Calculate the voltages V”DS . 3. c NXP Semiconductors 2009 7 . thus forming the external charge output quantities. and V”SB . Add the overlap charges to the nodal charges. 4.3 Embedding Procedure of MOS Model 20 in a Circuit Simulator In order to embed MOS Model 20 correctly into a circuit simulator. VGS . As a DMOS is an asymmetric device.2 May 2009 10 SDth SDTH A2 s Spectral density of the thermal-noise current of the channel region 11 SDfl SDFL A2 s Spectral density of the flicker-noise current of the channel region 12 SGth SGTH A2 s Spectral density of the thermal-noise current induced in the gate 13 SGDth SGDTH A2 s Cross spectral density of the thermal-noise current in- duced in the gate and the thermal-noise current of the channel 2. Level 2002. Based on n. nodal charges. We have assumed that indeed the simulator provides the nodal potentials VeD . V”GS . weak-avalanche current.or p-channel devices. Correct for a possible p-channel transformation. VeS . and VBe based on an a priori assignment of drain.Unclassified Technical Note PR-TN-2005/00406 MOS Model 20. and the additional voltages V”DG and V”SG . Evaluate all the internal output quantities – channel current. no source-drain interchange is applied as is done in a conventional (symmetric) MOSFET. The latter are used for calculating the charges associated with overlap capacitances. and bulk. only n-channel behaviour needs to be considered. The following steps are taken: 1.

Ve .VGS .VGS .VGS . Level 2002. VSB ) SDth = SDth (VDS . Ve VD G S B ? V”DS = VeD − VeS V”GS = VeG − VeS V” = Ve − Ve SB S B V”DG = VeD − VeG V” = Ve − Ve SG S G ? @ @ n-channel Channel@ p-channel @ type @ @ VDS = V”DS VDS = −V”DS V = V” GS GS V = −V ” GS GS VSB = V” SB VSB = −V”SB ? QD = QD (VDS .VGS .2 Unclassified Technical Note PR-TN-2005/00406 e . VSB ) IAVL = IAVL (VDS . VSB ) IDS = IDS (VDS . Ve . VSB ) SDfl = SDfl (VDS .VGS . VSB ) SGth = SGth (VDS .VGS . VSB ) 8 c NXP Semiconductors 2009 .VGS .May 2009 MOS Model 20.VGS .VGS . VSB ) QS = QS (VDS . VSB ) QG = QG (VDS . VSB ) QB = − (QD + QS + QG ) SGDth = SGDth (VDS .

Level 2002. Unclassified Technical Note PR-TN-2005/00406 MOS Model 20.2 May 2009 A ? @ @ yes VDS ≥ 0@ no @ @ @ ’ =I IDB I’DB = 0 AVL ’ I =0 I’ = I SB SB AVL n o S’D = SDfl + SDth ’ SD = SDth + SDfl + SGth + 2Re SGDth S’G = SGth ’ =S SG Gth n o S’ = S + S + S S Dfl Dth Gth + 2Re SGDth S’ = S + S S Dfl Dth S’DG = S*GD ’ = −S − S * SDG Gth GD th th S’ = −SGth − SGDth ’ =S SGS GS GDth S’SD = −SGDth − SDfl − SDth S = −S* ’ SD GDth − SDth − SDfl ? @ @ n-channel Channel@ p-channel @ type @ @ S”D = S’D S”D = S’D Q”D = QD S”G = S’G QD” = −Q D S”G = S’G I”DS = IDS I”DS = −IDS ” = I’ Q”G = QG S” = S’ ” QG = −QG S” = S’ I”DB = −I’DB S S S S IDB Q” = Q S”DG = S’DG Q ” = −Q S”DG = S’DG DB ” ’ S S I =I S I” = −I’ S Q”B = QB S” = S’ QB” = −QB S” = S’ SB SB SB SB GS GS GS GS S”SD = S’SD S”SD = S’SD ? B c NXP Semiconductors 2009 9 .

10 c NXP Semiconductors 2009 . it is easy to use a different set of reference and scaling parameters for the two channel types.May 2009 MOS Model 20.2 Unclassified Technical Note PR-TN-2005/00406 B ? SeD = S”D e = I” + I” ID DS DB e = Q” + C QD D ” GDO · VDG SeG = S”G e =0 IG e = Q” − C ” ” Se = S” QG G GDO · VDG − CGSO · VSG S S Ie = −I” + I” S DS SB Qe = Q” + C S S · V” GSO SG SeDG = S”DG IBe = −I”DB − I”SB QBe = Q”B Se = S” GS GS SeSD = S”SD ? IeD IG e Ie Ie S B QeD QeG QeS QeB SeD SeG SeS SeDG SeGS SeSD Figure 5: Transformation scheme. As a consequence. Level 2002.and p-channel transis- tors. It is customary to have separate user models in the circuit simulators for n. In that manner. The changes should not be included in the simulator. the changes in the parameter values necessary for a p-channel type transistor are normally already included in the parameter sets on file.

1 List of Numerical Constants No. Symbol Program name Units Description 1 Ta Ta ◦C Ambient circuit temperature 2 f F Hz Operation frequency c NXP Semiconductors 2009 11 .15 K Offset for conversion from Celsius to Kelvin temperature scale 2 kB K BOLTZMANN 1.6021918 · 10−19 C Elementary unit charge 4 ǫox PHY EPSOX 3.2 List of Physical Constants No. Constant Program name Value 1 A LN MINDOUBLE −800 3.Unclassified Technical Note PR-TN-2005/00406 MOS Model 20.3806226 · 10−23 JK−1 Boltzmann constant 3 q Q ELECTRON 1.1.1.4531438 · 10−11 Fm−1 Absolute permittivity of the oxide layer 3.3 List of Circuit Simulator Variables No.1 Input Variables and Quantities 3.2 May 2009 3 Nomenclature 3.1. Constant Program name Value Units 1 T0 KELVIN CONVERSION 273. Level 2002.

and geometry- scaling parameters.2 Geometrical Model To characterize a high-voltage MOS process as a whole.k0 . Width scaling coefficient for k0D 14 PHIB φB V Surface potential at the onset of strong inversion in the channel region.May 2009 MOS Model 20.2.VFB VK−1 Temperature scaling coefficient for VFB 8 VFBD VFBD V Flat-band voltage of the drift region.2. Temperature scaling exponent for β 12 c NXP Semiconductors 2009 . and all temperature. Level 2002. at reference temperature 7 STVFB ST . the reference temperature. at reference temperature 15 STPHIB ST .φBD VK−1 Temperature scaling coefficient for φBD 18 BETW βW AV−2 Gain factor of a channel region of 1 µm width. while its scaling rules are listed in Section 3. together referred to as the maxiset. both n-channel and p-channel devices have been assigned the same default parameter values.VFBD VK−1 Temperature scaling coefficient for VFBD 10 KOR k0R V1/2 Body factor of the channel region of an infinitely wide transistor 11 SWKO SW . at reference tem- perature 9 STVFBD ST . in the geometrical MOS Model 20.1. at ref- erence temperature 19 ETABET ηβ . This model uses as input the actual transistor dimensions. Must be set to 2002 1 W W m Drawn width of the channel region 2 WVAR ∆W m Width offset of the channel region 3 WD WD m Drawn width of the drift region 4 WDVAR ∆WD m Width offset of the drift region 5 TREF Tref ◦C Reference temperature 6 VFB VFB V Flat-band voltage of the channel region. Width scaling coefficient for k0 12 KODR k0DR V1/2 Body factor of the drift region of an infinitely wide transistor 13 SWKOD SW .1 List of Geometrical Model Parameters No. at reference temperature 17 STPHIBD ST .φB VK−1 Temperature scaling coefficient for φB 16 PHIBD φBD V Surface potential at the onset of strong inversion in the drift region. For simplicity. 3. Parameter Symbol Units Meaning 0 LEVEL level .2.2 Unclassified Technical Note PR-TN-2005/00406 3. the geometrical model can be used. The model parameters of the geometrical model are listed in Section 3. the electrical parameters for a reference device dimension and temperature.3.k0D .

due to velocity saturation 31 ETATHE3 ηθ3 . due to the vertical depletion field in the channel region 29 SWTHE2 SW . Factor for channel-length modulation 39 VP VP V Characteristic voltage of channel-length modulation 40 SDIBL σdibl V−1/2 Factor for drain-induced barrier lowering 41 MSDIBL mσdibl .θ3D . Exponent for the drain-induced barrier lowering de- pendence on the backgate bias 42 MO m0 V Parameter for the (short-channel) sub-threshold slope 43 SSF σsf V−1/2 Factor for static feedback c NXP Semiconductors 2009 13 . Temperature scaling exponent for RD 24 LAMD λD . Level 2002.Unclassified Technical Note PR-TN-2005/00406 MOS Model 20. Temperature scaling exponent for βacc 22 RDW RDW Ω On-resistance of a drift region of 1 µm width. Temperature scaling exponent for θ3 32 SWTHE3 SW . Width scaling coefficient for θ3 33 MEXP m . at refer- ence temperature 23 ETARD ηRD . due to velocity saturation 35 ETATHE3D ηθ3D .2 May 2009 No.θ1 . Smoothing factor for the transition from the linear to the quasi-saturation regime 38 ALP α . Width scaling coefficient for θ2 30 THE3R θ3R V−1 Mobility reduction coefficient in the channel region of an infinitely wide transistor.θ3 . Quotient of the depletion layer thickness to the effec- tive thickness of the drift region at VSB = 0 V 25 THE1R θ1R V−1 Mobility reduction coefficient of an infinitely wide transistor.θ2 . Width scaling coefficient for θ3D 37 MEXPD mD . due to the vertical strong-inversion field in the channel region 26 SWTHE1 SW . at reference temperature 21 ETABETACC ηβacc . Smoothing factor for the transition from the linear to the saturation regime 34 THE3DR θ3DR V−1 Mobility reduction coefficient in the drift region of an infinitely wide transistor. Parameter Symbol Units Meaning 20 BETACCW βacc W AV−2 Gain factor of a drift region of 1 µm width. Width scaling coefficient for θ1 27 THE1ACC θ1acc V−1 Mobility reduction coefficient in the drift region due to the vertical electrical field caused by accumulation 28 THE2R θ2R V−1/2 Mobility reduction coefficient for VSB > 0 of an in- finitely wide transistor. Temperature scaling exponent for θ3D 36 SWTHE3D SW .

at reference temperature. accounting for the contribution of the channel region to the total avalanche current 45 STA1CH ST .a1dr K−1 Temperature scaling coefficient for a1dr 51 SWA1DR SW .a1ch K−1 Temperature scaling coefficient for a1ch 46 SWA1CH SW . Width scaling coefficient for a1dr 52 A2DR a2dr V Exponent of drift-region weak-avalanche current 53 A3DR a3dr . Factor of the drain-source voltage above which weak avalanche occurs 54 COXW CoxW F Oxide capacitance for an intrinsic channel region of 1 µm width 55 COXDW CoxDW F Oxide capacitance for an intrinsic drift region of 1 µm width 56 CGDOW CGDOW F Gate-to-drain overlap capacitance for a drift region of 1 µm width 57 CGSOW CGSOW F Gate-to-source overlap capacitance for a channel re- gion of 1 µm width 58 NT NT J Coefficient of thermal noise. Factor of weak-avalanche current of an infinitely wide transistor. Parameter Symbol Units Meaning 44 A1CHR a1chR . Width scaling coefficient for a1ch 47 A2CH a2ch V Exponent of channel-related weak-avalanche current 48 A3CH a3ch . Number of devices in parallel 14 c NXP Semiconductors 2009 . at reference temperature.2 Unclassified Technical Note PR-TN-2005/00406 No. Level 2002.a1dr . accounting for the contribution of the drift region to the total avalanche current 50 STA1DR ST .May 2009 MOS Model 20. Factor of the internal-drain–source voltage above which weak avalanche occurs 49 A1DRR a1dr R .a1ch . Factor of weak-avalanche current of an infinitely wide transistor. at reference temperature 59 NFAW Nf A W V−1 m−4 First coefficient of flicker noise for a channel region of 1 µm width 60 NFBW Nf B W V−1 m−2 Second coefficient of flicker noise for a channel region of 1 µm width 61 NFCW Nf C W V−1 Third coefficient of flicker noise for a channel region of 1 µm width 62 TOX tox m Thickness of the oxide above the channel region 63 DTA ∆Ta K Temperature offset to the ambient temperature 64 MULT M .

Parameter Symbol Units Meaning 64 RTH RTH ◦ C/W Thermal resistance 65 CTH CTH J/◦ C Thermal capacitance 66 ATH ATH .Unclassified Technical Note PR-TN-2005/00406 MOS Model 20. Number of devices in parallel c NXP Semiconductors 2009 15 .2 May 2009 The additional parameters for the model including self-heating are listed below. Level 2002. Thermal coefficient of the thermal resistance The parameter MULT for all level-2002 models is detailed here: No. Parameter Symbol Units Meaning 67 MULT M . No.

- 27 THE1ACC θ1acc V−1 0. - 33 MEXP m .0 . - 13 SWKOD SW . 0. 0 . - 30 THE3R θ3R V−1 0. - 22 RDW RDW Ω 4. 2002 . - 25 THE1R θ1R V−1 0. 1.0 . 0 . - 16 PHIBD φBD V 0. - 1 W W m 20×10−6 1.6 . 1. - 19 ETABET ηβ . - 20 BETACCW βacc W AV−2 7. - 29 SWTHE2 SW .k0 .09 . 0 .0×10−5 . - 21 ETABETACC ηβacc .1 . - 15 STPHIB ST .78 .2×10−3 . - 7 STVFB ST .VFB VK−1 0 .0×10−9 - 2 WVAR ∆W m 0 . - 24 LAMD λD .03 . - 32 SWTHE3 SW . - 8 VFBD VFBD V −0. 0 .86 .θ3 .May 2009 MOS Model 20. 2. - 9 STVFBD ST .φB VK−1 −1. 1.2 .VFBD VK−1 0 .k0D . Parameter Symbol Units Default Clip low Clip high 0 LEVEL level . - 23 ETARD ηRD .φBD VK−1 −1.0 . - 16 c NXP Semiconductors 2009 .6 . - 17 STPHIBD ST . - 3 WD WD m 20×10−6 1. - 11 SWKO SW . 1.0×10−5 .θ2 . - 10 KOR k0R V1/2 1.0×103 .5 .θ1 .02 .5 . - 18 BETW βW AV−2 7.0×10−9 - 4 WDVAR ∆WD m 0 - 5 TREF Tref ◦C 25 −273 - 6 VFB VFB V −1.4 . - 26 SWTHE1 SW .2 Default and Clipping Values of Geometrical Model Parameters No. - 28 THE2R θ2R V−1/2 0.2 Unclassified Technical Note PR-TN-2005/00406 3. 0 . - 31 ETATHE3 ηθ3 . - 12 KODR k0D R V1/2 1. - 14 PHIB φB V 0.0 .2.2×10−3 . Level 2002.

- 46 SWA1CH SW . - 63 DTA ∆Ta K 0 .05 . - 50 STA1DR ST . - 49 A1DRR a1drR . - 35 ETATHE3D ηθ3D .θ3D .a1dr K−1 0 .3×101 . - 45 STA1CH ST . - 39 VP VP V 0.0 .0×108 . 1.0 . - 57 CGSOW CGSOW F 0 .a1ch K−1 0 . - 41 MSDIBL mσdibl .0×10−3 . - 38 ALP α . - 56 CGDOW CGDOW F 0 . 1. 0 . - 53 A3DR a3dr . - 51 SWA1DR SW . - 58 NT NT J 1. 0. 0 . 2.0 0 - c NXP Semiconductors 2009 17 . 0 .75×10−15 . - 62 TOX tox m 3. - 36 SWTHE3D SW .5×101 . - 47 A2CH a2ch V 7. - 42 MO m0 V 0. 1.a1dr .0×10−3 . - 59 NFAW Nf A W V−1 m−4 1.0 . Parameter Symbol Units Default Clip low Clip high 34 THE3DR θ3DR V−1 0.Unclassified Technical Note PR-TN-2005/00406 MOS Model 20. - 37 MEXPD mD . - 40 SDIBL σdibl V−1/2 1. 3. - 61 NFCW Nf C W V−1 0 . - 52 A2DR a2dr V 7.0×10−12 .a1ch . - 60 NFBW Nf B W V−1 m−2 2. 0. 0. - 67 MULT M .75×10−15 .8 .8 . - 43 SSF σsf V−1/2 1. - 44 A1CHR a1chR .2 May 2009 No.0 0 - 65 CTH CTH J/◦ C 3.5×101 .0 .8×10−8 . - 54 COXW CoxW F 0.0 . 1. 2. - 64 RTH RTH ◦ C/W 300. - 55 COXDW CoxDW F 0.4×1025 .3×101 .0 . - 48 A3CH a3ch .645×10−20 .0 × 10−9 0 - 66 ATH ATH . Level 2002.

May 2009 MOS Model 20.2 Unclassified Technical Note PR-TN-2005/00406 18 c NXP Semiconductors 2009 . Level 2002.

φBD (3.8) q VFBT = VFB + ∆T · ST .0 × 10−6 (m) (3.6) WEN = 1.13) φBD T = φBD + ∆T · ST .VFB (3.19) WE c NXP Semiconductors 2009 19 .3 Geometry and Temperature Scaling Effective temperature and dimensions: TKamb = T0 + Ta + ∆Ta (3.1) TKdev = T0 + Ta + ∆Ta + VdT (3.17) WED TK ref   WEN θ1 = θ1R · 1 + · SW .10)   WEN k0 = k0R · 1 + · SW .VFBD (3.12) WED φB T = φB + ∆T · ST .15) WEN TK dev TKref ηβacc   WED βacc T = βacc W · · (3.9) VFBDT = VFBD + ∆T · ST .2) TK ref = T0 + Tref (3.φB (3.θ1 (3.θ2 (3. Level 2002.k0 (3.14) TKref ηβ   WE βT = βW · · (3.3) ∆T = TKdev − TKref (3.4) WE = W + ∆W (3.7) Actual parameters: kB · TKdev φT = (3.16) WEN TKdev TKdev ηRD   WEN RDT = RDW · · (3.2.18) WE   WEN θ2 = θ2R · 1 + · SW .11) WE   WEN k0D = k0DR · 1 + · SW .2 May 2009 3.5) WED = WD + ∆WD (3.k0D (3.Unclassified Technical Note PR-TN-2005/00406 MOS Model 20.

a1ch ) · 1 + · SW . Level 2002.25) WEN WED CGDO = CGDOW · (3.2 Unclassified Technical Note PR-TN-2005/00406 TKref ηθ3     WEN θ3T = θ3R · · 1+ · SW .27) WEN TKdev NTT = NT · (3.May 2009 MOS Model 20.32) TK ref 20 c NXP Semiconductors 2009 .20) TKdev WE TK ref ηθ3D     WEN θ3DT = θ3DR · · 1+ · SW .θ3D (3.26) WEN WE CGSO = CGSOW · (3.31) WE  ATH TKamb RTHT = RTH · (3.24) WEN WED CoxD = CoxDW · (3.28) TK ref WEN Nf A = Nf A W · (3.a1dr ) · 1 + · SW .θ3 (3.30) WE WEN Nf C = N f C W · (3.23) WED WE Cox = CoxW · (3.a1dr (3.21) TK dev WED   WEN a1chT = a1chR · (1 + ∆T · ST .22) WE   WEN a1drT = a1dr R · (1 + ∆T · ST .a1ch (3.29) WE WEN Nf B = N f B W · (3.

at reference temperature 3 STVFB ST . This model uses as input the electrical parameters for a reference temperature. Quotient of the depletion layer thickness at VSB > 0 to the effective thickness of the drift region at VSB = 0 V 19 THE1 θ1 V−1 Mobility reduction coefficient in the channel region due to the vertical electrical field caused by strong in- version c NXP Semiconductors 2009 21 . at reference tempera- ture 17 ETARD ηRD . Temperature scaling exponent for βacc 16 RD RD Ω On-resistance of the drift region. at reference temperature 9 STPHIB ST . the reference temperature. the electrical model can be used. Temperature scaling exponent for β 14 BETACC βacc AV−2 Gain factor for accumulation in the drift region.Unclassified Technical Note PR-TN-2005/00406 MOS Model 20.1.φBD VK−1 Temperature scaling coefficient for φBD 12 BET β AV−2 Gain factor of the channel region. both n-channel and p-channel devices have been assigned the same default parameter values.VFBD VK−1 Temperature scaling coefficient for VFBD 6 KO k0 V1/2 Body factor of the channel region 7 KOD k0D V1/2 Body factor of the drift region 8 PHIB φB V Surface potential at the onset of strong inversion in the channel region.3. Must be set to 2002 1 TREF Tref ◦C Reference temperature 2 VFB VFB V Flat-band voltage of the channel region.3 Electrical Model To characterize a single LDMOS device including self-heating effects. Parameter Symbol Units Meaning 0 LEVEL level . Temperature scaling exponent for RD 18 LAMD λD . For simplicity.3.φB VK−1 Temperature scaling coefficient for φB 10 PHIBD φBD V Surface potential at the onset of strong inversion in the drift region. in the electrical MOS Model 20. The model parameters of the electrical model are listed in Section 3.VFB VK−1 Temperature scaling coefficient for VFB 4 VFBD VFBD V Flat-band voltage of the drift region. at reference tem- perature 5 STVFBD ST . while its temperature scaling rules are listed in Section 3.3. and all temperature-scaling parameters. at ref- erence temperature 15 ETABETACC ηβacc .3.1 List of Electrical Model Parameters No. at reference temperature 11 STPHIBD ST . at reference temper- ature 13 ETABET ηβ .2 May 2009 3. 3. Level 2002. together referred to as the miniset.

Smoothing factor for the transition from the linear to the saturation regime 25 THE3D θ3D V−1 Mobility reduction coefficient in the drift region due to the horizontal electrical field caused by velocity satu- ration 26 ETATHE3D ηθ3D . at reference temper- ature.May 2009 MOS Model 20. Factor of weak-avalanche current. Temperature scaling exponent for θ3 24 MEXP m . Temperature scaling exponent for θ3D 27 MEXPD mD . Exponent for the drain-induced barrier lowering de- pendence on backgate bias 32 MO m0 V Parameter for the (short-channel) sub-threshold slope 33 SSF σsf V−1/2 Factor for static feedback 34 A1CH a1ch .a1dr K−1 Temperature scaling coefficient for a1dr 40 A2DR a2dr V Exponent of drift-region weak-avalanche current 41 A3DR a3dr .2 Unclassified Technical Note PR-TN-2005/00406 No. Factor of internal drain-source voltage above which weak avalanche occurs 38 A1DR a1dr . accounting for the contribution of the channel region to the total avalanche current 35 STA1CH ST . Factor of drain-source voltage above which weak avalanche occurs 42 COX Cox F Oxide capacitance for the intrinsic channel region 22 c NXP Semiconductors 2009 . Smoothing factor for the transition from the linear to the quasi-saturation regime 28 ALP α . Parameter Symbol Units Meaning 20 THE1ACC θ1acc V−1 Mobility reduction coefficient in the drift region due to the vertical electrical field caused by accumulation 21 THE2 θ2 V−1/2 Mobility reduction coefficient at VSB > 0 in the chan- nel region due to the vertical electrical field caused by depletion 22 THE3 θ3 V−1 Mobility reduction coefficient in the channel region due to the horizontal electrical field caused by veloc- ity saturation 23 ETATHE3 ηθ3 . Factor for channel-length modulation 29 VP VP V Characteristic voltage of channel-length modulation 30 SDIBL σdibl V−1/2 Factor for drain-induced barrier lowering 31 MSDIBL mσdibl .a1ch K−1 Temperature scaling coefficient for a1ch 36 A2CH a2ch V Exponent of channel-related weak-avalanche current 37 A3CH a3ch . Factor of weak-avalanche current. at reference temper- ature. Level 2002. accounting for the contribution of the drift region to the total avalanche current 39 STA1DR ST .

Level 2002. Parameter Symbol Units Meaning 43 COXD CoxD F Oxide capacitance for the intrinsic drift region 44 CGDO CGDO F Gate-to-drain overlap capacitance 45 CGSO CGSO F Gate-to-source overlap capacitance 46 NT NT J Coefficient of thermal noise. Number of devices in parallel c NXP Semiconductors 2009 23 .2 May 2009 No. at reference temperature 47 NFA Nf A V−1 m−4 First coefficient of flicker noise 48 NFB Nf B V−1 m−2 Second coefficient of flicker noise 49 NFC Nf C V−1 Third coefficient of flicker noise 50 TOX tox m Thickness of the oxide above the channel region 51 DTA ∆Ta K Temperature offset to the ambient temperature 52 RTH RTH ◦ C/W Thermal resistance 53 CTH CTH J/◦ C Thermal capacitance 54 ATH ATH .Unclassified Technical Note PR-TN-2005/00406 MOS Model 20. Thermal coefficient of the thermal resistance 55 MULT M .

0×10−12 - 13 ETABET ηβ .4×10−3 1. 2. 2.0×10−3 0 - 29 VP VP V 0.0×10−12 - 19 THE1 θ1 V−1 0.1 .5 33 SSF σsf V−1/2 1. - 6 KO k0 V1/2 1.05 - 25 THE3D θ3D V−1 0. - 18 LAMD λD .3. - 3 STVFB ST .φBD VK−1 −1.4 0 - 23 ETATHE3 ηθ3 .09 0 - 20 THE1ACC θ1acc V−1 0.5 .0 .2 Unclassified Technical Note PR-TN-2005/00406 3.2×10−3 .4×10−3 1.0 0 0.0×10−3 0 - 31 MSDIBL mσdibl . - 5 STVFBD ST . 1. - 24 MEXP m .0×10−12 - 30 SDIBL σdibl V−1/2 1.2×10−3 . - 27 MEXPD mD .86 1. 1.0×10−12 - 8 PHIB φB V 0.0 .0 .0×102 1.VFBD VK−1 0 .VFB VK−1 0 .0×10−12 - 11 STPHIBD ST .0×10−12 - 17 ETARD ηRD .0 1.0×10−12 - 7 KOD k0D V1/2 1.0 0 - 32 MO m0 V 0.78 1. - 16 RD RD Ω 2. Parameter Symbol Units Default Clip low Clip high 0 LEVEL level .5 .0 0 - 26 ETATHE3D ηθ3D . - 10 PHIBD φBD V 0.May 2009 MOS Model 20.6 . 1.0 0.05 1.0×10−12 - 9 STPHIB ST .03 0 - 22 THE3 θ3 V−1 0.0×10−12 - 24 c NXP Semiconductors 2009 . 1. - 4 VFBD VFBD V −0. 3.0×10−12 1.2 1. 2002 .0 0.φB VK−1 −1. Level 2002. - 14 BETACC βacc AV−2 1.2 Default and Clipping Values of Electrical Model Parameters No. 0. - 1 TREF Tref ◦C 25 −273 - 2 VFB VFB V −1.6 1.02 0 - 21 THE2 θ2 V−1/2 0.05 - 28 ALP α .0×10−12 - 15 ETABETACC ηβacc . 2. - 12 BET β AV−2 1. 1.

Level 2002.0×10−12 - 41 A3DR a3dr .2 May 2009 No. 0.a1dr K−1 0 . Parameter Symbol Units Default Clip low Clip high 34 A1CH a1ch . 0.645×10−20 0 - 47 NFA Nf A V−1 m−4 7.0×107 0 - 49 NFC Nf C V−1 0 0 - 50 TOX tox m 3.0 0 - c NXP Semiconductors 2009 25 .8×10−8 1. - 36 A2CH a2ch V 7. 1.0×10−12 - 51 DTA ∆Ta K 0 . - 55 MULT M .3×101 1.8 0 - 38 A1DR a1dr .Unclassified Technical Note PR-TN-2005/00406 MOS Model 20. 1.5×101 0 - 35 STA1CH ST .a1ch K−1 0 .3×101 1. - 40 A2DR a2dr V 7.0×1023 0 - 48 NFB Nf B V−1 m−2 1.0×10−12 - 37 A3CH a3ch .0 × 10−9 0 - 54 ATH ATH .8 0 - 42 COX Cox F 15×10−15 0 - 43 COXD CoxD F 15×10−15 0 - 44 CGDO CGDO F 0 0 - 45 CGSO CGSO F 0 0 - 46 NT NT J 1.0 . 1.0 0 - 53 CTH CTH J/◦ C 3.5×101 0 - 39 STA1DR ST . - 52 RTH RTH ◦ C/W 300. 0.

43) TKdev TK dev ηRD   RDT = RD · (3.40) φBD T = φBD + ∆T · ST .46) TK dev a1chT = a1ch · (1 + ∆T · ST .36) Actual parameters: kB · TKdev φT = (3.41) TK ref ηβ   βT = β· (3.50) TKref 26 c NXP Semiconductors 2009 .33) TKdev = T0 + Ta + ∆Ta + VdT (3.44) TK ref TKref ηθ3   θ3T = θ3 · (3.39) φB T = φB + ∆T · ST .34) TKref = T0 + Tref (3.37) q VFBT = VFB + ∆T · ST .49) TK ref  ATH TKamb RTHT = RTH · (3.VFBD (3.48) TKdev NTT = NT · (3.2 Unclassified Technical Note PR-TN-2005/00406 3. Level 2002.35) ∆T = TK dev − TK ref (3.3 Temperature Scaling Effective temperature: TK amb = T0 + Ta + ∆Ta (3.a1dr ) (3.47) a1drT = a1dr · (1 + ∆T · ST .38) VFBDT = VFBD + ∆T · ST .42) TKdev TKref ηβacc   βacc T = βacc · (3.φBD (3.VFB (3.φB (3.3.45) TKdev TKref ηθ3D   θ3DT = θ3D · (3.a1ch ) (3.May 2009 MOS Model 20.

61) M 1 CTH → CTH · (3. The clip- ping values of these parameters are the same as those for the electrical model parameters. temperature.62) M 3.52) 1 RDT → RDT · (3.55) CGDO → CGDO · M (3.58) M 1 Nf B → Nf B · (3.4.1 MULT Scaling Since equal. parallel-circuited transistors is implemented by adjust- ing the following parameters.56) CGSO → CGSO · M (3. the actual parameters are clipped.Unclassified Technical Note PR-TN-2005/00406 MOS Model 20. charges.53) M Cox → Cox · M (3. and noise spectral densities for these equal.57) 1 Nf A → Nf A · (3.59) M 1 Nf C → Nf C · (3.2. and MULT scaling. parallel-circuited transistors are frequently employed in circuit design. the simulation of currents.3.2 Clipping of Actual Parameters After the geometry. In MOS Model 20.4 Postprocessing 3. the specifica- tion of one transistor together with a multiplication factor MULT (M ) in the circuit description is convenient and saves computation time. Level 2002.2 May 2009 3.4. as listed in Section 3.60) M 1 RTH → RTH · (3.54) CoxD → CoxD · M (3. c NXP Semiconductors 2009 27 . according to βT → βT · M (3.51) βacc T → βacc T · M (3.

where F denotes the function name and the function variables are enclosed by braces [].2 Unclassified Technical Note PR-TN-2005/00406 4 Implemented Equations In the following sections. Level 2002.].May 2009 MOS Model 20. .1 Internal Parameters Gmin = 1 · 10−15 ǫ1 = 2 · 10−2 ǫ2 = 1 · 10−2 ǫ3 = 4 · 10−2 ǫ4 = 1 · 10−1 ǫ5 = 1 · 10−4 ǫ6 = 1 · 10−5 ǫ7 = 2 · 10−1 ǫ8 = 3 · 10−2 V1 = 1 Vlimit = 4 · φT 1 φ0 = 2 (φB T + φBD T ) 1 Acc = √ 1 + k0 2 · φT 1 AccD = √ 1 + k0D 2 · φT Cox FL = Cox + CoxD 28 c NXP Semiconductors 2009 . The definitions of the hyp.and hypm functions are found in Appendix A. 4. a function is denoted by F [variable. . .

6) k δ= p 0 (4. VDS < 0 VGSt = VGS − VFBDT (4.2 Current Equations Effective potentials: VGBt0 = VGS + VSB − VFBT (4. m] .5) Channel-region quantities: h p i Vinv0 = hyp VGBt0 − VSBt − k0 · VSBt .17) c NXP Semiconductors 2009 29 .Unclassified Technical Note PR-TN-2005/00406 MOS Model 20.3) hypm [VDS . Level 2002. ǫ2 ] + 0.4) VGDt = VGSt − VDS1 (4. VDS ≥ 0 ( VDS1 = (4. VSBt . ǫ1 ] − φ0 flin = hyp 1 − λD · √ .9 · φB T .16) βacc T · RDT 1 Fmobacc = 1 + 2 · θ1acc · (hyp [VGSt .10) 1 + 1 + 2 · θ3T · VDiSsat0 VSBt0 = hyp [0.12) p Vdep00 = k0 · VSBt0 (4.1) VSBt = hyp [VSB + 0.9) ξ 2 · VDiSsat0 VDiSsat = p (4. ǫ2 (4. ǫ2 ] + hyp [VGDt .2 May 2009 4. ǫ2 ]) (4.13) Vdep0 − Vdep00 Fmob = 1 + θ1 · Vinv0 + θ2 · (4. ǫ2 (4.15) φ0 flin Voxp = (4.1 · φB T (4.9 · φB T .11) p Vdep0 = k0 · VSBt (4.7) 2 · V1 + VSBt ξ =1+δ (4.14) k0 Drift-region quantities: " p √ # φ0 + hyp [VSB .8) Vinv0 VDiSsat0 = (4.2) VDS .1 · φB T (4. ǫ2 ] + 0.

Level 2002. VDDisat .May 2009 MOS Model 20. Fmob ] = (4.2 Unclassified Technical Note PR-TN-2005/00406 Numerical iteration procedure for the internal drain voltage: VDiSeff = hypm [VDiS . VDS1 . 8 .19) 1  V − · ξ · V · V  inv0 DiSeff DiSeff   2   βT · F · (1 + θ · V DiSeff )  mob 3      + Gmin · k02 · VDiS . VGDit < 0     VGDit .23) 2 · Vqdr eff VDDisat = q (4. VDiSsat .22)   − k0D · − + − VGDit  . mD ] (4. ǫ2 (4. ǫ2 ] + 0.20)   VGDit . Fmobacc ] =   (4.1 · φBD T (4. VGDit < 0   2 2 h i Vqdr eff = hyp Vqdr [VGDit eff ] . Vinv0 .    VDiS < 0 Ich [VDiS . VDDi < 0  30 c NXP Semiconductors 2009 . VGSt .27)  dr 1 V − · V · VDDi  DDi    q eff 2   βacc T · Fmobacc · (1 − θ3DT · VDDi )      2  + Gmin · k0D · VDDi .26)    dr 1   Vq eff − 2 · V DDieff · VDDieff β ·  acc   T     Fmobacc · (1 + θ3DT · VDDieff )  2     + Gmin · k0D · VDDi . VDDi ≥ 0 Idr [VDiS .25) VDDieff = hypm [VDDi . VDiSsat .24) 1+ 1 + 2 · θ3DT · Vqdr eff VDDi = VDS1 − VDiS (4.21) hypm VGDit . VGDit ≥ 0     Vqdr [VGDit ] = Voxp + s 2 k0D k0D (4. VDiS ≥ 0  VDiBt = hyp [VSB + VDiS + 0. VDiBt + k0D · VDiBt . m] (4.9 · φBD T . ξ. VGDit ≥ 0 VGDit eff =  p  (4. VSB .18) 1   V inv0 − 2 · ξ · V DiS · VDiS βT ·        Fmob · (1 − θ 3 · V DiS )   + Gmin · k02 · VDiS .

i = i + 1 do begin if { ((VDiS − VDiS H ) · ∆H − H) · ((VDiS − VDiS L ) · ∆H − H) > 0 or |2 · H| > |∆VDiS0 · ∆H|} then (4. VGSt . Vinv0 . Fmobacc ] H1 = Ich [VDS1 . VSB . VDiSsat .Unclassified Technical Note PR-TN-2005/00406 MOS Model 20. Fmob ] − Idr [0. ξ. VSB . VDS1 .29) c NXP Semiconductors 2009 31 .2 May 2009 Newton-Raphson/bisection iteration procedure: H0 = Ich [0. Vinv0 . VGSt . VDiSH = 0} 1 VDiS = · (VDiS L + VDiS H ) 2 H = Ich [VDiS . VDiSsat . ξ.28) { ∆VDiS0 = ∆VDiS 1 ∆VDiS = · (VDiSH − VDiSL ) 2 VDiS = VDiSL + ∆VDiS } else { ∆VDiS0 = ∆VDiS H ∆VDiS = ∆H VDiS = VDiS − ∆VDiS } error = |∆VDiS | H = Ich [VDiS . VDS1 . ξ. ξ. VDS1 . Fmobacc ] ∂Ich ∂Idr ∆H = − ∂VDiS ∂VDiS ∆VDiS0 = |VDiSH − VDiSL | ∆VDiS = ∆VDiS0 error = |∆VDiS |  for i = 0. Level 2002. VDiSsat . Fmobacc ] ∂Ich ∂Idr ∆H = − ∂VDiS ∂VDiS if H < 0 then VDiSL = VDiS else VDiSH = VDiS end VDDi = VDS1 − VDiS (4. Fmob ] − Idr [VDS1 . VGSt . VDS1 . Fmob ] − Idr [VDiS . Vinv0 . VDiSsat . VSB . i < 100 and error > 1 × 10−12 . Fmob ] − Idr [VDiS . Vinv0 . VSB . VDiSH = VDS1 } else {VDiSL = VDS1 . VGSt . Fmobacc ] if H0 = 0 then VDiS = 0 if H1 = 0 then VDiS = VDS1 if H0 < 0 then {VDiSL = 0.

ǫ4 · σsf ] (4. ǫ1 ] (4. VCBt ] = f1 [ψsat .33) D = Ddibl + hyp [Dsf − Ddibl .31) 2 k0 /2 + VGBeff0 + (k0 /2 ) p !mσ dibl p VSB Ddibl = σdibl · φB T · p t (4. ∆acc .35) Vlimit2 + VDS1 2 ∆VG = D · VDSeff (4.40) 2 k/2 + VGBeff + ∆acc + (k/2 ) ψsat = Ψsat [VGBeff . ∆acc . VGBeff ] = VGBeff − f2 [ψsat .32) φB T p Dsf = σsf · hyp [ψsat0 − VSBt . ǫ1 ] (4.43) (ψsat − f1 [ψsat . VCBt ] + s (4.39) φT  2 VGBeff + ∆acc Ψsat [VGBeff . ǫ3 ] (4. ǫ1 ] (4.34) VDS1 4 VDSeff = 3/2 (4.42) ψsat − f1 [ψsat .2 Unclassified Technical Note PR-TN-2005/00406 Drain-induced barrier lowering and static feedback: VGBeff0 = hyp [VGBt0 .38)     Acc · (VGBeff − ǫ1 ) ∆acc = φT · exp − −1 (4. VCBt . VCBt ] = ψsat − hyp [ψsat − VCBt . VCBt ])2 1+ 16 · φT 2 f3 [ψsat . Level 2002. VCBt ] f2 [ψsat .41) f1 [ψsat .36) Surface potential at the source: VGBt = VGBt0 + ∆VG (4.37) VGBeff = hyp [VGBt . k0 ] (4.44) 32 c NXP Semiconductors 2009 .May 2009 MOS Model 20.30)  2 VGBeff0 ψsat0 =  q  (4. k] =  q  − ∆acc (4. VCBt ] (4.

Unclassified Technical Note PR-TN-2005/00406 MOS Model 20, Level 2002.2 May 2009

Ψs [VGBeff , ψsat , ∆acc , VCBt ; k, m0 ] = f1 [ψsat , VCBt ]
  2 
f3 [ψsat , VCBt , VGBeff ]
− f1 [ψsat , VCBt ] − ∆acc  (4.45)
 k
+ φT · (1 + m0 ) · ln 1 +
 
φT

 

ψs0 = Ψs [VGBeff , ψsat , ∆acc , VSBt ; k0 , m0 ] (4.46)

Recalculation of channel-region quantities:
h p i
Vinv [VGBeff , ψs , ∆acc ; k] = hyp VGBeff − ψs − k · hyp [ψs + ∆acc ; ǫ2 ]; ǫ5 (4.47)

Vinv0 = Vinv [VGBeff , ψs0 , ∆acc ; k0 ] (4.48)
p
Vdep [ψs , ∆acc ; k, ǫ] = k · hyp [ψs + ∆acc ; ǫ] (4.49)

Vdep0 = Vdep [ψs0 , ∆acc ; k0 , ǫ2 ] (4.50)

ψs00 = Ψs [VGBeff , ψsat , ∆acc , VSBt0 ; k0 , m0 ] (4.51)

Vdep00 = Vdep [ψs00 , ∆acc ; k0 , ǫ2 ] (4.52)

hyp [Vdep0 − Vdep00 ; ǫ5 ]
Fmob = 1 + θ1 · Vinv0 + θ2 · (4.53)
k0

k0
δ= p (4.54)
2 · V1 + hyp [ψs0 + ∆acc ; ǫ5 ]

ξ =1+δ (4.55)

Vinv0
VDiSsat0 = (4.56)
ξ

2 · VDiSsat0
VDiSsat = p (4.57)
1 + 1 + 2 · θ3T · VDiSsat0

VDiSsateff = Vlimit + hyp [VDiSsat − Vlimit ; ǫ3 ] (4.58)

Surface potential at the internal drain:

VDiSeff = hypm [VDiS , VDiSsateff ; m] (4.59)

VDiBt,eff = hyp [VSB + VDiSeff + 0.9 · φB T ; ǫ2 ] + 0.1 · φB T (4.60)
 
ψsL = Ψs VGBeff , ψsat , ∆acc , VDiBt,eff ; k0 , m0 (4.61)

c NXP Semiconductors 2009 33

May 2009 MOS Model 20, Level 2002.2 Unclassified Technical Note PR-TN-2005/00406

Drain-source current:

Vinvex [ψs , ∆acc , VCBt ; k, m0 ]
 
ψs − VCBt
φT · exp (4.62)
(1 + m0 ) · φT
= k·s  
ψs − VCBt p
hyp [ψs + ∆acc ; ǫ8 ] + φT · exp + hyp [ψs + ∆acc ; ǫ8 ]
(1 + m0 ) · φT

Vinvex0 = Vinvex [ψs0 , ∆acc , VSBt ; k0 , m0 ] (4.63)

 
VinvexL = Vinvex ψsL , ∆acc , VDiBt,eff ; k0 , m0 (4.64)

∆ψs = ψsL − ψs0 (4.65)

1
Vinv = Vinv0 − 2 · ξ · ∆ψs (4.66)

Fmobsat = 1 + θ3T · ∆ψs (4.67)

Gmob = Fmob · Fmobsat (4.68)

  q  
VDS 1 − VDiSeff + (VDS 1 − VDiSeff )2 + VP2
G∆L = hyp 1 − α · ln   ; ǫ5  (4.69)
VP

ψsat + φT − VSBt
x0 = 2 · (4.70)
φT

ψsat + φT − VDiBt,eff
xL = 2 · (4.71)
φT

exp[x0 ] + exp[xL ]


 , x0 ≤ 80 ∧ xL ≤ 80,
G= 1 + exp[x0 ] + exp[xL ] (4.72)

1, x0 > 80 ∨ xL > 80

Vinv · ∆ψs
Idrift = βT · G · (4.73)
Gmob · G∆L

Vinvex0 − VinvexL
Idiff = βT · φT · (4.74)
Gmob · G∆L

IDS = Idrift + Idiff (4.75)

34
c NXP Semiconductors 2009

Unclassified Technical Note PR-TN-2005/00406 MOS Model 20, Level 2002.2 May 2009

Avalanche current:
 
a2ch a2ch

 a1chT · |IDS | · exp −
 , |VDiS | − a3ch · VDiSsateff > − ,
IAVLch = |VDiS | − a3ch · VDiSsateff A
 0, a2ch
|VDiS | − a3ch · VDiSsateff ≤ −

A
(4.76)

Fmobsatsat = 1 + θ3T · VDiSsateff (4.77)

Gmobsat = Fmob · Fmobsatsat (4.78)

1
 
Vinvsat = hyp Vinv0 − 2 · ξ · VDiSsateff ; ǫ2 (4.79)

Vinvsat · VDiSsateff
Isat = βT · G · (4.80)
Gmobsat

Vchsat = RDT · Isat (4.81)

βaccT · RDT
facc = (4.82)
Fmobacc

flin
Voxpavl = (4.83)
facc

s  
2 2 · Vchsat
VDSsat = Voxpavl + VGSt − hyp (Voxpavl + VGSt − VDiSsateff ) − ; ǫ5 (4.84)
facc

VDSsateff = Vlimit + hyp [VDSsat − Vlimit; ǫ3 ] (4.85)

 
a2dr a2dr

 a1drT · |IDS | · exp −
 , |VDS1 | − a3dr · VDSsateff > − ,
IAVLdr = |VDS1 | − a3dr · VDSsateff A
 0, a2dr
|VDS1 | − a3dr · VDSsateff ≤ −

A
(4.86)

IAVL = IAVLch + IAVLdr (4.87)

4.3 Charge Equations

Surface potential for accumulation in the channel region:

f1acc [VGBt , VGBeff ; Acc] = Acc · (VGBt − VGBeff ) (4.88)

c NXP Semiconductors 2009 35

Acc]  (4.99) 12 · ξ ( )! Cox ∆VGT Fj Fj2 QDmos = − · VGT − · 1− − (4. Acc] − f2acc [VGBt . VGBeff . Acc] f2acc [VGBt . VGBeff . VGBeff . Acc] = VGBt − VGBeff − f2acc [VGBt .90) Ψsacc [VGBt .91)  k = −φT · ln 1 +   φT    ψsacc = Ψsacc [VGBt . VGBeff . ψs0 . k0 ] (4. Acc]   2  f3acc [VGBt . k0 ] (4.96) 1 VGT = 2 · (VGT0 + VGTL ) (4. Level 2002. VGBeff .102) Qch G = QGmos (4.92) Charges in the channel region: 1 Vox = VGBt − 2 · (ψs0 + ψsL ) − ψsacc (4. k.106) 36 c NXP Semiconductors 2009 .94) VGTL = Vinv [VGBeff . VGBeff .2 Unclassified Technical Note PR-TN-2005/00406 f1acc [VGBt . k0 . VGBeff .95) ∆VGT = VGT0 − VGTL (4.May 2009 MOS Model 20.89) f 2 [VGBt . ∆acc .101) 2 6 2 20 QBmos = − (QGmos + QDmos + QSmos ) (4.103) Qch D = FL · QDmos (4. Acc] (4. ψsL .105)   Qch ch ch B = − QG + QD + QS ch (4.98) VGT + ξ · φT   Fj QGmos = Cox · Vox + · ∆VGT (4. VGBeff . VGBeff .100) 2 6 2 20 ( )! Cox ∆VGT Fj Fj2 QSmos =− · VGT + · 1+ − (4. ∆acc . Acc] = s (4. Acc] 1 + 1acc 16 · φT 2 f3acc [VGBt . Acc] (4.104) Qch S = QSmos + (1 − FL ) · QDmos (4.97) ∆VGT Fj = (4.93) VGT0 = Vinv [VGBeff .

ǫ2 + 0.119) h i Vqdr Di eff = V limit + hyp V dr qDi − V . ∆accDi .108)   VDiGeff = hyp −VGDit.eff (4. VDiGeff .114) Drift-region charges at the internal drain: dr Vox Di = VGDit.1 · φBD T (4.118) Vqdr Di = Voxp + Vqaccdep Di (4.116) VinvDi = Vinv [VDiGeff . AccD (4.113)   ψsaccDi = Ψsacc −VGDit.eff + 0. ∆accDi .122) c NXP Semiconductors 2009 37 .117) Vqaccdep Di dr = Vox Di + VinvDi (4. ǫ7 (4. ∆accDi .eff + ψsDi + ψsaccDi (4. k0D ] (4.112) ψsDi = Ψs [VDiGeff . ψsatDi . ǫ2 ] (4. limit 7ǫ (4. k0D . k0D .121) 1+ 1 + 2 · θ3D T · Vqdr Di eff VDDieff = hypm [VDDi .107) VGDit. mD ] (4.9 · φBD T .109)     AccD (VDiGeff − ǫ7 ) ∆accDi = φT · exp − −1 (4.eff .Unclassified Technical Note PR-TN-2005/00406 MOS Model 20. k0D ] (4.2 May 2009 Surface potential at the internal drain in the drift region: VDiSdr.eff = VDiS (4. VDDisat .eff . VDiBt .115) VdepDi = Vdep [ψsDi . ψsDi .111)   VDiBt = hyp VSB + VDiSdr.eff = VGSt − VDiSdr. Level 2002.110) φT ψsatDi = Ψsat [VDiGeff . ∆accDi .120) 2 · Vqdr Di eff VDDisat = q (4. m0 ] (4. k0D .

140) 2 6 2 20 ( )! CoxD ∆Vqaccdep Fj Fj2 Qaccdep S =− · Vqdr eff + · 1 + dr − dr (4. limit 7ǫ (4.135) h i Vqdr D eff = V limit + hyp V dr qD − V .131) VdepD = Vdep [ψsD . k0D ] (4.eff = VGSt − VDSdr.2 Unclassified Technical Note PR-TN-2005/00406 Surface potential at the drain in the drift region: VDSdr.1 · φBD T (4.eff .141) 2 6 2 20 38 c NXP Semiconductors 2009 . VDBt .eff . ψsD .124)   VDGeff = hyp −VGDt. m0 ] (4.eff + VDDieff (4. k0D .125)     AccD (VDGeff − ǫ7 ) ∆accD = φT · exp − −1 (4.134) Vqdr D = Voxp + Vqaccdep D (4.137) ∆Vqaccdep = Vqaccdep Di − Vqaccdep D (4.136) Total charges in the drift region:   Vqdr eff = 21 · Vqdr Di eff + V q dr D eff (4.126) φT ψsatD = Ψsat [VDGeff .eff (4. k0D ] (4.132) VinvD = Vinv [VDGeff .9 · φBD T . ǫ2 ] (4. ∆accD . ǫ2 + 0. VDGeff . ǫ7 (4. ∆accD . Level 2002.127)   VDBt = hyp VSB + VDSdr.123) VGDt.eff = VDiSdr. k0D . AccD (4. ∆accD .eff + 0. ∆accD .139) Vqdr eff ( )! CoxD ∆Vqaccdep Fjdr Fj2dr Qaccdep D =− · Vqdr eff − · 1− − (4.129)   ψsaccD = Ψsacc −VGDt.eff + ψsD + ψsaccD (4. k0D .133) Vqaccdep D dr = Vox D + VinvD (4.138) ∆Vqaccdep Fjdr = (4. ψsatD .May 2009 MOS Model 20.130) Drift-region charges at the drain: dr Vox D = VGDt.128) ψsD = Ψs [VDGeff .

lim + VGDacc.lim ( )! CoxD ∆Vacc.155) QD = Qch dr D + QD (4.lim (4.lim (4.eff − hyp VGDit.150) 2 6 2 20 Total drift-region charges: accdep Qdr D = QD + FL · Qaccdep S + (1 − FL ) · QSacc.Unclassified Technical Note PR-TN-2005/00406 MOS Model 20.lim = hyp [VGDilim .158) c NXP Semiconductors 2009 39 .lim = (4.144) VGDacc.147) 1  Vacc.lim = VGDiacc.157) QB = − (QG + QD + QS ) (4.152) CoxD Qdr B = · (VinvD + VinvDi ) (4.eff (4.146) ∆Vacc.lim Fjacc.142)   VGDilim = VGDit.2 May 2009 Inclusion of asymmetry: q VTt = VFBT + φB T − VFBDT + k0 · VDiBt.156) QS = Qch dr S + QS (4. ǫ7 (4.lim (4. ǫ7 ] (4.lim + Voxp Fj2acc.143) VGDlim = VGDilim − VDDieff (4.153) 2   Qdr G = − Q dr S + Q dr D + Q dr B (4.lim = hyp [VGDlim . Level 2002.lim (4.148) ∆Vacc.lim − VGDacc.149) Vacc.154) Total charges: QG = Qch dr G + QG (4.lim + · 1+ − (4.eff − VTt .lim QSacc.lim Fjacc.151)   accdep Qdr S = (1 − FL ) · Q S − Q Sacc.lim = 2 · VGDiacc.lim =− · Vacc. ǫ7 ] (4.145) VGDiacc.

2 Unclassified Technical Note PR-TN-2005/00406 4. ǫ2 (4.164) 1+ 1 + 2 · θ3DT · Vqdr eff VDDieff = hypm [VDDi . 1 × 10−10 (4.166) " # ∂Vqdr eff ∂VGDit eff VDDieff gmdr = max βacc T · · · dr .May 2009 MOS Model 20.4 Noise Equations Noise transfer function:     ∆ψs Vinv −10 gmch = max βT · · 1 − θ1 · . VDiBt + k0D · VDiBt .0 (4. 1 × 10 (4. ǫ2 ] + 0.160) Gmob · Fmobsat VDiBt = hyp [VSB + VDiS + 0.1 · φBD T (4.159) Gmob Fmob " # Vinv0 + ξ · Vlimit − ξ · ∆ψs − 21 · θ3T · ξ · (∆ψs )2 gdsch = max βT · . VGDit ≥ 0 VGDit eff =  p  (4.168) dr Fmobacc · Fmobsat gdsdr + gmdr gtransfer = (4. VGDit < 0  h i Vqdr eff = hyp Vqdr [VGDit eff ] . 1 × 10−10 (4.9 · φBD T .169) gdsch + gdsdr + gmdr Flicker noise: ǫox N0 = · Vinvex0 (4. 8 .165) dr Fmobsat = 1 + θ3DT · VDDieff (4.162) hypm VGDit .163) 2 · Vqdr eff VDDisat = q (4.167) ∂VGDit eff ∂VGDit Fmobacc · Fmobsat 1 · θ3DT · (VDDieff )2 " # Vqdr eff − VDDieff − 2 gdsdr = max βacc T · 2 .161)   VGDit . VDDisat .171) q · tox ǫox N∗ = · ξ · φT (4.172) q · tox 40 c NXP Semiconductors 2009 . mD ] (4. Level 2002.170) q · tox ǫox NL = · VinvexL (4.

if the value of VdT is 0. Level 2002.34).178) 4.174) f Thermal noise: ξ2 ∆ψs 2    Fmobsat · G∆L SDth0 = βT · · Vinv + · Fmob 12 Vinv + ξ · φT   (4.175) θ3T · Vinv · ∆ψs θ3T · ∆ψs − · 2− Fmob Fmobsat · G∆L 2 SDth = gtransfer · NTT · max [SDth0 .2) and (3.5. and is given by: e e Pdiss = ID VD + ISe VSe + IBe VBe (4. 0] SDfl = gtransfer · (4. (3.176) (2 · π · Cox )2 2 SGth = NTT · ·f (4.Unclassified Technical Note PR-TN-2005/00406 MOS Model 20.4 · j · SGth · SDth (4.2 Model Equations The total dissipated power is a sum of the dissipated power of each branch of the equivalent circuit. For the most important materials. the increase in temperature is 0. The value of the voltage VdT at the temperature node gives the increase in local temperature.180) c NXP Semiconductors 2009 41 . [8].179) ′′ ′′ ′′ ′′ ′′ ′′ ′′ = IDS VDS + IDB · (VDS − VSB ) + ISB VSB (4. 4. which is included in the calculation of the temperature- scaling relations.5.1 Equivalent Circuit Self-heating is part of the model. which is largely based on Ref. The resistor and capacitor are both connected between ground and the temperature node dT. 0] (4. we recommend using values from literature that describe the temperature scaling of the thermal conductivity.5 degrees Celsius. see Eqns.2 May 2009 q · φ2T · tox · βT · IDS    ∗ ∗2  N0 + N ∗ SDfl0 = Nf A − N · Nf B + N · Nf C · ln ǫox · N ∗ · Gmob NL + N ∗  ∗ Nf C 2 2  + (Nf B − N · Nf C ) · (N0 − NL ) + · N0 − NL (4.5 V.5 Self-Heating 4. For the value of ATH . the values are given in Figure 6.177) 3 · gmch p SGDth = 0. For example. It is defined in the usual way by adding a self-heating network (see Figure 6) containing a current source describing the dissipated power and both a thermal resistance RTH and a thermal capacitance CTH . see also [1].173) 2 2 Nf A + Nf B · NL + Nf C · NL2 + φT · IDS · (1 − G∆L ) · (NL + N ∗ )2 2 max [SDfl0 .

3.2). the node dT is available to the user. Level 2002. circuit. dc. pdiss. 4.May 2009 MOS Model 20.5. mos2002et2 ) and geometrical model (mnt1 . e_ssl (3. 0) 0. end. the self-heating network. dT) level=2002. mos2002t2 ). end. mnet_1(1. run. mpt1 . 0) 1e6.3. 4. where the node voltage VdT is used in the temperature-scaling relations. rth=300. The total dissipation applies for the electrical model (mnet1 . mpet1 . Note that only the steady-state currents contribute to the dissipated power. r_2 (dT. On the right are parameter values that can be used for ATH . 0) 2. cth=3e-9.2 Unclassified Technical Note PR-TN-2005/00406 Figure 6: On the left. 0) 20.3 Usage A Pstar example is given below to illustrate how self-heating works. 1 Pstar model name 2 Spectre/ADS model name 42 c NXP Semiconductors 2009 . 2. print: vn(dT). where all variables are given in Figure 5 in section 2. Example: Title: Example of self-heating in MOS Model 20 (2002. e_bbl (4. e_ddl (1.mnet_1. Note that for increased flexibility. e_gl (2. 0) 0.

2 May 2009 Result: DC Analysis.556E-03 The voltage on node dT is 1.MNET_1 = 3. c NXP Semiconductors 2009 43 . Level 2002. Ground node is set to node 0.066E+00 Pdiss.066E+00 V. VN(DT) = 1. which means that the local temperature is increased by 1.Unclassified Technical Note PR-TN-2005/00406 MOS Model 20.066 ◦ C.

−3. extraction of miniset parameters (including temperature scaling parameters) 3. Therefore. Level 2002. max VDS = −100 mV VSB = 0. extraction of width scaling parameters Notice that. [4]. The reason is that once self-heating has been incorporated. 2. . in contrast to a conventional MOS transistor. 1. . VGS. . max VSB = 0. 3. Further insight into this division can be obtained if one has various LDMOS transistors of different drift-region lengths Ldr available. and 4 V p-channel : VGS = 0. .2 Unclassified Technical Note PR-TN-2005/00406 5 Parameter Extraction Strategy The parameter extraction strategy for MOS Model 20 excluding the effect of self-heating is ana- loguous to the four different steps described in Ref.1 Measurements The parameter extraction routine consists of four different DC measurements and one capacitance measurement1 : • Measurement I (idvg): ID and gm versus VGS characteristics in the linear region: n-channel : VGS = 0. −1. and −4 V 1 The bias conditions to be used for the measurements are dependent on the maximum voltages VDS. the following three steps are performed: 1. . the miniset parameters are internally corrected for this temperature rise due to self- heating. the division of this length into a length Lch of the channel region and a length Ldr of the drift region is difficult. 2. . −2. −1.May 2009 MOS Model 20. and can therefore not be determined from measurements performed at only one single temperature.6 V. to extract parameters for a device including self-heating. Of course. 44 c NXP Semiconductors 2009 . −2. The above three steps of the parameter extraction strategy will be briefly described in the following sections. max VSB = 0. and −4 V • Measurement II (subvt): Sub-threshold ID versus VGS characteristics: n-channel : VGS = VT − 0. 1. 3. However. max VDS = 100 mV VSB = 0.3 V VDS = 3 values starting from 100 mV to VDS.3 V VDS = 3 values starting from −100 mV to −VDS. max and VGS. . physical effects atypical for normal transistor operation (and therefore less well described by MOS Model 20) may dominate the characteristics. Hence. one cannot divide the parameter extraction procedure into a separate parameter extraction of miniset parameters at room temperature and a separate parameter extraction of the temperature scaling parameters. . and 4 V p-channel : VGS = VT + 0. measurements 2. . −3. . . . Otherwise. .6 V. in case of a non-negligible temperature rise due to self-heating. usually the LDMOS transistor has only one gate length L available in a process. max ... VT − 0. 5. VT + 0. it is advisable to restrict the range of voltages to these maximum voltages. −VGS. .

. max /4) to −VGS. 2. VGS.1 V VSB = 0. . .. . VT + 3.1 V.1 V VBS = 0. max + 2 V. max VSB = 0 V p-channel : VDS = 0. . . and −4 V • Measurement IV (idvdh): ID and gDS versus VDS characteristics: n-channel : VDS = 0. respectively. . max − 4 V. VT + 2. measurements I through V have to be performed for a certain device width at various temperatures.1 V. VDS. and Cbg versus VGS characteristics: n/p-channel : VGS = −VGS. VT − 2. Csg . max VDS = 0 V VSB = 0 V The values of transconductance gm and output conductance gDS are determined from the I-V curves by numerically calculating the derivative of ID with respect to VGS and VDS . max VDS = −VDS. . . max − 2 V. ranging from about Tmin = −40 ◦ C to Tmax = 125 ◦ C. VT − 3. . . −VDS. to determine the width scaling parameters. . max VDS = VDS.1 V. . Finally. . c NXP Semiconductors 2009 45 . The way VT is determined is rather arbitrary: it can be either obtained by the use of a linear extrapolation method or by a constant-current criterion.Unclassified Technical Note PR-TN-2005/00406 MOS Model 20. −2.. −VGS. which has to be determined for all of the source-bulk bias values VSB used in measurement I (idvg).. max + 4 V. . max VSB = 0 V • Measurement V (ibvg): ID and IB versus VGS characteristics in high-field operation regions: n-channel : VGS = 0. and 4 V p-channel : VDS = 0. VGS. use is made of the threshold voltage VT . max VGS = 4 values starting from (VGS. −VDS. . max VSB = 0 V p-channel : VGS = 0. max /4) to VGS.1 V. and VDS... max .. max VSB = 0 V • Measurement VI (Cvg): Cgg . and −VDS. In measurements II and III. . max VGS = VT − 0. . Level 2002. For the miniset extraction. VT + 1.1 V. VDS. −VDS. VDS. the measurements at room temperature need to be performed for a narrow and broad transistor. max VGS = 4 values starting from −(VGS.1 V. VT − 1. . Cdg . . max VGS = VT + 0.2 May 2009 • Measurement III (idvd): ID and gDS versus VDS characteristics: n-channel : VDS = 0. ..

This thermal network provides the temperature rise ∆Tself−heating due to self-heating. At T = 27 ◦ C. based on an estimate for the oxide thickness tox . according to the following table: 46 c NXP Semiconductors 2009 . Next. Here. tSi represents the thickness of the silicon wafer. The reference temperature Tref is chosen equal to the chuck temperature Tchuck . a first estimate of the miniset parameters is given for a certain device width W . respectively. the thermal resistance is given by   tBOX tSi 1 tSi 1 RthSOI = + · .2 Unclassified Technical Note PR-TN-2005/00406 5. according to ∆Tself−heating = Rth · IDS · VDS . and drift-region length Ldr . The physical constants kSi and kox are the thermal conductivity of silicon and oxide. the channel length Lch . More details on how to incorporate the effect of self-heating into the parameter extraction strategy can be found in e. Level 2002. Ref.g. (5.2 Extraction of Miniset Parameters (including Temperature Scaling) In case of a non-negligible temperature rise due to self-heating. respectively. or Rthbulk = · . tBOX the thickness of the buried oxide (BOX) layer.1) Here. in general Rth depends on the device temperature as well as device geometry.4 W/(K·m) and kSi = 1. the extraction of miniset param- eters is performed by the use of an external thermal network. and A denotes the area over which dissipation takes place.2) kox kSi A kSi A for an SOI process and a bulk process. Rth denotes the thermal resistance (in kelvins per watt). In case of a one-dimensional heat flow. these conductivities are given by kox = 1.May 2009 MOS Model 20.41 · 102 W/(K·m). and has to be determined before one starts the extraction of miniset parameters. while the temperature rise ∆T is set equal to the temperature rise ∆Tself−heating due to self-heating. see Figure 7. A A SOI k Si k Si t BOX BOX k ox t Si k Si Si−substrate t Si Si−substrate chuck T=Tchuck chuck T =Tchuck Figure 7: Geometry for the one-dimensional heat flow in a transistor in an SOI process (left) and a bulk process (right). [7]. Thus. (5.

0 0.5 · 104 · (Ldr /W) ηRD ETARD 1.0 −1. and oxide thickness tox (m).5 1.0 2.0 a1dr A1DR 18 18 ST .0 k0 KO 1.0 ST .6 RD RD 5.0 1.05 θ2 THE2 0.6 1.05 θ1acc THE1ACC 0.8 ST .0 0.0 1.03 0.2 θ1 THE1 0.8 0.0 · 10−3 2.0 a2dr A2DR 73 73 a3dr A3DR 1.0 · 10−3 1.0 · 10−3 −1.0 · 10−3 −1.9 ST .0 · 10−3 VFBD VFBD 0.6 1.a1dr STA1DR 0.0 0.0 a2ch A2CH 73 73 a3ch A3CH 1.03 θ3 THE3 0.4 ηθ3 ETATHE3 1.453 · 10−11 /tox ) · W · Lch CoxD COXD (3.VFB STVFB −1.8 · 10−12 /tox ) · (W/Lch ) ηβ ETABET 1.0 · 10−3 φBD PHIBD 0.0 · 10−2 5.0 ηθ3D ETATHE3D 1.0 · 10−3 β BET (2.0 α ALP 2.453 · 10−11 /tox ) · W · Ldr CGDO CGDO 3.2 · 10−12 /tox ) · (W/Lch ) (0.0 1.0 · 10−10 · W Table 1: Starting miniset parameter values for parameter extraction of a typical DMOS transistor with channel length Lch (m). device width W (m).0 · 10−6 a1ch A1CH 18 18 ST .0 mD MEXPD 2.0 · 103 · (Ldr /W) 1.φB STPHIB −1.0 · 10−10 · W 3.a1ch STA1CH 0.0 · 10−3 1.2 May 2009 Parameter Program Parameter Value Name NMOS PMOS VFB VFB −1. c NXP Semiconductors 2009 47 .0 · 10 −3 −1.5 λD LAMD 0.0 θ3D THE3D 0.6 k0D KOD 1.6 βacc BETACC −12 (2.0 · 10−3 mσdibl MSDIBL 1.0 2.0 ST .9 0.8 · 10−12 /tox ) · (W/Ldr ) ηβacc ETABETACC 1.φBD STPHIBD −1.4 0.0 m MEXP 2.0 · 10−3 VP VP 5.0 1.0 · 10−10 · W CGSO CGSO 3. drift-region length Ldr (m).2 0.0 0.0 φB PHIB 0.0 · 10−10 · W 3.0 · 10−6 1.0 · 10−3 σsf SSF 1. Level 2002.0 1.0 · 10−2 σdibl SDIBL 1.VFB STVFB 0.05 0.0 Cox COX (3.453 · 10−11 /tox ) · W · Lch (3.Unclassified Technical Note PR-TN-2005/00406 MOS Model 20.2 · 10 /tox ) · (W/Ldr ) (0.453 · 10−11 /tox ) · W · Ldr (3.6 1.05 0.0 0.0 1.0 m0 MO 1.

a2ch . a3dr V (ibvg). m0 . . T = Tmin . AC parameters: The extraction strategy for the AC parameters for an n-channel DMOS tran- sistor is outlined in Table 3. T = Tref gDS rel in saturation. σsf III (idvd). k0 I (idvg). . The optimisation is either performed on the absolute (abs) or relative (rel) deviation between the model and measurements. Tmax IB abs - 16 a1dr . in practice the parameters PHIBD. . ηRD = ηβacc 10 θ1acc I (idvg). . T = Tmin . . . it is more practical to split the parameters into several groups. a2dr .May 2009 MOS Model 20. the simultaneous determination of all miniset parameters is not advisable. . . all voltages and currents have to be multiplied by −1. ηβ III (idvd).maxidvg 2 φB . . ηβacc .maxidvg 4 θ1 .1 V 9 βacc . T = Tmin .1 V 8 β. all voltages and currents have to be multiplied by −1. Level 2002. T = Tref ID abs VSB > 0 13 a1ch . . a3ch V (ibvg). . CGSO. ηβ IV (idvdh). mσdibl II (subvt). RD IV (idvdh).1 · ID. . Tmax ID abs in saturation 5 θ3D . . Therefore. T = Tref IB abs - 17 ST .1 · ID. and CGDO are only important for the charge model. ηθ3 IV (idvdh). and STVFBD cannot be determined accurately from DC measurements. For p-channel DMOS transistors. The optimisation is either performed on the absolute (abs) or relative (rel) deviation between the model and measurements. T = Tref ID abs ID < 0. For p-channel DMOS transistors. VGS = VT + 3. . Next. VGS < VT + 3. DC parameters: The extraction strategy for the DC parameters for an n-channel DMOS tran- sistor is outlined in Table 2. and do not affect the DC model. where each parameter group can be determined using specific measurements. T = Tmin . . because the value of some parameters can be wrong due to correlation and suboptimization. . .1 · ID. θ3 . Furthermore. . Tmax ID abs in linear region.φB I (idvg).a1dr V (ibvg). . T = Tmin . COXD.maxidvg 3 ST . 48 c NXP Semiconductors 2009 . T = Tref ID rel ID < 0. . . STPHIBD. ηθ3D IV (idvdh). Tmax ID abs ID < 0. T = Tref gDS rel in saturation. . KOD. T = Tref IB abs - 15 ST . T = Tref ID abs - 11 θ2 III (idvd). . including self- heating.a1ch V (ibvg). they have to be extracted from C-V characteristics. for both DC and AC measurements. the parameter extraction strategy is described. σdibl . . and as a consequence they are determined from C-V measurements. Tmax ID abs in saturation 7 α. .2 Unclassified Technical Note PR-TN-2005/00406 Parameters COX. . VP . . . Tmax ID abs in saturation 6 β. T = Tmin . Step Optimised Measurement Fitted abs/ Specific Parameters on rel Conditions 1 φB . VFBD. In general. T = Tmin . T = Tref ID abs VSB > 0 12 λD I (idvg). Tmax IB abs - Table 2: DC-parameter extraction strategy for an n-channel DMOS transistor.

versus mask width W .φBD . 5. the sensitivities of the parameters to the width can be found. . respectively. Tmax CGG abs - Table 3: AC-parameter extraction strategy for an n-channel DMOS transistor. φBD . . Here.2 May 2009 Step Optimised Measurement Fitted abs/ Specific Parameters on rel Conditions 1 Cox . . 2.3.2. Level 2002. a three-step procedure is recommended: 1. T = Tmin . the width and length sensitivity coefficients are optimised by fitting the result of the scaling rules and current equations to the measured currents of all devices simultaneously. as explained in Section 5. .2. To accomplish this. there is no length scaling scheme present in MOS Model 20. VFBD VI (Cvg).3 Extraction of Maxiset Parameters Since in most high-voltage processes the LDMOS transistor has only one gate length L. the AC. As an LDMOS transistor may have different mask widths for the source and the drain. see Section 3. CoxD . transistors of different widths have to be measured. k0D . ST .3. Thus. Using these measurements. geometry scaling consists of only width scaling. ST . different values of ∆W and ∆WD can also be obtained. and can be separated into a width scaling scheme for the channel region and a width scaling scheme for the drift region.2. it is possible to calculate a parameter set for a process. finally.VFBD VI (Cvg). determine minisets (φB . the width sensitivity coefficients are optimised by fitting the appropriate geometry scaling rules to these miniset parameters. When using the physical scaling relations of Section 3.VFB . β. c NXP Semiconductors 2009 49 . and the noise model.) including temperature scaling for all measured devices. . including self- heating. k0 . ∆W and ∆WD can be determined from the extrapolated zero-crossing in the gain factors β and βacc (or 1/RD ). 3. T = Tref Cig abs - 2 ST . since it affects the DC. For the determination of a geometry-scaled parameter set. . . given the parameter set of typical transistors of this process. The most important part of the geometry scaling scheme is the determination of ∆W and ∆WD .Unclassified Technical Note PR-TN-2005/00406 MOS Model 20.

and bulk terminals respectively.S.dT) <parameters> p-channel geometrical model : mpt i (D.G.5). source.B.S.G. G.1 Syntax Model without self-heating: n-channel geometrical model : mn i (D.G.B) <parameters> p-channel electrical model : mpe i (D.May 2009 MOS Model 20. gate. Level 2002.S.S. For the model including self-heating. and B are the drain. 50 c NXP Semiconductors 2009 .S.B. the extra terminal dT is required (see Section 4.B) <parameters> n-channel electrical model : mne i (D.B) <parameters> Model including self-heating: n-channel geometrical model : mnt i (D.G.B) <parameters> p-channel geometrical model : mp i (D.G.G.S.G. S.dT) <parameters> where: i : occurrence indicator <parameters> : list of model parameters D.G.B.B.S.dT) <parameters> n-channel electrical model : mnet i (D.2 Unclassified Technical Note PR-TN-2005/00406 6 Pstar-Specific Items 6.dT) <parameters> p-channel electrical model : mpet i (D.S.

2 DC Operating Point Output The DC operating point output facility gives information on the state of a device at its operation point. Level 2002.Unclassified Technical Note PR-TN-2005/00406 MOS Model 20. The objective of the DC operating point facility is twofold: • Calculate small-signal equivalent circuit element values • Open a window on the internal bias conditions of the device and its basic capabilities. which are then also given (e. Besides terminal currents and voltages. No. Here. In some cases. the magnitudes of linearized internal elements are given. fT ). Cxy indicates the derivative of the charge Q at terminal x to the voltage at terminal y.g. The printed items are described below. when all other terminals remain constant. Symbol Program Units Description Name 0 IDS IDS A Drain current. meaningful quantities can be derived.2 May 2009 6. excluding avalanche current 1 IAVL IAVL A Substrate current due to weak avalanche 2 VDS VDS V Drain-source voltage 3 VGS VGS V Gate-source voltage 4 VSB VSB V Source-bulk voltage 5 VT0 VTO V Zero-bias threshold voltage of the channel region (after p temperature scaling): VT0 = VFBT + geometric and φB T + k0 · φB T 6 VTS VTS V Threshold voltage including p back-bias effects: VTS = VFBT + φB T + k0 · VSBt 7 VTH VTH V Threshold voltage including back-bias p and drain-bias effects: VTH = VFBT + φB T + k0 · VSBt − ∆VG 8 VGT VGT V Effective gate drive voltage including back-bias and drain voltage effects: VGT = Vinvex0 9 VTOD VTOD V Threshold voltage of the p drift region: VTOD = VFBD T − φBD T − k0D · φBD T 10 VDiSeff VDISEFF V Effective internal drain to source voltage at actual bias 11 VDiSsateff VDISSAT V Saturation voltage of the channel region at actual bias 12 VDDisat VDDISAT V Saturation voltage of the drift region at actual bias 13 gm GM A/V Transconductance (assuming that VDS > 0): gm = ∂IDS /∂VGS 14 gmb GMB A/V Substrate-transconductance (assuming VDS > 0): gmb = ∂IDS /∂VBS 15 gds GDS A/V Output conductance: gds = ∂IDS /∂VDS c NXP Semiconductors 2009 51 .

Transistor gain: u = gm /gds 35 Rout ROUT Ω Small-signal output resistance: Rout = 1 /gds 36 VEarly VEARLY V Equivalent Early voltage: VEarly = |IDS | /gds 37 βeff BEFF A/V2 2 Gain factor: βeff = 2 · |IDS | /Vinv ex0 38 fT FUG Hz Unity gain frequency at actual bias: fT = gm 2 · π · (CGG + CGSO + CGDO ) 39 gmch GMMOS A/V Transconductance of the channel region p √ 40 SVGth SQRTSFW V/ Hz Input-referred p p RMS thermal noise voltage density: SVGth = SDth /gmch p √ 41 SVGfl SQRTSFF V/ Hz Input-referred p RMS p flicker noise voltage density at 1 kHz: SVGfl = SDfl [1kHz] /gmch 42 fknee FKNEE Hz Cross-over frequency above which thermal noise is dominant: fknee = 1Hz · SDfl [1Hz] /SDth 52 c NXP Semiconductors 2009 . Level 2002.2 Unclassified Technical Note PR-TN-2005/00406 No.May 2009 MOS Model 20. Symbol Program Unit Description Name 16 CDD CDD F CDD = ∂QD /∂VDS 17 CDG CDG F CDG = −∂QD /∂VGS 18 CDS CDS F CDS = CDD − CDG − CDB 19 CDB CDB F CDB = ∂QD /∂VSB 20 CGD CGD F CGD = −∂QG /∂VDS 21 CGG CGG F CGG = ∂QG /∂VGS 22 CGS CGS F CGS = CGG − CGD − CGB 23 CGB CGB F CGB = ∂QG /∂VSB 24 CSD CSD F CSD = −∂QS /∂VDS 25 CSG CSG F CSG = −∂QS /∂VGS 26 CSS CSS F CSS = CSG + CSD + CSB 27 CSB CSB F CSB = ∂QS /∂VSB 28 CBD CBD F CBD = −∂QB /∂VDS 29 CBG CBG F CBG = −∂QB /∂VGS 30 CBS CBS F CBS = CBB − CBD − CBG 31 CBB CBB F CBB = −∂QB /∂VSB 32 WE WEFF m Effective channel region width for geometrical model 33 WED WDEFF m Effective drift region width for geometrical model 34 u U .

Thesis. pp. Solid-State Electronics. 2001.T. pp.T. IEEE Trans. December 2002 (see http://www.D. SISPAD. Modelling of High-Voltage SOI-LDMOS Transistors including Self-Heating. Proc. and D. [6] D. 703–708.C. J. 246–249.J. D’ Halleweyn. Vol. pp. Aarts. Dutton. MOS Model 11. van Langevelde. An Explicit Surface-Potential Based MOSFET Model for Circuit Simulation. van Langevelde. 2005. A Charge-Oriented Model for MOS Transistor Capaci- tances. Proc.com/models/). 2002. [7] A. 5. [4] R. Klaassen.E. van Langevelde. A Robust and Physically Based Compact SOI- LDMOS Model. 409–418. 5. 455–458. Level 2002. Aarts. level 1101.C.J. No. Klaassen. 13. Philips Research Unclassified Report. Aarts and R. Vol. University of Southampton. 44. [5] A. No. [8] A.Unclassified Technical Note PR-TN-2005/00406 MOS Model 20. Solid-State Electronics.T. Electron Devices.W. A Surface-Potential-Based High- Voltage Compact LDMOS Transistor Model.B. Ward and R.C. 52. A.M. Scholten. Kloosterman. [3] R. ESSDERC. M. Ph. pp. 999–1007. 2001. Modelling and Characterisation of Silicon-On-Insulator Lateral Dou- ble Diffused MOSFETs for Analogue Circuit Simulation. van Langevelde and F.M. and W. c NXP Semiconductors 2009 53 . Springer. pp.nxp. Vol.com/models/ [2] N. and R. N. 1978. NL-UR 2002/802. D’Halleweyn.nxp. J.2 May 2009 References [1] http://www.J. Swanenberg. 2000.

Level 2002.2 Unclassified Technical Note PR-TN-2005/00406 54 c NXP Semiconductors 2009 .May 2009 MOS Model 20.

2) (x2·m + y2·m )1/(2·m) c NXP Semiconductors 2009 55 .1) 2 The hypm function: x·y hypm [x.2 May 2009 A Auxiliary Functions The hyp function: 1  p  hyp [x.Unclassified Technical Note PR-TN-2005/00406 MOS Model 20. m] = (A. y. Level 2002. ǫ] = · x + x 2 + 4 · ǫ2 (A.