EE5703 : VLSI DESIGN LAB

Sequence Detector(Moore type)

A sequence detector accepts as input a string of bits: either 0 or 1. Its output
goes to 1 when a target sequence has been detected. A finite state machine can
be divided into two types :Mealy and Moore . A Mealy machine is a finite-state
machine whose output values are determined both by its current state and the
current inputs. This is in contrast to a Moore machine, whose output values are
determined solely by its current state.
In this assignment we are implementing Moore type fsm with non overlapping
sequence detection .The sequence to be detected is 10100101.
State machine diagram is given below :

. parameter S0 = 0. nstate. reset. reset. S5 = 5.Verilog code : module pattern_moore (clk. S2 = 2. S4 = 4. always @(posedge clk) begin if (reset) begin cstate <= S0. S6 = 6. reg out. S7 = 7. S8 = 8. S3 = 3. out ). S1 = 1. output out. input in. input clk. // Registers to hold current and next state reg [3:0]cstate. in.

end else begin cstate <= nstate. end . case (cstate) S0: begin if (in == 'b1) begin nstate = S1. end else begin nstate = S0. end end S1: begin if (in == 'b0) begin nstate = S2. end end always @(cstate or in) begin nstate = cstate. end else begin nstate = S0.

end else begin nstate = S3. end end S3: begin if (in == 'b0) begin nstate = S4. end S2: begin if (in == 'b1) begin nstate = S3. end . end end S4: begin if (in == 'b0) begin nstate = S5. end else begin nstate = S0. end else begin nstate = S1.

end else begin nstate = S1. end S5: begin if (in == 'b1) begin nstate = S6. end else begin nstate = S0. end else begin nstate = S0. end end S6: begin if (in == 'b0) begin nstate = S7. . end end S7: begin if (in == 'b1) begin nstate = S8.

end end default: begin nstate = S0. end else begin nstate = S0. end // // always @ (cstate) . end end S8: begin if (in == 'b1) begin nstate = S1. end endcase // case (cstate) end // always @ (cstate or in) always @ (cstate) begin out = (cstate == S8).

out(out)). reg clk. // Instantiate module to be tested pattern_moore dut(. wire out. clk = 0.endmodule // fsm Verilog code for testbench : module pattern_moore_tb.in(in). out = %b".clk(clk). inputs). in. initial begin $readmemb("seqin. integer i. always #5 clk = ~clk. parameter NUMINPUTS = 100. reg inputs[0:NUMINPUTS-1]. . .reset(reset). . "in = %b.txt". . in. out). $monitor($time. reset.

@ (posedge clk). reset = 1. end $finish. for (i=0. // Simple way to wait until next clock edge: @ (posedge clk). i<NUMINPUTS. end endmodule // pattern_tb Results : . i=i+1) begin in = inputs[i]. #10 reset = 0.

A Mealy machine is a finite-state machine whose output values are determined both by its current state and the current inputs. . This is in contrast to a Moore machine.Exercise : In the example sequence detector to detect 101 sequence it was Mealy fsm. whose output values are determined solely by its current state. In Moore we have one extra state which has its output value set high to indicate that he pattern is detected .