EE16M044

Apte Priya Narayanrao

EE5703 : VLSI DESIGN LAB
Sequence Detector(Moore type)

A sequence detector accepts as input a string of bits: either 0 or
1. Its output goes to 1 when a target sequence has been
detected. A finite state machine can be divided into two types
:Mealy and Moore . A Mealy machine is a finite-state machine
whose output values are determined both by its current state and
the current inputs. This is in contrast to a Moore machine, whose
output values are determined solely by its current state.
In this assignment we are implementing Moore type fsm with non
overlapping sequence detection .The sequence to be detected is
10100101.
State machine diagram is given below :

input in. reg out.Verilog code : module pattern_moore (clk. reset. S2 = 2. input clk. in. out ). output out. . parameter S0 = 0. reset. S1 = 1.

always @(posedge clk) begin if (reset) begin cstate <= S0. S8 = 8. end . end else begin cstate <= nstate. nstate. end end always @(cstate or in) begin nstate = cstate. S7 = 7. // Registers to hold current and next state reg [3:0]cstate. S4 = 4. S6 = 6. S3 = 3. case (cstate) S0: begin if (in == 'b1) begin nstate = S1. S5 = 5.

end end S1: begin if (in == 'b0) begin nstate = S2. else begin nstate = S0. end else begin . end end S2: begin if (in == 'b1) begin nstate = S3. end end S3: begin if (in == 'b0) begin nstate = S4. end else begin nstate = S0. end else begin nstate = S0.

end else begin nstate = S0. end else begin nstate = S1. end end S5: begin if (in == 'b1) begin nstate = S6. nstate = S1. . end end S4: begin if (in == 'b0) begin nstate = S5. end else begin nstate = S3. end end S6: begin if (in == 'b0) begin nstate = S7.

end endcase // case (cstate) end // always @ (cstate or in) always @ (cstate) begin . end else begin nstate = S0. end end default: begin nstate = S0. end end S7: begin if (in == 'b1) begin nstate = S8. end else begin nstate = S0. end end S8: begin if (in == 'b1) begin nstate = S1.

reg inputs[0:NUMINPUTS-1]. initial begin .out(out)). wire out. integer i. parameter NUMINPUTS = 100. . reg clk. . end // // always @ (cstate) endmodule // fsm Verilog code for testbench : module pattern_moore_tb.in(in).clk(clk). . in. reset.reset(reset). out = (cstate == S8). always #5 clk = ~clk. // Instantiate module to be tested pattern_moore dut(.

@ (posedge clk). $readmemb("seqin. end $finish. i=i+1) begin in = inputs[i]. i<NUMINPUTS. $monitor($time. end endmodule // pattern_tb Results : .txt". out = %b". "in = %b. #10 reset = 0. // Simple way to wait until next clock edge: @ (posedge clk). out). clk = 0. in. reset = 1. inputs). for (i=0.

In Moore we have one extra state which has its output value set high to indicate that he pattern is detected . This is in contrast to a Moore machine. A Mealy machine is a finite-state machine whose output values are determined both by its current state and the current inputs.Exercise : In the example sequence detector to detect 101 sequence it was Mealy fsm. . whose output values are determined solely by its current state.