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EE Dept, IIT Bombay
EE 712 Embedded System Design
Spring 2010 / Semester-End Examination
Thursday, 20.April.2010, 0930 -- 1230
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Note: Answer all the SEVEN questions. Marks: 8 + 8 + 6 + 8 + 6 + 6 + 8 = 50.

Q1 A) Show the interconnection and the best arrangement for dc termination (including the
resistance values for
(i) Half-duplex RS-485 communication between two systems,
(ii) Ring interconnection of 3 systems using simplex RS-485 interfacing.
B) An asynchronous serial communication uses transmission clock of 1 MHz, 1 start bit, 16
data bits, 1 parity, 3 stop bits. Find
(i) Data bandwidth of transmission,
(ii) Lowest and highest clock rate at the receiver to avoid data error.
C) In synchronous serial communication,
(i) Why are the different edges of the clock used for transmitting and receiving the data?
(ii) Why can the data bandwidth be higher than asynchronous communication using the same
clock rate?
D) Give the circuit of a polarity insensitive receiver circuit for current loop serial data
transmission.
E) Compare the bandwidth and noise performance of (i) parallel-pair of wires, (ii) twisted-pair
of wires for balanced differential data transmission.
[2+2+2+1+1 = 8 marks]

Q2 A microcontroller has following 8-bit ports with individually programmable I/O pins: A --
open-drain, B and C -- internal passive pull-up, and D -- tri-stated. The microcontroller is to be
used in a system consisting of the following peripheral devices
(i) Two status indicator LEDs (L1, L2),
(ii) 16 keys (K1, K2, .., K16) with the possibility of 0/1/2 key presses, and 3 keys (K17, K18,
K19) with the possibility of any combination of key presses,
(iv) Two 8-bit ADCs (ADC1, ADC2), each having internal latch and 8-bit parallel tri-stated
outputs and two control inputs: Start, Output_Enable,
(v) Two 6-bit DAC (DAC1, DAC2), each having internal latch and 6-bit parallel inputs and
one control input: Latch_Enable.
The two ADC's convert analog inputs simultaneously and periodically at a rate set by the
internal programmable timer. The two DAC outputs are to be given data periodically but at
different rates. All the keys are software debounced.

(Page 1 of 4 pages)

i) Conditional execution and flag setting in instructions ii) Availability of a barrel shifter in data processing instructions. giving the values and power rating of the resistors. (Check by an example to show that you have understood the algorithm). Draw an interconnection of the peripheral devices and the microcontroller. B) Briefly comment on the use of sample-and-hold with (i) dual-slope converter. Give first priority to speed of operation and second priority to saving pins for further design expansion. (iv) appropriate number of resistors and diodes. B) A background routine written to scan a 4x4 keyboard as shown below returns valid key presses in an 8-bit format. Show the circuit for driving the relay using (i) 12 V supply SB1. We want to convert this 8-bit code to a 4-bit key number (as marked in the diagram above) by the following algorithm (assuming the 8-bit code is in R0): Initialize the key number to 0. Next. [1 + 1 +2 + 2 = 6 marks] Q4 A) Illustrate with examples the advantages of the following features of the ARM architecture. Show the connection of 5x7 matrix of pixels. (iii) one transistor (NPN or PNP). as shown in the diagram. Shift R0 right 4 times by 1-bit. (ii) successive approximation converter. The input 8-bit code is to be found in the 8 LSB of R0 and this value should be replaced by the key number on return. C) Briefly explain as to how the use of a sigma-delta converter relaxes the requirement of an anti-aliasing filter. with one of the best possible assignment of port pins. using special features of the ARM architecture as much as possible. [8 marks] Q3. C0 C1 C2 C3 R0 0 1 2 3 R1 4 5 6 7 R2 8 9 10 11 R3 12 13 14 15 Example data for key 10 (row R2. shift R0 right 4 times by 1-bit. D) A 6 V relay has coil resistance of 500 ohm. (ii) open-drain output pin of a microcontroller powered by 5 V supply SB2. whose position shows the row and the lower 4 bits have exactly one zero. Show the circuit. Write a subroutine in ARM assembly language for implementing the above. adding 4 to the key number till a 0 emerges. every time adding 1 to the key number till a 0 emerges. A) An LCD controller has 4 backplanes. whose position shows the column of the pressed key. column C2 R3 R2 R1 R0 C3 C2 C1 C0 1 0 1 1 1 0 1 1 The upper 4 bits have exactly one zero. Any other (Page 2 of 4 pages) .

Similarly. Show state diagrams for the talker and listener to implement this protocol. The talker places data on the bus and asserts RQS to be TRUE. The talker now waits for ACK to become TRUE. The listener on seeing RQS become FALSE. P0 and P1 are high priority. TheTalker uses the control signal RQS (Request to Send) to indicate that valid data is available on the bus. it checks if the ’rcv’ signal is TRUE. processes are scheduled from the low priority queue. It now waits for RQS to become FALSE. if modified. The Listener uses the signal ACK (Acknowledge) to indicate that it has accepted previous data and is ready for more. the listener receives an internal ’rcv’ signal from the consumer of data to start receiving data from the bus. Now we are at the initial condition and transfer of next word on the bus can follow the same procedure. When the internal ‘send’ signal becomes TRUE. least slack time first priority is used. [2+6 = 8 marks] Q5 A scheduler maintains two ready queues. When the Talker sees ACK as TRUE. (Page 3 of 4 pages) . The Talker receives an internal signal ‘snd’ from the data generator to indicate that data is waiting to be sent. Only if the high priority queue is empty. There has to be a unique test in each state which returns a binary answer. Assume that state transitions are event driven and the Talker state machine is invoked whenever there is an event on snd or ACK. register. while the rest are low priority processes. so they can run in that slot itself. ACK. makes ACK FALSE. If the high priority queue has any entries. \Show the state list. tests and actions for both state machines. while the listener state machine is invoked whenever there is an event on rcv or on RQS. it latches the data and and asserts ACK as TRUE. snd and rcv FALSE. The following protocol is used: Initially. it makes RQS FALSE. A TRUE signal on RQS makes the internal ‘send’ signal FALSE. The following table gives the arrival time. if selected. [6 marks] Q6 We want to implement an asynchronous finite state machine to implement the data transfer between a ‘Talker’ and a ‘Listener’ connected by a data bus and 2 control signals. For scheduling from either queue. Assume that the stack- pointer points to a pre-decrement post-increment type stack. should be saved to and restored from the stack. Ready to run processes are inserted in the appropriate ready queue before scheduling decisions are taken. justifying why a process is chosen to run at that time. processes are scheduled from this queue. When ‘rcv’ is TRUE. total run time and deadlines for a few processes in units of T. till all processes are over. Scheduling takes places at the beginning of each time slot of duration T. one for high priority processes and the other for low priority ones. both Talker and Listener are in their idle states with RQS. When the listener sees RQS become TRUE. Priority High Low Process P0 P1 P2 P3 P4 Ready to run at 4 1 0 3 6 Total Run Time 3 5 3 2 1 Deadline 11 15 16 12 10 Show the detailed scheduling of these processes at each time slot (beginning at 0).

SR : (Status reg to reg). SUBC RSB (Reverse Subtract). R5 unchanged STR R2. then R5=R5+8 LDR R2. UMLAL (unsigned multiply accumulate). [R5. load R2 from address=updated R5 (Page 4 of 4 pages) .Rd=Rn AND NOT OP2 ADD. STM (Load Store Multiple). discard result) Multiply: 32bit MUL{Con}{S} Rd. SUB. ORR. ADC.}{S} Rd. C) Priority inversion and prevention through priority inheritance. UMULL (unsigned mult). discard result) CMN (Add to set flags. [R5] # 8 : Store R2 at address R5. [2+2+2+2 = 8 marks] ---------------------------------------. where status reg SR is either CPSR or SPSR. SMLAL (signed multiply accumulate). D) Architecture of Real Time Linux.PAPER ENDS ----------------------------------------------- REFERENCE DATA ARM Data Processing Instructions: Instr{Cond. Rm. MVN (move not). RSC (Rev. [R5. Examples: LDR R2. STR with and without pointer update LDM.# 8] : Load R2 from address R5+8. Rn : (Rd=Rn+Rm*Rs) Long Multiply: SMULL (signed mult). {Rn. OR or XOR) BIC (Bit Clear.} OP2: OP2 through shifter MOV (move). Load-Store Instructions: LDR. Rm. [6 marks] Q7 Explain the following briefly: A) The need for and the use of mutual exclusion semaphores for shared resources. AND. Status Register Access: MRS{Con} Rd. #-1]! : R5=R5-1. Subtr with carry) TST (AND to set flags. Rd : (reg to status reg). B) User managed threads and Kernel threads. Rs : (Rd=Rm*Rs) MLA{Con}{S} Rd. discard result) TEQ(EOR to set flags. Rs. MRS{Con} SR. discard result) CMP (Subtract to set flags. EOR: (AND.