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EE Dept, IIT Bombay
EE 712 Embedded System Design
Spring 2012 / Mid-semester Examination
Tuesday, 21.Feb.2012, 17:30 -- 19:30
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Note: Answer all the FOUR questions. Marks: 10 + 10 + 10 + 20 = 50.

Q-1. (A) Why should we normally use either hardware or software debouncing for
interfacing keys as input devices ? Give the hardware debouncing circuit, with
typical component values, for interfacing a key to a CMOS inverting gate. Show
the input and output waveforms for both the transitions.

(B) An external memory is to be interfaced to I/O port of a microcontroller.
Comment on the suitability of using a port with (i) open drain, (ii) internal
passive pull-up, and (iii) tri-stated outputs.
[5+5 = 10 marks]

Q-2. A microcontroller has two 8-pin I/O ports: port A with outputs having internal
passive pull-ups, port B with open collector outputs.

The microcontroller is to be connected to (i) 4 LED's, (ii) 4 keys with direct
interfacing and software debouncing, and (iii) 12 keys with scanned interfacing
and software debouncing.

Show the most appropriate circuit for connecting the LED's and keys to the port
pins.

If the LED's are available either as common anode or common cathode, which
type should be used?
[10 marks]

Q-3 A) Show the circuit for driving an EM relay using an open drain output (max
sink = 1 mA), BJT, R, diodes. The relay and microcontroller both are operated
with 5 V. The relay has coil resistance of 100 Ω. Find the βmin of the transistor.

B) Show the above circuit using an optocoupler. What is the advantage of using
an optocoupler in the relay drive circuit?

C) Give an appropriate external circuit for interfacing the 8 open drain output
pins of a microcontroller to an 8-segment LCD with a single backplane.

D) A LCD with 5x5 dot array is to be interfaced to a LCD driver with 4
backplane lines. How many frontplane lines are needed? Show a suitable
connection for the dots in the display to the frontplane and backplane lines.
[3+2+3+2 = 10 marks]

C) An ARM processor is running in the “Thumb” state when an IRQ interrupt occurs.Q-4 Explain the following with illustrative examples for the ARM architecture: A) Describe how the subroutine call/return mechanism works in the ARM instruction set. The operational part of the handler is also written in Thumb instruction set. Assume x and y are available in registers R0 and R1. E) Write efficient ARM assembly code for the following: if(x > 0) z = x + 8 * y. B) Describe the sequence of events which take place after an exception occurs.x. Return address must be saved when necessary in a pre-decrement. Explain how the various changeovers of instruction set will occur in this case. whereas z has to be stored in the memory at the address contained in R2. post-increment kind of stack. How does the interrupt handler return control to the program which was running when the interrupt occurred? Your description should indicate which of these actions are automatically taken by the processor and which have to be taken by the programmer. as we enter the interrupt service routine and when we return from it. else z = 4 * y . (x. (No pseudo instructions are to be used. D) What is a literal pool? What is the advantage of using PC relative addressing for loading a constant from a literal pool? Illustrate how a constant may be loaded from the literal pool by an assembly language example. [4+4+4+4 = 20 marks] PAPER ENDS . y and z are signed 32-bit integers). Use the example of a main routine calling a subroutine. which then calls another subroutine.

[R5. MRS{Con} SR. UMULL (unsigned mult). discard result) TEQ(EOR to set flags. REFERENCE DATA ARM Data Processing Instructions Instr{Cond. ORR. EOR: (AND. load R2 from address=updated R5 LDM. Rm. STR with and without pointer update Examples: LDR R2. discard result) CMN (Add to set flags. Load-Store Instructions: LDR. STM (Load Store Multiple). [R5] # 8 : Store R2 at address R5. Rd : (reg to status reg). Rs : (Rd=Rm*Rs) MLA{Con}{S} Rd. AND. Rn : (Rd=Rn+Rm*Rs) Long Multiply: SMULL (signed mult). Status Register Access: MRS{Con} Rd. In case of immediate operands. RSC (Rev.}{S} Rd. SUBC RSB (Reverse Subtract). {Rn. discard result) Multiply: 32bit MUL{Con}{S} Rd. A register operand may be shifted logically or arithmetically or rotated up to 31 positions. ADC. #-1]! : R5=R5-1. then R5=R5+8 LDR R2.# 8] : Load R2 from address R5+8 STR R2. MOV (move). UM- LAL (unsigned multiply accumulate). where status reg SR is either CPSR or SPSR. OR or XOR) BIC (Bit Clear. Rm. an 8bit immediate may be rotated right an even number of positions. SMLAL (signed multiply accumulate). Subtr with carry) TST (AND to set flags. .Rd=Rn AND NOT OP2 ADD. [R5. Rs. MVN (move not). discard result) CMP (Subtract to set flags.} OP2: OP2 through shifter The Barrel Shifter can be used with the last operand. SR : (Status reg to reg). SUB.