Proceedings of the 2010 IEEE Students’ Technology Symposium

3-4 April 2010, IIT Kharagpur

Low Voltage Low Power Pipelined ADC for Video
Hameed Zohaib Samad #1, Patri Sriharirao #2, K. Sarangam #3
#Department of Electronics and Communication Engineering
National Institute of Technology Warangal, India

Abstract— In today’s world application of battery powered λ (Channel length Modulation) = 0
analog and mixed mode electronic device requires designing KP (Transconductance) = 20µA/V2
analog circuit to operate at low voltage levels. There are many µ (Mobility) = 600cm2/V.s
issues which are involved in implementing low voltage circuits Body Effect = 0
such as reduced noise immunity, greater delay and poor
Surface Potential = 0.6V
linearity. There is a need to use certain MOSFET techniques so
that the MOSFET can be used even in sub-threshold region Vth (Threshold voltage) = 0V
without any significant change in its performance. Certain
techniques have been put forward corresponding to low voltage
analog circuits using CMOS Technology to be used in variety of
applications. Accordingly we propose to design a 10 bits
30Msample/s CMOS Analog to Digital Converter (ADC) using a
1.5-bits/stage pipeline architecture for high speed signal
processing to be used in video related applications

With the growing demand for low power mixed signal
integrated circuits for portable or non-portable high
performance systems, analog circuit designers are challenged
with making analog circuit blocks with lower power
consumption with little or no performance degradation. A
possible solution to get higher dc voltage on chip is voltage
multiplication. This technique is noisy and is not compatible
with sensitive analog circuits. Circuit operation at reduced
voltage is a common practice adopted to reduce power Fig. 1. Current Mirror Circuit using N-type enhancement MOSFET
consumption. However, the circuit performance degrades and
one gets low circuit bandwidth and low voltage swings at low Fig.1 shows a current mirror circuit in which a voltage of
voltages. Scaling down the threshold voltage of MOSFETs 3V ensures the current mirror operation to take place
compensates for this performance loss to some degree, but this smoothly. The minimum required input voltage so that
result in increased static power dissipation [1]. current mirroring operation takes place can be obtained from
Low voltage analog circuit design techniques differ the following equations.
considerably from those of high voltage analog circuit design. ID = [Kn (VGS – VTn)2 (1+ λVDS)] / 2
This generates a need for adaptation of alternative design
techniques to suit the low voltage environments. This paper is For the above circuit shown in Fig.1
aimed at providing a comprehensive treatment of all possible VDS = VGS = VTn + 2Iref / Kn 1 λVDS
Low voltage design techniques prevalent today for analog Since λ 0 and VTn = 0 and Kn= 20µA/V2
circuits. VDS = 2.236 V
For the current to be mirrored, a voltage greater than
II. CRITICAL ISSUES 2.236V has to be applied where in Fig.1 VDS2 = 3V causes 50
There are certain issues involved when a CMOS circuit is µA to appear at the output.
made to work in sub threshold conditions. This could be Considering a case where VDS2 < 2V
explained easily by considering the following analysis done in
Pspice by taking an example of Current Mirror Circuit. Some
of the parameters as defined in Pspice are as follows

TE01025 978-1-4244-5974-2/10/$26.00 © 2010 IEEE 161

For example. The current flowing from the The solution to the threshold limitation must remove or source to drain is modulated by the reverse bias on the bulk- circumvent the requirement to provide at least Vt volts to turn channel junction.6 to 0. 2. at low voltages. component. 3 shows a Bulk Driven MOSFET with a forward bias There is a need to employ certain low voltage analog circuit applied to the bulk-source terminal. However. Similarly. The Lateral BJT: between the bulk and the source. Bulk-Driven MOSFET with forward bias. METHODS OF ACHIEVING LOW VOLTAGE ANALOG D. E. For high gain one needs higher output impedance and short channel MOSFETs cannot provide high B. The drain is connected normally and the signal is applied A. Fig. there are ways to use existing technology that provide the desired results on a reliable basis. One possible solution is the lateral BJT. Proceedings of the 2010 IEEE Students’ Technology Symposium 3-4 April 2010. The result is a junction field-effect transistor on the MOSFET. A positive bias of 555mV design techniques which assists in low voltage operation of will reduce the threshold voltage and will allow the circuit to analog circuits without affecting the performance. source voltage for current flow result. Although.7V which do not provide that much advantage over the MOSFET. The Channel JFET: CIRCUITS The most significant solution to the threshold voltage Some of the methods of achieving low voltage operation in limitation is the channel JFET. an additional advantage of the lateral BJT is that it Owing to channel length modulation because of shrinking has a low value of VCE(sat) which is also important for low devices the output impedance of the MOSFET is also voltage analog circuits [2]. possibly improve the output swing of the conventional the value of VDS(sat) is extremely small. Subthreshold Operation: gain structure. the MOSFET conducts To overcome the limited input common mode voltage and currents at voltages less than the threshold voltage.2 one can easily see that to obtain perfect current mirroring operation a minimum amount of voltage is necessary to be applied which is dependent upon the magnitude of the current. Effect of VDS on current mirroring From Fig. Cascode Technique: However. The primary cascode. In this realm of operation. IIT Kharagpur The real solutions to the threshold voltage problem come from an intimate knowledge of the technology. The main disadvantage of subthreshold operation is small currents and advantage of the folded structure is the freedom of choosing very low frequency response. becoming smaller. Thus one can infer that for higher value of current more amount of voltage is required to be applied hence making it impossible for higher current to work Fig 3. The gate-source potential is analog circuits are as follows taken to a dc voltage that is sufficient to turn the MOSFET on. Forward-Biased Bulk-Source: upper MOS device in a way that has less effect on the output TE01025 162 . the lateral BJT requires turn on voltages of 0. be used in Low Voltage applications III. the technology cannot be changed. Fig. MOSFET. Consequently a high- This solution has the added advantage of much less 1/f noise input impedance depletion device that requires no dc bulk- because current flow is in the bulk of the material. In addition. a forward bias on this junction will cause the threshold voltage to decrease [3]. If the conventional cascode structure is changed to bias the C. it is well known that a reverse bias on the well-source junction will cause the threshold voltage to increase. There does appear to be an the bias voltage levels since it folds the two opposite type important area in which subthreshold operation may provide devices instead of putting one device on the top of another an impact in low voltage and low power circuits. with the bulk as the signal input (gate). The use of cascode structure increases the gain A second solution is subthreshold operation of the but it decreases the output swing at the same time. a general principle that has been consistent throughout the history of electronics. a structure called “folded cascode” is used.

The The values are usually stored electronically in binary form. an ADC with a resolution of 10 circuits. Characteristic of various Techniques for CMOS Design E.5LSB Depending on the application of the circuit one should choose F. In consequence.e. In the above example of a 10-bit ADC. the output impedance of the connection may be Hence to serve a wide range of applications resolution of 1mV increased with sufficient output swing at low supply voltage is chosen. This composite present in any analog-to-digital conversion. so purpose of this circuit is to hold the analog value steady for a the resolution is usually expressed in bits. the complementary input pairs have to be loaded with folded To deliver 1mV resolution a reference voltage of around cascode instead of current mirrors 2V-3V will require 10 bits. Reference Voltage and Number of Bits maintain the rail-to-rail capabilities of the input stage.1%. that can be implemented in a variety of applications. Proceedings of the 2010 IEEE Students’ Technology Symposium 3-4 April 2010. System Energy Requirements Technique Available Supply Voltage Power A figure of merit for ADC‘s which takes into account the BW Requirement Consumption sampling rate. In most power of two. or about known technique for realization of rail-rail input stage is to 0. Integral Non-Linearity Table 1 clearly shows that there are tradeoffs involved in most of the techniques used for Low Voltage Operation Practical value of integral non-linearity should be less than between available bandwidth and power consumption [4]. an compels the use of rail-rail input and output stages. Sample and Hold Circuit The resolution of the converter indicates the number of A Sample and Hold Circuit is one of the simplest ADC discrete values it can produce over the range of analog values. This drawback can be removed by using resolution is decided accordingly. B.5LSB Some of the specifications of ADC which must be taken care of before choosing ADC architecture are as follows V. ADC DESIGNING FOR LOW VOLTAGE APPLICATIONS than 0. Hence depending upon the transconductance varies by a factor of two over the common reference voltage the number of bits can be chosen and the mode input range. ADC ARCHITECTURE FOR LOW VOLTAGE APPLICATIONS A. the short time while the converter or other following system number of discrete values available. depending on the application. place complimentary differential pairs in parallel. Resolution A. a capacitor is used to store the analog voltage and an bits can encode an analog input to one in 1024 different levels. unsigned integer) or from -512 to 511 (i. A linear type of ADC structure can be obtained by A survey of recently reported ADC was done to find out the using a sample and hold circuit. Quantization error is degeneration to give high output gains. At low voltage operation the dynamic range is at premium. Accuracy connection provides high output impedance due to source An ADC has several sources of errors. The values can represent the ranges from 0 disconnect the capacitor from the analog input. value). This can be easily shown by A major drawback with the rail-to-rail input stage is that its (2V/1024) is almost equal to 1mV. Table 1. In order to C. is promising in low voltage low revealed when digitizing a time-variant signal (not a constant power op amp design. is usually a performs some operation that takes a little time. which combines the regular active devices called aperture error which is due to a clock jitter and is with weak inversion devices. biasing circuit at the input stage. IIT Kharagpur voltage swing. This B. A well error of one LSB is 1/1024 of the full signal range. 6]. signed which this switch is operated is the sampling rate of the integer). Most of the ADC’s has offered the resolution in the range of 1mV. For example. D. There is also a so- cascode approach. One practice is to make both of the gates of MOS driven by the input signal and share a single bias source. Differential Non-Linearity a proper CMOS design techniques. or "levels". electronic switch or gate is used to alternately connect and since 210 = 1024.e. resolutions of recent Low Voltage Low power ADC’s. system. Practical value of differential non-linearity should be less IV. Direct Conversion ADC/Flash ADC TE01025 163 . number of bits and power dissipation is given Sub-Threshold Low 2VT Low by MOSFET E = Power Dissipation Bulk-Driven Low 2VT High 2N × Sampling Frequency MOSFET This figure of merit (FOM) gives energy requirements of the system which is measured in joules per quantization levels. Self Cascode Medium >2VT High For most of the low voltage ADC’s the Figure of Merit MOSFET (FOM) was in the range of fJ/QL [5. 0. [3]. The rate at to 1023 (i. These errors are measured in a unit called the LSB (Least Every effort must be made to maximize the value which Significant Bit).

Pipeline ADC uses two or more steps of subranging. In a second stepp. Proceedings of the 2010 IEEE Students’ Technology Symposium 3-4 April 2010.5 bits/stage architecture TE01025 164 . This models a parallel processsing system. The output of each stage is digitally corrected to obtain converter (DAC). (iii) Lower power consumption (iv) stages work in different clock cyclles. and be largely depended on its front-end d. This may the input voltage to the output of an internall digital to analog be followed by DAC (Digital to Analog A Converter). four bits) 2. T The SAR uses a reference voltage for comparison. Two bits area required to implement stage optimize correction for overlapping errrors.2 MHz is requiired which is not practical in most of the cases. 9]. Overall chip size is reduced because b the sample rate is rather than just the next-most-significant bit.5 bits/stage architecture is most desirable as it offers the advantages likee (i) Extra bits per adopted for this design. This ccan be considered the conversion into many stages are: a refinement of the successive approximatioon ADC wherein 1. 2N . IIT Kharagpur Direct conversion is very fast. One cannot imagine the usage of this type ADC for video applications where the frequency is in tens of MHz. First. Att each step in this but lower resolution). architecture is cost-efficient and su uitable for the deep sub- doubles with each additional bit. sampling rates. 3. This type of ADC has various disaddvantages as well frequency is relatively high. The advaantages of breaking down the results are combined in a last step. This means that the componentts in each stage must settle conversion of multiple samples simultaneoously in different to its final value in half of the clocck period. Amongg various ADC architectures. small die size. When the input signal circuit. a binary value of the approximation is stored in a and on-chip CMOS current/voltage references. Pipeline A/D Converter Block Diagram m D. The 1. Each stage conversion occurs during two clock phases previous T/H to process the next incoming sample. has a high resolution. PIPELINE ARC CHITECTURE Though this type of ADC offers several advantages like higher resolution possible etc this suffers froom the most basic disadvantage like higher clock frequency is required. digital correcttion logic. high power dissipation. typicall) entail less cost from one stage to the next.5-bits/stage pipeline architecture is a very C. use an ADC in video applications [7. VII. (v) Feewer comparators new sample as the old sample is prrocessed by the following required compared to most of the architecturee stage. Since alternate stages of the pipeline. This difference is then connverted finer. the perfformance of the ADC will like high input capacitance. So the ADC employs a glitches present on the output. requiring a large expensive micrometer digital CMOS technolog gies. DESIGNING PIPELINE ADC FOR LOW VOLLTAGE CIRCUITS IN VIDEO APPLICATIONS Msample/s CMOS We intend to design a low bit (8 bits) 30M Analog to Digital Converter (ADC) for hhigh speed signal processing to be used in video related applications. P Pipelined ADC is A total of 9 stages with 1. the preevious stage can take in a and less design time and effort. Flash converter (DAC. (ii) Separate 1. sample-and-hold (S/H) circuit to o increase the sampling linearity [10]. as the sample moves Higher-speed ADCs (fCONV < 100ns. By combining not governed by the number of pipeline p stages. This naturally lowers the resoluution.5 bits thus a raw output of 18 bits is digitally corrected to 10 track-and-hold (T/H) amplifiers for each sttage release each bits.1. Pipeline ADC The pipeline converter architectu ure consists of high speed. conversion of a whole range of bits (for exxample. the difference to Figure 4 shows a block diagram off a general pipeline with k the input signal is determined with a ddigital to analog stages. a coarse conversion is done.r successive approximation register (SAR). enabling [11]. If chip space is available addittional stages can be added One can easily conclude from the above discussion that to for increased resolution. andd only requires a chip. Thus the the merits of the successive approximation and flash ADCs number of stages can be chosen to minimize the size of the this type is fast. clock generator process. Key advantage is high conveersion rate. but usually has only 8 bitss of resolution or Recently reported results also in ndicate that the pipeline fewer. capabble of gigahertz tradeoff between the performance and power consumption. 8. VI. For example to sample an output of 100 kHz at 332 bit resolution a clock frequency of over 3. and an accurate digital output. 1. There is one the feedback reference signal consists of the interim complete conversion per clock cyclee. Successive Approximation ADC popular architecture because it could c reduce the power Successive approximation works by consstantly comparing consumption and simplify the desig gn of the ADC. pipelined converters could provide a good Fig 5. We propose to use a pipelined ADC architectuure as it offers a good figure of merit (FoM). Fig 4. since the number of comparators needed. fed by the current value of tthe approximation) ADC (for usage in video application ns ie for higher frequencies until the best approximation is achieved. low resolution cascaded stages to obtain o a final conversion.

2005. 278–279. When the initial sample is cloocked through all Engineering. T. H. forward biasing g the bulk-source junction circuitry at the front end. "Design Consideration on n Low-Voltage Low Power Data Converters. 33. there are about twwice as many bits Yawei Guo. University of Michigan. A.N. The difference lies in the designer'ss choice of logic circuitry to perform a particular function. D. Proceedings of the 2010 IEEE Students’ Technology Symposium 3-4 April 2010. correction block contains a simple shift register and digital [2] Phillip E. Anderseen. During this latency perriod samples are Techniques”. Vol. A.” C In Proc. 40. November 1995. Blalock k. “Compaact Low-Voltage Power Efficient word which is sent to the digital correction bblock. and Juo-Jung Hung. P. and poor analog modeling. pp. The primary limitations of analoog circuits at low voltage are a large threshold voltage.13 μm Digital CMOS. S. sub-ADC and gainstage simultaneously. Ann shift register. Wang. shown in figure6. output.E. Andersen. The collected data bits are then added using 1-bit overlap methodology. These logic functions are built inside the correction logic circuit. Lei Xie. The digital Operational Amplifier Cells for VLSI”. vol. Rincon. Jianyun Zh hang. Jamuar. VIII. “10 Bit 5Mhz Pipeline A/D These bits must be digitally corrected to prroduce the correct Converter”. vol. 10. and Ø.” IEEE Transactions On Circuits and Systems-I: Fundamental Theory And Application ns.. B. IIT Kharagpur A signal input to a stage is transferreed onto the S/H threshold operation. and G. generated through the pipeline than requireed for the output. Thus a complete 10 bit digital ooutput is available Arbor MI.6 Concept of digital correction Solid-State Circuits Conf. Dept. T. Huan Deng and In pipeline converters. on each successive clock cycle. Xun Gong . Johns. the siggnal is sent to the and the channel JFET. IEEE Int. Piero Malcovati. 11. This redundancy compensatees for component [3] Lisha Li. Langen and J. (ISSCC). after the initial latency period.E. This analog signal is subtracted from the initial sample creating a residue. T This design breaks down the operations into simple logic functtions. [9] R. July.. [6] Franco Maloberti. [7] T. sub- TE01025 165 . Each stage proviides a 2 bit digital [1] K. Feeb. CONCLUSION The solution to the threshold limitation is to remove or circumvent the requirement to provide at leaast Vt volts to turn on the MOSFET. S.5 bit redundanccy. 2002. Feb. [10] Jian Li. Fabrizio Francescon ni. pp. Hernes. GA. Hernes.1483–1496 6. stages then the first digital output is availablle from the digital [4] S. The last two limitations are caused by short-channel technology. 2006 [11] Kannan Sockalingam and Rick Thibod deau. Thhe sample is then Advantages of different ADC’s can be together used in converted into a low-resolution digital word by the sub-ADC. A. This paper has focused on circuit design techniques that would permit the implemenntation of analog circuits at low power supply voltages in standard CMOS technology. J. F. “Design of an ADC for subsampling video applications”. “A cost-efficient c high-speed 12-bit pipeline ADC in 0. pp. “High gain low power op perational amplifier design and compensation techniques”.” IEEE Journalof Solid- State Circuits. The 1 bit redundanccy in each stage is Voltage Analog Circuits using Standard CMOS Technology”. and Gabriel A. “Low Voltage Analog Circuit Design correction block. “A Low power 10bit 80MS/s Pipeline ADC”. Benjamin J. Brigham Young Universiity. Moldsvor. Burra. The concept behind the correction logic is repressented in figure 6. 256–526. Bjørnsen. 42. July 2005. largge channel length modulation. July 30. No. Once held.3 mW 12 MSs 10 b pipelined ADC in 90 nm digital CMOS. and Ø. no. (ISSCC). Of Electrical and Computer non-idealities.2 V 220 MS/s 10 1 b Pipeline ADC Implemented in 0. October 1998. “Low correction logic circuits. There are many ways to implementt the final output calculation. S. F. The threshold voltage limitation is solved by the lateral BJT. The concept is the same regarrdless of method used. Xiaoyang Zeng. Nys. 2002. Huijsing.5bits/stage. Solid-State Circuits Conf. “A 1. IEEE Journal of Solid-State Circuits. continually taken.N. thus the term Institute of Technology Atlanta. EECS Department. T. Briskem myr. 2004. Allen. The sub-DAC then converts this digital word into an analog signal. Georgia usually referred to as the 0. 1. and Olivier J. architecture (Pipeline) where paralleel processing can be used. Telstø. This residue is sent to thhe following stage REFERENCE ES and the process is repeated. The outputs of the earlier stages are kept inn the shift register until stage N provides an output. Individual stage outputs are stored in the [5] Hao Yu. Briskemyr.18-spl mum digitall CMOS.” In Proc. Fig. Bonnerud. B “A 3. Bonnerud. Martin. Telstø. 1506–1513. pp. Rajput. [8] B. Moldsvor. IE EEE Int. K.