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Table of Contents

Edge-Triggered Flip-flops
Pulse-Triggered (Master-Slave) Flip-flops
Data Lock-Out Flip-flops
Operating Characteristics

Flip-flops are synchronous bistable devices. The term synchronous means
the output changes state only when the clock input is triggered. That is,
changes in the output occur in synchronization with the clock.

Flip-flop is a kind of multivibrator. There are three types of multivibrators:

1. Monostable multivibrator (also called one-shot) has only one

stable state. It produces a single pulse in response to a triggering

2. Bistable multivibrator exhibits two stable states. It is able to

retain the two SET and RESETstates indefinitely. It is commonly
used as a basic building block for counters, registers and

3. Astable multivibrator has no stable state at all. It is used

primarily as an oscillator to generate periodic pulse waveforms
for timing purposes.

In this tutorial, the three basic categories of bistable elements are emphasized:
edge-triggered flip-flop, pulse-triggered (master-slave) flip-flop, and data
lock-out flip-flop. Their operating characteristics and basic applications will
also be discussed.
Edge-Triggered Flip-flops
An edge-triggered flip-flop changes states either at the positive edge (rising
edge) or at the negative edge (falling edge) of the clock pulse on the control
input. The three basic types are introduced here: S-R, J-K and D.
Click on one the following types of flip-flop. Then
its logic symbol will be shown on the left. Notice the
small triangle, called the dynamic input indicator, is
used to identify an edge-triggered flip-flop.

Positive edge-triggered (without bubble at Clock input):

S-R, J-K, and D.

Negative edge-triggered (with bubble at Clock input):

S-R, J-K, and D.

The S-R, J-K and D inputs are called synchronous inputs because data on
these inputs are transferred to the flip-flop's output only on the triggering
edge of the clock pulse.On the other hand, the direct set (SET) and clear
(CLR) inputs are called asynchronous inputs, as they are inputs that affect the
state of the flip-flop independent of the clock. For the synchronous operations
to work properly, these asynchronous inputs must both be kept LOW.

Edge-triggered S-R flip-flop

The basic operation is illustrated below, along with the truth table for this
type of flip-flop. The operation and truth table for a negative edge-triggered
flip-flop are the same as those for a positive except that the falling edge of the
clock pulse is the triggering edge.

As S = 1, R = 0. Flip-flop SETS on the

rising clock edge.
Note that the S and R inputs can be changed at any time when the clock input
is LOW or HIGH (except for a very short interval around the triggering
transition of the clock) without affecting the output. This is illustrated in
the timing diagram below:

Edge-triggered J-K flip-flop

The J-K flip-flop works very similar to S-R flip-flop. The only difference is
that this flip-flop has NO invalid state. The outputs toggle (change to the
opposite state) when both J and K inputs are HIGH. The truth table is shown

Edge-triggered D flip-flop
The operations of a D flip-flop is much more simpler. It has only one input
addition to the clock. It is very useful when a single data bit (0 or 1) is to be
stored. If there is a HIGH on the D input when a clock pulse is applied, the
flip-flop SETs and stores a 1. If there is a LOW on the D input when a clock
pulse is applied, the flip-flop RESETs and stores a 0. The truth table below
summarize the operations of the positive edge-triggered D flip-flop. As before,
the negative edge-triggered flip-flop works the same except that the falling
edge of the clock pulse is the triggering edge.
Pulse-Triggered (Master-Slave) Flip-flops
The term pulse-triggered means that data are entered into the flip-flop on the
rising edge of the clock pulse, but the output does not reflect the input state
until the falling edge of the clock pulse. As this kind of flip-flops are sensitive
to any change of the input levels during the clock pulse is still HIGH, the
inputs must be set up prior to the clock pulse's rising edge and must not be
changed before the falling edge. Otherwise, ambiguous results will happen.

The three basic types of pulse-triggered flip-flops are S-R, J-K and D. Their
logic symbols are shown below. Notice that they do not have the dynamic
input indicator at the clock input but havepostponed output symbols at the

The truth tables for the above pulse-triggered flip-flops are all the same as
that for the edge-triggered flip-flops, except for the way they are clocked.
These flip-flops are also called Master-Slave flip-flops simply because their
internal construction are divided into two sections. The slave section is
basically the same as the master section except that it is clocked on the
inverted clock pulse and is controlled by the outputs of the master section
rather than by the external inputs. The logic diagram for a basic master-slave
S-R flip-flop is shown below.
Data Lock-Out Flip-flops
The data lock-out flip-flop is similar to the pulse-triggered (master-slave) flip-
flop except it has a dynamic clock input. The dynamic clock disables (locks
out) the data inputs after the rising edge of the clock pulse. Therefore, the
inputs do not need to be held constant while the clock pulse is HIGH.

The master section of this flip-flop is like an edge-triggered device. The slave
section becomes a pulse-triggered device to produce a postponed output on the
falling edge of the clock pulse.

The logic symbols of S-R, J-K and D data lock-out flip-flops are shown below.
Notice they all have the dynamic input indicator as well as the postponed
output symbol.

Again, the above data lock-out flip-flops have same the truth tables as that for
the edge-triggered flip-flops, except for the way they are clocked.
Operating Characteristics
The operating characteristics mention here apply to all flip-flops regardless of
the particular form of the circuit. They are typically found in data sheets for
integrated circuits. They specify the performance, operating requirements,
and operating limitations of the circuit.

Propagation Delay Time - is the interval of time required

after an input signal has been applied for the resulting output change to occur.

Set-Up Time - is the minimum interval required for the logic levels
to be maintained constantly on the inputs (J and K, or S and R, or D) prior to
the triggering edge of the clock pulse in order for the levels to be reliably
clocked into the flip-flop.

Hold Time - is the minimum interval required for the logic levels
to remain on the inputs after the triggering edge of the clock pulse in order for
the levels to be reliably clocked into the flip-flop.

Maximum Clock Frequency - is the highest rate that a

flip-flop can be reliably triggered.

Power Dissipation - is the total power consumption of the

Pulse Widths - are the minimum pulse widths specified by the
manufacturer for the Clock, SET and CLEAR inputs.

Frequency Division
When a pulse waveform is applied to the clock input of a J-K flip-flop that is
connected to toggle, the Q output is a square wave with half the frequency of
the clock input. If more flip-flops are connected together as shown in the
figure below, further division of the clock frequency can be achieved.

The Q output of the second flip-flop is one-fourth the frequency of the original
clock input. This is because the frequency of the clock is divided by 2 by the
first flip-flop, then divided by 2 again by the second flip-flop. If more flip-
flops are connected this way, the frequency division would be 2 to the power n,
where n is the number of flip-flops.
Parallel Data Storage
In digital systems, data are normally stored in groups of bits that represent
numbers, codes, or other information. So, it is common to take several bits of
data on parallel lines and store them simultaneously in a group of flip-flops.
This operation is illustrated in the figure below.

Each of the three parallel data lines is connected to the D

input of a flip-flop. Since all the clock inputs are
connected to the same clock, the data on the D inputs are
stored simultaneously by the flip-flops on the positive
edge of the clock. Registers, a group of flip-flops use for
data storage, will be explained in more detail in a later


Another very important application of flip-

flops is in digitalcounters, which are
covered in detail in the next chapter.

A counter that counts from 0 to 3 is

illustrated in the timing diagram on the
right. The two-bit binary sequence repeats
every four clock pulses. When it counts to
3, it recycles back to 0 to begin the
sequence again.
Table of Contents
Asynchronous (Ripple) Counters
Asynchronous Decade Counters
Asynchronous Up-Down Counters
Synchronous Counters
Synchronous Decade Counters
Synchronous Up-Down Counters

Circuits for counting events are frequently used in computers and other
digital systems. Since a counter circuit must remember its past states, it has to
possess memory. The chapter about flip-flops introduced how flip-flops are
connected to make a counter. The number of flip-flops used and how they are
connected determine the number of states and the sequence of the states that
the counter goes through in each complete cycle.

Counters can be classified into two broad categories according to the way
they are clocked:

1. Asynchronous (Ripple) Counters - the first flip-flop is clocked by

the external clock pulse, and then each successive flip-flop is
clocked by the Q or Q' output of the previous flip-flop.

2. Synchronous Counters - all memory elements are simultaneously

triggered by the same clock.
In this tutorial, pure binary, decade and up-down counters within the two
categories will be introduced.

(Ripple) Counters

A two-bit asynchronous counter is shown

on the left. The external clock is connected
to the clock input of the first flip-flop
(FF0) only. So, FF0 changes state at the
falling edge of each clock pulse, but FF1
changes only when triggered by the falling
edge of the Q output of FF0. Because of
the inherent propagation delay through a
flip-flop, the transition of the input clock
pulse and a transition of the Q output of
FF0 can never occur at exactly the same
time. Therefore, the flip-flops cannot be
triggered simultaneously, producing an
asynchronous operation.

Note that for simplicity, the transitions of Q0, Q1 and CLK in the timing
diagram above are shown as simultaneous even though this is an
asynchronous counter. Actually, there is some small delay between the CLK,
Q0 and Q1 transitions.

Usually, all the CLEAR inputs are connected together, so that a single pulse
can clear all the flip-flops before counting starts. The clock pulse fed into FF0
is rippled through the other counters after propagation delays, like a ripple on
water, hence the name Ripple Counter.
The 2-bit ripple counter circuit above has four different states, each one
corresponding to a count value. Similarly, a counter with n flip-flops can
have 2 to the power n states. The number of states in a counter is known as
its mod (modulo) number. Thus a 2-bit counter is a mod-4 counter.

A mod-n counter may also described as a divide-by-n counter. This is because

the most significant flip-flop (the furthest flip-flop from the original clock
pulse) produces one pulse for every n pulses at the clock input of the least
significant flip-flop (the one triggers by the clock pulse). Thus, the above
counter is an example of a divide-by-4 counter.

The following is a three-bit asynchronous binary counter and its timing

diagram for one cycle. It works exactly the same way as a two-bit
asynchronous binary counter mentioned above, except it has eight states due
to the third flip-flop.
Decade Counters
The binary counters previously introduced have two to the power n states.
But counters with states less than this number are also possible. They are
designed to have the number of states in their sequences, which are
called truncated sequences. These sequences are achieved by forcing the
counter to recycle before going through all of its normal states.

A common modulus for counters with truncated sequences is ten. A counter

with ten states in its sequence is called a decade counter. The circuit
below is an implementation of a decade counter.

Once the counter counts to ten (1010), all the flip-flops are being cleared.
Notice that only Q1 and Q3 are used to decode the count of ten. This is
called partial decoding, as none of the other states (zero to nine) have both Q1
and Q3 HIGH at the same time.
The sequence of the decade counter is shown in the table below:
Up-Down Counters
In certain applications a counter must be able to count both up and down.
The circuit below is a 3-bit up-down counter. It counts up or down
depending on the status of the control signals UP and DOWN. When the UP
input is at 1 and the DOWN input is at 0, the NAND network between FF0
and FF1 will gate the non-inverted output (Q) of FF0 into the clock input of
FF1. Similarly, Q of FF1 will be gated through the other NAND network into
the clock input of FF2. Thus the counter will count up.

When the control input UP is at 0 and DOWN is at 1, the inverted outputs of

FF0 and FF1 are gated into the clock inputs of FF1 and FF2 respectively. If
the flip-flops are initially reset to 0's, then the counter will go through the
following sequence as input pulses are applied.

Notice that an asynchronous up-down counter is slower than an

up counter or a down counter because of the additional
propagation delay introduced by the NAND networks.
Synchronous Counters
In synchronous counters, the clock inputs of all the flip-flops are
connected together and are triggered by the input pulses. Thus, all the flip-
flops change state simultaneously (in parallel). The circuit below is a 3-bit
synchronous counter. The J and K inputs of FF0 are connected to HIGH.
FF1 has its J and K inputs connected to the output of FF0, and the J and K
inputs of FF2 are connected to the output of an AND gate that is fed by the
outputs of FF0 and FF1.

Pay attention to what happens after the 3rd clock pulse. Both outputs of FF0
and FF1 are HIGH. The positive edge of the 4th clock pulse will cause FF2 to
change its state due to the AND gate.

The count sequence for the 3-bit counter is shown on the right.

The most important advantage of synchronous counters is that

there is no cumulative time delay because all flip-flops are
triggered in parallel. Thus, the maximum operating frequency
for this counter will be significantly higher than for the
corresponding ripple counter.
Decade Counters
Similar to an asynchronous decade counter, a synchronous decade
counter counts from 0 to 9 and then recycles to 0 again. This is done by
forcing the 1010 state back to the 0000 state. This so called truncated
sequence can be constructed by the following circuit.

From the sequence on the left, we notice that:

Q0 toggles on each clock pulse.

Q1 changes on the next clock pulse each

time Q0=1 and Q3=0.

Q2 changes on the next clock pulse each

time Q0=Q1=1.

Q3 changes on the next clock pulse each

time Q0=1, Q1=1 and Q2=1 (count 7), or
when Q0=1 and Q3=1 (count 9).

These characteristics are implemented with the AND/OR logic connected as

shown in the logic diagram above.
Up-Down Counters
A circuit of a 3-bit synchronous up-down counter and a table of its sequence
are shown below. Similar to an asynchronous up-down counter, a
synchronous up-down counter also has an up-down control input. It is used to
control the direction of the counter through a certain sequence.

An examination of the sequence table shows:

for both the UP and DOWN sequences, Q0 toggles

on each clock pulse.

for the UP sequence, Q1 changes state on the next

clock pulse when Q0=1.

for the DOWN sequence, Q1 changes state on the

next clock pulse when Q0=0.

for the UP sequence, Q2 changes state on the next

clock pulse when Q0=Q1=1.

for the DOWN sequence, Q2 changes state on the

next clock pulse when Q0=Q1=0.

These characteristics are implemented with the AND, OR & NOT logic
connected as shown in the logic diagram above.
Digital counters are very useful in many applications. They can be easily
found in digital clocks and parallel-to-serial data conversion (multiplexing).
In this section, we will use the later as an example on how counters are being

A group of bits appearing simultaneously on parallel lines is called parallel

data. A group of bits appearing on a single line in a time sequence is
called serial data. Parallel-to-serial conversion is normally accomplished by
the use of a counter to provide a binary sequence for the data-select inputs of
a multiplexer, as illustrated in the circuit below.

The Q outputs of the modulus-8 counter are

connected to the data-select inputs of an
eight-bit multiplexer. The first byte (eight-
bit group) of parallel data is applied to the
multiplexer inputs. As the counter goes
through a binary sequence from 0 to 7, each
bit beginning with D0, is sequentially
selected and passed through the multiplexer
to the output line.

After eight clock pulses, the data byte has

been converted to a serial format and sent
out on the transmission line. Then, the
counter recycles back to 0 and converts
another parallel byte sequentially again by
the same process.
Table of Contents
Serial In - Serial Out Shift Registers
Serial In - Parallel Out Shift Registers
Parallel In - Serial Out Shift Registers
Parallel In - Parallel Out Shift Registers
Bidirectional Shift Registers
Shift Register Counters

Shift registers are a type of sequential logic circuit, mainly for storage of
digital data. They are a group of flip-flops connected in a chain so that the
output from one flip-flop becomes the input of the next flip-flop. Most of the
registers possess no characteristic internal sequence of states. All the flip-
flops are driven by a common clock, and all are set or reset simultaneously.

In this chapter, the basic types of shift registers are studied, such as Serial In -
Serial Out, Serial In - Parallel Out, Parallel In - Serial Out, Parallel In -
Parallel Out, and bidirectional shift registers. A special form of counter - the
shift register counter, is also introduced.
Serial In - Serial Out
Shift Registers
A basic four-bit shift register can be constructed using four D flip-flops, as
shown below. The operation of the circuit is as follows. The register is first
cleared, forcing all four outputs to zero. The input data is then applied
sequentially to the D input of the first flip-flop on the left (FF0). During each
clock pulse, one bit is transmitted from left to right. Assume a data word to
be 1001. The least significant bit of the data has to be shifted through the
register from FF0 to FF3.

In order to get the data out of the register, they must be shifted out serially.
This can be done destructively or non-destructively. For destructive readout,
the original data is lost and at the end of the read cycle, all flip-flops are reset
to zero.

To avoid the loss of data, an arrangement for a non-destructive reading can be

done by adding two AND gates, an OR gate and an inverter to the system.
The construction of this circuit is shown below.
The data is loaded to the register when the control line is HIGH (ie WRITE).
The data can be shifted out of the register when the control line is LOW (ie
READ). This is shown in the animation below.

Serial In - Parallel Out

Shift Registers
For this kind of register, data bits are entered serially in the same manner as
discussed in the last section. The difference is the way in which the data bits
are taken out of the register. Once the data are stored, each bit appears on its
respective output line, and all bits are available simultaneously. A
construction of a four-bit serial in - parallel out register is shown below.
In the animation below, we can see how the four-bit binary number 1001 is
shifted to the Q outputs of the register.

Parallel In - Serial Out

Shift Registers
A four-bit parallel in - serial out shift register is shown below. The circuit uses
D flip-flops and NAND gates for entering data (ie writing) to the register.

D0, D1, D2 and D3 are the parallel inputs, where D0 is the most significant bit
and D3 is the least significant bit. To write data in, the mode control line is
taken to LOW and the data is clocked in. The data can be shifted when the
mode control line is HIGH as SHIFT is active high. The register performs
right shift operation on the application of a clock pulse, as shown in the
animation below.
Parallel In - Parallel Out
Shift Registers
For parallel in - parallel out shift registers, all data bits appear on the parallel
outputs immediately following the simultaneous entry of the data bits. The
following circuit is a four-bit parallel in - parallel out shift register constructed
by D flip-flops.

The D's are the parallel inputs and the Q's are the parallel outputs. Once the
register is clocked, all the data at the D inputs appear at the corresponding Q
outputs simultaneously.
Bidirectional Shift Registers
The registers discussed so far involved only right shift operations. Each right
shift operation has the effect of successively dividing the binary number by
two. If the operation is reversed (left shift), this has the effect of multiplying
the number by two. With suitable gating arrangement a serial shift register
can perform both operations.

A bidirectional, or reversible, shift register is one in which the data can

be shift either left or right. A four-bit bidirectional shift register using D flip-
flops is shown below.

Here a set of NAND gates are configured as OR gates to select data inputs
from the right or left adjacent bistables, as selected by the LEFT/RIGHT
control line.

The animation below performs right shift four times, then left shift four times.
Notice the order of the four output bits are not the same as the order of the
original four input bits. They are actually reversed!
Shift Register Counters
Two of the most common types of shift register counters are introduced here:
the Ring counter and the Johnson counter. They are basically shift registers
with the serial outputs connected back to the serial inputs in order to produce
particular sequences. These registers are classified as counters because they
exhibit a specified sequence of states.

Ring Counters
A ring counter is basically a circulating shift register in which the output of
the most significant stage is fed back to the input of the least significant stage.
The following is a 4-bit ring counterconstructed from D flip-flops. The
output of each stage is shifted into the next stage on the positive edge of a
clock pulse. If the CLEAR signal is high, all the flip-flops except the first one
FF0 are reset to 0. FF0 is preset to 1 instead.

Since the count sequence has 4 distinct states, the

counter can be considered as a mod-4 counter.
Only 4 of the maximum 16 states are used,
making ring counters very inefficient in terms of
state usage. But the major advantage of a ring
counter over a binary counter is that it is self-
decoding. No extra decoding circuit is needed to
determine what state the counter is in.

Johnson Counters

Johnson counters are a variation of standard ring

counters, with the inverted output of the last
stage fed back to the input of the first stage. They
are also known as twisted ring counters. An n-
stage Johnson counter yields a count sequence of
length 2n, so it may be considered to be a mod-
2n counter. The circuit above shows a 4-bit
Johnson counter. The state sequence for the
counter is given in the table as well as the
animation on the left.

Again, the apparent disadvantage of this counter is that the maximum

available states are not fully utilized. Only eight of the sixteen states are being

Beware that for both the Ring and the Johnson counter must initially be
forced into a valid state in the count sequence because they operate on a
subset of the available number of states. Otherwise, the ideal sequence will
not be followed.
Shift registers can be found in many applications. Here is a list of a few.

To produce time delay

The serial in -serial out shift register can be used as a time delay device. The
amount of delay can be controlled by:

1. the number of stages in the register

2. the clock frequency

To simplify combinational logic

The ring counter technique can be effectively utilized to implement
synchronous sequential circuits. A major problem in the realization of
sequential circuits is the assignment of binary codes to the internal states of
the circuit in order to reduce the complexity of circuits required. By assigning
one flip-flop to one internal state, it is possible to simplify the combinational
logic required to realize the complete sequential circuit. When the circuit is in
a particular state, the flip-flop corresponding to that state is set to HIGH and
all other flip-flops remain LOW.

To convert serial data to parallel data

A computer or microprocessor-based system commonly requires incoming
data to be in parallel format. But frequently, these systems must
communicate with external devices that send or receive serial data. So, serial-
to-parallel conversion is required. As shown in the previous sections, a serial
in - parallel out register can achieve this.
by Lee Chin Wei
and Andrew Long

1. An Overview

2. Different types of Synchronous Counters

o Binary UP Counters

o Binary Down Counters

o Binary Up/Down Counters

o MOD-N/Divide-by-N Counters

o BCD Counters

o Ring Counters

o Johnson/Twisted-Ring Counters

o Loadable/Presettable Counters

3. A Comparison between Synchronous and Asynchronous Counters

4. Synchronous Counter Design

o Multiplexer
o Read-Only Memory

o Programmable Logic Array

5. Making Fast Counters

o Where speed is a concern...

o General Structure of a Synchronous Binary Counter

o Prescaling

o Pipelining

o Fast Counters From Xilinx

6. Referennces

An Overview
The purpose of the survey is to collate information on Digital Synchronous
Counters. Particular emphasis was placed on the following areas :

1. Types of Synchronous Counters and How they work

2. Fast Counter Techniques

3. Fast Counters from Xilinx

4. Implementation of Counters :
Dedicated Hardware and Alternative Devices

The material is presented in a manner suitable for a teaching tool. It seeks to

enlighten and to spark off interest in the design of counters. As R.S.S Obermann
remarks " of counters has, in my experience, always been an excellent
proving ground for anyone who has mastered Boolean algebra... Have fun
reading !!!!!
Different types of Synchronous
Binary Up Counters
A synchronous binary counter counts from 0 to 2N-1, where N is the number of
bits/flip-flops in the counter. Each flip-flop is used to represent one bit. The flip-
flop in the lowest-order position is complemented/toggled with every clock pulse
and a flip-flop in any other position is complemented on the next clock pulse
provided all the bits in the lower-order positions are equal to 1.

Take for example A4 A3 A2 A1 = 0011. On the next count, A4 A3 A2 A1 = 0100. A1,

the lowest-order bit, is always complemented. A2is complemented because all the
lower-order positions (A1 only in this case) are 1's. A3 is also complemented
because all the lower-order positions, A2 and A1 are 1's. But A4 is not
complemented the lower-order positions, A3 A2 A1 = 011, do not give an all 1

To implment a synchronous counter, we need a flip-flop for every bit and an AND
gate for every bit except the first and the last bit. The diagram below shows the
implementation of a 4-bit synchronous up-counter.
4-bit Synchronous Binary Up-Counter

From the diagram above, we can see that although the counter is synchronous and
is supposed to change simultaneously, we have a propagation delay through the
AND gates which add up to give an overall propagation delay which is
proportional to the number of bits of the counter. To overcome this problem, we
can feed the outputs from the flip-flops directly to a many-input AND gate as
follows :
4-bit Synchronous Binary Up Counter using speedup technique

This method does overcomes the problem of additive propagation delay but
introduces some other problem of its own. From the diagram above, we can see
that the third flip-flop gets its J-K input from the output of a 2-input AND gate and
the fourth flip-flop gets its input from a 3-input AND gate and so on. If we have a
counter that counts to for example 16 bits, we will need to have :
1 * 15-input AND gate,
1 * 14-input AND gate,
1 * 3-input AND gate and
1 * 2-input AND gate.

This method obviously usus a lot more resources than the first method. Not only
that, in the first method, the output from each flip-flop is only used as an input to
one AND gate. In the second method, the output from each flip-flop is used as an
input to all the higher-order bits. If we have a 12-bit counter, the output of the first
flip-flop will have to drive 10 gates (called fan-out. The output from the flip-flop
may not have the power to do this.
The "solution" to this is to use a compromise between the two methods. Say we
have a 12-bit counter, we can organise it into 3 groups of 4. Within each group of
4, we use the second method and between the 3 groups, use the first method. This
way, we only have an overall gate propagation delay and a maximum fan-out of 3
instead of 10 using the first and second method respectively.

There are many variations to the basic binary counter. The one described above is
the binary up counter (counts upwards). Besides the up counter, there is the binary
down counter, the binary up/down counter, binary-coded-decimal (BCD) counter
etc. Any counter that counts in binary is called a binary counter.

Binary Down Counters

In a binary up counter, a particular bit, except for the first bit, toggles if all the
lower-order bits are 1's. The opposite is true for binary down counters. That is, a
particular bit toggles if all the lower-order bits are 0's and the first bit toggles on
every pulse.

Taking an example, A4 A3 A2 A1 = 0100. On the next count, A4 A3 A2 A1 = 0011.

A1, the lowest-order bit, is always complemented. A2is complemented because all
the lower-order positions (A1 only in this case) are 0's. A3 is also complemented
because all the lower-order positions, A2 and A1 are 0's. But A4 is not
complemented the lower-order positions, A3 A2 A1 = 011, do not give an all 0
4-bit Synchronous Binary Down Counter

The implementation of a synchronous binary down counter is exactly the same as

that of a synchronous binary up counter except that the inverted output from each
flip-flop is used. All the methods used improve a binary up counter can be
similarly applied here.

Binary Up/Down Counters

The similarities between the implementation of a binary up counter and a binary
down counter leads to the possibility of a binary up/down counter, which is a
binary up counter and a binary down counter combined into one. Since the
difference is only in which output of the flip-flop to use, the normal output or the
inverted one, we use two AND gates for each flip-flop to "choose" which of the
output to use.
3-bit Synchronous Binary Up/Down Counter

From the diagram, we can see that COUNT-UP and COUNT-DOWN are used as
control inputs to determine whether the normal flip-flop outputs or the inverted
ones are fed into the J-K inputs of the following flip-flops. If neither is at logic
level 1, the counter doesn't count and if both are at logic level 1, all the bits of the
counter toggle at every clock pulse. The OR gate allows either of the two outputs
which have been enabled to be fed into the next flip-flop. As with the binary up
and binary down counter, the speed up techniques apply.

MOD-N/Divide-by-N Counters
Normal binary counter counts from 0 to 2N - 1, where N is the number od bits/flip-
flops in the counter. In some cases, we want it to count to numbers other than 2 N -
1. This can be done by allowing the counter to skip states that are normally part of
the counting sequence. There are a few methods of doing this. One of the most
common methods is to use the CLEAR input on the flip-flops.
3-bit Synchronous Binary MOD-6 Counter

In the example above, we have a MOD-6 counter. Without the NAND gate, it is a
MOD-8 counter. Now, with the NAND gate, the output from the NAND gate is
connected to the asynchronous CLEAR inputs of each flip-flop. The inputs to the
NAND gate are the outputs of the B and C flip-flops. So, all the flip-flops will be
cleared when B = C = 1 (1102 = 610 ). When the counter goess from state 101 to
state 110, the NAND output will immediately clear the counter to state 000. Once
the flip-flops have been cleared, the B = C = 1 condition no longer exists and the
NAND output goes back to high. The counter will therefore count from 000 to 101,
and for a very short period of time, be in state 110 before the counter is cleared.
This state is called the temporary state and the counter usually only remains in a
temporary state for a few nanoseconds. We can essentially say that the counter
skips 110 and 111 so that it goes only six different states; thus, it is a MOD-6
counter. We also have to note that the temporary state causes a spike or glitch on
the output waveform of B. This glitch is very narrow and will not normally be a
problem unless it is used to drive other circuitry outside the counter. The 111 state
is the unused state here. In a state machine with unused states, we need to make
sure that the unused states do not cause the system to hang, ie. no way to get out of
the state. We don't have to worry about this here because even if the system does
go to the 111 state, it will go to state 000, a valid state) on the next clock pulse.
Binary Coded Decimal (BCD) Counters
The BCD counter is just a special case of the MOD-N counter (N = 10). BCD
counters are very commonly used because most human beings count in decimal. To
make a digital clock which can tell the hour, minute and second for example, we
need 3 BCD counters (for the second digit of the hour, minute and second), two
MOD-6 counters (for the first digit of the minute and second), and one MOD-2
counter (for the first digit of the hour).

Ring Counters
Ring counters are implemented using shift registers. It is essentially a circulating
shift register connected so that the last flip-flop shifts its value into the first flip-
flop. There is usually only a single 1 circulating in the register, as long as clock
pulses are applied.

4-bit Synchronous Ring Counter

In the diagram above, assuming a starting state of Q 3 = 1 and Q2 = Q1 = Q0 = 0. At

the first pulse, the 1 shifts from Q3 to Q2 and the counter is in the 0100 state. The
next pulse produces the 0010 state and the third, 0001. At the fourth pulse, the 1 at
Q0 is transferred back to Q3, resulting in the 1000 state, which is the initial state.
Subsequent pulses will cause the sequence to repeat, hence the name ring counter.

The ring counter above functions as a MOD-4 counter since it has four distinct
states and each flip-flop output waveform has a frequency equal to one-fourth of
the clock frequency. A ring counter can be constructed for any MOD number. A
MOD-N ring counter will require N flip-flops connected in the arrangement as the
diagram above.

A ring counter requires more flip-flops than a binary counter for the same MOD
number. For example, a MOD-8 ring counter requires 8 flip-flops while a MOD-8
binary counter only requires 3 (23 = 8). So if a ring counter is less efficient in the
use of flip-flops than a binary counter, why do we still need ring counters? One
main reason is because ring counters are much easier to decode. In fact, ring
counters can be decoded without the use of logic gates. The decoding signal is
obtained at the output of its corresponding flip-flop.

For the ring counter to operate properly, it must start with only one flip-flop in the
1 state and all the others at 0. Since it is not possible to expect the counter to come
up to this state when power is first applied to the circuit, it is necessary to preset
the counter to the required starting state before the clock pulses are applied. One
way to do this is to apply a pulse to the PRESET input of one of the flip-flops and
the CLEAR inputs of all the others. This will place a single 1 in the ring counter.

Johnson/Twisted-Ring Counters
The Johnson counter, also known as the twisted-ring counter, is exactly the same as
the ring counter except that the inverted output of the last flip-flop is connected to
the input of the first flip-flop.

4-bit Synchronous Johnson Counter

The Johnson counter works in the following way : Take the initial state of the
counter to be 000. On the first clock pulse, the inverse of the last flip-flop will be
fed into the first flip-flop, producing the state 100. On the second clock pulse, since
the last flip-flop is still at level 0, another 1 will be fed into the first flip-flop,
giving the state 110. On the third clock pulse, the state 111 is produced. On the
fourth clock pulse, the inverse of the last flip-flop, now a 0, will be shifted to the
first flip-flop, giving the state 011. On the fifth and sixth clock pulse, using the
same reasoning, we will get the states 001 and 000, which is the initial state again.
Hence, this Johnson counter has six distinct states : 000, 100, 110, 111, 011 and
001, and the sequence is repeated so long as there is input pulse. Thus this is a
MOD-6 Johnson counter.

The MOD number of a Johnson counter is twice the number of flip-flops. In the
example above, three flip-flops were used to create the MOD-6 Johnson counter.
So for a given MOD number, a Johnson counter requires only half the number of
flip-flops needed for a ring counter. However, a Johnson counter requires decoding
gates whereas a ring counter doesn't. As with the binary counter, one logic gate
(AND gate) is required to decode each state, but with the Johnson counter, each
gate requires only two inputs, regardless of the number of flip-flops in the counter.
Note that we are comparing with the binary counter using the speed up technique
discussed above. The reason for this is that for each state, two of the N flip-flops
used will be in a unique combination of states. In the example above, the
combination Q2 = Q1 = 0 occurs only once in the counting sequence, at the count of
0. The state 010 does not occur. Thus, an AND gate with inputs (not Q 2) and (not
Q2) can be used to decode for this state. The same characteristic is shared by all the
other states in the sequence.

A Johnson counters represent a middle ground between ring counters and binary
counters. A Johnson counter requires fewer flip-flops than a ring counter but
generally more than a binary counter; it has more decoding circuitry than a ring
counter but less than a binary counter. Thus, it sometimes represents a logical
choice for certain applications.

Loadable/Presettable Counters
Many synchronous counters available as ICs are designed to be presettable. This
means that they can be preset to any desired starting value. This can be done either
asynchronously (independent of the clock signal or synchronously (on the active
transition of the clock signal). This presetting operation is also known as loading,
hence the name loadable counter. The diagram below shows a 3-bit asynchronously
presettable synchronous up counter.
3-bit Synchronous Binary Presettable Counter

In the diagram above, the J, K and CLK inputs are wired the same way as a
synchronous up counter. The asynchronous PRESET and CLEAR inputs are used
to perform the asynchronous presetting. The counter is loaded by applying the
desired binary number to the inputs P 2, P1 and P0 and a LOW pulse is applied to the
PARALLEL LOAD input, not(PL). This will asynchronously transfer P 2, P1 and
P0 into the flip-flops. This transfer occurs independently of the J, K, and CLK
inputs. As long as not(PL) remains in the LOW state, the CLK input has no effect
on the flip-flop. After not(PL) returns to high, the counter resumes counting,
starting from the number that was loaded into the counter.

For the example above, say that P2 = 1, P1 = 0, and P0 = 1. When not(PL) is high,
these inputs have no effect. The counter will perform normal count-up operations if
there are clock pulses. Now let's say that not(PL) goes low at Q 2 = 0, Q1 = 1 and
Q0 = 0. This will produce LOW states at the CLEAR input of Q 1, and the PRESET
inputs of Q2 and Q0. This will make the counter go to state 101 regardless of what
is occuring at the CLK input. The counter will remain at state 101 until not(PL)
goes back to HIGH. The counter will then continue counting from 101.

A comparison between
Synchronous and
Asynchronous Counters
Asynchronous counters, also known as ripple counters, are not clocked by a
common pulse and hence every flip-flop in the counter changes at different times.
The flip-flops in an asynchronous counter is usually clocked by the output pulse of
the preceding flip-flop. The first flip-flop is clocked by an external event. A
synchronous counter however, has an internal clock, and the external event is used
to produce a pulse which is synchronised with this internal clock. The diagram of
an ripple counter is shown below.

4-bit Ripple Counter

It can be seen that a ripple counter requires less circuitry than a synchronous
counter. No logic gates are used at all in the example above. Although the
asynchronous counter is easier to construct, it has some major disadvantages over
the synchronous counter.

First of all, the asynchronous counter is slow. In a synchronous counter, all the flip-
flops will change states simultaneously while for an asynchronous counter, the
propagation delays of the flip-flops add together to produce the overall delay.
Hence, the more bits or number of flip-flops in an asynchronous counter, the
slower it will be.

Secondly, there are certain "risks" when using an asynchronous counter. In a

complex system, many state changes occur on each clock edge and some ICs
respond faster than others. If an external event is allowed to affect a system
whenever it occurs (unsynchronised), there is a small chance that it will occur near
a clock transition, after some IC's have responded, but before others have. This
intermingling of transitions often causes erroneous operations. And the worse this
is that these problems are difficult to forsee and test for because of the random time
difference between the events.

Synchronous Counter Design

A synchronous counter usually consists of two parts: the memory element and the
combinational element. The memory element is implemented using flip-flops while
the combinational element can be implemented in a number of ways. Using logic
gates is the traditional method of implementing combinational logic and has been
applied for decades. Since this method often results in minimum component cost
for many combinational systems, it is still a popular approach. However there are
other methods of implementing combinational logic which offers other advantages.
Some of the alternative methods which are discussed here are: multiplexers
(MUX), read-only memory (ROM) and programmable logic array (PLA).

The multiplexer, also called the data selector, it has n select inputs, 2 n input lines
and 1 output line (and usually also a complement of the output). The 2 n possible
combinations of the select inputs connects one of the input lines to the output.
When used as a combinational logic device, the n select inputs represent n
variables and the 2n input lines represent all the minterms of the n variables.

Read-Only Memory
The ROM is usually used as a storage unit for fixed programs in a computer.
However, it can also be used to implement combinational logic. It is useful for
systems requiring changeable functions. When a different function is required, a
different ROM producing this function can be plugged into the circuit. No wiring
change is necessary. The ROM has n input lines pointing to 2 n locations within the
ROM that store words of M bits. As with the MUX, each input line is used to
represent a variable and the 2n locations represent the minterms.

Programmable Logic Array

The PLA is very similar to the ROM. It can be thought of as a ROM with a large
percentage of its locations deleted. A ROM with 16 input address lines must have
216, or 65,536 storage locations, and all the words stored in these have to be
decoded. The PLA only decodes a small percentage of the minterms. The PLA is
sometimes used to produce a system with a small number of chips in a minimum

More information on these devices are given in article 2 of cwl3.

Making Fast Counters

Where speed is a concern....
In certain application, speed is an important factor affecting the choice of a
counter. For example, counters used in communication and certain instrumentation
applications are necessarily fast. We will be looking at some technique commonly
used to improve the speed of a counter. To reinforce, the concepts presented, some
commercial counters (by Xilinx) will be considered.

General Structure of a Synchronous Binary

There are two common ways in which a synchronous binary counter is structured.
These are, namely, the series carry synchronous counter and the parallel carry
synchronous counter. These two counters are illustrated
as follows :

Series Carry Synchronous Counter

Parallel Carry Synchronous Counter

Both counters depicted above are binary-up counters.

The T implies a T flip-flop. The flip-flop complements/toggles its output on the

rising edge of a clock pulse provided its enable (EN) input is high.

From the diagrams, it can be seen that the least significant bit Q0 toggles on every
clock pulse, and subsequent bits toggle when preceding bits are high. The
important distinction between the two counters is the way the EN signals propagate
from Q0 to Q3. This is illustrated by the highlighted paths. The signals are
propagated serially and in parallel (to each AND gate) in the first and second case

The parallel carry scheme results in a much faster counter. This difference in speed
is accounted for by the delay encountered during the propagation of the EN signals.
To illustrate the worst case delay in both cases, we consider a change in Q0 from 0
to 1. (see diagrams above)

In the series carry scheme, the time to propagate the change in Q0 must take into
account the propagation delays of the 3 AND gates (A, B, C). In the parallel carry
scheme, only the propagation delay of 1 AND gate has to be considered. Therefore,
the minimum clock periodof the parallel scheme is shorter. Thus, the parallel
synchronous carry counter operates at a greater maximum frequency. This structure
is believed to be the fastest synchronous binary counter structure. In applications
that require speed, this scheme is commonly used.

This structure does have limitations. From the diagrams, it can be seen that a single
flip-flop output(consider Q0) has to drive a number of subsequent AND gates. The
output current of a flip-flop may not be large enough to drive that many gates. It
becomes a problem when the counter gets bigger. To overcome this, a tree of AND
gates is usually used. How exactly this tree will look like is an engineering choice.
This choice will reflect the trade-off between speed requirements and the constraint
mentioned above.

Although the series carry scheme is slower, it does not suffer the same drawback as
the parallel carry scheme. This makes it a suitable basis for making big counters.
Its speed can be improved by using some form of Prescaling. This technique will
be considered in subsequent sections.


" The Concept "

The idea of prescaling is to provide a "prescaling" stage between the incoming

clock frquency and the counting circuit. The prescaling stage is sometimes
provided by a dedicated prescaling device known as the Prescaler. This
device/circuit is designed primarily using Emitter Coupled Logic (ECL) . ECL
benefits from very fast switching capabilities. This makes it suitable for high speed
counting work.

Despite its suitability to high speed counting work, it has little or no counting
features since such features will only impede its operating speed. The reader does
not have to concern himself or herself with the implementation of the prescaler.
The reader should, however, understand the function it performs in the overall

A prescaler generates a "clock" pulse after it has received a number of input pulses.
This "clock" pulse is then fed to the counting circuit. For example, a divide-by-
n prescaler will generate a pulse when it has received n input pulses. At present,
there are prescalers that can accept a range of frequencies ranging from a few
hundred Megahertx to a few Gigahertz. The point of the prescaler is to divide an
incoming clock and, thereby provide a clock to a larger, slower counting circuit.

The curious reader would probably be wondering how the actual (and faster)
incoming clock frequency is actually reflected in the slower counting circuit. There
are a number of ways in which a prescaler can be used, but one sophisticated setup
is the "pulse swallowing"counter. The characteristic of a "pulse swallowing"
counter is that it stops counting when a predetermined number of pulses has been

The following diagram shows a down-counting Binary Coded Decimal (BCD)

counter in a simplified "pulse swallowing" setup.

BCD Pulse Swallowing Counter

In the above setup, the Tens and Units sections of a BCD counter are shown. Note
that a section stops counting when zero has been reached. Consequently, a carry is
also generated ( UC and TC) . Both sections are presettable via P3-P0. The
outputs(Q3-Q0) reset to the preset values when Pe is high. UC is fed back to the
prescaler as the Mode(M) input signal. When M is high or low, the prescaler
divides-by- 10 or 11 repectively before generating a "clock" pulse. To demonstrate
the principle of "pulse swallowing", let's consider an example.
Suppose we preset a value of 32 (0011 0010). The outputs will have values as
shown below :

Tens Units Mode(M) Decimal Value

---------after 0 clock pulses-----------

0011 0010 0 32

---------after 11 clock pulses----------

0010 0001 0 21

---------after 22 clock pulses----------

0001 0000 1 10

---------after 32 clock pulses----------

0000 0000 1 00


Effectively, a "pulse swallowing" counter "swallows up" fast incoming clock

pulses. This is reflected in the slower counter by simultaneously driving the Tens
and Units section. Therefore the net effect of such a combination (of prescaler and
counter) is a counter operating at a much higher speed than what it was capable of


Pipelining is a "predict and store" technique. It "predicts" an event one(usually)

clock cycle before it is to occur. Upon prediction, certain output value(s) (resulting
that from that event) are set. These new value(s) are stored/latched using flip-flops
(usually D type). They appear at the outputs on the next clock pulse when the event
actually occurs. How does this actually help in speeding things up?

Let's say the detection of an event and the setting of the required outputs take 20ns.
The propagation of the outputs takes another 10ns.
Consider the two situations where pipelining is used and not used. If the above
actions had to be performed in one clock cycle, the minimum clock period would
be 30 ns(without pipelining). If these two sets of actions were performed in two
separate clock periods, the minimum clock period is 20ns(with pipelining). With
pipelining, the overall frequency/speed of the circuit is improved. This is illustrated
schematically as follows :

" Pipelining speeds things up!! "

Fast Counters From Xilinx

# Synchronous Presettable Counter
(Xilinx Application Notes XAPP 003.002)

Maximum Clock Frequency

8 bits : 71 MHz
16 bits : 55 Mhz

This counter demonstrates the parallel carry synchronous counter structure and
the pipelining technique.

Let's consider an up-counting version of this counter.

Presettable Up Counter

Q- counter bits
D- preset via these inputs

On first sight, it looks complicated but the reader may have noticed that there are
many similar blocks of logic circuitry. Let's take a look at some of these blocks and
see how they work.
Consider block producing Q0

Block Producing Q0 (least significant bit)


As seen below, an inverted version of Q0 is propagated through AND gate A. D0 is

not propagated through A because an inverted version of TERMINAL COUNT is
fed into B. Therefore the output of B is low. With this setup, Q0 toggles on every
rising edge of the clock pulse.


As seen below, the inverted version of Q0 is not propagated through A. D0 is

propagated through B because an inverted version of TERMINAL COUNT is fed
into B. The output of the OR gate will have the value of D0. Therefore, Q0 will
have the value ofD0 on the next clock pulse.It is noted that the preset
value D appears as the output Q on the next clock pulse (after terminal count). This
applies to all bit stages.

Consider block producing Q3

Block Producing Q3


As seen below, the output of the EX-OR gate C will be propagated through A. The
output of C is high when either(not both) T3 or Q3 is high. T3 is
the ANDED version of all preceding outputs(Q0-Q2 ).(Note that in the Q1 stage,
the T input is replaced by Q1) Effectively, Q3 stays the same when T3 is low.
When T3 is high, Q3 toggles. Therefore, in all the bit stages, an output bit toggles
when the preceding bits are high.


The preset value is loaded on the next clock pulse as before.

Consider the Carry connections

The Carry Connections

Let's focus our attention on the generation of the T outputs(see above). This
counter uses an adapted version of the parallel carry scheme by employing an AND
gate tree. The different outputs driving the AND gates are summarised
schematically as follows :
AND Gate Tree Diagrams

In this setup, Q0 is fed directly to the next bit stage and in parallel to all the T(T2-
T6) AND gates. This minimises the worst case delay (compare with the series carry
scheme). Subsequent bits feed in parallel to the relevant AND gates. The additional
gate delay introduced by Tx does not affect the critical paths
from Q0 to Q7 because of the way the numbers change.

Consider the Pipelining block


When the counter output is 11111110, the NAND gate output is low. Therfore,
when the value preceding terminal count is detected, the required TERMINAL
COUNT value (low) is fed to the input of the flip-flop. On the next clock
pulse(when it is terminal count), TERMINAL COUNT is low ("load preset value").
This propagates the preset values (D0-D7) to the inputs of the flip-flops. Note :
when any other values are detected, the NAND gate output is high.
Thus TERMINAL COUNT is high ("do not load preset value").

# High-Speed Synchronous Prescaler Counter

( Xilinx Application Notes 001.002)

Max Clock Frequency

8 bits : 200 MHz
16 bits : 115 MHz

The counter demonstrates prescaling and pipelining.

The counter can be represented in a block diagram as follows :

Non-Loadable Binary Counter

The counter is implemented on a Field Programmable Logic Device (FPGA). This

requires it to be implemented as tri-bit blocks(TB1 and TB2 ) for optimal resource
usage. The reader does not need to concern himself/herself with this.

The counter employs the concept of prescaling but does not use a dedicated
prescaler (ECL device). Instead, the least significant (LS) tri-bit(Q0-Q2 ) provides
the prescaling function. All tri-bits respond (increment) to a clock pulse if
its Count-Enable inputs (CE, CEP , CET) are high. The CEO of the LS tri-bit
is high once in every 8 clock cycles when all its outputs are high.
The "prescaler" pulse effectively reduces the clock rate to the rest of the tri-bits by
a factor of 8. Note that there is no change in the original clock rate. The 7 clock
cycles when the LS CEO is low gives the CEO-CET ripple chain (of subsequent
tri-bits) time to settle. If this prescaling was not done, the settling time would have
to be taken into account when determining the minimum clock period of the
counter. This would significantly limit the minimum clock period, thereby slowing
the counter down. This would become clearer when we examine the actual
implementation of this counter.

Note : all clock inputs are assumed to be driven by a common

clock. Qa and Qc represent the LSB and MSB of a tri-bit respectively.
Generation of CEO in TB1(A) and TB2(B)

CEOs are high only when CEs(or CET s) and the outputs Q(Qa-Qc)are high.

Generation of Qa in TB1(A) and TB2(B)

When the Count-Enable inputs are high, the EX-OR gate complements Qa.
Therefore, the Count-Enable inputs effectively "enable" or "disable" the
complementing function.

Generation of Qb in TB1(A) and TB2(B)

When both Qa and the Count-Enable inputs are high, the complementing function
is enabled.

Generation of Qc

The generation of Qc is similar to the generation of Qb except that the value of Qb

is also fed into the AND gate.
The Ripple Chain

The delay of this ripple chain is the sum of all the gate delays presented by the
chain of AND gates. To appreciate the sigificance of this delay, let's consider an
example. Suppose the current values from Q23-Q3 is 01111...(all ones)...110. On
the next "prescaler" pulse, Q3 will become 1. This "information" about the change
in Q3 has to be propagated to subsequent tri-bits before the next clock pulse. This
is necessary to ensure the correct changes(on the next clock pulse) to subsequent
bits. As evident from the diagrams, the worst case delay is the propagation of this
"information" from Q3 through the ripple chain and to the flip-flop input of Q23.
This delay is a major and common problem with most binary counters. The
"prescaler" accommodates this delay by allowing time for the propagation of this
"information". This does not affect the effective operating frequency of the counter
because the "prescaler"(LS tri-bit) still operates at the faster clock rate.

The speed of the counter can be improved further by pipeliningthe LS CEO signal :

Pipelining CEO
We see that when 110 is detected, CEO is set and fed to the flip-flop input. This
value appears as CEO on the next clock pulse(when 111 occurs).

The actual implemetation of LS tri-bit with pipelining is seen below :

Implemention of LS tri-bit with Pipeline

# Ultra-Fast Synchronous Counter
(Xilinx Application Notes XAPP 014.001)

Maximum Clock Frequency

8 bits : 256MHz
16 bits : 108MHz
Ultra-Fast Counter

In this counter, the LS bit Q0 acts as the "prescaler". The effective "clock" rate
provided by this prescaler is 1/2 of the actual clock rate.

In the previous example, the distribution of the CEO signal (from the LS to the MS
tri-bit) introduces a line transmission delay. This counter eliminates the delay by
replicating QO for bits after Q1. This is done by the following chain/network of
flip-flops :
Network To Replicate Q0

To best describe the function of such a network, let's take a look at the timing
diagram depicting the output values :
The Timing Diagram

It is seen that all QX0 outputs are in sync with Q0 after the initial delays. The
effect of this is that bits after Q1 appear to be driven directly by Q0 and without the
line transmission delay. This improves the minimum clock period.

The Second "Prescaler"

Here Q1 and Q2 act as the second "prescaler". This additional prescaler is needed
to accommodate a large counter(more bits). The effective "clock" rate provided by
this prescaler to the rest of the counter is 1/8 of the actual clock rate. This second
prescaling stage allows the rest of the counting circuit to employ the series carry
scheme . The use of such a carry scheme allows a larger counter to be constructed.

From the diagram, CEP2 is pipelined. When the LS three bits are 101(Q2-Q0), the
output of AND gate A is high. Since Q0 is high at this point, the value of A is
selected and appears at the output of multiplexer B. This value is fed to the Flip-
flop input. On the next clock cycle, the value appears as CEP2(high). At this point,
the LS three bits is 110. Since QY01 is low, CEP2 is selected by the multiplexer.
Thus, on the next clock cycle, CEP2 is high again. This is summarised below :

Q2 Q2 Q1 A D-input(flip-flop) CEP2

1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 0 1 1
1 1 1 0 0 1
The Shift Register

The Shift Register

The Shift Register is another type of sequential logic circuit that can be used for the storage
or the transfer of data in the form of binary numbers.

This sequential device loads the data present on its inputs and then moves or shifts it to its
output once every clock cycle, hence the name Shift Register.
A shift register basically consists of several single bit D-Type Data Latches, one for each
data bit, either a logic 0 or a 1, connected together in a serial type daisy-chain
arrangement so that the output from one data latch becomes the input of the next latch and so
Data bits may be fed in or out of a shift register serially, that is one after the other from either
the left or the right direction, or all together at the same time in a parallel configuration.
The number of individual data latches required to make up a single Shift Register device is
usually determined by the number of bits to be stored with the most common being 8-bits
(one byte) wide constructed from eight individual data latches.
Shift Registers are used for data storage or for the movement of data and are therefore
commonly used inside calculators or computers to store data such as two binary numbers
before they are added together, or to convert the data from either a serial to parallel or parallel
to serial format. The individual data latches that make up a single shift register are all driven
by a common clock ( Clk ) signal making them synchronous devices.
Shift register ICs are generally provided with a clear or reset connection so that they can be
SET or RESET as required. Generally, shift registers operate in one of four different
modes with the basic movement of data through a shift register being:
Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a
time, with the stored data being available at the output in parallel form.
Serial-in to Serial-out (SISO) - the data is shifted serially IN and OUT of the
register, one bit at a time in either a left or right direction under clock control.
Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time under clock control.
Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into the
register, and transferred together to their respective outputs by the same clock pulse.
The effect of data movement from left to right through a shift register can be presented
graphically as:

Also, the directional movement of the data through a shift register can be either to the left,
(left shifting) to the right, (right shifting) left-in but right-out, (rotation) or both left and right
shifting within the same register thereby making it bidirectional. In this tutorial it is assumed
that all the data shifts to the right, (right shifting).

Serial-in to Parallel-out (SIPO) Shift Register

4-bit Serial-in to Parallel-out Shift Register

The operation is as follows. Lets assume that all the flip-flops ( FFA to FFD ) have just been
RESET ( CLEAR input ) and that all the outputs QA to QD are at logic level 0 ie, no parallel
data output.
If a logic 1 is connected to the DATA input pin of FFA then on the first clock pulse the
output of FFA and therefore the resulting QA will be set HIGH to logic 1 with all the other
outputs still remaining LOW at logic 0. Assume now that the DATA input pin of FFA has
returned LOW again to logic 0 giving us one data pulse or 0-1-0.
The second clock pulse will change the output of FFA to logic 0 and the output
of FFBand QB HIGH to logic 1 as its input D has the logic 1 level on it from QA. The
logic 1 has now moved or been shifted one place along the register to the right as it is
now at QA.
When the third clock pulse arrives this logic 1 value moves to the output of FFC ( QC ) and
so on until the arrival of the fifth clock pulse which sets all the outputs QA to QDback again to
logic level 0 because the input to FFA has remained constant at logic level 0.
The effect of each clock pulse is to shift the data contents of each stage one place to the right,
and this is shown in the following table until the complete data value of 0-0-0-1is stored in
the register. This data value can now be read directly from the outputs of QAto QD.
Then the data has been converted from a serial data input signal to a parallel data output. The
truth table and following waveforms show the propagation of the logic 1 through the
register from left to right as follows.

Basic Data Movement Through A Shift Register

Note that after the fourth clock pulse has ended the 4-bits of data ( 0-0-0-1 ) are stored in the
register and will remain there provided clocking of the register has stopped. In practice the
input data to the register may consist of various combinations of logic 1 and 0.
Commonly available SIPO ICs include the standard 8-bit 74LS164 or the 74LS594.

Serial-in to Serial-out (SISO) Shift Register

This shift register is very similar to the SIPO above, except were before the data was read
directly in a parallel form from the outputs QA to QD, this time the data is allowed to flow
straight through the register and out of the other end. Since there is only one output,
the DATA leaves the shift register one bit at a time in a serial pattern, hence the name Serial-
in to Serial-Out Shift Register or SISO.
The SISO shift register is one of the simplest of the four configurations as it has only three
connections, the serial input (SI) which determines what enters the left hand flip-flop, the
serial output (SO) which is taken from the output of the right hand flip-flop and the
sequencing clock signal (Clk). The logic circuit diagram below shows a generalized serial-in
serial-out shift register.
4-bit Serial-in to Serial-out Shift Register

You may think whats the point of a SISO shift register if the output data is exactly the same
as the input data. Well this type of Shift Register also acts as a temporary storage device or it
can act as a time delay device for the data, with the amount of time delay being controlled by
the number of stages in the register, 4, 8, 16 etc or by varying the application of the clock
pulses. Commonly available ICs include the 74HC595 8-bit Serial-in to Serial-out Shift
Register all with 3-state outputs.

Parallel-in to Serial-out (PISO) Shift Register

The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-
out one above. The data is loaded into the register in a parallel format in which all the data
bits enter their inputs simultaneously, to the parallel input pins PA to PD of the register. The
data is then read out sequentially in the normal shift-right mode from the register
at Q representing the data present at PA to PD.
This data is outputted one bit at a time on each clock cycle in a serial format. It is important
to note that with this type of data register a clock pulse is not required to parallel load the
register as it is already present, but four clock pulses are required to unload the data.

4-bit Parallel-in to Serial-out Shift Register

As this type of shift register converts parallel data, such as an 8-bit data word into serial
format, it can be used to multiplex many different input lines into a single serial DATA stream
which can be sent directly to a computer or transmitted over a communications line.
Commonly available ICs include the 74HC166 8-bit Parallel-in/Serial-out Shift Registers.
Parallel-in to Parallel-out (PIPO) Shift Register
The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of shift
register also acts as a temporary storage device or as a time delay device similar to the SISO
configuration above. The data is presented in a parallel format to the parallel input
pins PA to PD and then transferred together directly to their respective output pins QA to QA by
the same clock pulse. Then one clock pulse loads and unloads the register. This arrangement
for parallel loading and unloading is shown below.

4-bit Parallel-in to Parallel-out Shift Register

The PIPO shift register is the simplest of the four configurations as it has only three
connections, the parallel input (PI) which determines what enters the flip-flop, the parallel
output (PO) and the sequencing clock signal (Clk).
Similar to the Serial-in to Serial-out shift register, this type of register also acts as a
temporary storage device or as a time delay device, with the amount of time delay being
varied by the frequency of the clock pulses. Also, in this type of register there are no
interconnections between the individual flip-flops since no serial shifting of the data is

Universal Shift Register

Today, there are many high speed bi-directional universal type Shift Registersavailable
such as the TTL 74LS194, 74LS195 or the CMOS 4035 which are available as 4-bit multi-
function devices that can be used in either serial-to-serial, left shifting, right shifting, serial-
to-parallel, parallel-to-serial, or as a parallel-to-parallel multifunction data register, hence the
name Universal.
These universal shift registers can perform any combination of parallel and serial input to
output operations but require additional inputs to specify desired function and to pre-load and
reset the device. A commonly used universal shift register is the TTL 74LS194 as shown
4-bit Universal Shift Register 74LS194

Universal shift registers are very useful digital devices. They can be configured to respond to
operations that require some form of temporary memory storage or for the delay of
information such as the SISO or PIPO configuration modes or transfer data from one point to
another in either a serial or parallel format. Universal shift registers are frequently used in
arithmetic operations to shift data to the left or right for multiplication or division.

Shift Register Tutorial Summary

Then to summarise a little about Shift Registers
A simple Shift Register can be made using only D-type flip-Flops, one flip-Flop for
each data bit.
The output from each flip-Flop is connected to the D input of the flip-flop at its right.
Shift registers hold the data in their memory which is moved or shifted to their
required positions on each clock pulse.
Each clock pulse shifts the contents of the register one bit position to either the left or
the right.
The data bits can be loaded one bit at a time in a series input (SI) configuration or be
loaded simultaneously in a parallel configuration (PI).
Data may be removed from the register one bit at a time for a series output (SO) or
removed all at the same time from a parallel output (PO).
One application of shift registers is in the conversion of data between serial and
parallel, or parallel to serial.
Shift registers are identified individually as SIPO, SISO, PISO, PIPO, or as a Universal
Shift Register with all the functions combined within a single device.
In the next tutorial about Sequential Logic Circuits, we will look at what happens when the
output of the last flip-flop in a shift register is connected directly back to the input of the first
flip-flop producing a closed loop circuit that constantly recirculates the data around the loop.
This then produces another type of sequential logic circuit called a Ring Counter that are
used as decade counters and dividers.

The D-type Flip Flop

The JK Flip Flop
Sequential Logic Circuits

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