A redundant binary (RB) representation is used for designing high performance multiplier. Because of its high modularity and carry free addition. The error correcting word (ECW) plays an important role in redundant binary multiplier. The redundant binary (RB) coding and modified booth (MB) encoding creates the error correcting word. The extra error correcting is eliminated by combining the error correcting word into partial product (PP) row. Therefore it saves RBPP accumulation stage. In conventional method, the final addition is carried out by carry select adder (CSA). In the proposed method the parallel prefix adder used. The simulation result shows the significant improvement in area and power when compared with existing RB multiplier.

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A redundant binary (RB) representation is used for designing high performance multiplier. Because of its high modularity and carry free addition. The error correcting word (ECW) plays an important role in redundant binary multiplier. The redundant binary (RB) coding and modified booth (MB) encoding creates the error correcting word. The extra error correcting is eliminated by combining the error correcting word into partial product (PP) row. Therefore it saves RBPP accumulation stage. In conventional method, the final addition is carried out by carry select adder (CSA). In the proposed method the parallel prefix adder used. The simulation result shows the significant improvement in area and power when compared with existing RB multiplier.

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Prefix Adder

Maria Baby. R1 Priya L. R2

1

P.G Scholar 2Associate Professor

1,2

Francis Xavier Engineering College, Tirunelveli

Abstract A redundant binary (RB) representation is used Twos complement multiplier is designed in [6]. The

for designing high performance multiplier. Because of its technique is presented to reduce the partial product array by

high modularity and carry free addition. The error correcting one from the maximum height of the array. This technique is

word (ECW) plays an important role in redundant binary suitable for any square, n x l regular multiplier and high radix.

multiplier. The redundant binary (RB) coding and modified The regular partial product array is generated using redundant

booth (MB) encoding creates the error correcting word. The binary tree [5]. Two types of multipliers are designed, they

extra error correcting is eliminated by combining the error are MBE multiplier and post truncated multiplier. Two

correcting word into partial product (PP) row. Therefore it multipliers have significant improvement in area, delay and

saves RBPP accumulation stage. In conventional method, the power consumption. An efficient reverse converter [7] is

final addition is carried out by carry select adder (CSA). In presented for transforming the redundant binary (RB)

the proposed method the parallel prefix adder used. The representation into twos complement form. The carry

simulation result shows the significant improvement in area equation for the reverse conversion algorithm creates a

and power when compared with existing RB multiplier. regular multilevel structure, from which a high-speed hybrid

Key words: modified booth encoding, partial product row, carry-look ahead/ carry-select (CLA/CSL) architecture is

error correcting word proposed to fully exploit the redundancy of RB encoding for

VLSI efficient implementation.

I. INTRODUCTION In the next section we will discuss about the related

This paper describes the low power redundant binary work for radix 4 and the modified booth encoding scheme. In

multiplier. In VLSI digital multipliers plays as an important section III, we will explain the existing system and section IV

role in arithmetic units of microprocessor, multimedia and explaining the proposed system. In section V, result and

digital signal processor. To design a high speed and low discuss is explained and in section VI, the references will be

power multiplier many algorithms and architectures are used. added in section VII.

The multiplication takes low time consuming and low power

consuming compared with other arithmetic operation. The II. RELATED WORK

repeated addition is called multiplication. In generally the A. Modified Booth Encoding:

multiplication process has three steps. The partial products

Modified booth encoding scheme is introduced for reduce the

are generated in the first step. In the second step, the partial

partial product by half. This technique is also called as Radix-

products are reduced using either compressor or the

4 Booth Encoding. The high speed floating point processors

redundant binary representation. In the third step, the reduced are designed using this technique. Multiplication process

partial product row is added using any high speed adder. The consists of multiplicand and multiplier bits. Therefore X= xn-

redundant binary is used because of its high modularity and

1 xn-2....x2 x1 x0 stands for multiplicand bits, and Y= yn-1

carry-free addition. The RB multiplier has four modules: the

yn-2.... y2 y1 y0 stands for multiplier bits. From that the

booth encoder, RB decoder, RB accumulator and the last one

multiplier bits are grouped into three and produce the one

is RB-to-NB converter.

multiplier bit in Radix-4 Booth Encoding, therefore the

The high speed digital multiplier uses the redundant partial product row reduced by half.

binary representation. It is the signed number representation From the below table clearly explain a grouping of

introduced by Avizienis [1] in 1961. Signed numbers are the

the multiplier bits, where x describes the multiplicand bit.

different group of number representation, when addition or

The operation includes -1,-2 means 1s and 2s complement

subtraction is performed it limits the carry propagation. This

of the multiplicand bits. The obtained partial products rows

number is not suitable for overflow detection, round off and are shifted by 2-position and then placed. The height of the

multiple precision operation. The multiple- level partial product array is (N/2).

conditional-sum adder (MLCSMA) is introduced in [2] in

2000. With a use of this adder speed improved in 25% and B. Error Correcting Word:

the delay is reduced by 8%. The tows complement The error correcting word is formed by modified booth

conversion algorithm is introduced in [3With the use of this encoding and redundant binary coding. In redundant binary

algorithm the speed is increased in 13% and power is coding the error is formed at each stage of converting normal

improved by 14%.The new RB booth encoding scheme is binary into redundant binary numbers. When the multiplier

introduced in [4]. The partial products are formed by polarize bit has the value of -1 or -2, it requires the error value to

two adjacent booth encoding digits. The high radix scheme is produce the correct value. The error correcting word is

used for reduce the partial product row by four. The high usually written in the form of

radix posses a hard multiple and high complexity in nature. ECW= E 0 F 0 E 0 F. . . .

With the use of new scheme achieve speed 14% and 17%

energy delay product.

A Low Power Design of Redundant Binary Multiplier using Parallel Prefix Adder

(IJSRD/Vol. 4/Issue 04/2016/077)

Table 2: RB Encoding

In CRBBE-2, we use redundant binary representation and

booth encoding scheme. Modified Booth encoding algorithm

is an easy way to reduce the number of partial products by

grouping bits in one of the two operands to form the negative

multiples. The bit that is Booth encoded is called the

multiplier and the other operand is called the multiplicand. In

Table 1: Radix-4 Mbe this multiplier it has N/4 RBPP rows and one error correcting

Where, E represents the error due to booth coding word. Generally the EWC is explained by

and F term represents the error due to redundant binary EWC= E (N/4) 0 F (N/4) . . . 0 E1 0 F1

coding. The E term has two values 0 and 1.when the Where, ECW has two terms. First term is E it stands

multiplier bit is -1 or -2, the error bit is 1 otherwise the value for booth encoding and it has two values (0, 1). Second term

is 0. The F term also has two values 0 and -1. When is F, it stands for RB encoding and it has two values (0, -1). .

converting the normal binary into redundant binary the error The block diagram of conventional method is shown below.

value is -1 otherwise the value is 0. Due to the error correcting It has four stages

word the accumulation stage is increased. The accumulation

stage is finding by power of two word length (2n bit). The

number of RBPP accumulation stage (NRBPPAS)

NRBPPAS = [log2 (N/4+1)]

= n-1, if N=2n

For 8-bit multiplication the accumulation stage is

NRBPPS = n-1; N=23

= 3-1=2

2 accumulation stages are required for 8-bit

multiplication. Similarly 34-bit multiplication requires 4

accumulation stages. If the error correcting word is removed

from the multiplication then the accumulation stage is Fig. 1: Block Diagram of Existing System

reduced to 3 and 25% of memory is saved. The 24X24 and In the existing system we use a major adder of carry

54X54 bit multiplication does not have an error correcting select adder. The carry select adder comes in the category of

word; the ECW is existing only on regular matrix. conditional sum adder. Conditional sum adder works under

particular condition. The carry select adder has three blocks

C. RB Encoding: .they are two adder unit and one multiplexer. The addition

The RB coding is used to generate the RB partial product. performed in two ways, in first method assuming first adder

Each digit must be converted to the sign and correct value carry as zero. Second one is assuming second adder carry as

with the use of OR-gate and Exclusive-OR-gate that increase zero. Initially adder assumes carry value is 1 and prior value

the hardware and delay time. In our RB architecture, two NB is 0.when the multiplier obtains the input it finds the original

number creates the RB partial product only by inverting one value of sum and carry. The earlier carry select adder has two

of the pair. No additional hardware is needed. types adders, one uses ripple carry adder for least significant

The two normal binary bits are used to represents bit (LSB) and another uses binary one for most significant bit

one RB digit. The RB digit only consists of three numbers (MSB).

they are (0, 1, and -1). If both binary words are zero or one The two adders assume two carry value for

then the RB digit is zero. If the binary word has alternative calculating sum value. The least significant adder used for

value the RB digit is has the value of 1 or -1. The -1 is nothing obtaining the final sum and carry value. The fastest adder is

but a complement operation. carry select adder (CSLA) and it is mainly used for cal

In the proposed system, we introduce new algorithm. The RB

number has the capability to be represented in different ways.

Fast multipliers can be designed using redundant binary

addition trees.

A Low Power Design of Redundant Binary Multiplier using Parallel Prefix Adder

(IJSRD/Vol. 4/Issue 04/2016/077)

Combine the ECW2 into partial product rows and

generate the new partial product elements .after this stage

final addition is performed using parallel prefix adder

The proposed system output is verified using xilinx and

quartus 2 software. The schematic diagram of proposed booth

algorithm is shown below and it e has five inputs are X ,Y ,

INPUT VALID ,CLK and RST and the outputs are decode,

encode and final out. Its nothing but a product of the

multiplication

The redundant binary representation has also been

applied to a floating-point processor and implemented in

VLSI. High performance RB multipliers have become

popular due to the advantageous features, such as high

modularity and carry-free addition. A RB multiplier consists Fig. 4: simulation result for proposed method

of a RB partial product (RBPP) generator, a RBPP reduction The ordinary booth coding simulation was done

tree and a RB-NB converter. A Radix-4 Booth encoding or a using Xilinx and the output was verified. The result has been

modified Booth encoding (MBE) is usually used in the partial obtained for the input x = 38, y =- 47, clk=1, rst=1 and input

product generator of parallel multipliers to reduce the number valid =1and the output as 1786. The encoding value is

of partial product rows by half. The block diagram for 11001100000000 and the decoding value is 00000110

proposed system is shown bellow The area and power is evaluated using a quartus II

tool and the outputs are shown below; the area is reduced up

to 50% from the conventional one.

The proposed RBMPPG based designs significantly

improve the area and power consumption when the word Fig. 5: Area analysis

length has above 32 bits; the conventional NB multiplier The power is also reduced when the number of total

design has delay about 5%. The power-delay product can be used and the total logic elements. Total pins usage is also

reduced by up to 59% when using the proposed RB reduced with the use of new redundant binary scheme

multipliers compared with existing RB multipliers. In

proposed system the error correcting word is given by

ECW= E12 0 F12 0 E22 0 F22

The error correcting word is splited into two ECW1

and ECW2. ECW1 is expressed as

ECW1= 0 E12 0 F12

The ECW2 (also defined as an extra ECW) is

expressed as

A Low Power Design of Redundant Binary Multiplier using Parallel Prefix Adder

(IJSRD/Vol. 4/Issue 04/2016/077)

covalent redundant binary Booth encoder, in Proc.

IEEE Int. Symp. Circuits Syst. (ISCAS), vol. 1, pp. 69

72, 2005

[7] G. Dimitrakopoulos and D. Nikolos, High-speed

parallel prefix VLSI Ling adders, IEEE Trans.

Computers, vol. 54, pp. 225-231, 2005.

VI. CONCLUSION

A new redundant binary multiplier was designed with

modified partial product generator. This multiplier eliminates

the extra error correcting word that is introduced by both RB

coding and modified booth encoding. Therefore the partial

product row reduced from N/4+1 to N/4. It also saves one

RBPP accumulation stage. The proposed design uses high

efficient parallel prefix adder. Therefore we got significant

improvement in area and power consumption compared with

existing RB multiplier.

A redundant binary (RB) representation is used for

designing high performance multiplier. Because of its high

modularity and carry free addition. The error correcting word

(ECW) plays an important role in redundant binary

multiplier. The redundant binary (RB) coding and modified

booth (MB) encoding creates the error correcting word. The

extra error correcting is eliminated by combining the error

correcting word into partial product (PP) row. Therefore it

saves RBPP accumulation stage. In conventional method, the

final addition is carried out by carry select adder (CSA). In

the proposed method the parallel prefix adder used. The

simulation result shows the significant improvement in area

and power when compared with existing .

REFERENCES

[1] F. Lamberti, N. Andrikos, E. Antelo, and P. Montuschi,

Reducing the computation time in (short bit-width)

twos complement multipliers, IEEE Trans.

Computers, vol. 60, pp. 148- 156, 2011.

[2] S. Kuang, J. Wang, and C. Guo, Modified Booth

multiplier with a regular partial product array, IEEE

Trans. Circuits Syst.II, vol. 56, pp. 404-408, 2009.

[3] Y. He and C. Chang, A new redundant binary Booth

encoding for fast 2n-bit multiplier design, IEEE Trans.

Circuits Syst. I, Reg. Papers, vol. 56, pp. 1192 1199,

2009.

[4] Y. He and C. Chang, A power-delay efficient hybrid

carry look-ahead carryselect based redundant binary to

twos complement converter, IEEE Trans. Circuits

Syst. I, Reg. Papers, vol. 55, pp. 336346, 2008

[5] J. Kang and J. Gaudiot, A simple high-speed multiplier

design, IEEE Trans. Computers, vol. 55, pp.1253-1258,

2006.

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