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A110 MIDAS: « Multi-standard Integrated

Devices for broadband DSL Access and
www.medeaplus.org
home powerline communicationS »

Objectives
. Consortium &. Organization

‰ To develop new wireline communication systems and architectures with
increased bandwidth, capacity, security and QoS
¾ New DSL: ADSL2, ADSL2+, symmetric DSL (10MDSL, Ethernet over DSL)
¾ New broadband PLC for in-home networking
‰ To work on mechanisms, protocols and associated architectures for
MAC, QoS, Security/Safety and user Privacy
‰ To develop and manufacture low-power and cost-effective components
for wireline communication devices
‰ To develop wireline integrated platforms bridging xDSL and PLC and
demonstrate these platforms in the field
‰ To participate to international standardization and promote the
technologies and concepts developed in the project Pisa

‰ To work on the convergence of wireline communication technologies

Value . chain
• 16 partners
Universities Research institutes • Start date: 1 July 2003
– End date: 30 June 2005
KULeuven,
KULeuven, LTH, IMEC, Project leader
ENS, IMSE-
IMSE-CNM France Telecom R&D PCC STM Belgium
• Budget : ± 177 person.years
Algorithms,
Algorithms, architecture concepts,
feasibility studies • Countries involved:
Belgium, France, Spain, Sweden

System
System
requirements
requirements
System Equipment Target DS2 Alcatel STM B Thomson B

Manufacturers Enabling design
Multi-standard
Security/Safety Building blocks
methodologies & Next generation
Alcatel, Thomson, Ericsson, Veyado, & & platform
flexible SoC xDSL and PLC
Seba service, Upzide Labs,
Labs, LEA Feedback on System Quality of Service chipsets demonstrators
design tools
Test chips, chip sets performances
System Platforms and ‰ soft generation of analog ‰ next generation xDSL & PLC ‰ security/safety issues related ‰ line drivers ‰ integrated access platforms
requirements and Specs demonstrators IP blocks systems and architectures to life-line support, remote and gateways
‰ high speed converters
powering and maintenance
‰ versatile Application ‰ novel advanced DSP ‰ demonstration and tests
‰ integrated analogue front-ends
Specific Signal Processor algorithms ‰ network traffic models
‰ Real time VDSL loop emulator
‰ digital building blocks
‰ Fast prototyping ‰ advanced error correction ‰ spectrum regulation and based on digital techniques
‰ active splitters
Design houses and Operators ‰ Co-emulation codes for improved
performances
management
‰ bonding & inverse multiple
chipmakers France Telecom
access
‰ higher layer protocols
DS2, Target, ST, Thomson

Activities. in WP1
« Enabling design methodologies and tools for Graphical
the design of flexible Wireline IPs and SoC » debugger on
host computer

¾ Contributors:
Contributors:
ƒ Target (B), ST (B), ESAT-
ESAT-KUL (B), IMSE-
IMSE-CNM (SP), DS2 (SP)
¾ Responsible:
Responsible: API (Tcl/TK, C++)

ƒ Target (B) ISS JTAG bit streams
kernel
¾ Activities:
Activities:
TCP/IP socket
ƒ A.1.1: Methodologies and tools for soft generation of analog IP blocks
ƒ A.1.2: Methodologies and tools for design of versatile Application Specific
JTAG
Signal Processor (ASSP) ctrler
ƒ A.1.3: Methodologies and tools for fast-
fast-prototyping and co-
co-emulation Hardware
Debug Target
ctrler core

On chip debugging support Co-simulation environment

Activities. in WP2
« Next generation xDSL and PLC, new advanced DSP algorithms and Tester
Noise injection (ANSI norm)

error correction codes for DSL and PLC improved performances » Noise File

Twisted copper wire
Noise Generator50
Ω 120Ω

1kΩ 1kΩ

¾ Contributors:
Contributors: liaison SDSL
Customer SDSL modem

ƒ DS2 (SP), ST (B), Ericsson (Sw), France Telecom R&D (F), LTH (Sw), Impulsive noise injection for xDSL transmission
ENS (F), Thomson (B), LEA (F) SNR with RFI − loop 54
Data rate 30

¾ Responsible:
Responsible: [Mbits/sec]
25

ƒ DS2 (Spain
(Spain)) 60

¾ Activities:
Activities: 20

ƒ A2.1: Study of next generation xDSL systems and architectures
dB

15

VDSL
ƒ A2.2: Study of next generation PLC systems and architectures ADSL2+ 10

ADSL2
8
ƒ A.2.3: Study of new advanced DSP algorithms and 5
ADSL
ADSL
advanced Error correction codes 24
48

for DSL and PLC improved performances 2 SHDSL ADSL/R 0
dec−24

120 130 140 150 160 170 180 190 200 210
tone

1 km 2 km 3 km 4 km 5 km RFI cancellation by powerfull PTEQ In-home scenario for next generation PLC

STMicroelectronics Belgium N.V. For further information,
Industriepark Keiberg please contact Project Leader:
Excelsiorlaan 44-46 Patrick Wouters
B-1930 Zaventem, Belgium patrick.wouters@st.com
http://www.st.com
With thanks to all MIDAS partners
MEDEA+ Forum 2004, 23-24 November, Paris, France