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Polytechnic University of Puerto Rico
Mechanical engineering department
Mechatronics ME-5250

Professor: Sandra L. Ordóñez.

Digital Logic

Many controls systems use digital circuits and digital logic basis. For example, all the
computer’s processes run based in two states (1, 0).

1. Number systems
Table 1 summarize the number systems

Table 1. Number systems

Name Base Symbol
Decimal 10 None or D
Binary 2 B or bin
Octal 8 Q or O
Hexadecimal 16 H

1.1. Decimal system
The decimal system is based on the use of 10 symbols or digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9.
Since we have been using this system all our lives, we just use it without thinking in its
representation and weight each of the digits. However, this system uses weighted digits
according to its position in the number. The least important digit will be the digit in the right
(the units) of the number, and the most important will be the digit at the left. A number
represented in the decimal system uses the following notation:

10n … 103 102 101 100 units
thousands hundreds tens

If we want to represent not-integer numbers, we can use the same base (10) but with negative
exponents:

10-1 10-2 10-3

0.1 0.01 0.001

Example 1
Represent the number 187D  1x102 + 7x101 + 8x100 = 1x100 + 7x10 +8x1 = 178D

Example 3. Bit if it is 1 bit. 1 0 1 1 0 0 1 0 MSB LSB To convert a binary number into a decimal number. and the most significative bit (MSB) is the bit in the left. Page 2 of 16 1. The first remainder will be the LSB and the last remainder will be the MSB. Example 2. Byte 8. Binary system The binary system is based on two symbols or states: 0 and 1. and with the remainder we organize the binary number. 1 0 1 1 0 0 1 0 27 26 25 24 23 22 21 20 128 +0 +32 +16 +0 +0 +2 +0 = 178 If we want to convert a number from decimal to binary we have to divide repetitively (until the quotient is 0) using the base 2. The least significative bit (LSB) is the right.2. When a number is represented by this system. . Word 16 and Double-word 32. each of the state is called a bit or digit. Decimal to binary conversion Convert the decimal number 178D to binary Number Quotient Remainder Binary number 178 2 178 89 0 0 18 89 2 0 09 89 44 1 10 44 2 1 04 22 44 22 0 010 2 0 02 22 11 0 0010 11 2 0 1 11 5 1 10010 5 2 5 2 1 110010 2 2 2 1 0 0110010 0 1 2 1 0 1 10110010 1 0 According to the quantity of bits in a binary number it receives a name. each bit is multiplied by a power of 2 (starting with the LSB multiplied by 2 0. and the exponent will be increased by 1 for each bit) and the results will be summed. Table 2 shows some equivalence between the first sixteen decimal numbers and its binary code. Nibble 4. Binary to decimal conversion Convert the binary number 10110010B to a decimal number. Those bits have a weight according to its position.

5.3. Octal system The octal system is based on eight digits: 0. Example 4. that it is only a 3 bit representation. This is because the octal number system uses the digits 0-7. We have to divide repetitively (until the quotient is 0) using the base 8. 6. Octal to decimal conversion Convert the octal number 4755Q to decimal 4 7 5 5 4x8 + 7x8 + 5x8 + 5x80 3 2 1 4x512 + 7x64 + 5x8 + 5x1 = 2541D Example 5. The first remainder will be the LSB and the last remainder will be the MSB. 2. Decimal equivalent of some binary numbers Decimal Binary Decimal Binary Decimal Binary Decimal Binary 0 0000 4 0100 8 1000 12 1100 1 0001 5 0101 9 1001 13 1101 2 0010 6 0110 10 1010 14 1110 3 0011 7 0111 11 1011 15 1111 1. 4. The octal word can be converted to the decimal system similarly to the conversion from the binary system but it should be used the base 8. Convert the decimal number 2541D to octal Number Quotient Remainder Octal number 2541 8 2541 317 5 5 14 317 8 61 77 317 39 5 55 5 39 8 5 7 4 39 4 7 755 8 4 0 4 4755 4 0 Example 6. Convert the binary number 100111101101B to octal 100 111 101 101 4 7 5 5  4755Q Example 7. 7. Binary to octal conversion To convert a binary number to an octal number we have to separate the binary number into sections of 3 bits. but using base 8 instead of 2. Decimal to octal conversion To convert a decimal number into an octal number we use the same procedure used to convert a decimal number into a binary number. We have to separate the sections from the LSB to the MSB and then we convert from binary (3 bits) to decimal. 3. 1. Page 3 of 16 Table 2. This system is old and it is rarely used today. and 7 can be represented in binary by 111. Octal to binary conversion . and with the remainder we organize the binary number.

E. Table 3. Hex. 8. Page 4 of 16 To convert an octal number into a binary number. Binary Dec. C. we just separate the digits of the number and convert each digit to its binary equivalent. 9. Decimal to Hexadecimal conversion To convert a decimal number into a Hexadecimal number we use the same procedure used to convert a decimal number into a binary number. F. The hexadecimal word can be converted to the decimal system similarly to the conversion from the binary or octal system but using base 16. Table 3 shows the equivalent of the digits/letters used in the hexadecimal system to the decimal and binary system. We have to divide repetitively (until the quotient is 0) using the base 16. Binary 0 0 0000 4 4 0100 8 8 1000 12 C 1100 1 1 0001 5 5 0101 9 9 1001 13 D 1101 2 2 0010 6 6 0110 10 A 1010 14 E 1110 3 3 0011 7 7 0111 11 B 1011 15 F 1111 Example 8. Binary Dec. Binary Dec. 3. Hexadecimal system The hexadecimal system is based on 16 digits that are the 10 digits from the decimal system and 6 letters: 0. Convert the decimal number 2541D to hexadecimal Remainder Hexadecimal 2541 16 Number Quotient 94 number 158 16 141 14 2541 158 13 D 13 9 16 158 9 14 ED 9 0 9 0 9 9ED Example 10. Hexadecimal equivalent of some decimal and binary numbers Dec. A. Convert the octal number 4755Q to binary 4 7 5 5 100 111 101 101  100111101101B 1. D. Binary to Hexadecimal conversion . 6. Hexadecimal to decimal conversion Convert the octal number 9EDH to decimal 9 E D 9x162 +Ex161 +Dx160 9x256 + 14x16 + 13x1 = 2541D Example 9. The first remainder will be the LSB and the last remainder will be the MSB. 5. and with the remainder we organize the binary number. 7. Hex. Hex. Hex. 4.4. 2. but using base 16 instead of 2. 1. B.

The one complement is obtained changing all the bits to its opposite (all the 1s to 0s. to represent the decimal number 13 in BCD we represent 1 in binary and 3 in binary. 0 to represent a positive number and 1 to represent a negative number. This is because the hexadecimal number system uses the digits 0-F (being FH = 16D). For example. The two complement is obtained adding 1 to the one complement. and its two complement will be: 101 0101 Signing and summing the two numbers: 0011 1001 . Convert the hexadecimal number 9EDH to binary 9 E D 1001 1110 1101  100111101101B 1. and all the 0s to 1s). Convert the binary number 100111101101B to hexadecimal 1001 1110 1101 9 E D  9EDH Example 11. and FH can be represented in binary by 1111. 1dec = 0001bin 3dec = 0011bin  13dec = 0001 0011BCD 2. Binary mathematics Rules: 0+0=0 0–0=0 0+1=1 1–0=1 1 + 1 = 10 = 0 + carry 1 1–1=0 0 – 1 = 1 + borrow 1 To represent the sign of a binary number an additional bit can be used before the MSB. we just separate the digits of the number and convert each digit to its binary equivalent. For example. BCD system (Binary coded decimal system) This system does not have a base. to subtract 43D (010 1011bin) from 57D (0011 1001bin): The one complement of 43D will be 101 0100. that it is only a 4 bit representation. Page 5 of 16 To convert a binary number to a hexadecimal number we have to separate the binary number into sections of 4 bits. Hexadecimal to binary conversion To convert a hexadecimal number into a binary number. and each decimal digit is represented by 4 bits (binary). We have to separate the sections from the LSB to the MSB and then we convert those sections from binary (4 bits) to decimal.5. To calculate the subtraction of binary numbers it is used the two complement.

NOT AND A Q (OUTPUT) A B Q (OUTPUT) 0 1 A AB 0 0 0 A A 1 0 B 0 1 0 1 0 0 1 1 1 OR A B Q (OUTPUT) NAND A B Q (OUTPUT) A 0 0 0 A AB 0 0 1 A+B B 0 1 1 B 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 NOR A B Q (OUTPUT) XOR A B Q (OUTPUT) A 0 0 1 A A+B 0 0 0 A+B B B 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 0 1 . AND. NAND. NOT. and a special gate (XOR or Exclusive OR). OR. 4. NOR. NOR that means Not- OR). four or more inputs. XOR Gates Below you can observe the basic logic gates (AND.1. Parity In order to detect transmission errors an additional bit is used at the beginning of the binary word to indicate the parity of the 1s of the word. All the gates shown below have only 2 inputs. but they also exist with three. Logic Gates 4. 3. An even-parity number represents an even number of 1s (including the parity bit). Additionally. Page 6 of 16 1101 0101 0000 1110 + carry 1 (this bit is usually ignored). and an odd-parity number represents an odd number of 1s in the word (including the parity bit). while OR is a sum). OR. the complements of this gates are presented (NAND that means Not-AND. This method detects only single transmission errors. NOT) with their truth table and the operation that they represent (AND is a multiplication.

while C will be 1 only when A and B are 1. A A C B  Q Figure 2 A B A C Q A B A C Q A B A C Q A B A C Q 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 0 1 0 1 0 0 1 0 0 0 1 1 1 1 1 0 1 1 0 0 Figure 3. we can determine the total output Q that it will be one when either B or C. so you can fill the spaces of the last input column with 0 and 1 as it is shown below in Figure 3. Then. Note that the partial outputs (for example C) do not count as an input so you will not count it as a part of the combinations (in this case we have two inputs and 22 = 4 combinations). Remember that you will have 2 n combinations for n inputs. Then. you fill it with four zeros and then four ones. partial output and the total output. A B  Q Figure 1 We first name each partial output and create the truth table with one column for each input. The order of the combinations is always the same. Then if you have a third input in the right of those two first inputs. but this time you should put two zeros and two ones as it is shown below in Figure 3. Example 12 Determine the truth table of the logic circuit shown in Figure 1. you fill the input column that it is at the left of the one you filled before. For example. Page 7 of 16 Digital circuits use one or more logic gates connected to each other as it is shown in Figure 1. Then. We can determine the truth table establishing what state will result in each partial output (it is easier if we name each partial output and add a column for its possible states in the truth table) and then determine the total output Q. A that it is the complement of A. we write the possible states (0 or 1) in each column. A will be the opposite of A. or both are 1. and C that it is A AND B. A B A C Q 0 0 1 0 0 0 1 1 1 1 1 0 0 0 0 1 1 0 0 1 . How to create a truth table After determining the possible states of the inputs we start to fill the columns of the partial outputs.

Page 8 of 16 Figure 4 Example 13 Determine the truth table of the logic circuit shown in Figure 5. B and C) we will have 2 3 = 8 possible combinations. A B Q C Figure 5 We first name each partial output and create the truth table with one column for each input. Since we have three inputs (A. partial output and the total output. A D Q B B E C C Figure 6 A B C B C D E Q A B C B C D E Q 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 1 0 0 1 0 0 1 1 1 1 1 1 1 0 0 0 0 1 0 0 Figure 7 .

Boolean algebra properties A A = 0 A0 = 0 A+ A = 1 A1 = A A+A = A A+0 = A AA = A A+1 = 1 1  0.2. and that A  A  B  A What we usually do to simplify a Boolean expression is to associate some variable with its complement so we can turn this part of the expression into 1. Page 9 of 16 4. we can describe each digital circuit with Boolean algebra and simplify it to the smallest expression. Morgan’s Law With this law. Boolean algebra simplification Since each digital gate represent a Boolean operation. Table 4 shows the properties and rules of the Boolean algebra.2. Table 4. C  AB Q C B AB B  Q  A B  BB  A B  B Example 16 Find the simplest Boolean expression for  A  B  C  A  C 1  A  B  C  A  C  A  C  B  C  A  C  A   C  C   B  C  A  B  C 4. 0  1 A=A A+B = B+A A (B+C) = AB+AC AB = BA A+(BC) = (A+B)  (A+C) A+AB = A A+ A B=A+B Example 14 Demonstrate that A  A  B  A  B . you can separate the complement of a product (or sum) into the sum (or product) of the complements of each variable.   A  A  B  A  A   A  B  1   A  B  A  B A  A  B  A  1  B   A  1  A Example 15 Find the simplest Boolean expression for the circuit in shown in Figure 2.1. Boolean algebra has rules and properties as well as the numeric algebra. This law applies both ways as follows: AB AB = = = = . This can be done applying the properties.

2. After determine the expression for each row.  Q  AB C  The only way to simplify this expression is using Morgan’s Law:   Q  AB C  A BC    A   B  C  A   B  C  A  B  C 4. the Boolean expression would have the complement of the element. Boolean function generation from truth tables If we do not have the circuit but we have the truth table. so. each row was expressed as a multiplication of the values of their inputs. the total output Q will be the algebraic sum of the expression that results in a Q = 1 in the truth table. the Boolean expression would have the same element. 0 0 0 AB 0 1 0 AB 1 0 1 AB 1 1 0 AB Figure 8 As you can see. Example 18 Find the simplest Boolean expression for the truth table in Figure 8. If the value of the element is 1. in each row we express the output as the product of the elements (A. the simplest Boolean expression for the truth table in Figure 8 will be Q  A  B Example 19 Find the simplest Boolean expression for the truth table in Figure 9. 0 0 0 AB 0 1 0 AB 1 0 1 AB 1 1 1 AB . B. We choose the expressions that will result in Q = 1 in the truth table (circled in the figure) and then we sum them. In this example we only have one row that will result in Q = 1. Page 10 of 16 AB AB Example 17 Find the simplest Boolean expression for the circuit in shown in Figure 6. etc). A B Q Prod.2. we can still determine a Boolean expression equivalent to that truth table. To do so. but if the value of that element is 0. A B Q Prod.

Page 11 of 16 Figure 9 Following the same procedure applied at Example 18. we will join by pairs (or fourths) the adjacent 1s. we will have 16 spaces.2. In the map. and if we have 8 inputs. This will result in the cancellation of the adjacent different variable (C with C for example). If we have 3 inputs. Example 21 Using a Karnaugh map. that Q is 1 only when A is 1. while the other inputs will remain the same. Karnaugh Maps This is a graphical method to determine the simplest Boolean expression from a truth table. we can determine that Q  A  B  A  B . Example 20 Find the simplest Boolean expression for the truth table in Figure 10. BB A A 1 . 0 0 0 1 ABC Q  A  B  C  A  B  C  A  C  ( B  B)  A  C 0 0 1 0 ABC 0 1 0 1 ABC 0 1 1 0 ABC 1 0 0 0 ABC 1 0 1 0 ABC 1 1 0 0 ABC 1 1 1 0 ABC 0 Figure 10 4. This is 2n where n is the number of inputs. we will mark as 1 the product combination that results in Q = 1.3. The organization of the combinations is predetermined (is always the same). A B C Q Prod. The total output will be the algebraic sum of the products remaining. We can see this in the truth table. this time we have to simplify the expression: Q  A  ( B  B)  A . our Karnaugh map will have 4 spaces. but. Then. If we have two inputs. we will have 6 spaces. determine the simplest Boolean expression for the truth table from Figure 8 (Example 18).

we determined that the expression that will result in Q = 1 was AB . Since there is only one “1”. determine the simplest Boolean expression. A 1 1 Figure 12 Example 23 Using a Karnaugh map. A B C Q Prod. this method simplifies the process and avoids the use of the properties. we put a 1 in the space of the map that represents this. then. 0 0 0 1 ABC CC ABC AB 0 0 1 0 1 0 1 0 1 ABC AB 1 0 1 1 0 ABC AB Q  AC 1 0 0 0 ABC AB 1 0 1 0 ABC 1 1 0 0 ABC 1 1 1 0 ABC 0 Figure 13 As you can see. BB A QA because we will cancel the adjacent different elements ( B with B). Example 22 Using a Karnaugh map. CC AB AB 1 A  B1 1 AB 1 . determine the simplest Boolean expression for the truth table from Figure 10 (Example 20). Page 12 of 16 Figure 11 From the referenced example. the result will be the same: AB . Example 24 Using the Karnaugh map shown in Figure 14. determine the simplest Boolean expression for the truth table from Figure 9 (Example 19).

In this case. then. Example 26 Using the Karnaugh map shown in Figure 16. A and A are one in the intercept with BC. and finally. Page 13 of 16 Figure 14 Since C and C have a one in the intercept with AB then a component of the total output will be AB. the total output Q = AB + AC + BC. determine the simplest Boolean expression. Example 25 Using the Karnaugh map shown in Figure 15. CDCD CD CD AB 1 AB 1 AB 1 1 AB Figure 15 Since D and D have a one in the intercept with ABC then a component of the total output will be ABC. Also. determine the simplest Boolean expression. Another component of the output will come from the ones in the intercept of A B with . The total output Q = ABC + A  C  D. D ) then they can be cancelled originating the output component A B . C  D. B and B are one in the intercept with A  C  D then another component of the total output will be A  C  D. the C and D are connected with their complements C  D. C  D and C  D ( C . CDCDCD CD AB AB 1 AB 1 1 1 AB 1 1 1 1 Figure 16 Since A and A are “1” in the adjacent cells that intercept with B  C  D then one of the components of the output will be B  C  D . and that is the simplest expression equivalent to the Karnaugh map from Figure 15. . and that is the simplest expression equivalent to the Karnaugh map from Figure 14. B and B are one in the intercept with AC. Also.

the outputs do not change until the signal clock enables it. A synchronous flip-flop uses a clock signal to activate or deactivate the outputs. This is. or with the positive edge of the clock signal (when this signal changes from low “0” to high “1”). There are basically three types of flip-flop that are described below. The flip-flop can be activated (or “triggered”) with the state of the clock signal. 5. The “edge triggered” flip-flop are represented with a small triangle in the CLK input. if the inputs change. The basic memory element is the FLIP-FLOP. the only elements that do not have an intercept with its complement are A and C. The asynchronous flip-flop does not use the clock signal then its outputs changes at any moment the inputs do. This will make AC a term for the output expression. 5. The total output Q = B  C  D  A  B  A  C  A  D . In this case. Page 14 of 16 A similar case occurs with the ones in the intercept of A  B with A  B with C  D and C  D . A  B. R Q SET S Q R CLR Q S Q . C  D and C  D will generate the last term of our expression: A  D . The synchronous flip-flops have a third input (CLK). and that is the simplest expression equivalent to the Karnaugh map from Figure 16. This is used in systems that require an output which depends of earlier values of the inputs. SR (Set-Reset) Figure 17 shows the representation of the SR flip-flop and its internal circuit. They are usually represented by a square with two inputs (that are named after the flip-flop name) and two outputs (Q and Q ). Sequential logic This is digital logic with a sequential characteristic.1. All the flip-flop can be asynchronous or synchronous. A  B.

If we put a 1 in the input S (Set) while R = 0. then Q  1  1 = 0. f1 = f/2 f2 = f1/2 = f/4 f3 = f2/2 = f/8 1 SET 1 SET 1 SET 1 SET clock J Q J Q J Q J Q 1 1 1 1 f K CLR Q K CLR Q K CLR Q K CLR Q Figure 19 Since both inputs J and K are 1 always. However. it will be 0 and 0 in the input of the second NOR gate.2. If we now put a 1 in the “reset” terminal (R) and 0 in the “set”. With a 1 in Q . this flip-flop produces an ambiguous result when both inputs (R and S) are 1. while a 1 in the “reset” terminal will reset the outputs (Q = 0. while its signal analysis is represented in Figure 20. . the output Q will change from 0 to 1 and 1 to 0 with the positive edge of the triggered. the output Q will be in the same state as the input J when the CLK enables it. If we put a 1 in the input R and S remains in 0. If the inputs are different (0 and 1 or 1 and 0 respectively). A frequency divider is shown in Figure 19. When both inputs are 1. but the most common application is the frequency divider or what it is the same. With a zero in Q. then the output Q will remain in 0 ( Q  1  1 ). the inputs of the first NOR will be 0 and 1. 5. Q  1 ). Then we have proved that a 1 in the “set” terminal activates the flip-flop (Q = 1. and then. the output will be 0  0  1. the outputs change if the clock signal enables them. the outputs will be Q  1  0  0 and Q  0  0  1 . then the output of the second NOR gate will be Q  1  0  0 and Q = 1. Q  0 ). This can be observed in the signal analysis in Figure 20. a binary counter. Flip-flop JK This type of flip-flop is widely used and it does not have the inconvenient of ambiguous results when the inputs are both 1. This flip-flop has many applications. The representation of this type of flip-flop is shown in Figure 18. we will analyze its internal circuit. Page 15 of 16 Figure 17 To understand how the flip-flop SR works. The circuit initial inputs and outputs are 1. SET J Q K CLR Q Figure 18 When both inputs (J and K) are 0 the inputs do not change.

Flip-flop D This type of flip-flop is called the “basic memory cell”. It stores the value of the data line connected to its terminal D.3. Its name is D after “Data”. The main application of this type of flip-flop is in registers which hold information until is needed. so it is said that the data in transition is “latched”. Figure 21 shows the representation of a D flip-flop. SET D Q CLR Q Figure 21 . Page 16 of 16 f f1 f2 f3 Figure 20 5.