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# NC State University ECE 546 Spring 2017

ECE Department VLSI Systems Design W. Rhett Davis

Homework #7
Problems

1. Hierarchical Design
Work through Layout Tutorial #3 and answer the questions below.
a. Include a plot of your layout in your solution archive (10 points)
b. Include your LVS results (the contents of the file with the extension “.lvs.report”)
in your solution archive (10 points)
c. Include the HSPICE netlists you used for simulation in your solution archive (10
points)
d. What sequences of input vectors did you use to demonstrate the rising and falling
critical-path delays (tpLH and tpHL)? For full credit, these vectors must sensitize
the critical path and have a mix of rising and falling transitions. (10 points)
e. Determine tpLH and tpHL with an HSPICE simulation of your RC-extracted netlist.
(10 points)
2. Dynamic Flip-Flops
Consider the positive-edge triggered TSPC flip-flop shown below. Sketch the transient
response of voltages X, Y, and the output for a positive going clock transition that occurs
after the input goes positive (10 points). Repeat for the input going negative just prior to
the rising clock edge (10 points). Be sure to note on your graphs if a node is high-
impedence (i.e. not pulled high or low).

3. Dynamic Pipelining
Design a pipelined circuit of the function F  ( A  B)(C  D) . Use C2MOS latches (not
flip-flops) and static complementary CMOS gates for the combinational logic between
stages. Remember that a C2MOS latch inverts the input data and that only non-inverting
logic can be placed between pipeline stages. Draw the transistor-level circuit schematics
assuming you are allowed to introduce two pipeline stages between input and output.
Place the latches so that the delay is equally divided between the stages.
Scoring breakdown: partition for equal delay (10 points), non-inverting logic (5 points),
logic function (10 points) schematic (5 points)