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7, JULY 2008

A 65 nm CMOS Multistandard, Multiband TV Tuner

for Mobile and Multimedia Applications
Iason Vassiliou, Member, IEEE, Kostis Vavelidis, Member, IEEE, Nikos Haralabidis, Senior Member, IEEE,
Aris Kyranas, Member, IEEE, Yiannis Kokolakis, Stamatis Bouras, George Kamoulakos,
Charalambos Kapnistis, Member, IEEE, Spyros Kavadias, Member, IEEE, Nikos Kanakaris,
Emmanouil Metaxakis, Christos Kokozidis, and Hamed Peyravi

AbstractThis paper presents a direct conversion, multistan- 900 MHz GSM band in Europe. Deployment in the VHF III
dard TV tuner implemented on a 65 nm digital CMOS process band (170240 MHz) and L-band (14501490 MHz for Europe
occupying less than 7 mm2 . The tuner is compliant with several and 16701675 MHz for USA) is also discussed. T-DMB
digital terrestrial, fixed and mobile TV standards, including
DVB-T, DVB-H, T-DMB, and ISDB-T. It achieves a 3/3.2/3.5 dB (Terrestrial Digital Multimedia Broadcasting) [2], defined in
noise figure at VHF, UHF, and L-band, respectively, while the the VHF III, L-bands and already deployed in Korea, is also
measured sensitivity at UHF for the QPSK-1/2 DVB-T mode is OFDM-based and uses the DAB (Digital Audio Broadcasting)
98 dBm at the PCB connector. The implemented RF front-ends physical layer [3] for mobile TV operation. In Japan, a lower
support both single-ended and differential inputs. An integrated
61 fractional-N synthesizer operating from 1.2 to 1.8 GHz
bandwidth, mobile version of ISDB-T has been deployed using
430 kHz channels in UHF. Finally, several more mobile TV
achieves less than 1 integrated phase error, thus enabling a max-
imum SNR in excess of 37 dB for VHF and UHF. Multistandard standards, both terrestrial and satellite, are emerging world-
capability is also enabled by programmable channel-select filters. wide, such as MediaFLO [4] and ATSC-mobile in the USA,
Power consumption is less than 140 mW in DVB-T mode for all DMB-T and satellite-based CMMB in China. Taking into
three bands. account the above requirements, a multistandard tuner needs
Index TermsDirect conversion, DVB-H, DVB-T, fractional-N to support multiple RF bands, arbitrary channel spacing and
synthesizer, ISDB-T, mobile TV, OFDM, RF CMOS, RF receiver, channel bandwidths from 0.43 to 8 MHz. Furthermore, all
system-on-a-chip (SOC), T-DMB, TV tuner, wireless.
sensitivity, blocking and intermodulation specifications of the
different standards should be met, ideally without sacrificing
I. INTRODUCTION the optimality of the solution.
In addition to multistandard operation, low-cost, low-power
and small physical size required by cellular phones and other
S DIGITAL mobile TV is being deployed in several
A countries using a variety of standards, video reception
becomes the latest feature of multimedia-enriched handheld
mobile terminals necessitates moving into smaller geometries
and integrating more functionality into a single piece of silicon.
High performance radios in nanometer digital CMOS processes,
devices. To allow for user flexibility and enable economies
is a critical step towards single-die implementations of complex
of scale for handset and multimedia terminal manufacturers,
communication and broadcast standards.
multistandard digital video receivers, supporting both mobile
This paper presents the implementation such a radio tuner
and broadcast TV, are desirable.
using a 65 nm digital CMOS process, supporting most popular
In broadcast TV, the most dominant standards expected to
mobile and fixed broadcast TV standards, such as DVB-T/H,
co-exist are DVB-T in Europe, ISDB-T in Japan/Brazil, both
T-DMB and ISDB-T (including one- and three-segment mobile
based on OFDM modulation (orthogonal frequency-division
versions). Section II describes challenges related to mobile TV
multiplexing), and ATSC in USA based on 8-VSB (vestigial
specifications, while Section III gives an overview of the se-
sideband modulation). In mobile TV, the frontrunner appears
lected architecture. The circuit implementation is presented in
to be DVB-H [1], which is an extension of DVB-T. Its main
detail in Section IV, while Section V discusses in depth chal-
features are 1) low-power reception, enabled by operation in
lenges related to the 65 nm process. Finally, detailed measure-
bursts (time-slicing) with a typical 1:10 on/off ratio at the
ment results, including system-level testing with a digital de-
expense of lower resolution and 2) additional error-coding
modulator in a field programmable gate array (FPGA), are pre-
(FEC) for more robust Doppler performance, needed for mo-
sented in Section VI.
bile operation. DVB-H is defined mainly for a portion of the
UHF band, 470750 MHz, to allow interoperability with the II. MULTISTANDARD TUNER DESIGN CHALLENGES
Manuscript received November 28, 2007; revised January 28, 2008.
I. Vassiliou, K. Vavelidis, N. Haralabidis, A. Kyranas, Y. Kokolakis,
To support the terrestrial broadcast TV range of 48900 MHz,
S. Bouras, C. Kapnistis, S. Kavadias, N. Kanakaris, C. Kokozidis, and typical broadcast TV tuners need to address issues related to
H. Peyravi are with Broadcom Hellas S.A., 17455 Alimos, Greece (e-mail: covering several octaves, such as rejection of interference at in- teger multiples of the wanted signal and in-band image rejec-
G. Kamoulakos and E. Metaxakis are with Elxys Innovations, Marousi,
Athens, Greece. tion. These issues have been extensively addressed in the tech-
Digital Object Identifier 10.1109/JSSC.2008.923721 nical literature[5], [6], and typical techniques include using ex-
0018-9200/$25.00 2008 IEEE

ternal RF tracking filters with limited bandwidth that track

the signal carrier [7], or the up-down conversion super-hetero-
dyne architecture [8]. Such tuners tend to be power-hungry and
bulky, which makes them unsuitable for mobile TV. In addition,
covering a range of several octaves with a single RF front-end
requires wideband low-noise amplifiers (LNAs), which usually
have poor noise figure (NF) performance. Since most mobile
TV standards use only a portion of the 48900 MHz broadcast
TV band, namely the VHF III and UHF bands with the addi-
tion of L-band, harmonic rejection requirements are not as se-
vere, thus making direct conversion with multiple RF front-ends
a viable, low-cost, low-power alternative [9][11]. Multiple RF
front-ends also support flexibility in the final implementation,
since depending on the application, it is desirable to support one
or more of the above bands at a time using different antennae
configurations. For example, in cellular phones it may be desir-
able to have two different antennas that support the UHF and
L-band or one antenna supporting UHF only.
Among the radio standards that this implementation is in- Fig. 1. L1 DVB-T/H specification, 1f = 16 MHz for 8 MHz channel spacing.
tended to support, DVB-T and DVB-H pose the most stringent
sensitivity and blocking requirements. In the MBRAI 2.0 spec-
ification [12] for DVB-T/H, a noise figure (NF) below 4 dB is wanted channel, this specification poses stringent analog
required. In addition to the low NF, the 64-QAM modulation filtering requirements. For an 8-MHz channel raster, to
used requires a signal-to-noise ratio (SNR) in excess of 25 dB avoid saturation of the ADC, at least 25 dB attenuation is
in mobile reception conditions (Portable and Doppler channels). needed at 5.25 MHz from the baseband analog filters. In
In OFDM systems, when a high SNR is required, other impair- addition, reciprocal mixing of the LO phase noise with the
ments such as I/Q mismatch and phase noise may affect the picture carrier will also result into in-band interference. To
overall bit-error rate (BER) [13]. To avoid degrading an SNR of meet this specification with at least 3 dB margin, the inte-
25 dB due to additive white Gaussian noise (AWGN), additional grated phase noise from 1.25 to 9.25 MHz offset from the
circuit noise should be at least 10 dB below the AWGN noise LO should less than 60 dBc.
level, which translates into an equivalent SNR of 35 dB when 3) L1 pattern in DVB-T/H: interference from digital and
input signal is not limited by AWGN. To achieve this SNR, an- analog TV, two and four channels away from the wanted
alytical calculations [14] and simulations show that to an rms channel, as depicted in Fig. 1. Since the interferers are
in-band integrated phase noise error of less than 1 ( 37 dBc) defined to be 40 and 45 dB stronger than the wanted
and I/Q phase and gain mismatch of less than 1 and 0.1 dB, 16-QAM signal, taking into account other sources of SNR
respectively, are needed. Since the tuner is continuously tuned degradation, such as NF, and allowing for 3 dB margin,
to a channel, I/Q mismatch can be corrected by blind adaptive this translates into an IIP3 requirement of 5 dBm and an
calibration in the demodulator [15]. NF of less than 8 dB.
Both T-DMB and DVB-T/H standards define several recep- Additional challenges include the presence of GSM interfer-
tion conditions in the presence of other interfering TV channels, ence from a cell-phone up-link in DVB-H, which calls for high
some of which have significant impact on the tuner specifica- LNA linearity and filtering. Given the requirements for low cost
tions. Some of the most significant are the following [2], [12]: and low power, the above specifications call for careful design
1) S2 pattern in DVB-T/H: digital TV interference 2 channels and innovative techniques.
away and higher, up to 40 dB stronger than the 64-QAM,
( ) wanted signal. In addition to sharp channel-
select filters, in direct conversion or low-IF architectures,
this implies high second-order linearity. Analysis shows Fig. 2 shows the tuner in the context of a digital TV system
that in order to meet this specification with a 3 dB imple- that could support a single or multiple antennas. Depending on
mentation margin, an IIP2 in excess of 30 dBm is needed, the application any combination of RF bands could be used.
while the NF should be less 10 dB. In T-DMB/DAB, the The block diagram of the direct-conversion multistandard TV
40 dB far-away blocking specification for digital interfer- tuner is shown in Fig. 3 [16]. By using three RF front ends cov-
ence results into a lower IIP2 requirement. ering the 174240 MHz (VHF III), 470862 MHz (UHF IV/V)
2) S1 pattern in DVB-T/H: analog TV (PAL/SECAM) adja- and 1.41.7 GHz (L-band for T-DMB in Europe and DVB-H
cent channel interference, up to 35 dB stronger than the in US) bands, respectively, most mobile TV standards deployed
wanted 64-QAM ( ) signal (43 dB stronger for worldwide are supported. Since each RF front-end is separate,
interference at other channels than adjacent). As the carrier interference at harmonics of the local oscillator frequency is al-
of the analog TV picture carrier (where the signal power is ways out of band; thus it can be rejected by an external RF filter,
concentrated) is only 5.25 MHz away from the center of the which is typically required in cellphone applications to reject

Fig. 2. Multistandard tuner IC in digital TV system implementation.

Fig. 3. Multistandard TV tuner block diagram.

GSM interference, or the tuning of matching circuits and in- demodulator, which implements the RF AGC algorithm: when
ternal low-noise amplifiers (LNAs). Even though most applica- interference is large, RF gain is reduced thus helping to achieve
tions use one or two of the three RF bands and typically separate the high linearity required in meeting the blocking and inter-
antennas are used to optimize performance and antenna area for modulation specifications for DVB-H/T and T-DMB.
each band, connection to a single antenna is still possible by The analog baseband path consists of two digitally pro-
the appropriate combination of external switches and RF filters grammable gain amplifiers (PGAs) before and after the
(Fig. 2). channel-select filters. An on-chip analog-to-digital converter
All three RF front-ends employ variable-gain LNAs and pas- (ADC) is included for analog gain control of the PGAs,
sive mixers as in [10]. At the LNA outputs, a logarithmic am- allowing versatility in the system implementation. A pro-
plifier is connected to provide an RSSI, used to detect wideband grammable look-up table is used for the optimization of the
interference. The RSSI is digitized by the companion baseband gain distribution between the PGAs and filter for optimal NF

Fig. 4. (a) LNA simplified schematic. (b) Passive mixers.

and linearity, depending on the standard. Similarly, an on-chip potentially high I/Q mismatch due to the polyphase filters and
digital-to-analog converter (DAC) can be used to digitally the divide-by-three circuits.
control the LNA gain. The tuner also provides options to take advantage of the
As in [10], a fractional-N synthesizer is used for LO digital processing power of the companion demodulator. As
generation. This allows a wide range in selecting the external discussed in detail in Section IV, the LO signal can be used to
crystal reference, which ultimately can be shared with other ap- calibrate both the baseband filters and the resonance frequency
plications to save cost, while maintaining a fine frequency step of the LNAs load. Finally, to allow for optimization depending
which is necessary for multistandard operation. A high com- on the standard requirements, all circuit blocks have pro-
parison frequency makes the phase-locked loop (PLL) division grammable bias. This feature can also be used by the baseband
ratio small and allows the use of a high loop bandwidth, modem to dynamically adapt power consumption depending
which reduces the overall integrated phase noise. To minimize on the channel conditions, as detected by the wideband RSSI
the required VCO frequency range of operation, the PLL covers and the ADC input signal.
a range from 1.2 to 1.8 GHz. Quadrature LO for the UHF and
VHF mixers is generated by division of the VCO frequency by IV. CIRCUIT DESIGN
2/3 or 6/8, respectively, while a first-order polyphase filter is
used for the L-band. Since the receiver operates continuously re- A. RF Front-End
ceiving signal from the same transmitter, adaptive I/Q mismatch The LNAs for all three bands use a common-source, cas-
calibration at the baseband modem can be used to eliminate the code topology with degeneration, as shown in Fig. 4(a). For the

Fig. 5. Fractional-N synthesizer and VCO.

UHF band, wideband input matching is achieved by using ex- that maximizes the RSSI indication. This is especially useful
ternal series inductors and an on-chip switched capacitor bank for the VHF LNA where narrow tuning is used to filter out
, which is adjusted according to the desired tuning frequency. potential interference at the third harmonic of the LO that
Typically in a system-on-a-chip (SoC) environment, it is prefer- can be down-converted by the third harmonic of the mixer.
able to use fully differential RF input stages to minimize digital With this tuning the RF front-end is stabilized versus process
noise coupling. However, some performance degradation from tolerances, power supply variations and temperature.
single-ended operation could be acceptable in applications sen- To achieve high linearity and low flicker noise, all RF
sitive to cost/area, where eliminating external baluns is impor- paths employ double-balanced current mode passive mixers
tant. For this reason, all three LNAs can support both differen- [Fig. 4(b)], which are commonly used in applications de-
tial and single-ended inputs by adjusting the external matching manding high linearity. The mixers are followed by low-noise,
and appropriately programming internal switches. For the UHF high linearity baseband programmable-gain transimpedance
and L-band LNAs, in the single-ended mode, device M1B is amplifiers to convert the output current into voltage.
switched off by S1 and RF switch S2 is turned on to adjust the
primary coil inductance of the output transformer. The VHF B. Phase-Locked Loop
LNA uses external output load inductors and can operate as The fractional-N synthesizer used for LO generation is
single-ended using only one of the two input branches. Switched shown in Fig. 5. The 19-bit fractional part of the division ratio
capacitor banks ( ) are also used at the outputs of the LNAs is modulated by a third-order MASH modulator achieving
to maintain optimal gain across the desired frequency ranges. a frequency resolution of better than 50 Hz. The VCO covers
Continuous analog gain control is achieved by current steering, a range from 1.2 to 1.8 GHz using complementary cross-cou-
controlled by a replica circuit that regulates the current of de- pled pairs and a MOS varactor for tuning. A switched varactor
vices M3C, M3D. A feedback loop generates voltage from bank provides the necessary tuning range. The loop filter used
an externally applied voltage , so that the current through is passive, third-order with programmable resistor values. The
devices M3Rn, M3Rp is proportional to variable transconduc- charge-pump current is programmable and is automatically ad-
tance . By programming , different slopes of the gain justed to keep the loop bandwidth constant despite the VCO gain
versus control voltage can be set. Typical LNA gain and NF in variation and process, temperature and power supply tolerances.
all bands is estimated at 25 dB and 2 dB, respectively, while IIP3 At channel-selection, a coarse tuning scheme is activated to
at maximum gain is 2 dBm. find the optimum varactor combination for the desired VCO
To implement the wideband RSSI function, a logarithmic oscillating frequency. This is achieved by initially charging
amplifier is used, tapping the signal at the LNA outputs. The the LPF at a DC voltage and allowing the PLL to operate in
pseudo-logarithmic, piecewise linear function is implemented closed-loop. By tracking the VCO control voltage with an ADC,
as a cascade of limiters with their outputs rectified and summed the tuning algorithm changes the varactor bank accordingly: if
together. the control voltage goes higher than a programmed threshold
The RSSI is also used at power-up to fine-tune the LNA a higher varactor setting is selected, if it goes lower a lower
output resonance at different carrier frequencies. By using an varactor setting is selected. Each time the LPF is re-charged,
RF switch, the LO signal is injected at the LNA output and an while the PLL is in open-loop state. The total lock time, in-
algorithm which runs at the companion digital demodulator, cluding coarse tuning, ranges from 90 to 120 s, depending on
finds the optimal combination of the switched capacitor bank the number of steps required during the binary varactor search.

Fig. 6. Analog baseband path (single-ended equivalent, actual path is differential).

A number of on-chip low dropout (LDO) regulators are used

to isolate the PLL supply from noise coupling that can prove
detrimental to LO spectral purity. Hard switching blocks like,
i.e., the PFD and the prescaler, are treated by the quiet-the-
speaker technique, using a separate power line and are physi-
cally isolated in the layout implementation.

C. Analog Baseband

The detailed block diagram of the analog baseband section

is shown in Fig. 6. Following the current-mode passive I/Q
mixers, low-noise/high gain-bandwidth, current-to-voltage am-
plifiers are used (PGA1). Gain programmability is achieved by Fig. 7. Gate rupture after an ESD HBM 2 kV zap.
using switched feedback resistors. The second programmable
gain block (PGA2) consists of three stages of resistive feedback
amplifiers. All gain stages use DC-servo loops. The output is The filters are implemented using opamp-RC integrators in
integrated on a sampling capacitor using an active RC filter leapfrog configuration with switched passive components.
with a programmable pole. By using a transconductor that con- An auto-calibration loop is enabled at power-up to tune the
verts the integrated output voltage to a current, a correction is filters to the desired , within 0.5% accuracy. The frac-
injected at the input of the gain stage that compensates for DC tional-N synthesizer provides the appropriate clock for an 8-bit
offset. To enable fast initial acquisition of DC offset, a higher direct digital synthesis frequency generator that produces a tone
frequency pole can be programmed during a training phase, at the desired 3 dB, which is then applied to the inputs of
while during normal reception the pole can be programmed to a the filters and is compared with the filter output using an rms
lower frequency to avoid corrupting the data. If required by the detector. A digitally controlled loop adjusts the filter bandwidth
demodulator, a hold/servo switch enables the DC servo loop to until the input attenuated by 3 dB equals the output. Even though
also operate in an open-loop mode after initial acquisition of calibration is done at power-up, the variation of due to the
the DC offset. resistors temperature coefficient for the 30 C to 85 C range
The order and attenuation of the filters needed was deter- was measured to be less than 2%, which does not affect system
mined by the S1, S2 blocking specifications for DVB-T/H. measurements.
These specifications call for a 3.8 MHz passband and 25/70 dB
attenuation at 5.25/13.25 MHz, respectively. To support dif- V. 65 NM PROCESS CONSIDERATIONS
ferent channel bandwidths required for multistandard operation, Continuously shrinking CMOS geometries have a direct
from 8 MHz for DVB-T/H to 430 kHz for one-segment ISDB-T, benefit in silicon area and allow more complex systems to be
sixth-order Chebyschev low-pass filters are used with a pro- integrated on a single die. However, this comes at the cost
grammable corner frequency from 100 kHz to 7 MHz. of increased design cycle and a multitude of issues involving

Fig. 8. ESD scheme.

complex device models, accurate interconnect impedance be taken into account during design and layout iterations. These
estimation/extraction, manufacturability and aging concerns. phenomena were handled by optimizing the per-device oper-
Analog and RF functions may suffer as standard circuit ating conditions in order not to stress it out of the combined
topologies are not directly transferable to nanometer scale safe operating limits.
digitally oriented processes. The combination of reduced power Efficient ESD protection, especially for RF devices, should
supply, high channel conductance, and low gate oxide break- handle both the requirements for low input capacitance in order
down voltage, along with the relatively high device threshold not to degrade the receiver noise figure and protecting sensitive
to mitigate leakage current in off state, lead to small output thin-oxide devices with small oxide breakdown voltage [17],
dynamic range in stacked-device topologies and difficulties in [18]. The snapback effect in nanometer CMOS processes is
meeting linearity requirements. To alleviate those concerns, not effective enough to be used for ESD protection since the
accurate device modelling, detailed RF tuning, and high quality snapback voltage of the MOS device is quite high and oxide
factor ( ) inductors and capacitors were used. In the analog breakdown risk is prominent. This is due to the low resistivity
baseband path, the 2.5 nominal I/O supply was used along substrate that does not present enough voltage drop at the base
with a mix of both thin and thick oxide devices. A well-ob- region of the parasitic BJT to forward bias the baseemitter
served principle was to employ self-calibration techniques that junction. The result of this behavior is seen in the failure
fine-tune the receiver blocks upon start-up, i.e., channel select analysis microphotograph of Fig. 7, where the gate of an LNA
filters, thus eliminating any process parameter spread affecting input device is severely ruptured after an HBM zap at 2 kV
the system performance. due to inefficient capability of the ESD structure to discharge
To avoid performance degradation due to gate leakage, fast enough, producing a high-voltage spike. Therefore, snap-
which is also significant in nanometer processes, standard back-based protection circuits cannot carry enough current and
design practices were used: currents and not voltages were used are limited only to secondary ESD protection. All critical ESD
for biasing circuitry, bias currents were kept above a certain paths were treated to present minimum impedance by using
threshold, and modest mirror ratios were used. Thin-oxide MOS multiple metal layer routing, provide fast clamping action with
capacitors were avoided and fringe metal capacitors were ex- adequate current capacity by careful design of the clamps, and
tensively used. Induced lattice stress and nonuniformity issues ensure uniform turn-on of the protecting devices by properly
[e.g., relative size of active area (LOD), well proximity effect symmetrical layout. Especially for the L-band LNA input, the
(WPE)] that affect matched-device performance requirements ESD protection network was measured to degrade the NF by
have been treated by proper device sizing, dummy insertion, an affordable 0.10.2 dB, while for the VHF and UHF LNAs,
accurate layout geometry modelling, and optimization of local no degradation was observed.
floorplanning. More intense aging phenomena [e.g., hot carrier Some of the measures taken are shown in Fig. 8 and include
injection (HCI), punchthrough, and negative bias temperature the following. i) Universal low resistance ESD ground path for
instability (NBTI)] are detrimental to analog circuits and should fast return of the pulse charge. This way the voltage built-up


is kept low enough to protect the gate oxide. ii) Power supply using a DVB-T/H demodulator implemented in FPGA. Both
decoupling capacitors have been extensively used to also keep single-ended and differential operation was verified, showing
the voltage build-up low. iii) A series poly resistance has been essentially the same performance in NF, linearity and related
placed in non-RF I/Os in order to provide isolation of the ac- system-level measurements.
tive circuits during an ESD event. iv) Secondary protection has Plots of NF and gain at all three bands in differential mode
been used when signals are crossing between power domains are shown in Fig. 10. In all bands, NF is less than 3.5 dB,
and it is physically placed close to the sensitive devices. v) It which includes external balun and PCB losses. A slight in-
is important to guarantee a low-resistance discharge path for crease of NF of 0.5/0.2 dB at maximum gain was observed
cross-coupled power domain ESD events that will not require in ISDB-T/T-DMB modes respectively, where the baseband
a voltage level higher than the oxide breakdown for the power opamp-RC filters use larger resistors and the lower signal band-
clamps and the in-series diodes to conduct. vi) When a sepa- width increases the contribution of flicker noise to the overall
rate digital GND is used, this is connected to global ESD GND SNR. Measurements over a temperature range of 30 C to
via a pair of back-to-back diodes for switching noise isolation 85 C and power supply corners show NF degradation of
purposes. Finally, vii) the specific package model was used to less than 1 dB, while a gain degradation of 4 dB is tolerated
evaluate the ESD discharge characteristics and locate any weak due to the excess gain budgeted. No significant degradation of
points in the implemented scheme. the NF was observed due to stringent ESD requirements and
initial tests proved no damage to the sensitive RF ports up to
VI. MEASUREMENTS 2 kV HBM stress. NF performance was also verified by system
The chip is implemented in a standard digital 65 nm CMOS sensitivity measurements. In Fig. 11, sensitivity for QPSK-1/2
and occupies a total area of less than 7 mm . A die micropho- and 64-QAM-3/4 DVB-T modes is plotted over the full UHF
tograph is shown in Fig. 9 and typical measurement results are range, indicating compliance with MBRAI2.0 with at least
summarized in Table I. Performance has been characterized in 1.5 dB margin. Sensitivity at VHF and L-band also exceeds
all bands and modes, verifying multistandard, multiband capa- 98 dBm in the QPSK-1/2 DVB-T mode.
bility. In addition to analog/RF measurements, the tuner has IIP2 and IIP3 requirements are met with significant margin,
also been extensively characterized for the full MBRAI 2.0 spec as indicated by system measurements. At a 5 dB backoff

Fig. 11. Sensitivity in DVB-T mode, UHF, 2 210 Vitterbi BER.

the 474858 MHz UHF range. The PLL locking range has been
Fig. 9. Die photo.
measured under all process, temperature, and supply variation
and exceeds the required 1.21.8 GHz range. Low integrated
phase noise error and accurate filter matching help achieve an
SNDR1 in excess of 35 dB, which is needed for robust mo-
bile operation. In Fig. 14, the SNDR is measured by calcula-
tion of the constellation error by the digital demodulator for dif-
ferent input powers and with AGC loops running in real-time.
In both plots (channel UHF 45 and channel VHF 8), the peak
SNR exceeds 37 dB, while for a significant input power range
SNR exceeds 30 dB. Initially SNDR in increases linearly, as it
is dominated by AWGN and then it reaches a maximum value
as it is limited by phase noise, linearity and frequency-depen-
dent I/Q mismatch. As signal increases further and LNA gain
is decreased, due to the steering technique used, the current
in the LNA main branch is reduced, which causes linearity to
drop thus dominating the overall SNDR. Fig. 15 shows a plot
of a 64-QAM 3/4 constellation achieving a 35 dB SNR at UHF
channel 45.
Fig. 10. Gain, NF versus frequency. In continuous DVB-T mode, the tuner consumes less than
140 mW in all bands, split between the 1.2 and 2.5 V nominal
supplies, while lower channel bandwidth and linearity require-
from maximum RF gain in UHF, where the RSSI-AGC loop ments help reduce power consumption in 1-segment ISDB-T
converges with typical RSSI target voltage for the DVB-T L1 and T-DMB modes.
blocking spec, IIP3 is 2 dBm while NF is 4.5 dB. Similarly,
at a 10 dB RF backoff, IIP2 and NF at UHF are 40 dBm and VII. CONCLUSION
5.5 dB, respectively. Linearity is also confirmed by DVB-T As a first step towards a multistandard mobile TV SoC,
blocking (S1S2) and intermodulation (L1L3) system mea- a multiband, multistandard direct-conversion tuner has been
surements, shown in Table I. In all bands, the stringent L1 spec implemented on a standard digital 65 nm CMOS process.
is met with more than 3 dB margin, while for S2, the margin is Nanometer CMOS implementation posed several hurdles,
at least 4 dB.
1To be precise, the SNDR measured here is actually error vector magnitude
A typical synthesizer phase noise plot is shown in Fig. 12,
(EVM), which is the overall constellation error as measured by the demodulator
while Fig. 13 shows the integrated phase error (after LO di- and includes all imperfections such as AWGN, phase noise, ADC quantization
vider) and spot phase noise at 100 kHz (before LO divider) for noise, sampling jitter, etc.

Fig. 12. Typical phase noise plot at synthesizer output.

Fig. 15. 64-QAM constellation with 35 dB SNR.

The authors acknowledge M. Margaras, P. Merakos, and
K. Tsilipanos for their support in board design and testing.

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[14] T. Pollet, M. Van Bladel, and M. Moeneclaey, BER sensitivity of Ioannis Kokolakis received the Diploma degree
OFDM systems to carrier frequency offset and wiener phase noise, from the Department of Electrical and Computer En-
IEEE Trans. Commun., vol. 43, no. 2/3/4, pp. 191193, Feb./Mar./Apr. gineering, Democritus University, Thrace, Greece,
1995. in 1993, where he is currently pursuing the Ph.D.
[15] M. Valkama et al., Advanced methods for I/Q imbalance compensa- degree.
tion in communication receivers, IEEE Trans. Signal Process., vol. 49, Since 2002, he has been with Athena Semiconduc-
pp. 23352344, Oct. 2001. tors, which is now Broadcom, in Greece. In his cur-
[16] K. Vavelidis et al., A 65 nm CMOS multi-standard, multi-band mobile rent position, he is a Senior IC Design Engineer re-
TV tuner, in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), 2007, sponsible for the design of CMOS frequency synthe-
pp. 424427. sizers for WLAN, cellular, and digital TV standards.
[17] M. Mergens et al., Application of an ESD-MOS Compact Model for
IC Design ESD Forum, Munich, Germany, 1999.
[18] V. A. Vashchenko et al., Physical limitation of the cascoded snapback
NMOS ESD protection capability due to the non-uniform turn-off,
IEEE Trans. Device Mater. Reliabil., vol. 4, no. 2, pp. 281291, Jun.
2004. Stamatis Bouras received the Diploma and Ph.D.
degrees in electrical engineering from the National
Technical University of Athens, Athens, Greece, in
Iason Vassiliou (S94M99) received the Diploma 1990 and 1996, respectively.
in electrical engineering from the National Technical He was a cofounder of Helic S.A and Hellenic
University of Athens, Greece, in 1991, and the M.Sc. Semiconductor Applications S.A. He worked as a
and Ph.D. degrees in electrical engineering from Technical Consultant at Theta S.A. and as Technical
the University of California at Berkeley in 1995 and Manager at Athena Semiconductor S.A. Since
1999, respectively. 2005, he has been an Engineering Manager with
He currently holds the position of Project Man- Broadcom, Athens, Greece.
agerSenior Principal Engineer at Broadcom,
Athens, Greece. From 2001 to 2005, he was Chief
Technologist with Athena Semiconductors, a startup
specializing in wireless solutions. He has authored
several papers on wireless transceivers and analog CAD.
George Kamoulakos received the B.S. degree
from the National Technical University of Athens
(NTUA), Athens, Greece, and the Ph.D. degree from
the the Kapodistrian University of Athens, in 1996
Kostis Vavelidis (M99) received the Diploma and and 2003, respectively.
Ph.D. degree in electrical engineering from the Previously, he has been a Senior Staff Design Sci-
National Technical University of Athens, Greece, in entist with Broadcom, a Senior RFIC Engineer with
1991 and 1996, respectively. AthenaSemi, an IC Designer with Helic, and a Ju-
From 1997 to 2001, he worked as an RF and nior Engineer with ISD. He is an author or co-au-
Mixed-Signal IC Design Consultant for several thor of many papers in scientific periodicals and con-
semiconductor companies. In 2001, he co-founded ferences. He is a co-founder of Elxys Innovations,
Hellenic Semiconductor Applications and in 2002, Marousi, Athens, Greece.
Athena Semiconductors, which was acquired by
Broadcom in 2005. He is currently Senior Manager
of Engineering at Broadcom, working on wireless
radio development and products for mobile digital TV and cellular.

Charalampos Kapnistis (M01) received the Ph.D.

degree from the National Technical University of
Nikos Haralabidis (M97SM07) received the Athens, Athens, Greece, in 2002.
Physics degree from the University of Thessaloniki, From 1996 to 1999, he was an R&D Engineer
Greece, and the Ph.D. degree from the National with the NCSR Demokritos, Athens, designing
Technical University of Athens, Greece. low-power CMOS analog circuits for radiation
From 1997 to 2001, he was with the Institute of detectors. Since 2001, he has been with Athena
Microelectronics, NCSR Demokritos, Athens, Semiconductors, which is now Broadcom, in
Greece, as a Postdoctoral Scientist and Lecturer. Greece. He is currently a Principal IC Design En-
In 2001, he co-founded Hellenic Semiconductor gineer responsible for several RF circuits including
Applications, which became part of Athena Semi- transmit modulators, power amplifiers, and high-fre-
conductors and was acquired by Broadcom in 2005, quency RSSI.
where he now holds the position of Senior Principal
Scientist. He has contributed 45 papers in journals and conference proceedings.

Spyros Kavadias (S91M97) received the B.Sc.

Aristeidis Kyranas (S95M03) was born in 1972 and Ph.D. degrees from the Physics Department,
in Athens, Greece. He received the Diploma and the University of Athens, Athens, Greece, in 1990 and
Ph.D. degree, both in electrical engineering, from the 1995, respectively.
National Technical University of Athens, Greece, in From 1997 to 2001, he was with IMEC, Leuven,
1995 and 2002, respectively. Belgium. In 2001, he joined Athena Semiconductor,
Since 1995, he has been working in the area of which was acquired by Broadcom in 2005. His inter-
analog IC design. He currently holds the position ests include the design of CMOS analog circuits for
of Senior Staff Design Scientist with Broadcom, wireless transceivers.
Greece. His research interests are in the area of
low-power RF IC design.

Nikos Kanakaris received the M.Sc. degree from Christos Kokozidis received the Diploma in
the Department of Electrical and Electronic Engi- Computer Engineering and Informatics from the
neering, Imperial College London, London, U.K., University of Patras, Greece, in 1998, and the M.Sc.
and the Diploma degree from the National Technical degree in micrelectronics from the Informatics and
University of Athens (NTUA). Telecommunications Department, University of
He was an RF Design Engineer with Oxtek, Athens, Greece, in 2000.
Atmel, and Helic S.A. He joined Athena Semicon- In 2002, he joined Athena Semiconductor, which
ductors (later acquired by Broadcom Corp.) in 2004. was acquired by Broadcom in 2005. He currently
He is currently with Broadcom, Athens, Greece, as holds the position of Staff IC Design Engineer
a Senior Staff Design Engineer. with Broadcom Hellas, where his interests include
the design of analog and mixed-signal circuits for
wireless telecommunication systems.

Emmanouil Metaxakis received the Dipl. Eng. and

Ph.D. degrees in electrical engineering from the Uni-
versity of Patras, Greece, in 1994 and 2003, respec- Hamed Peyravi received the B.S. degree from Shiraz
tively. University, Shiraz, Iran, in 1995, and the M.S. degree
He worked as a Consultant with Renaissance from Urmia University, Urmia, Iran, in 1998, both in
Wireless, Senior Staff Design Scientist with electrical engineering.
Broadcom, Senior RFIC Engineer WITH Athena He was with Urmia Semiconductors as an IC De-
Semiconductors, and RFIC and Systems Engineer sign Engineer, for two years. In 2002, he joined Helic
with Theta Microelectronics. He currently holds S.A., where he designed various circuits for BiCMOS
the position of CEO at Elxys Innovations, Marousi, transceivers. In 2005, he joined Athena Semiconduc-
Athens, Greece. tors which was acquired by Broadcom, where he has
been responsible for analog and RF circuit design.