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Introductions

Welcome to 6.111! Gim Hom


Lectures
Dylan Sherry
TA
Joe Colosimo
LA
Devon Rosner
LA
Kevin Zheng
LA

Introductions,
I d i course mechanics
h i
Course overview
Digital
g signaling
g g
6 111 L
6.111 Labkit
bkit
Combinational logic CIMstaff:
6M-gate FPGA +
JaneConnor
4 Handouts: slides, LP #1, safety info, info form JessieStickgoldSarah audio + video +
memories
m m +
Lecture material: Prof Anantha Chandrakasan and Dr. Chris Terman.

6.111 Fall 2012 Lecture 1 1 6.111 Fall 2012 Lecture 1 2

Course Website: http://web.mit.edu/6.111/www/f2012 Assignments


CIM
CIM
Participation Lecture
(technical&
3% Problems
writing)
One stop shopping for 15% 15%
all 6.111 information
Handouts
Labs
On-line submissions
Policies

Labs32%

Pl
Please readd Course
C FinalProject
info to get oriented 35%

A large number of students do "A" level work and are, indeed,


rewarded with a grade of "A". The corollary to this is that, since
average performance levels are so high
high, punting any part of the
subject can lead to a disappointing grade.

6.111 Fall 2012 Lecture 1 3 6.111 Fall 2012 Lecture 1 4


Labs: learning the ropes Final Project
Lab 1
Experiment with gates, design & implement some logic Done in groups of two or three; one person project by exception
Learn about lab equipment in the Digital Lab (38-600): oscilloscopes and Open-ended
logic analyzers
You and the staff negotiate a project proposal
Lab 2
Must emphasize digital concepts, but inclusion of analog interfaces
Introduction to Verilog, ModelSim & the labkit
(e.g., data converters, sensors or motors) common and often
Lab 3
desirable
Video circuits: a simple Pong game
Proposal Conference, several Design Reviews
Use Verilog to program an FPGA
Lab 4 Design presentation to staff
Design
D i and d iimplement
l t a Finite
Fi it State
St t Machine
M hi (FSM) CarC Alarm
Al Staff will provide help with project definition and scope
scope, design,
design
Lab 5 debugging, and testing
Design a complicated system with multiple FSMs (Major/Minor FSM) It is extremely difficult for a student to receive an A without
Voice recorder using AC97 codec and SRAMs or completing the final project.
project Sorry,
Sorry but we don
dontt give
Build your own remote control
incompletes.
All labs must be completed before starting final project.

6.111 Fall 2012 Lecture 1 5 6.111 Fall 2012 Lecture 1 6

6.111 Topics The First Computer


Combinational logic
Digital Sequential Logic
g Blocks
Building Memories
& Architecture Performance issues

The Babbage
Difference Engine
(1834)
25,000 parts
cost: 17,470
Design
Implementation
Methodologies
M h d l i
Technologies
& Tools

The first digital systems were mechanical and used base-10


base 10
Design metrics FPGAs representation.
HDL: Verilog Flash, ZBT ram
Simulation tools AC97, TripleDAC Most p
popular
p applications:
pp arithmetic and scientific
Synthesis, Place & Route computation

6.111 Fall 2012 Lecture 1 7 6.111 Fall 2012 Lecture 1 8
Meanwhile, in the World of Theory Key Link Between Logic and Circuits
(The Vacuum Tube)

AND OR NOT 0
0
1
0
0
0
0 1
1
+
0 0 0
0 0
0 1 0 1
1 1 Lee de Forest, 1906

1 1
0
0
0
1 1 0 Digital
1
1
1
1
Electronics
1 1

Despite existence of relays and introduction of vacuum tube in 1906,


digital
g electronics did not emerge
g for thirty
y years!
y
1854
1854: G
George B
Boolel shows
h that
h logic
l i is
i math,
h not just
j
Claude Shannon notices similarities between Boolean algebra and
philosophy! electronic telephone switches
g
Boolean algebra: the mathematics of binary
y values Shannon
Shannonss 1937 MIT Master
Masterss Thesis introduces the world to
binary digital electronics

6.111 Fall 2012 Lecture 1 9 6.111 Fall 2012 Lecture 1 10

Evolution of Digital Electronics The trouble with analog signaling


Vacuum Tubes Transistors VLSI
S Circuits
C
The real world is full of continuous-time continuous-
value (aka analog) signals created by physical
processes: soundd vibrations,
b llight
h ffields,
ld voltages
l and
d
currents, phase and amplitudes,

u if
But fw
we build
u p processing
ng elements
m n to m manipulate
n pu these
ENIAC, 1946
First Transistor 4004, 1971 signals we must use non-ideal components in real-world
Bell Labs, 1948 environments, so some amount of error (aka noise) is
Processing introduced. The error comes from component
Element tolerances electrical phenomenon (e.g.,
tolerances, (e g IR and LdI/dt
effects), transmission losses, thermal noise, etc. Facts
of life that cant be avoided

And the more analog processing we do, the worse it


Intel Poulson, 2012 gets: signaling errors accumulate in analog systems since
UNIVAC 1951
UNIVAC, IBM System/360,
y , 1964 8 Cores we can
cantt tell from looking at signal which wiggles were
1900 adds/sec 500,000 adds/sec >>2 Billion adds/sec there to begin with and which got added during
processing.
6.111 Fall 2012 Lecture 1 12
Building Digital Systems Building Digital Systems with HDLs
Goal of 6.111: Building binary digital solutions to Logic synthesis using a Hardware Description Language (HDL)
computational problems automates the most tedious and error-prone aspects of design

Labs & Design project Labs & Design project


Problem Statement Product specs Problem Statement Product specs
algorithm selection, algorithm selection,
flowcharts, etc. flowcharts, etc.
Algorithms, RTL, etc. Algorithms, RTL, etc.
Behavioral Description Flowcharts Behavioral Description Flowcharts
State transition diagrams State transition diagrams
conversion to binary,
binary software like
software-like
Booelan algebra programming
Logic equations Verilog code
Boolean Logic and State Circuit schematics HDL Description VHDL code
device selection
automated synthesis
and wiring
TTL Gates (AND,OR,XOR)
Programmable Logic
Hardware Implementation
p Modules (counter, shifter,) Hardware Implementation
p Custom ASICs
Programmable Logic

6.111 Fall 2012 Lecture 1 13 6.111 Fall 2012 Lecture 1 14

Verilog and VHDL Verilog HDL


VHDL Verilog Misconceptions
The coding style or clarity does not matter as long as it works
Commissioned in 1981 by Created by Gateway Design Two different Verilog encodings that simulate the same way will synthesize to
Department of Defense; Automation in 1985;; the same set of gates
g
now an IEEE standard now an IEEE standard Synthesis just cant be as good as a design done by humans
Shades of assembly language versus a higher level language
Initially created for ASIC Initially an interpreted
synthesis language for gate-level What can be Synthesized
simulation
i l ti Combinationall Functions
Strongly typed; potential for Less explicit typing (e.g., Multiplexors, Encoders, Decoders, Comparators, Parity Generators,
Adders, Subtractors, ALUs, Multipliers
verbose code compiler will pad arguments of Random logic
different widths) Control
C nt l LLogic
i
No special extensions for large FSMs
Strong support for package
management and large designs
What cant be Synthesized
designs Precise timing
timin blocks (e.g.,
(e delay a signal
si nal by 2ns)
Large memory blocks (can be done, but very inefficient)

Hardware structures can be modeled effectively in either Understand what constructs are used in simulation vs. hardware mapping
VHDL and Verilog.
Verilog Verilog is similar to c and a bit easier to learn
learn.

6.111 Fall 2012 Lecture 1 15 6.111 Fall 2012 Lecture 1 16


The FPGA: A Conceptual View Synthesis and Mapping for FPGAs
An FPGA is like an electronic breadboard that is wired together Infer macros: choose the FPGA macros that efficiently implement
by an automated synthesis tool various parts of the HDL code
Built-in components are called macros
... This section of code looks like
always @ (posedge clk) a counter. My FPGA has some
32
begin of those...
32 count <= count + 1; counter
+ SUM DQ
end
32 ...
HDL Code Inferred Macro
sel
Place-and-route:
Place and route: with area and/or speed in mind
mind, choose the
counter
interconnect needed macros by location and route the interconnect
a
b F(a,b,c,d)
c LUT G(a,b,c,d)
( , , , ) M M M M M M M
d
M M M M M M M This design only uses 10% of the
FPGA. Lets use the macros in
ADR M M M M M M M
R/W
RAM DATA one corner to minimize the
M M M M M M M distance between blocks.
((for everything
y g else))
M M M M M M M

6.111 Fall 2012 Lecture 1 17 6.111 Fall 2012 Lecture 1 18

Solution: go digital! The Digital Abstraction


Noise and inaccuracy are inevitable; we can
cantt reliably engineer
perfect components we must design our system to tolerate some
amount of error if it is to process information reliably.

Continuous values Ideal


Ideal
Digital World
Continuous time
Real
Analog World
0/1
Manufacturing
Variations
So we can detect small Noise
No se
Bits
changes and restore
original values Volts or
Electrons or
Discrete
Dis t values
l s Ergs or Gallons

Discrete time
Keep
p in mind that the world is not digital,
g , we would simply
p y like to
So we dont look engineer it to behave that way. Furthermore, we must use real
while its changing physical phenomena to implement digital designs!
6.111 Fall 2012 Lecture 1 19 6.111 Fall 2012 Lecture 1 20
Digital Signaling: sending Digital Signaling: receiving
To ensure we can distinguish signal from noise, well encode Since the channel/wire is imperfect and we will use non-ideal
information using a fixed set of discrete values called symbols. components in the receiver, we require the receiver to accept a
(larger) range of analog values for each symbol.
Given a bound N on the size of possible errors, if the analog
A B C D E
representations for the symbols are chosen to be at least 2N apart, we
should be able to detect and eliminate errors of up to N.N. -N
N +N
N -N
N +N
N -N
N +N
N -N
N +N
N -N
N +N
N

A B C D E RCV
-N +N -N +N -N +N -N +N -N +N
IDEAL
forbidden zones
Since we will use non-ideal components in the sender, we allow
each transmitted symbol to be represented by a (small) range of To avoid hard-to-make
hard to make decisions at the boundaries between
analog values. symbol representations, insert a forbidden zone between
A B C D E symbols so that some ranges of received values are not required
-N +N -N +N -N +N -N +N -N +N to be mapped to a specific symbol.
symbol
SEND

6.111 Fall 2012 Lecture 1 21 6.111 Fall 2012 Lecture 1 22

Digital processing elements Using voltages to encode binary values


Well
ll keep
k things
h simple
l by designing our processing elements
l
to use voltages to encode binary values (0 or 1). To ensure
D robust operation wed like to make the noise margins as large
as possible.
p ssible
-N +N
Digital processing elements restore noisy input 0OUT 1OUT
IN values to legal output values signaling errors
dont accumulate in digital
g systems.
y So the
number of processing elements isnt limited by OUTPUTS: F bidd Z
Forbidden Zone
Processing
noise problems!
volts
Element 0 VOL VOH VDD
The trick
Th i k is
i that
h weve
defined
d fi d our signaling
i li 0IN 1IN
convention so that we can tell from looking at a
D signal which wiggles were there to begin with and INPUTS:
-N +N
which got added during processing.
processing volts
0 VOL VIL VIH VOH VDD
OUT

Noise Margins
6.111 Fall 2012 Lecture 1 23 6.111 Fall 2012 Lecture 1 24
Digital Signaling Specification Sample DC (signaling) Specification

Digital input: VIN < VIL or VIN > VIH

Digital output: VOUT < VOL or VOUT > VOH

Noise margins: VILV


VOL and VOH V
VIH

Where VOL, VIL, VIH and VOH are ppart of the


specification for a particular family of digital
components.
Now that we have a way of encoding information
as a signal, we can define what it means to be
digital
g ta devicec . Source: Xilinx Virtex 5 Datasheet

6.111 Fall 2012 Lecture 1 25 6.111 Fall 2012 Lecture 1 26

A Digital Processing Element Why have processing blocks?


A combinational device is a processing element that has
The goal of modular design:
one or more digital inputs One of two discrete values
one or more digital outputs
a functional specification that details the value of ABSTRACTION
Static each output for every possible combination of valid
discipline p values
input What does that mean anyway
anyway:
a timing specification consisting (at minimum) of an Rules simple enough for a 6-3 to follow
upper bound tpd on the required time for the device Understanding BEHAVIOR without knowing
to compute
p the specified
p output
p values from an IMPLEMENTATION
arbitrary set of stable, valid input values
Predictable composition of functions
Output 1 if at Tinker-toy assembly
input A least 2 out of 3 of
my inputs are a 1. Guaranteed
G dbbehavior
h i under
d REAL WORLD circumstances
i
input B Otherwise, output 0.
output Y

input C I will generate a valid


output in no more than
2 minutes after
seeing valid inputs

6.111 Fall 2012 Lecture 1 27 6.111 Fall 2012 Lecture 1 28


A Combinational Digital System Example Device: An Inverter
+
A set of interconnected elements is a combinational device if VOUT VIN -
VOUT
0 1 1 0
each circuit element is a combinational device
every input is connected to exactly one output or a constant (e.g.,
(e g VOH
some vast supply of 0s and 1s)
Voltage Transfer Characteristic:
Plot of VOUT vs. VIN where each
the circuit contains no directed cycles
measurement is taken after any
t
transients
i t hhave di
died
d out.
t
Why is this true?
Given an acyclic circuit meeting the above constraints, we can derive VOL Note: VTC does not tell you
functional and timing specs for the input/output behavior from the anything about how fast a device
specs of its components! VIN isit measures static behavior not
Well see lots of examples soon. But first, we need to build some VIL VIH dynamic behavior
combinational devices to work with
Static Discipline requires that we avoid the shaded regions (aka
forbidden zones), which correspond to valid inputs but invalid
outputs.
p Net result: combinational devices must have GAIN > 1 and
be NONLINEAR.
VOUT
VIN
6.111 Fall 2012 Lecture 1 29 6.111 Fall 2012 Lecture 1 30

Combinational Device Wish List Wishes Granted: CMOS


Vout
Design our system to tolerate VOH
some amount of error
VIN VOUT
Add positive noise margins
VTC: gain>1 & nonlinearity VIN VOUT
VOUT Lots of gain big noise margin
Cheap,
Ch small
sm ll
VOL
Vin
VOH Changing voltages will require us VIL VIH

to dissipate power, but if no


voltages
lt s are changing,
h i wedd like
lik
zero power dissipation H H L
L
Want to build devices with useful
functi nality (what sort
functionality s rt of
f
VOL operations do we want to VOUT VOH VOUT VOL
VIN VIN VIL VIN VIH
perform?)
VIL VIH
VOUT eventually VOUT eventually
reaches VDD reaches GND
6.111 Fall 2012 Lecture 1 31 6.111 Fall 2012 Lecture 1 32
MOSFETS: Gain & Non-linearity Digital Integrated Circuits
gate IBM photomicrograph (SiO2 has been removed!)
source
Polysilicon wire

Inter-layer SiO2 insulation


Heavily doped (n-type or p-type) diffusions
W
Very thin (<20) high-quality SiO2
L Metal 2
insulating layer isolates gate from
channel region.
drain M1/M2 via

Channel region: electric field from


charges on gate locally inverts type of
substrate to create a conducting bulk D
Doped
d ((p-type
t or n-type)
t ) silicon
ili substrate
b t t
channel between source and drain.
Metal 1

Polysilicon

MOSFETs (metal-oxide-semiconductor
(metal oxide semiconductor field-effect
field effect transistors) are
four-terminal voltage-controlled switches. Current flows between the Diffusion
diffusion terminals if the voltage on the gate terminal is large enough
to create a conducting channel, otherwise the mosfet is off and the
diffusion terminals are not connected.
Mosfet (under polysilicon gate)

6.111 Fall 2012 Lecture 1 33 6.111 Fall 2012 Lecture 1 34

CMOS Forever!? Functional Specifications


A B C Y
0 0 0 0
Output
p 1 if at 0 0 1 0
input A least 2 out of 3 of
my inputs are a 1. 0 1 0 0
input B Otherwise, output 0.
output Y
0 1 1 1
2012 Intel Poulson input C I will generate a valid
Processor output in no more than 1 0 0 0
2 minutes after
32nm process seeing valid inputs 1 0 1 1
3.1 billion transistors 1 1 0 1
18.2mm x 29.9mm 1 1 1 1
8 multithreaded 3 binary inputs
cores so 23 = 8 rows in our truth table
170 watts
An concise, unambiguous technique for giving the functional
specification of a combinational device is to use a truth table to
specify the output value for each possible combination of input values
(N binary inputs -> 2N possible combinations of input values).

6.111 Fall 2012 Lecture 1 35 6.111 Fall 2012 Lecture 1 36


Timing Specifications Contamination Delay
an optional,
p additional timing
g spec
p
P
Propagation
ti d delay
l (tPD):
) AAn upper bound
b d on theth delay
d l
from valid inputs to valid Contamination delay(tCD): A lower bound on the delay
outputs (aka tPD,MAX) from invalid inputs to invalid
outputs
t t ((aka
k tPD,MIN)
VIN
VIN
VIH Do we really
D ll need
d
VIH tCD?
VIL
VIL
Design goal: Usually not it
itll
ll be
important when we
minimize
VOUT < tPD < tPD propagation
design circuits with
VOUT > tCD > tCD registers (coming
y
delay
VOH
s n!)
soon!)
VOH

If tCD is not
VOL VOL p
specified,, safe to
assume its 0.

6.111 Fall 2012 Lecture 1 37 6.111 Fall 2012 Lecture 1 38

The Combinational Contract Summary


Use voltages to encode information
A B Digital encoding
tPD propagation delay
A B 0 1 valid voltage levels for representing 0 and 1
tCD contamination delay forbidden
f bidd zone avoids ids mistaking
ist ki 0
0 for
f 11 andd vice
i versa
s
1 0
Noise
Want to tolerate real-world conditions: NOISE.
A Key:
K tougher
h standards
d d forf output than
h for
f input
i
devices must have gain and have a non-linear VTC
B
Combinational devices
Each logic family has Tinkertoy-set simplicity, modularity
> tCD
Must be ___________
predictable composition: parts work whole thing works
static discipline
< tPD
Must be ___________
digital inputs, outputs; restore marginal input voltages
Note: complete functional spec, e.g., a truth table
1. No Promises during valid inputs lead to valid outputs in bounded time (<tPD)
2 Default
2. D f lt (conservative)
( ti ) spec: tCD = 0

6.111 Fall 2012 Lecture 1 39 6.111 Fall 2012 Lecture 1 40