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Leakage power dissipation a major concern for scaling down portable devices. Improving high performance with reduced power consumption and chip area are the main constraint for designing VLSI CMOS circuits. In this paper, high performance and low power ONOFIC approach for VLSI CMOS circuits have been implemented. Mostly the concentrated part in deep sub micron regime is the power dissipation. Many techniques have been proposed for reducing leakage current in deep sub micron but with some limitations they are not suitable for actual requirements. Here we discussed two techniques named LECTOR & ONOFIC. The proposed On/Off Logic (ONOFIC) serves the needs for deep sub micron with its reduced power dissipation and increased performance in VLSI circuits. Thus the proposed ONOFIC approach results have been compared with the LECTOR technique and observed that the proposed technique improves the performance and reduce the power dissipation.

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ISSN : 2248-9622, Vol. 7, Issue 3, ( Part -6) March 2017, pp.71-76

using ONOFIC Approach

M.Sahithi Priyanka1, G.Manikanta2, K.Bhaskar3, A.Ganesh4, V.Swetha5

1.

Student of Lendi Institute of Engineering and Technology

2.

Student of Lendi Institute of Engineering and Technology

3.

Student of Lendi Institute of Engineering and Technology

4

.Student of Lendi Institute of Engineering and Technology

5.

Assistant Professor of Lendi institute of Engineering and Technology

ABSTRACT

Leakage power dissipation a major concern for scaling down portable devices. Improving high performance

with reduced power consumption and chip area are the main constraint for designing VLSI CMOS circuits. In

this paper, high performance and low power ONOFIC approach for VLSI CMOS circuits have been

implemented. Mostly the concentrated part in deep sub micron regime is the power dissipation. Many

techniques have been proposed for reducing leakage current in deep sub micron but with some limitations they

are not suitable for actual requirements. Here we discussed two techniques named LECTOR & ONOFIC. The

proposed On/Off Logic (ONOFIC) serves the needs for deep sub micron with its reduced power dissipation and

increased performance in VLSI circuits. Thus the proposed ONOFIC approach results have been compared with

the LECTOR technique and observed that the proposed technique improves the performance and reduce the

power dissipation.

Keywords: ONOFIC, Deep sub micron, LECTOR, Leakage current.

The design of low power circuits mainly are discussing Leakage control transistor (LCT)

focus on performance, power dissipation and chip technique to reduce the power consumption and

area. The concentrated part in VLSI CMOS circuits is power dissipation. Moreover, for designing high

deep sub micron regime. The constraint in deep sub performance and low power CMOS circuits a new

micron is to reduce the device dimensions leads to method is implemented which is On/Off logic

decrease in chip area. Supply voltage plays an (ONOFIC) approach. Section II briefly describes

important role in electronic devices to control the Power dissipation in CMOS designs. Section III

power consumption. By reducing supply voltage and describes LECTOR technique to reduce leakage

threshold voltage we can retains the performance. power. Section IV describes our proposed technique

Introducing new lower level technologies in which is ONOFIC to reduce the leakage power.

integrated circuits leads to increase in power Section V describes results. Section VI is about

dissipation. As the technology scaling down the conclusion.

leakage power dissipation goes up. Several

technologies have been implemented to reducing the II. POWER DISSIPATION

leakage power dissipation. Power dissipation is a major problem in

Kao and chandrakasan used power gating microelectronic circuit designing the, exclusively in

with Multi-Threshold transistors. This is the most wireless mobile applications and gadgets computing

efficient way to lowering the leakage power elements. This paper deals with the reduction and

dissipation of a VLSI circuits in the standby state is optimization techniques for leakage power

to turn off its supply voltage. However this technique dissipation in VLSI CMOS circuits. The causes of

cannot be used in sequential circuits and memory power dissipation in CMOS circuits are described by

cells, as it would result in loss of data stored. Self- the given below equation (1).

bias transistor (SBT) to minimize sub-threshold

leakage currents in static and dynamic circuits. P=1/2.C.VDD2. f. N + I leak .VDD + QSC

Which acts as smart switch by virtually power gating .VDD. f .N (1)

either pull-up or pull-down logic, and causes a Where P signifies the total power dissipated, VDD

considerable reduction in leakage currents in both represents the supply voltage, and f represents the

active and standby modes. S.Narendra et al. operating frequency. The first term denotes the power

discovered that by connecting off state transistors in required for charging and discharging the circuit

M.Sahithi Priyanka et al. Int. Journal of Engineering Research and Application www.ijera.com

ISSN : 2248-9622, Vol. 7, Issue 3, ( Part -6) March 2017, pp.71-76

switching action which gives the number of gate

transitions per clock cycle at the output. The second

term in Equation 1 signifies the static power

dissipation due to the leakage current I leak. The

third term in Equation 1 signifies power dissipation.

The term QSC shows the amount of charge carried

during each transition by the short circuit current in

the circuit.

LECTOR technique was proposed by the

authors N. Hachette and N. Ranganathan. In this

Fig.2.Coventional NAND design

technique two leakage control transistors are used to

control leakage current. These LCT transistors are

connected in such a manner so that one of the LCT

transistors will be in off state for any input signal.

Further, the gate of p channel and n channel

MOSFET is connected to the drain terminal of n

channel and p channel MOSFET respectively. The

generalized structure for leakage control gates is

shown in figure. 1. This technique gives an advantage

of reducing the leakage current in a path from VDD

to ground. The connection between pull up and pull

down is connected with leakage control transistors.

By breaking the path between pull up and pull

down networks reduces the leakage current. The

conventional NAND design and NAND design using Fig.3.NAND design using LECTOR

LECTOR technique also shown below respectively in

figure .2 and figure .3. Simultaneously the

conventional NOR design and NOR design using

LECTOR technique also shown below respectively in

figure .4 and figure .5.

control gates

M.Sahithi Priyanka et al. Int. Journal of Engineering Research and Application www.ijera.com

ISSN : 2248-9622, Vol. 7, Issue 3, ( Part -6) March 2017, pp.71-76

The proposed On/Off logic (ONOFIC) substrate of PMOS transistor is connected to the

approach reduces the leakage current and power VDD. The main concept of this technique is property

with single threshold voltage level approach. This of On/Off. The both ONOFIC transistors are in linear

technique efficiently reduces the leakage current in region when ONOFIC logic is in on condition while

both active and standby mode of logic circuit. Same ONOFIC logic is in off state both the transistors are

as LECTOR technique the ONOFIC approach also in cut-off mode. The good conducting path is

introduces an extra logic between pull-up and pull- obtained by turning on the ONOFIC block and it acts

down networks for leakage reduction. This additional as a good resistance to control the leakage current

introduced circuit is called On/Off logic (ONOFIC) when it is in off state. The proposed ONOFIC NAND

circuit. This proposed approach contains one PMOS design is shown in below figure .7. The proposed

and one NMOS transistor. Due to maintaining either ONOFIC NOR design is shown in below figure .8.

on or off condition for any output logic level this

technique is known as ONOFIC. The connection of

ONOFIC is shown in figure.4. This technique

provides the maximum resistance to the ONOFIC

block when it is in off state and minimum resistance

when it is in on state. This logic directly affects the

power dissipation and propagation delay of the logic

circuit.

transistor is connected to the gate of NMOS transistor

and the output is connected to the gate of PMOS

transistor. The drain of the pull-down network is

connected to the source of NMOS transistor and Fig.8. NOR design using ONOFIC

PMOS source terminal is connected to VDD of the

circuit. The NMOS transistor drain is connected to

the output of the circuit and the substrate of NMOS

Input level PMOS ONOFIC PMOS ONOFIC NMOS NMOS

Logic 0 On Off Off Off

Logic 1 Off On On On

From Fig.4 when compared to other circuit with any input combinations is given in

circuits of the NAND design the ONOFIC Equation (1),

technique uses the same threshold voltage

throughout the entire block which can improve the Slope = V out/Vin = (IoutRout)/ Vin; (2)

performance of the logic circuits. From the Fig.3 I = k/2 (VT) e 2 (Vin-Vth)/VT (1- e -Vout/VT) ;

out

shows the NAND design using LECTOR technique (3)

also uses the same threshold voltage throughout the

circuit block. The slope of the CMOS inverter

M.Sahithi Priyanka et al. Int. Journal of Engineering Research and Application www.ijera.com

ISSN : 2248-9622, Vol. 7, Issue 3, ( Part -6) March 2017, pp.71-76

voltage temperature. Where Vth is device depends upon the output logic. The concept of

threshold voltage and which depends on doping stacking provides the ONOFIC circuit for

densities of the material with materials quality controlling leakage current with maximum

factor, the flat voltage and charge storing resistance when it is in OFF state and minimum

capacitances. From the Equations (2) and (3) resistance when it is in ON state.

observed that the large slope is occurred due to The minimum propagation delay is obtained due to

large I out current which leads to large static power fast performance of turning-off and turning on of a

dissipation and hence LECTOR technique has low PMOS transistor when compared to other

static power dissipation when compared to techniques.

conventional and ONOFIC approach. Equation (3)

gives the propagation delay, V. RESULTS

Power consumption and Propagation

Tp = (RoutVout)/Iout; delay of basic CMOS designs are tabulated

(4) below as shown in TABLE II. Here, the basic

Where, Rout is the sum of loads of CMOS designs are simulated in tanner tools. In

resistive and capacitive of the CMOS circuit. the given table we gave the comparison among

ONOFIC and conventional circuits have less conventional circuits of different logic gates,

propagation delay when compared to LECTOR logic gates using LECTOR technique and logic

technique due to large Iout as observed from gates using our proposed ONOFIC approach.

Equation (4). Due to less propagation delay the We also showed the graphs of power

output values obtained quicker when input consumption and delay for NAND designs in

combination applied. the figure.9 and figure.10. Simultaneously

In ONOFIC block, the operation of NOR designs in the figure.11. and figure.12.

NMOS transistor is controlled by the PMOS

TABLE II: The Power Consumption (W) And Propagation Delay (Ns)

CMOS DESIGN DELAY POWER

INVERTER -102.2930n 6.385162e-005w

LECTOR INVERTER -101.7726n 5.345801e-005w

ONOFIC INVERTER -102.3982n 3.982539e-006w

NAND 29.8060n 1.232135e-004w

LECTOR NAND 59.8060n 8.846303e-005w

ONOFIC NAND -10.4715n 3.424948e-005w

NOR 9.5988n 6.783585e-005w

LECTOR NOR 9.6126n 6.624054e-005w

ONOFIC NOR 9.5340n 1.476662e-005w

TABLE II shows the delay and power consumption of various CMOS circuit designs. Here the

comparison is among conventional CMOS circuits, circuits using LECTOR and circuits using ONOFIC.

It is found that the delay and power consumption of ONOFIC decreases when compared to

conventional circuit results. It is also seen that LECTOR based (LCT ) circuits have less power

consumption but more delay as compared to conventional design as shown in below graphs. As

LECTOR technique consumes less power compared to conventional but has more delay so we went to

proposed ONOFIC approach. By observing the above table we get less delay and less power

consumption compared to conventional and LECTOR. So, our proposed ONOFIC technique gives high

performance compared to other techniques. It is more advantageous by using ONOFIC approach to

reduce power and delay. The power and delay graphs are shown below. By comparing ONOFIC circuit

designs with other conventional and LECTOR technique circuit designs ONOFIC consume less p ower

and delay.

M.Sahithi Priyanka et al. Int. Journal of Engineering Research and Application www.ijera.com

ISSN : 2248-9622, Vol. 7, Issue 3, ( Part -6) March 2017, pp.71-76

The problem of power dissipation is

reduced for different VLSI CMOS circuits by

using TANNER EDA tool. This work addresses

the challenge of obtaining low power losses

and efficiently uses ICs and electronic

devices. Our proposed ONOFIC approach gives

high performance when compared to

conventional circuits, LECTOR. So, it is

helpful in saving power in CMOS circuits.

Hence, our proposed ONOFIC approach gives

best results for saving power and gives high

performance.

REFERENCES

[1]. Preeti Verma,Estimation of leakage power

and delay inCMOS circuits using parametric

variationELSEVIER-2016.

Fig.10. Delay for NAND design [2]. Umesh jeevalu chavan, Siddarama R

PatilHigh Performance and Low Power

ONOFIC Approach for VLSI CMOS

Circuits DesignIEEE-2016.

[3]. Siddesh Gaonkar Design of CMOS inverter

using LECTOR technique to reduce the

leakage power. Issue 31(September, 2015).

[4]. Anjana R And Ajay Kumar Somkwar

Analysis Of Sub Threshold Leagake

Techniques In Deep Sub Micron Regime

For CMOS VLSI Circuits IEEE-2013 978-

1-4673-5301-4/13.

[5]. Fallah, F., Pedram, M., 2005. Standby and

active leakage current control and

minimization in CMOS VLSI

circuits.IEICE Trans. Electron. 88 (4),

509519.

[6]. Gopalakrishnan, H., Shiue, W.T., 2004.

Fig.11. Power consumption for NOR design Leakage power reduction using self bias

transistor in VLSI circuits. In: Micro. and

Electron Devices IEEE Workshop, pp. 71

74.

M.Sahithi Priyanka et al. Int. Journal of Engineering Research and Application www.ijera.com

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[7]. Gu, R.X., Elmasry, M.I., 1999. Power CMOS circuits. In: IEEE Conf., No. 2, pp.

dissipation analysis and opti-mization for 131134.

deep submicron CMOS digital circuits. [10]. Ye, Y., Borkar, S., De, V., 1998. A new

IEEE J. Solid-State Circuits, 707713. technique for standby leakagereduction in

[8]. Hanchate, N., Ranganathan, N., 2004. high performance circuits. In: IEEE

LECTOR: a technique for leakage reduction Symposium on VLSI Circuits Digest of

in CMOS circuits. IEEE Trans. VLSI Syst. Technical Papers, pp. 4041.

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[9]. Verma, P., Mishra, R.A., 2012. HTLCT-A

new technique for Leakage reduction in

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