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Final exam of 2007 - EE 466

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2nd Examination

November 9, 2007

Parts (a) through (c) assume the Elmore Delay model.

A0

A1

A2

A3 AND

Vout A4

A5

A6

A7

a) For the combinational circuit above (i) annotate transistor sizes that would result in

the circuit delivering as much current as a unit sized inverter (assume the unit sized

inverters Wp:Wn ratio of 2:1) . (ii) Provide the input capacitance of input signal D

(does not differ from that of input A, B, C or E). (iii) What is the value of the

intrinsic load capacitance?

b) Find (i) the worse case rise and fall times of this combinational logic circuit. (ii) Also

find the fastest rise and fall times. (Hint: For both questions b(i) and b(ii) you can first

determine the combination of inputs that results in the critical path (worse case delay)

and shortest path (best case delay)).

c) Provide the average propagation delay of each case in (b).

d) The 8-input CMOS AND gate must be designed to provide as much current as a unit

sized inverter (Wp:Wn ratio of 2:1). (i) Determine the A0s input capacitance. (ii) The

inverter of this AND gate is 10 times the unit sized inverter, determine the

intrinsic/internal loading of this gate.

e) Calculate the best path delay D of this gate. Equations of interest are:

1

CL

D NF N P, with F GBH , G g i , B bi , H , P pi N is the

C g1

number of stages.

f) It is impractical to design a gate with more than for devices in series. Please design an

equivalent 8-input AND gate that eliminates the long chain of series devices. (This

could use any logic style of your choice i.e. transmission gate, pass transistor logic,

pseudo-nMOS etc).

g) Provide the propagation delay of your proposed gate.

h) The delays of questions 1(d) through (g) have no units. What information would we

need to get the units of seconds?

Problem 2: Inverter Stages [40 points]

4

Initial Driver

400

to be driven by a chain of CMOS inverters. Assume the input

capacitance of a minimum size inverter is 4. Calculate the number of

inverter stages required and the resulting delay to drive the off chip

capacitance.

Problem 3: Digital Circuits Performance. [20 points]

a) Provide the equations for the three components of power.

b) An inverter is considered to a good representative CMOS circuit i.e.

if we understand how it operates and are able to perform its

performance analysis we can practically estimate other logic gates

performance. Inverters always dissipate short circuit power, would

this be true for the combinational circuit of the first figure? It there

is any possibility for short circuiting, would the short circuit current

of that circuit be of equal amount as that of a unit sized inverter?

c) The short circuit power equation has no capacitance (C L) as one of

the variables. Study the inverter circuit below and determine

whether short circuit power will increase or decrease with increasing

CL. Please justify your answer.

VDD

Vin

Vout

CL

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