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I-MOS: A Novel Semiconductor Device with a Subthreshold Slope lower than kT/q

Kailash Gopalakrishnan, Peter B. Griffin and James D. Plummer

Center for Integrated Systems, Stanford University

Stanford, CA 94305.

Abstract contributing to increased static power dissipation as is seen in

Fig. 1.
One of the fundamental problems in the continued scaling
of MOSFETs is the 60 mV/decade room temperature limit in Any attempt to modify the subthreshold slope must
subthreshold slope. In this paper, we report initial studies on a necessarily involve one or more of the following
new kind of transistor, the I-MOS. The I-MOS uses mechanisms:
modulation of the breakdown voltage of a gated p-i-n (1) Changing the mode of carrier injection from diffusion
structure in order to switch from the OFF to the ON state and based to tunneling based mechanisms (eg. the Schottky
vice versa. Since impact-ionization is an abrupt function of barrier MOSFET). However, to the best of the authors
the electric field (or the carrier energy), simulations show that knowledge, no three terminal tunneling based devices have
the device has a subthreshold slope much lower than kT/q. ever been demonstrated that have subthreshold slopes better
Simulations also show that it is indeed possible to make than kT/q.
complementary circuits with switching speeds comparable to (2) The second mechanism to enhance subthreshold slope
or exceeding CMOS. Experimental results on a silicon based stems from a different, albeit interesting, way of looking at
prototype verify the basic concept and show very steep the problem. Enhancing the steepness of a log (Io) vs. VC
subthreshold slopes with high speed turn-on and turn-off, curve simply amounts to amplifying the nonlinearity of the
Lower bandgap materials are also being investigated to system. As is known from OUI understanding of analog
reduce the value of the breakdown voltage and permit lower systems, the nonlinearity of any system can be enhanced by
voltage operation. using an amplifier. Physically this means that one uses an
amplification mechanism to amplify the ON-state and
Introduction suppress the OFF-state. Using an amplifier to enhance the
nonlinearity of any system seem like an interesting way of
The non-scalability of the subthreshold slope has its origin in solving the problem but this approach has the following
the Fermi-Dirac distribution of carriers and the drift-diffusion major challenges:
mode of transport in most known devices. This gradual (a) The amplification mechanism must be internal to the
transition from the OFF to the ON state makes it very device and must arise from some gain mechanism within the
difficult to achieve high ION/IOFFcurrent ratios in scaled device. Using an external amplifier for every single transistor
devices. The increasing need for higher performance with is clearly not a practical option.
scaling has led to increased leakage c u e n t s in these devices (b) Most devices that have internal feedback (such as PNF
structures) tend to latch up, so that the gate electrode does not
Drain Leakage Current (Alum)
have any control on the drain current. In addition to having
1.0E-04 I I gate control, one must also envision a fast mechanism like




&e----- -

drift, rather than recombination, that can remove all the
injected carriers when it switches from the ON to the OFF
(c) And finally, the most fundamental challenge arises from
the understanding that there is a fmite bandwidth associated
with every gain mechanism and, depending on the magnitude
0 0 lourn of the gain desired, this gain-bandwidth product may impose
1.OE-09 Temperature (C) fundamental limitations on intrinsic device switching
15 35 55 75 95 115
We fmd one such gain mechanism that satisfies all of the
Figure 1: Subthreshold leakage cumns for CMOS for different above conditions is impact ionization related breakdown.
technology nodes. The subthreshold leakage c~rrentis increasing
exponentially with decreasing channel lengths. Increasing chip When a simple p-n junction diode is used in the pre-
temperatures are exacerbating the problem (from Birovije breakdown mode (i.e. with voltages less than the breakdown
Nikolic, Second Nanotransistor Workshop, NET)

0-7803-7462-2/02/$17.M)02002 IEEE IEDM 289
voltage), the device exhibits a finite gain-bandwidth product Simulations
as is seen in avalanche photodiodes (APD) [I]. However,
when used in the post-breakdown mode (i.e. with voltages Simulations were done in MEDICITMon a germanium based
higher than the breakdown voltage), the delay is proportional device. Germanium was chosen because of its very high
to the log of the desired gain and is very fast. This mode has impact ionization coefficients. Impact-ionization coefficients
already been demonstrated in IMPATT and TRAPATT were calibrated to available experimental data on germanium
oscillators that operate at 100's of GHz [2]. Thus gated p-n devices [3], [4]. Fig. 3 shows a typical 1 0 - v ~simulated curve
diodes pulsed into breakdown can show subthreshold slopes for a device with 25 nm gate-length and 25 nm 1 region
much lower than kT/q and can potentially he very fast (outside the gate), with appropriately chosen gate work-
because carriers can he easily removed by drift. The I-MOS function. These simulations include models for both impact
(impact-ionization MOS) thus uses modulation of the ionization and BTBT and were done at 400 K in order to
breakdown voltage of a gated p-i-n structure in order to simulate the worst-case scenario as the leakage is higher,
switch 6om the OFF state to the ON state and vice-versa. impact ionization coefficients are lower and BTBT currents
are higher at 400K. The simulated subthreshold slope for this
Device Structure and Physics device was approximately 5 mV/decade. The above device
simulations were done with the standard local field impact-
The basic device structure for the n-channel version of the 1- ionization model which uses local electric fields to determine
MOS is shown in Fig. 2 in an SO1 implementation. Bulk the impact ionization coefficients. At dimensions much
structures work in a similar fashion. The device is a gated p-i- smaller than 100 nm, nonlocal dead-space effects have been
n diode and works by modulating its channel length. At low shown to play an important role in determining avalanche
gate-voltages, there is no inversion layer under the gate and multiplication and breakdown voltages. However, even
the effective channel length is the entire I region. The electric though the local field model overestimates multiplication at
field under these conditions is below breakdown and low biases, it has been shown to accurately predict the
consequently the off-state current is limited by the reverse- breakdown voltage in a wide variety of materials including Si
leakage current of the p-i-n diode. As the gate-voltage is [SI, GaAs [6] etc. with dimensions down to 25 nm. This is
increased, an inversion layer forms under the gate, reducing because the velocity overshoot effect (and the resulting'

the effective channel length of the device, and therefore impact ionization overshoot) tends to cancel the nonlocal
increasing the electric fields. The device breaks down. A p-i- dead space effect so that the breakdown voltages are
n structure with a lightly doped (or undoped) breakdown accurately predicted. This was verified using simulations and
region is chosen so as to reduce the fields required for impact comparison to experimental data in Si and GaAs. However
ionization which prevents band-to-band tunneling (BTBT)
related soft-breakdown. Note that while the formation of the
inversion layer may be limited by the normal 60 mvldecade
limit, the strong dependency of the impact ionization
coefficients on the electric field and the feedback inherent in
the avalanche multiplication process produces a much steeper
subthreshold slope in the I-MOS device.


T ? tL, 4 + ~ ~ ~ ~ ~ +
p' tsi N+
1.OE-I1 I
0 0.2 0.4 0.6
Gate Voltage VG (v)
Figure 3: Simulated lo vs. V O characteristic for a n-channel
germanium I-MOS device shown in Fig. 2 with LI = I*im = 25 nm.
Figure 2: Basic device structure for the nshannel SO1 version of Simulations were done at T400K which is the worst case for leakage
the I-MOS. The I-MOS uses modulation of the channel length to and breakdown. Simulations show that the subthreshold slope is very
switch fmm the OFF IO the ON state via avalanche breakdown. small (- Smvl decade), Gain mechanisms inherent in avalanche
Subthreshold characteristics are s h o w in fig. 3. multiplication result in very abrupt ON to OFF switching.

Monte-Carlo simulations are currently being used to
determine ultimate scalability.
1 5
Device simulations show that these devices switch very fast
(in picoseconds). There is no latch-up because with the gate
switched off, the electric fields (and the multiplication) are
reduced to below the breakdown value and the excess carriers
are removed by drift because of the high electric field in the
p-i-n diode. Thus the turn-off mode of the I-MOS is
fundamentally different from a conventional APD which
exhibits a finite delay in turning off because the electric field
in the i-region is unchanged even when the source of carriers
is switched off.
-<ran*.11 <-

The avalanche build-up delay is usually small and is of the Figurc 5: Transient FO, simulations far the I-MOSinverter-chain.
same order of magnitude as the transit time of the device [7]. The simulated circuit (lop)-consists of 4 inverters each sized 4
The statistical retardation delay (which is the delay in times more lhan the previous stage. The delay is measured between
nodes 3 and 4. The rising and falling delay both are in picoseconds
generating the seed carrier) is avoided because large seed and are unequal because the NMOS and PMOS transistors were
currents are generated 6om two primary sources: not sized optimally.
(a) Large displacement currents when the voltages across the
device swing in the picoseconds regime [8] and power is roughly equal to that dissipated by a CMOS inverter
(b) Tunneling induced impact ionization waves [9]. with a 0.85 V supply. The reduced swing results in smaller
These modes have been observed in other high speed impact- delay as well but comes at the expense of reduced noise
ionization based devices including IMPATT and TRAPATT margins. These simulation results have not been optimized so
oscillators. that better performance may be expected.

Experimental Results and Measurements

, bx 1,,,1 I b.
In order to verify the basic concept, a silicon based prototype
of the device was fabricated. A p-channel version of the
device was fabricated on a 0.2 pm SO1 wafer with g-line



PMOS I lithography using IO masks in the Stanford Nanofabrication

Facility (SNF). Most of the fabrication steps were similar to
those of a standard CMOS process.
Figure 4: N-channel and P-channel versions of the I-MOS. It is vs. Vo forthe I-MOS
easy lo generate complementary devices simply by moving the

t -
position of the gate. An I-MOSinverter shown next consisls of a
1.OOE-03 silicon r s b m n * 1-MOS
n-channel and p-channel I-MOScascaded in series

It is easy to generate complementary devices simply by t.OOE-05 .

moving the position of the gate (Fig. 4). Circuit mode 50 mv :
simulations were done on an I-MOS inverter chain using the 1.00E-07 . -10mvl
local model in MEDICITM.Each inverter consisted of a n-
channel and a p-channel version of the I-MOS. Simulations 1.0OE-09
verified that the device has switching speeds matching -5 4 -3 -2 -1 0
CMOS with a F 0 4 delay of less than IO ps (Fig. 5 ) and orders Yo I" Voln
of magnitude lower static power as compared to CMOS. It
should be noted that the output voltage swing across the I- Figurc 6: Roum-lempr.raturvrxpcrirnmral IOi s VG ;huazImslics
MOS device (and the inverter) is not rail-to-rail because a for a silicon based pro1ol)pe of Ihc pchanncl v m i o n uilhe I-hlOS
finite drain to source voltage is needed in order to sustain fabrocatrd m SNP 'Ihc pmamcicn lor lhe drvice are indicalrd tn Ihc
breakdown. Thus for the simulations in Fig. 5 , a higher figure As indicalcd abovc. thc rublhrcshold slopr. IS appnximaal)
I U m V I decadc Rewlb arc not uptimiicd
supply voltage of approximately 1.6V had to be chosen so
that both then I-MOS and p I-MOS devices have around 1 V
across them. The reduced swing at the output of these devices Typical DC experimental results for the device are shomn in
offsets the increased supply voltage so that the net dynamic Fig. 6 We note that the device behaves as expected, i.e. has a
subthreshold slope of approximately IO mV decade or lower


IEDM 291
at a drain bias of approximately 2OV. Different devices in the RC time constants. This however does not establish the
layout had drain biases in the range from about IOV to 25V ultimate switching speed of these devices which is estimated
depending on the length of the 1 region outside the gate but to be of the same order as the transit time (less than 50 ps) in
all of them had very steep subthreshold slopes. The these large geometry devices.
breakdown voltages obviously scale down in smaller
geometry devices. The prototype device had some problems, Conclusions
all of which are solvable by modifying the material or the
device structure: In conclusion, the I-MOS is a high speed semiconductor
( I ) The drain current for these devices is quite low because of device that has a subthreshold slope much lower than kT/q as
large parasitic resistances from very long source-drain verified by both simulations and experimental results. The
extensions and non-silicidation of these regions. switching delays and dynamic power in these devices are
(2) These devices also suffer from significant hot carrier comparable to those of CMOS devices with comparable
effects that result in threshold voltage shifts. These hot carrier dimensions with the added advantage of ultra-low static
effects can be avoided by keeping the breakdown region power dissipation. The I-MOS thus has the potential to
away from any interface or by using a buried channel device. replace CMOS for low power and high performance digital
(3) And finally, high drain voltages are required for two applications. The I-MOS also provides an interesting
reasons. Silicon has a higher bandgap and a large ratio of the template to obtain high gain with very low delays. This may
ionization coefficients (aN/ ap > IO) which leads to high have interesting implications for analog applications as well
breakdown voltages. The surface impact ionization as in optical clocking applications.
coefficients are much lower than the hulk ionization
coefficients because of a reduction in the mean free path due However challenges lie ahead primarily in the reduction of
t o interface scattering [IO]. The best design for the I-MOS breakdown voltage that would enable further scaling of the
device would thus need to have a low bandgap material and supply voltages. This may require further research in novel
the breakdown region kept away from any interface so as to materials as well as in new structures (eg. heterostructures).
reduce the breakdown voltages. New approaches in circuit design may also be needed to
account for the reduced output swing in these devices.
Input Acknowledgements

The authors gratefully acknowledge Dr. Krishna Saraswat,

Dr. Robert Dutton, Dr. Mark Lundstrom, Raymond Woo,
Richard Chang, Sameer Jain, Yusuke Jono, Rohit Shenoy and
Pranav Kalavade for useful discussions, directions and help
with measurements. We would also like to thank the SNF
staff for assistance during device fabrication. The funding of
-- this work by the Stanford Graduate Fellowship Program and
DARPA is gratefully acknowledged.
Figure 'I: Transient characteristicsa f a reverse-bias p-i-n diode References
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