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A Design Scheme of Toggle Operation Based Johnson Counter with Efficient Clock

Gating

Electrical, Electronic and Communication Engineering

Military Institute of Science and Technology, Bangladesh University of Professionals

Dhaka, Bangladesh

sani@ulkasemi.com, saadmaan1009@ymail.com, mizanjewel@ymail.com, neelanjana_subin_ferdous@ymail.com

AbstractThe performance of any system strongly depends on benefits of avoiding unnecessary clock pulses and applying

effective design methods applied on various segments of that only effective clock sequences. Researches have been

system. To provide an intelligent and smart architecture of a conducted to improve various systems using different clock

computer system, a dedicated design is needed which is both gating schemes. Clock transition provides vital contribution

power friendly and less complicated. As computer system in power dissipation. Several researches claim that around 15

consists of sequential circuits mostly, it is very important to to 45% of power dissipation in a system occurs due to clock

design sequential circuits effectively and flawlessly for signals [1]. So, total power dissipation in a circuit can be

ensuring least power dissipation and architectural simplicity. greatly reduced if efficient clock management system is

Different kinds of counters are considered to be very

applied in the system.

important segments of sequential circuit system. In this paper,

In this paper, we have described a power efficient design

we have proposed a design scheme to develop a Johnson

counter with necessary clock gating which is based on toggle of Johnson counter. We have proposed a toggle operation

operation of J-K flip-flops. This design scheme is more based Johnson counter with clock gating considering this

sophisticated and prominent than the conventional shift power dissipation issue as well as interconnection issues. In

register based design as this scheme provides fewer section II, we have described the power dissipation in CMOS

interconnections and comparatively lower power dissipation. sequential circuits. In section III, we have described the

conventional design of Johnson counter and in section IV,

Keywords-clock gating; digital circuit; J-K flip flop; Johnson we have described our proposed design. In section V, we

counter; VLSI interconnection; VLSI power dissipation have described some relationships among several parameters

of our proposed system. In Section VI, relevant simulations

I. INTRODUCTION are discussed and in section VII, we have described the

power and interconnection friendly characteristics of our

Johnson counter is a very useful counter system in the system compared to conventional design.

vast world of computer design as it provides a specific

pattern of data in loop synchronously, which is essential for II. POWER DISSIPATION IN SEQUENTIAL CIRCUITS

various logic designs. In practical computer design, we need

CMOS logic gates are very power-efficient as they

to provide this kind of specific pattern of data to specific

dissipate almost zero power at idle mode. Power dissipation

segments of a particular system in order to establish a desired

was not a very serious concerning matter for various chips

logic function. For applying various kinds of logic, all kinds

before. But in recent time, power dissipation has become an

of counter systems are quite useful as they provide different

alarming issue because of the development of clock

kinds of sequences in a synchronous manner.

frequencies and size of chips [2]. Different kinds of power

All computer operations are executed synchronously

dissipations (e.g. static and dynamic power dissipation) have

following a clock cycle. So, sequential circuits are of great

been studied and discussed for finding an efficient way to

value in any computer design. Sequential circuits along with

reduce them.

combinational circuits are integrated in a small area of a

Static power dissipation occurs due to various incidents

chip. As chip area is shrinking gradually, various reliabilities

in CMOS like sub threshold conduction through inactive

are becoming vital alarming design issues. One of the

transistors, oxide gate tunneling current, reverse biased

reliabilities, which is a prime concern to the CMOS

diodes leakage, contention current etc. Dynamic power

designers, is known as power dissipation. A sequential

dissipation occurs due to load capacitance discharging and

circuit system is based on clock pulses which also causes

short circuit current while in switching mode [2].

vital power dissipation in CMOS circuit. Power dissipation

Several researches on sequential circuits power

in sequential circuits will be discussed in the next section

dissipation have been developed to ensure maximum power

broadly.

savings [3]-[5]. Sequential logic circuits are considered to be

Various techniques have been introduced to reduce

the prime contributors to power dissipation as they are fully

power dissipation. One of the most effective techniques is

operated by a clock input [6]. Clock input forces sequential

clock gating technique. Clock gating system provides the

circuits to change their present states synchronously

393

DOI 10.1109/CIMSim.2012.52

according to the logic. Sequential circuits operate only on

positive or negative edge transitions or sometimes these

sequential circuits can be operated on both edge transitions

[7]-[10]. So, clock pulses make a sequential circuit

operational according to the logic applied. But at the same

time, clock transition also provides a vital contribution to

power dissipation. Clock transition means the change of the

clock value, from 0 to 1 or from 1 to 0.

Dynamic power dissipates in sequential circuits when the

clock provides a transition due to short circuit between VDD

and ground and charging and discharging of load

capacitance. To describe the power dissipation for clock

pulses, we can consider a simple CMOS logic inverter which

is considered as a vital element in CMOS design.

Fig. 1 represents a basic CMOS inverter which provides

inverted output. When the clock provides positive edge, the

NMOS will be activated and the PMOS will be deactivated,

providing the output 0. When the clock provides negative Figure 2. Clock edge rise time

edge, the PMOS will be activated providing VDD or 1 at the

output node.

Unlike these two switching actions, there is another

switching phenomenon which provides major contribution to

power dissipation. In CMOS design, PMOS and NMOS are

both activated for a certain amount of time while clock

transition occurs. The rise time and fall time of clock edges

are considered to be 0 ideally. But practically, clock has a

specific rise time and fall time (Fig. 2) which is not

negligible if we consider switching power dissipation. At a

certain point of rise time and fall time, both NMOS and

PMOS are on. This creates an electrical path between VDD

and ground to pass current. This current is known as short

circuit current or through current. This current appears as a

spike (Fig. 3) in every clock transitions for a very short time.

As current passes, power dissipation occurs. Transient power Figure 3. Current spike in Inverter MOSFET due to clock

consumption also occurs due to switching current which is transitions

required to charge the internal node during switching.

Load capacitance also plays a vital role in CMOS power half cycle, when the PMOS is active, the load capacitance is

dissipation. Recalling the basic CMOS inverter in Fig. 1, at charged. At the next half cycle, when the PMOS is off and

NMOS is on, the load capacitance will be discharged by

providing current through the NMOS to ground. So, in a full

cycle, certain amount of power is dissipated due to current

provided by the load capacitance [2].

As Sequential circuit requires frequent clock transitions

to operate according to logic applied, power dissipation is

very much serious concern here. It is seen that, almost all

kinds of dissipations are executed at clock transitions, so it is

very important to design an efficient clock management

system or clock gating system to control clock pulses to a

certain segment of sequential circuit. Sometimes, a clock

pulse has no effect on the stored value of flip-flop according

to logic. This kind of clock transition is called ineffective

clock pulse. This ineffective clock pulses, logically dont

change the value stored in flip-flops, but contribute in power

dissipation as it is causing switching in corresponding flip-

flops. For low power design, these clock pulses can be

masked at that certain time for those certain flip flops so that

clock pulses are allowed to that part of sequential circuit only

when it changes the value stored in it. This process will be

Figure 1. CMOS inverter

very effective for minimizing power dissipation [10]-[11].

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388

We have developed our proposed Johnson counter According to the truth table and the schematic, it is seen

keeping these power dissipation matters in mind. First of all, that inverted output of the first D-flip flop is connected with

we have designed a J-K toggle operation based Johnson the D input of the last D-flip flop. All other flip-flops are

counter as it requires comparatively less interconnections provided their corresponding D input from the output of the

than conventional D or J-K shift register based Johnson next flip flop. All flip flops are provided the same clock so it

counter. Also we have developed a very effective clock is a synchronous counter system. According to this design,

gating system so that flip-flops in our design are provided the system is working as a shift register to count the value

clock pulses only when they are effective for the given in Table I.

corresponding flip-flop, blocking the clock ineffective N-bit Johnson counter can be developed following this

modes. Thus our proposed system will play a supreme role in design. In that case, all the flip-flops will be provided

minimizing power dissipation of the whole system. common clock and D-input of any flip-flop will be provided

from the output of next flip-flop as usual.

III. CONVENTIONAL DESIGN OF JOHNSON COUNTER We have noticed some disadvantages of this

Generally, Johnson counter is designed with D or J-K conventional design which has been described below:

flip-flops based on shift register technique. The truth table A. Absence of Clock Management or Clock Gating System

of a 2 bit positive edge Johnson counter [12] is given in

TABLE I. The schematic diagram of 2-bit Johnson counter This system is a synchronous system where all the flip-

(conventional design) is illustrated in Fig. 4. flops are provided same clock. As we have discussed before

in section II that ineffective clock pulses in sequential

TABLE I. TRUTH TABLE OF 2-BIT JOHNSON COUNTER circuits provide unnecessary power dissipation, thats why a

State Q1 Q0 Clock pulse

controlled clock management or clock gating system is

S1 0 0 1 needed to be installed to provide only the necessary clock

S2 1 0 2 pulses to a corresponding flip-flop.

S3 1 1 3 After clock transition or switching occurs, if the present

S4 0 1 4 value stored in the flip-flop is same as the value stored at

previous state, then it can be said that the flip-flop is in

holding mode or holding state. That means, in this mode,

the flip-flop value is independent of the switching edge of

the clock. These ineffective clock pulses can be blocked at

that instant for that certain flip-flop, only the effective clock

pulses can be allowed. This process is useful for ensuring

lower power dissipation [3-5]. Fig. 5 shows the holding

states of 2 bit Johnson counter. The circled portion in the

figure represents the effective clock edges for the

corresponding flip-flops signals.

B. Interconnections

The interconnection within the system components is

also a prime concern. In CMOS VLSI design, when a large

amount of circuit components are integrated in a very tiny

space of a chip, interconnection issues are carefully

considered. As interconnections create various parasitic and

stray capacitances, so an efficient scheme is needed to

develop a system routing which provides less capacitance

problems. It will be observed that our proposed system is

more efficient considering interconnection issues.

Figure 5. Holding states and effective clock edges for 2 bit Johnson

Figure 4. Johnson counter (conventional design with D flip-flop) counter (conventional design)

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389

IV. PROPOSED DESIGN FOR JOHNSON COUNTER TABLE II. TRUTH TABLE OF 4-BIT JOHNSON COUNTER

provide individual services. The system is illustrated in the pulse

S1 0 0 0 0 1

block diagram (Fig. 6). S2 1 0 0 0 2

A. Master Clock S3 1 1 0 0 3

S4 1 1 1 0 4

Master clock is the system default clock. In a complete S5 1 1 1 1 5

system, variety of clock sequences needed to be provided to S6 0 1 1 1 6

a variety of segments. All those clock sequences should be S7 0 0 1 1 7

generated by a controlled operation between master clock S8 0 0 0 1 8

and several masking clocks.

We have developed both 2-bit and 4-bit Johnson

B. Masking Clock Counter according to our design scheme. The circuit

Masking clocks are needed to mask the unnecessary diagrams are illustrated in Fig. 7. In our system, each and

clock pulses of master clock to provide power efficient every flip flop will get the clock pulse when it is needed to

clock sequence to a certain flip-flop. toggle the value stored in it, so there is no scope for

ineffective clock pulse transition when a flip-flop is in

C. Combinational Logic Circuit holding mode. Thus power dissipation has been minimized.

Master clock and Masking clocks are processed in a Also, as J-K flip flop has been used with toggle

combinational logic circuit system which provides operation, so we have been able to avoid several

necessary clock sequences. This segment works as clock interconnections (e.g. last flip-flop D-input to first flip-flop

gating system. inverted output connection, different flip-flops connections).

Thus the system has become very sophisticated and

D. Series of Flip-flops practically effective for ensuring both fewer

This block executes the main operation of Johnson interconnections and lower power dissipation.

counter. We have proposed the toggle operation of J-K flip-

flop (both inputs at 1) rather than shift register technique. V. RELATIONSHIPS AND DERIVED EQUATIONS

We have connected all the J, K inputs of the flip-flops to We have established some relationships between the

VDD or 1. Whenever a flip-flop will get a clock edge master clock and the clock sequences provided in the flip

(positive edge for positive edge triggered flip-flop), the flops in our proposed Johnson counter and derived some

stored value in it will be changed. We have developed the equations. We have also defined a relationship between

clock gating system to control the clock pulses in these flip clock sequences of 2 bit system and 4 bit system and

flops. proposed that clock sequences of n bit system can be

E. Output defined with certain protocols or common equations.

This section will provide the output of the Johnson A. Number of States

counter. The output of the Johnson Counter is provided in If number of bit is n, then number of states Sn will be:

the truth table in TABLE I (2 bit) and TABLE II (4 bit).

Sn = 2 n (1)

n = 1, 2, 4,8,16,............2k

k= 0 and positive integers

number of bits = 4, there will be 8 states and so on. This

equation resembles the relationship between the number of

bits and number of states in Johnson Counter.

B. Relationships Between Master Clock and Clock

Sequences

Assume that the frequency of master clock is f. If we

consider the 2 bit Johnson counter we have proposed, then

there are two flip-flops (Q0 and Q1) with two different clock

sequences (clkQ0 and clkQ1).

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390

(a)

(b)

Figure 7. Proposed design of Johnson counter system: (a) 2-bit, (b) 4-bit

The relationship equations between the master clock These are the relationships between the master clock and

(clkf) and clock sequences (clkQ0 and clkQ1) for 2 bit the clock sequences of flip flops. The clock gating circuit of

proposed Johnson counter are given below: our system is designed following these equations. It is

observed that lower frequency clocks are used as masking

clocks (e.g. clk_f/2, clk_f/4). These masking clocks consist

clkQ 0 ( 2 bit ) = clkf clkf 1 (2) of and of master clock frequency respectively. So, the

masking clock can be generated from the master clock by

clkQ1( 2 bit ) = clkf clkf 1 (3) reducing frequency. For different bit Johnson Counter,

different masking clocks needed with different frequencies.

Where, f1= f (4) But a rule or protocol or more specific equations can be

2

derived to establish a relationship between master clock and

several clock sequences provided in several flip-flops for

In case of 4 bit Johnson counter we have proposed, the

different bit operations.

relationships between clock sequences in 4 flip-flops and

However, we have established relationships between 2-

the master clock are as follows:

bit system and 4 bit system. From equation (2), (3) and

equation (5), (6), (7), (8) we find that:

clkQ 0 ( 4 bit ) = clkf clkf 1 clkf 2 (5)

clkQ1( 4 bit ) = clkf clkf 1 clkf 2 (6) clkQ 0( 4 bit ) = clkQ 0( 2 bit ) clkf 2 (10)

clkQ 2 ( 4 bit ) = clkf clkf 1 clkf 2 (7) clkQ1( 4 bit ) = clkQ1( 2 bit ) clkf 2 (11)

clkQ 3( 4 bit ) = clkf clkf 1 clkf 2 (8) clkQ 2 ( 4 bit ) = clkQ 0 ( 2 bit ) clkf 2 (12)

clkQ 3( 4 bit ) = clkQ1( 2 bit ) clkf 2 (13)

f2= f (9)

4

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391

So, we can established general equations for clock

sequences of n bit ( n= 0,1,2,4,8,16 2k) Johnson counter

with respect to basic 2 bit Johnson counter clock sequences

clkQ 0 ( 2 bit ) and clkQ1( 2 bit ) . These relationships will be helpful

to develop a clock tree for n bit system. As the entire clock

sequences of n bit system can be derived from basic 2 bit

system clock sequences and they are related with systematic (a)

equations, we can develop the clock tree for n bit system

using programmable logic array circuit.

It is important to notify that the value n, which

resembles bit number of a system, should be a value 2k

where k is 0 or any positive integers. If the value of n is any

other value except 2k like 3, 34 or 24, then they dont follow

the established relationships. It is because the binary number

system is of 2 digits (0, 1). Thats why our derived

relationships only support 2k bit system.

But different kinds of bit systems used in computer

design are the value 2k (e.g. 32 bit system, 64 bit system

etc.). Thats why it can be stated that 2k system relationships

described here are adequate for designing clock tree of any

computer system. (b)

VI. SIMULATIONS

We have simulated the system we have design in

ALTERA QUARTUS software using schematic simulation

technique.

First we have simulated the conventional design of

Johnson counter for number of bit 2. The simulation is

illustrated in Fig. 8 (a).

From the simulation, it is seen that, although each of the

flip flop needs only 2 clock pulses in a cycle to operate

correctly, it is provided with 2 extra clock pulses which have

no activity on the corresponding flip-flop. That two extra

clock pulses are causing unnecessary power dissipation.

Then we have simulated our proposed design (2-bit and

4-bit) in the same software in same simulation environment. (c)

The simulations are illustrated in Fig. 8 (b) and 8 (c)

respectively. It is seen that any flip-flop is getting a pulse Figure 8. Simulation of Johnson counter: (a) conventional design, (b)

when it is necessary. There might be several clocks (master proposed design (2bit), (c) proposed design (4bit)

clock, masking clocks) in the system, but every flip flop is

receiving a controlled clock sequence generated by the In conventional system, all the four flip-flops receive

combinational logic circuit (different for different bit total of 32 pulses as clock triggering signals, where in our

operation), processing master clock and all available proposed system, the four flip-flops receive a total of only 8

masking clocks. Thus the total power dissipation in the clock pulses. So, theoretically power dissipation due to

whole system is controlled efficiently. clock transitions is minimized (32-8)/32 %= 75% (Fig.

9(a)).

VII. CONCLUSIONS But practically power dissipation is decreased less than

Our proposed design is more prominent and efficient this percentage as we have used some additional clock

than the conventional design considering power dissipation gating system consists of combinational logic circuit [9].

due to clock transitions and simplicity of interconnections. Considering power dissipation in clock gating system also,

In case of power dissipation, our observation is more power dissipation in Johnson counter has been lowered

focused on power dissipation due to clock transitions as around 45% (Fig. 9(b)). So, the overall power dissipation

majority of power dissipation occurs due to clock due to clock transitions can be minimized a lot by adopting

transitions. It is observed that in one process cycle of 4 bit our proposed system. For 2 bit system, the percentage value

Johnson counter (from 0000 to next 0000), there are total 8 of power dissipation minimization will be 50 (not

master clock pulses. considering power dissipation in clock gating system).

398

392

output point as there is no schematic requirement of

connecting one cell output with anothers input. Connecting

inputs with common internal VDD layer rather than

interconnections between cells is more routing friendly

process (proposed system). So, it is obvious that our

proposed system is both power and interconnection friendly.

It has been noticed than only the positive edges are

necessary for executing the positive edge triggered system

properly. Negative edges are not required for operations but

they are causing power dissipation. Similarly positive edges

cause extra power dissipation in negative edge triggered

system. But we cannot mask just one type of edges because

(a)

to provide another positive edge, negative edge transitions

are required and vice versa. But there is one solution in [7]-

[10] proposing double edge triggering of flip-flops.

Adopting this process we can trigger the flip flops in both

edges where power dissipation for unnecessary edge

transitions will be reduced and system will be made faster.

As our system requires additional clock gating system, it

may increase delay and size of the whole system. Moreover,

clock gating system itself dissipates a certain amount of

power which may not be negligible for further processing of

larger systems with larger clock gating circuit. So, further

research is suggested to take the clock gating technique to a

whole new advanced efficiency level.

(b)

REFERENCES

Figure 9. Comparison of total power dissipation between conventional

[1] M. Pedram, Power minimization in IC design: Principles and

design and proposed design: (a) without considering clock gating, (b)

applications, ACM Trans. Design Automation, vol. 1, no. 1, pp. 3-

considering clock gating

56, Jan. 1996

[2] Neil H. E. Weste, David Harris and Ayan Banerjee, CMOS VLSI

In Fig. 9, comparison of total power dissipation after a Design , 3rd edition, Dorling Kindersley Pvt. Ltd. 2006.

clock cycle is illustrated between conventional design and

[3] K. Roy and S. Prasad, Circuit activity based logic synthesis for low

proposed design. It is observed that toggle operation based power reliable operations, IEEE Transitions, VLSI Systems, 1(4):

system with clock gating is dramatically power friendly 503-513, 1993.

compared to shift register based Johnson counter system. [4] E. Olson and S. Kang, State assignment for low power synthesis

Although clock gating system contributes in power using genetic logic local search, in IEEE Proc. Custom Integrated

dissipation, but still from Fig. 9(b), it is observed that Circuit Conf., 140-143, May 1994.

overall power dissipation is much less than that of [5] L. Benini and G.D. Michel, State assignment for low power

conventional design of Johnson counter. dissipation, IEEE Journal of Solid-State Circuits, 30(3): 258-268,

1995.

Our proposed system also consists of more economical

[6] Q. Wu, M. Pedram and X. Wu, Clock gating and its application to

interconnections compared to conventional design. In low power design of sequential circuits, IEEE Transactions on

CMOS VLSI design, like other components, each Flip-flop Circuits and Systems I: Fundamental Theory and Applications, 3(47),

is also considered as unique cell. In a complete circuit, all March 2000.

these necessary cells are interconnected among them in [7] M. Pedram, Q. Wu and X. Wu, A new design of double edge

layout design according to the schematic of the circuit triggered flip-flops, In Proc. Of ASP-DAC, Yokohama, 417-421,

system. Designers always try their best to connect them with February, 1998.

minimum routing possible, maintaining all the design rules. [8] X. Wu, J. Wei and M. Pedram, Low-power design of sequential

As various parasitic capacitances are of great concern in circuits using a quasi-synchronous derived clock, in Proc. Of ASP-

DAC, Pacifico Yokohama, January 2000.

CMOS, unnecessary routing is always avoided. In case of

[9] X. Wu and Massoud Pedram, Low power sequential circuit design

conventional Johnson counter, considering each flip-flop as using priority encoding and clock gating, Power Electronics and

a unique cell, we need to route the input of one cell with the Design, 2000. ISLPED '00. Proceedings of the 2000 International

output of another according to the design. Also each D flip Symposium on, 143-148, July 2000.

flop cell consists of extra inverter (as one input is inverted [10] S.H. Unger, Double-edge-triggered flip-flops, IEEE transactions on

with another input in each cell). On the other hand, in our Computers, 30(6): 447-451, 1981.

proposed system, all the J, K input ports are connected with [11] E. Macii, M. Pedram and F. Somenzi, High level power modeling,

the VDD layer (Metal2 layer generally) with Metal1 and estimation and optimization, IEEE Transactions on Computer Aided

Design, 17(11): 1061-1079, 1998.

Metal1_Metal2 contacts which requires less metal routing

[12] Thomas L. Floyd, Digital Fundamentals, Pearson education, Inc.,

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design, we need to expand only output pin layer from the

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