You are on page 1of 7

Mechanism of Void Formation in Cu Post Solder Joint under Electromigration

Min-Young Kim1, Liang-Shan Chen1, 2, Seung-Hyun Chae3, Choong-Un Kim1, 4

Department of Materials Science and Engineering, University of Texas at Arlington
501 West First Street, Box 19031, Arlington, Texas 76019
present: Globalfoundries, 400 Stone Break Extension, Malta, New York 12020
Texas Instruments, 12500 TI Boulevard, Dallas, TX 75243
contact e-mail:

The proliferation of Cu-pillar or Cu-post based flip chip

Abstract packaging technology has resulted in a large number of
This paper reports experimental observations made on the investigations in recent years with an aim to identify factors
mechanism of electromigration (EM) voiding and its kinetics and mechanisms affecting the stability of the joint in the
active in low-profile solder joint consisting of long Cu-post assembly [1,3-4,8-13,15]. These studies are successful in
(~300x110m), thin solder layer (15m), and Ni coated Cu- revealing mechanisms of microstructure development, its
lead frame assembly. When EM testing on the samples was relation with process conditions, and its impacts on the joint
conducted at accelerated conditions it revealed that although reliability. However, focused more on the thermo-mechanical
they are immune to EM failure, they contained a small reliability, these studies are less successful in identifying
amount of residual void as a result of EM. Kinetic analysis of factors affecting the electromigration (EM) reliability
EM voiding was done based on the analysis of resistance specially when EM induced failure is emerging as one of the
change and post EM microstructural characterization. Our critical reliability concerns in those assemblies [9-13]. The
analysis suggests that the origin of the residual voids is EM in high density electric current can subject the solder layer to
Sn and it occurred prior to conversion of Sn to Cu6Sn5 phase. more severe EM condition than in the conventional assembly
It further suggests that the extent of voiding is determined by and may make the joint to be EM failure prone. A simple
the two competing kinetic factors that are producing opposite extension of understandings made from the EM studies
effect on the voiding. The first is the kinetics of Sn EM conducted on the conventional solder joint may not work in
because it determines the amount of vacancy responsible for this case because kinetic mechanism of EM and the resulting
voiding while the second is the Cu EM as it promotes the void development can be substantially different in low-profile
growth of Cu6Sn5 phase that interrupts voids growth by solder joint.
removing Sn phase in the joint. The kinetic interplay between One obvious reason why the EM voiding mechanism is
these two factors makes EM voiding kinetics of the low- expected to be different in low profile solder joint is related to
profile solder joint to be different from the more conventional the fact that the joint contains limited amount of solder so that
solder joint where Cu EM has a rather insignificant influence. it can be quickly converted to Cu-Sn intermetallic compounds
(IMC) prior to EM developing sizable damage [1]. In solder
Keywords: low-profile solder joint; Cu-post, Cu-bump, joint, there are at least two active atomic species, Sn and Cu,
electromigration voiding, Intermetallic compounds constituting the total EM flux. Among these two, Sn EM flux
Introduction is regarded as the main source of voids because commonly
used Pb-free solder contains Sn in excess of 95 wt.% [1,14].
Continuing demand for high performance as well as high
The contribution of Cu EM on void volume should be
power electronic devices has spurred the recent development
negligibly small because extremely low solubility of Cu in Sn
of the packaging technology allowing the use of low-profile
solder makes Cu EM flux to be small and also Cu is
solder joints in the assembly [1-4,7-9]. Some of the known
continuously replenished by its source, i.e. cathode end of the
examples of such packaging structure include the ones used in
joint. However, Cu EM can play a significant role in low-
the flip chip (FC) assembly, including the flip chip on lead
profile solder joint not necessarily because it changes the rate
(FCOL) [10], where Cu pillars or Cu posts are placed on top
of Sn EM but because an accelerated growth of Cu-Sn IMC
of Si chip to join with the mating Cu bumps, pads or lead-
can interfere with the void growth. In cases where Sn solder
frame via thin Pb-free solder layer. Unlike in more
layer is very thin, the growth front of Cu-Sn IMC layers on
conventional packaging structure such as the Ball Grid Array
both sides of solder joints can converge prior to formation of
(BGA) [5-6], the solder joint in these structures can be as thin
EM voids in Sn solder. Once Sn solder is replaced with Cu-Sn
as a few tens of micro-meters, leading to extremely low-
IMCs, EM of both species and failure development should be
profile device form factor. While such packaging methods can
terminated. A few previous studies on EM voiding suggest
result in an increase in process complexity and requirement
such possibility. For example, the work conducted by Chao et
for tighter control of structural and process variables, their
al. [16-17] reports that EM voiding in Cu-Sn system cannot be
ability to produce low profile devices with high density
solely characterized by Sn EM flux but has to include the
interconnects makes them highly attractive and ideal for
influence of enhanced Cu-Sn IMC growth rate.
advanced electronics. Various devices with such packaging
structure are already introduced and used in places like mobile Consideration of EM mechanism suggests that EM failure
electronics and many more are expected to be introduced in mechanism in low-profile solder joint can be substantially
the near future [1,3,7]. different from what is known from the conventional solder

978-1-4799-8609-5/15/$31.00 2015 IEEE 135 2015 Electronic Components & Technology Conference
joint because the failure may develop by two kinetically substantially reduced. There exists a few places where IMC
competing processes, which are the rate of voiding by Sn EM growth is found to be highly enhanced, which is a subject of
and IMC growth by Cu EM. This speculation is indeed proven our ongoing research; however, the resulting solder joint
in our study that investigates the kinetic mechanism of EM microstructure, consisting of narrow channels of Sn encased
damage in low-profile solder joint made of Cu-post, Sn--Ag by thick IMC, provides us with an ideal condition for studying
solder, and Ni coated Cu lead-frame. Our study finds that EM the EM voiding mechanism with limited amount Sn in the
damage stops when Sn solder layer is fully converted to Cu- joint.
Sn IMCs and that the joint is left with residual voids In order to confine the EM damage to the target joint, we
developed in Sn prior to its conversion to Cu-Sn IMCs. The placed a number of supporting posts near the EM post and
residual damage appears as voids surrounded by IMC phase, used them to provide distributed current exit paths to the post
and the degree of voiding is found to be affected by EM under EM testing. This arrangement is used to make the test
condition. This paper presents examples of our data with current from the LF to Cu-post, meaning that EM occurs from
weighted emphasis on the effect of EM on the rate of Sn the post to the LF direction. Also developed for this study was
conversion to IMC and the degree of EM damage appearing a customized EM test oven to enable effective joule heat
as residual voids. dissipation and maintenance of temperature uniformity and
stability for duration of EM testing. The developed oven
Experimental Method and Sample Configuration system uses a large surface heater with high speed blower and
The samples used in our investigation are based on a flip min-air conduits made of Al fin arrays. High speed forced air
chip on lead-frame structure with Pb-free Sn solder containing circulation over the array of samples enabled us to keep the
approximately 2.5% Ag. As presented in Figure 1(a), where joule heat induced temperature rise to under 6oC at 7.6A
cross-sectional view of the joint is shown, the Cu-post is (~27kA/cm2) test current and 150oC test temperature. EM
patterned on top of Si wafer. The dimension of Cu post is testing was conducted at five different conditions: 150oC (6.4,
approximately 300m in length, 110m in width 35m in 7.0, 7.6A), 140oC/7.0A, and 160oC/7.0A. The temperatures
height. The mating electrode of the bump is the Cu-lead frame used in our testing were determined by the on-chip
(LF) coated with 1m thick Ni. The solder layer was formed temperature sensor. An average of 16 samples were used per
by plating the solder alloy and by subjecting the assembly to a test condition. During EM testing, resistance of the joint was
standard reflow condition. The distance between the top of the closely tracked in order to monitor the level of damage
Cu-post and bottom of LF is approximately 15m. Due to resulted by EM.
formation of Cu6Sn5 at the post interface and (Cu,Ni)6Sn5 at
the LF interface, the actual solder layer thickness is reduced to Results
~12m after the first reflow. In order to simulate the reflow 80
condition that the chip may receive in its application, the t
70 6.4A
samples were subjected to three additional reflow treatments.
60 R
R(t)/R(0), %


40 7.6A




0 500 1000 1500 2000 2500 3000
Time, hrs
Figure 2. A plot showing the representative change in the
sample resistance during EM testing at 150oC under three
different test currents.
Figure 1. Cross-section micrographs showing the overall view
of the Cu-post/LF solder joint (a), the joint microstructure
after the first reflow (b), and after additional reflow treatments EM Damage Measured by Resistance Change
(c). No complete EM failure was seen in our EM testing that
lasted well over 4000 hours in most test splits. There were a
This induces an additional growth of the Cu6Sn5 and few samples, less than 5%, that showed complete failure at
(Cu,Ni)6Sn5 IMCs but the growth is found to be more early stage of the testing but subsequent failure analysis
extensive in a few places along the long-axis direction. As indicated that these early failures were not the result of EM.
shown in Figures 1(b) and (c), where cross-sectional SEM Judging from the fact that they were more or less random in
view of the joint after the first reflow and additional reflow is terms of test conditions, we concluded that they were
compared, the growth of IMC phase on both interfaces, associated with the flaws introduced during assembly process,
post/solder and solder/LF, makes the solder layer to be such as uneven stand-off or residual stress distribution. Since

such flaws can be eliminated by improved process Cu6Sn5 is at its terminal stage where EM induced voiding is
optimization and they were not related to EM reliability, they disrupted. The amount of initial Sn in solder layer is likely to
were removed from our EM analysis. be similar among samples, making the contribution of Sn
While the majority of samples showed no clear sign of consumption by Cu6Sn5 on the joint resistance more or less
EM failure, we found a consistent trend that could be related the same irrespective of sample and EM test conditions.
to EM induced residual damage in the joint. The indicator for Therefore, it is reasonable to assume that the variation in the
the residual damage was found from the increase in the joint peak resistance reflects the total amount of EM induced
resistance. Figure 2 compares the most representative damage in the Sn phase prior to its complete conversion of
resistance traces taken from samples tested at 3 different Cu6Sn5 IMC phase. Also it is reasonable to assume the peak
stress currents at 150oC. Note that the resistance change is not time to be the time for completion of Sn to Cu6Sn5
a monotonic function of time. Rather, it shows an initial stage conversion.
of rapid increase followed by the slowly decaying stage. As a Post EM Joint Microstructure
result, there exists a peak point in the resistance change (RP). In order to substantiate our assumption that the phase
The existence of the resistance peak may appear odd because conversion and EM induced damage in Sn layer is responsible
both the conversion of Sn to Cu6Sn5 IMC and EM damage are for the unique change in the joint resistance shown in Figure
likely to increase the joint resistance. However, we find that 2, EM tested samples were subjected to microscopic
the peak resistance appears because conversion of Cu6Sn5 to inspection. This analysis, conducted on multiple samples per
Cu3Sn IMC phase reduces the joint resistance. test condition, revealed that the joint could be characterized
by two types of isolated voids trapped inside of Cu6Sn5 and
Cu3Sn formed at Cu6Sn5/Cu-post interface. An example of
such microstructure is shown in Figures 3, where SEM
micrographs of the joint taken after ~5200 hours of EM
testing at 150oC under 7.0A are presented. Note that there is
no Sn phase remaining in the joint. This means that Sn phase
is completely consumed and replaced by Cu6Sn5 phase. It also
indicates that the voids visible within the Cu6Sn5 phase are
developed during Sn consumption process because low
diffusivity of Sn and Cu in Cu6Sn5 phase would prevent EM
from occurring to a degree to induce voids of such a scale.
Our inspection on multiple samples suggests that there is no
clear preference for the voiding site.

Figure 3. SEM micrographs showing the post-EM

microstructure of the joint. This sample was tested at 150 oC
under 7.0A current for duration of ~5200 hours.

The electrical resistivity of Sn, Cu6Sn5 and Cu3Sn is

known to be 11.5, 17.5, and 8.9 ohm-cm at room
temperature, respectively [18], and the relative difference in
the resistivity among these phases should be maintained at
temperatures used in our EM testing. Upon commencement of
EM testing, both EM induced voiding and conversion of Sn to
Cu6Sn5 begins to proceed, constituting main part of the
resistance increase. The growth of Cu6Sn5 phase is deemed to
be faster at the LF side due to the polarity effect [17]. More
precisely, the growing IMC phase is (Cu,Ni)6Sn5 because of
the concurrent diffusion of Ni from the LF side, but we shall
call it Cu6Sn5 for simplicity. The Cu6Sn5 phase gradually
consumes the Sn layer while it is growing toward the IMC
layer at the Cu-post interface. Since the resistivity of Cu6Sn5
Figure 4. SEM micrographs comparing the thickness of Cu3Sn
is ~50% higher than that of Sn, this conversion plus the void
phase formed in (a) an EM stressed joint and (b) a reference
formation in Sn makes the joint resistance to increase. On the
joint without current stressing.
other hand, the formation and growth of low resistivity Cu3Sn,
which forms at the Cu-post/Cu6Sn5 interface, should make the
There are also small voids near the interface of Cu3Sn
joint resistance to decrease. As its growth is mainly driven by
and Cu-post. However, their formation is not related to EM as
the interdiffusion of Cu and Sn across Cu6Sn5 phase, it grows
various prior studies on Sn/Cu interfacial reaction suggest that
by consuming Cu6Sn5 as well as the Cu-post.
they are formed during the conversion of Cu6Sn5 to Cu3Sn
Since Cu3Sn growth begins after considerable growth of phase and that they can form without assistance of EM [13,
Cu6Sn5, its influence appears when the Sn conversion to 19]. While these Kirkendall voids are not related to EM, the

growth extent of Cu3Sn phase is found to be influenced by 120
EM. An example evidence of the accelerated Cu3Sn phase
growth is shown in Figures 4. The joint microstructure shown 100
in Figure 4 was taken from a sample tested at 150oC under 7.6A 6.4A
7.6A stress current after ~4900 hours. It can be seen that the 80
thickness of the Cu3Sn phase formed in EM tested joint is

considerably thicker than the one found in the reference joint 60
in the same sample that was subject to thermal aging only.
Since the reference joint was not subjected to EM, the Cu3Sn 40
phase must have been formed by pure inter-diffusion. Thus,
the net thickness difference in these two joints is attributed to 20
the growth acceleration by Cu EM while Sn phase was
surviving in the joint. It should be noted that the accelerated 0
0 500 1000 1500 2000 2500 3000 3500 4000
growth of Cu3Sn phase is not a result of Cu EM in Cu-post
tP, hrs
nor in Cu6Sn5 phase as low diffusivity of Cu in those phases
would make the Cu EM flux to be negligibly small. The Figure 6. A plot showing RP of samples tested at 150oC
growth of Cu3Sn is known to proceed when the Cu6Sn phase under 6.4 and 7.0A as a function of tP.
is sizable [20], and therefore thicker Cu3Sn phase seen in EM
stressed joint can be attributed to the fact that faster
conversion of Sn to Cu6Sn5 makes Cu3Sn growth process to Sn consumption, the result showing decrease in average tP
start faster. It then follows that Cu EM in Sn phase induces with increase in stress current is consistent with the
accelerated growth of both Cu6Sn5 and Cu3Sn IMC phases. expectation. What is unexpected at first glance, though, is the
This conclusion is in good agreement with the findings made result that the average RP is almost independent of current or
from the peak time analysis detailed below. slightly increases with decreasing current. There is a
considerable scatter in RP, but there exists an unmistakable
Dependence of RP and tP on EM Condition
trend that it is more or less independent of current. Since RP
Our attempts to characterize the peak time, tP, of EM is proportional to the amount of voids formed while Sn is
tested samples indicate that it is indeed affected by the EM remaining in the joint and Sn EM is a predominant source of
condition. We were not able to determine RP and tP from all the void, it is expected to increase with the current. In this
samples because some showed resistance with too much respect, the result shown in Figure 5 appears to be odd and
fluctuation when it approached to the peak point while the disagrees with the usual EM damage model. However, we
resistance of others, especially the ones tested at 140oC, did believe that our result may be explained when the effect of tP
not reach the condition to provide clear determination of the on EM voiding kinetics is considered. It is important to note
peak within the given EM testing time. However, we were here that the EM voiding stops when Sn phase is completely
able to collect RP and tP from a reasonably good number of consumed. In this circumstance, the extent of voiding may not
samples, which was sufficient to draw statistically meaningful be a function of the current but can be affected by tP. At lower
conclusions. current, it takes longer time for Sn to be consumed, providing
4 more time for Sn EM to continue, yet such effect is somewhat
1 10
counter-balanced by the smaller Sn-EM flux. This can result
in RP that is at similar or higher level than at higher current.
8000 While there may be other contributing factors, such as the
thermal voiding, our view is supported by the observation of
6000 the strong dependence of RP on tP within samples tested at
tP, hrs

R , %

identical condition. This result is shown in Figure 6 where


RP of samples tested at 150oC under 6.4 and 7.6A is plotted

as a function of their tP. The linear dependence of RP on tP is
clearly evident, suggesting that the extent of EM voiding is
2000 strongly affected by the time to consume the Sn phase.
The same analysis performed on the data collected from
10 samples tested at 140, 150, 160oC under 7.0A provides
6 6.5 7 7.5 8
Current, A additional evidence supporting that Sn conversion rate is
affected by EM and it affects the extent of EM damage. The
Figure 5. A summary plot showing the dependence of RP
analysis result is shown in Figure 7. As expected, temperature
and tP on stress current at 150oC.
affects the Sn conversion rate exponentially. A good portion
of the samples tested at 140oC did not show clearly definable
Figure 5 shows the summary of the data, average RP in stage of resistance decay within 5200 hours of EM testing,
percent increase and tP, collected from the samples tested at presumably due to slow rate of Cu6Sn5 and Cu3Sn growth.
150oC under 3 different currents. Decrease in the average tP This makes us unable to determine the average tP. The
with increasing stress current is evident in the plot. Because tP activation energy for complete Sn conversion time based on tP
approximately corresponds to the time for the completion of taken from 150 and 160oC is estimated to be ~0.9eV. This is

within the known range of activation energy for Cu diffusion high power electronic devices because the current carrying
in Sn phase [21-23]. capability of the joint can be substantially increased.
While the benefit of low-profile solder joint is evident in
150 terms of EM resistance, it results in a challenge in conducting
EM reliability assessment. It is important to realize that the
critical amount of solder for EM immunity is not fixed but
varies with EM condition. For aggressive EM condition, the
1000 100 EM immunity would require small amount of solder, while it

R , %
t , hrs

can be more for less aggressive EM condition. This means

that there is a possibility that EM failure kinetics do not scale

consistently with current and temperature. Also, EM failure

100 50
rate can show considerable scattering even within the samples
tested at the identical condition. This happens because small
160 C
150 C o
140 C change in solder amount or variation in EM condition can
10 0 result in substantial difference in the Sn conversion rate and
0.0023 0.00232 0.00234 0.00236 0.00238 0.0024 0.00242 0.00244
thus EM failure rate. This may make EM test results to appear
Temperature, 1/K chaotic and difficult to use. It is therefore necessary that more
extensive and careful EM testing would be done for the low-
Figure 7. A plot showing RP and tP as a function of profile solder joint.
temperature under 7.0A. The difficulty in conducting EM assessment is
compounded by the lack of reliable data on Cu EM and Sn
Unlike in the case of current effect, the RP is found to EM kinetics. Effective valence for Cu EM in Sn phase, for
increase with more aggressive EM condition, that is, higher example, is presently unknown, creating considerable
temperature. The exact reason why RP behaves differently difficulty in analyzing the failure kinetics by the means of
with temperature is presently unknown. Our speculation is computational analysis. Fundamental study on EM
that Sn EM rate increases much more rapidly with mechanism is necessary and is highly recommended in order
temperature than Cu EM rate. Even if time for Sn conversion to effectively resolve the challenges created by the complex
is reduced at higher temperature, its effect may be outweighed EM failure mechanism active in low-profile solder joint.
by increase in Sn EM rate. Also probable is the addition of Finally, it should be mentioned that the considerable
thermal voiding that is likely to be more active at higher scattering in tP is seen in our test (for example Figure 6),
temperature. which may be a result of the anisotropy in Sn EM rate. It is
well known that the rate of Cu EM as well as Cu diffusion in
Sn differs with the crystallographic orientation [28-29]. It was
Discussion our anticipation that the solder in our test structure would take
As is evidenced in our experimental result, the a polycrystalline structure due to a thin layer of solder in
mechanism of EM in solder joint with limited amount of Sn is lengthy Cu post. Although not included here, our electron-
significantly complicated and poses considerable theoretical back-scattered-diffraction (EBSD) analysis on limited number
and experimental challenges. Unlike in the conventional of samples reveals that the number of grains in the joint is
solder joint, EM mechanism is not a simple function of Sn surprisingly small. We believe that multiple reflow treatment
EM resulting in void formation at the upstream end of atomic we employed is a probable cause of excessive Sn grain
flow. The growth of Cu6Sn5 phase interferes with void growth. The joint to joint variation in crystallographic
formation by removing Sn and thus the competition between orientation of such grains may be the main cause of the large
the Cu-EM and Sn-EM determines the rate of joint failure by scattering in tP seen in our test. This finding suggests that
EM. In an extreme case where Sn amount is limited compared further enhancement in EM reliability is possible if Sn grain
to the rate of Cu6Sn5 phase growth, the joint can be immune to orientation is controlled and made to be uniform. More
EM failure. There may be small amount of left-over voids as a practical method may be the implementation of new assembly
result of short-lived Sn EM, but their amount can be process or alloys that can refine the grain structure. The
negligibly small to create negative impact to the joint refinement does not necessarily make the joint to be more EM
reliability. This, a complete EM failure immunity of low- immune but it would make tP to be more uniform to eliminate
profile solder joint, is what we found in this study and is other reliability issues caused by uneven physical properties
consistent with the results reported in previous studies [24- of solder joints within the assembly. Added benefit will be the
27]. As demonstrated in this paper, the process of EM result of tightly distributed EM performance, which will make
induced voiding completely stops when the joint is fully EM assessment to be much more accurate.
converted to Cu6Sn5 IMC. Our results further suggest that
such mechanism can be further exploited by designing a joint
structure or associated processes to induce quick conversion
of Sn to Cu6Sn5 phase. As long as structural reliability EM testing conducted on the low-profile solder joints
against mechanically driven failure mechanism is ensured, consisting of long Cu-post, thin solder layer and thick LF
superior EM resistance in package interconnects can be produced results suggesting that no complete joint failure
achieved by IMC joints. This is particularly attractive for occurs because void growth is interrupted by the removal of

Sn due to the growth of Cu6Sn5 IMC. The interruption of 11. F.-Y. Ouyang, H. Hsu, Y.-P. Su, and T.-C. Chang,
voiding leaves EM damage in Cu6Sn5 phase in the form of Electromigration induced failure on lead-free micro
residual voids. The amount of the residual voids is found to bumps in three-dimensional integrated circuits
vary with EM condition because the Cu6Sn5 phase growth rate packaging, Journal of Applied Physics, vol. 112, p.
is affected by the Cu EM. The kinetic interplay between the 023505, 2012.
Cu EM, responsible for Cu6Sn5 growth, and Sn EM, 12. Y. C. Chan, and D. Yang, Failure mechanisms of solder
responsible for voiding, is found to be the factor that interconnects under current stressing in advanced
determines the degree of EM damage. This kinetic interplay electronic packages, Progress in Materials Science, vol.
between these two factors makes EM voiding kinetics of the 55, pp. 428-475, 2010.
low-profile solder joint to be more complex than what is 13. D.-Q. Yu, T. C. Chai, M. L. Thew, Y. Y. Ong, V. S. Rao,
found from the more conventional solder joint. L. C. Wai, and J. H. Lau, Electromigration study of 50
m pitch micro solder bumps using four-point kelvin
structure, in Proc. 2009 Electronic Components and
1. K. N. Tu, H. -Y. Hsiao, and C. Chen, Transition from flip
Technology Conference (ECTC), IEEE, 2009, pp. 930-
chip solder joint to 3D IC microbump: Its effect on
microstructure anisotropy, Microelectronics Reliability,
14. K.-W. Moon, W. J. Boettinger, U. R. Kattner, F. S.
vol. 53, pp. 2-6, 2013.
Biancaniello, and C. A. Handwerker, Experimental and
2. H. Huebner , S. Penka, B. Barchmann, M. Eigner, W.
thermodynamic assessment of Sn-Ag-Cu solder alloys,
Gruber, M. Nobis, S. Janka, G. Kristen, and M.
Journal of Electronic Materials, vol. 29, pp. 1122-1136,
Schneegans, Microcontacts with sub-30 m pitch for 3D
chip-on-chip integration, Microelectronic Engineering,
15. M. Murugesan, Y. Ohara, T. Fukushima, T. Tanaka, and
vol. 83, pp. 21552162, 2006.
M. Koyanagi, Low-resistance Cu-Sn electroplated
3. C.-C. Lee, K.-S. Kao, R.-S. Cheng, C.-J. Zhan, and T.-C.
evaporated microbumps for 3D chip stacking, Journal of
Chang. Reliability enhancements of chip-on-chip
Electronic Materials, vol. 41, pp. 720-729, 2012.
package with layout designs of microbumps,
16. B. Chao, S.-H. Chae, X. Zhang, K.-H. Lu, J. Im, P.S. Ho,
Microelectronic Engineering, vol. 120, pp. 138-145, 2014.
Investigation of diffusion and electromigration parameters
4. O. M. Abdelhadi, and L. Ladani, Effect of joint size on
for CuSn intermetallic compounds in Pb-free solders
microstructure and growth kinetics of intermetallic
using simulated annealing, Acta Mater. vol. 55, pp. 2805-
compounds in solidliquid interdiffusion Sn-3.5Ag/Cu-
2814, (2009).
substrate solder joints, Journal of Electronic Packaging,
17. B. Chao, X. Zhang, S.-H. Chae, P.S. Ho, Recent
vol. 135, p. 021004. 2013.
advances on kinetic analysis of electromigration enhanced
5. C.-B. Lee, I.-Y. Lee, S.-B. Jung, and C.-C. Shur, Effect
intermetallic growth and damage formation in Pb-free
of surface finishes on ball shear strength in BGA joints
solder joints, Microelectronics Reliability vol. 49, pp.
with Sn-3.5 mass% Ag solder, Materials Transactions,
253-263, 2009.
vol. 43, pp. 751-756, 2002.
18. M. Li, Z. Li, Y. Xiao, and C. Wang, Rapid formation of
6. I. Shohji, F. Mori, and K. F. Kobayashi, Thermal fatigue
Cu/Cu3Sn/Cu joints using ultrasonic bonding process at
behavior of flip-chip joints with lead-free solders,
ambient temperature, Applied Physics Letters, vol. 102,
Materials Transactions, vol. 42, pp.790-793, 2001.
p. 094104, 2013.
7. M. Lee, M. Yoo, J. Cho, S. Lee, J. Kim, C. Lee, D. Kang,
20. K. Zeng, R. Stierman, T.-C. Chiu, D. Edwards, K. Ano,
C. Zwenger, and R. Lanzone, Study of interconnection
and K. N. Tu, Kirkendall void formation in eutectic SnPb
process for fine pitch flip chip, in Proc. 2009 Electronic
solder joints on bare Cu and its effect on joint reliability,
Components and Technology Conference (ECTC), IEEE,
Journal of Applied Physics, vol. 97, p. 024508, 2005.
2009, pp. 720-723.
21. Y. C. Chan, A. C. K. So, and J. K. L. Lai, Growth kinetic
8. H.-Y. Son, S.-K. Noh, Jung, W.-S. Lee, J.-S. Oh,
studies of CuSn intermetallic compound and its effect on
and N.-S. Kim, Reliability studies on micro-bumps for 3-
shear strength of LCCC SMT solder joints, Materials
D TSV integration, in Proc. 2013 Electronic Components
Science and Engineering B, vol. 55, pp. 5-13, 1998.
and Technology Conference (ECTC), IEEE,2013 , pp.29-
22. N. Mookam, and K. Kanlayasiri, Evolution of
intermetallic compounds between Sn0.3Ag0.7Cu low-
9. Y.-M. Lin, C.-J. Zhan, J.-Y. Juang, J. H. Lau, T.-H. Chen,
silver lead-free solder and Cu substrate during thermal
R. Lo, M. Kao, T. Tian, and K.-N. Tu, Electromigration
aging, Journal of Materials Science and Technology, vol.
in Ni/Sn intermetallic micro bump joint for 3D IC chip
28, pp. 53-59, 2012.
stacking, in Proc. 2011 Electronic Components and
23. Z. Mei, A. J. Sunwoo, J. W. Morris, Analysis of low-
Technology Conference (ECTC), IEEE, 2011, pp. 351-
temperature intermetallic growth in copper-tin diffusion
couples, Metallurgical Transactions A, vol. 23, pp. 857-
10. J. Kim, J.A. Noquil, T. K. Tan, C.-L. Wu, and S.-Y. Choi,
864, 1992.
Multi-flip chip on lead frame overmolded IC package: a
24. R. Labie, W. Ruythooren, K. Baert, E. Beyne, and B.
novel packaging design to achieve high performance and
Swinnen, Resistance to electromigration of purely
cost effective module package, in Proc. 2005 Electronic
intermetallic micro-bump interconnections for 3D-device
Components and Technology Conference (ECTC), IEEE,
2005, pp. 1819-1821

stacking, in Proc. 2008 Interconnect Technology
Conference (IITC), 2008, pp. 19-21.
25. Y. Wang, S.-H. Chae, R. Dunne, Y. Takahashi, K.
Mawatari, P. Steinmann, T. Bonifield, T. Jiang, J. Im, and
P. S. Ho, Effect of intermetallic formation on
electromigration reliability of TSV-microbump joints in
3D interconnect, in Proc. 2012 Electronic Components
and Technology Conference (ECTC), IEEE, 2012, pp.
26. C. C. Wei, C. H. Yu, C. H. Tung, R. Y. Huang, C. C.
Hsieh, C. C. Chiu, H. Y. Hsiao, Y. W. Chang, C. K. Lin,
Y. C. Liang, C. Chen, and T. C. Yeh, "Comparison of the
electromigration behaviors between micro-bumps and C4
solder bumps in Proc. 2011 Electronic Components and
Technology Conference (ECTC), IEEE, 2011, pp.706-710.
27. D.-Q. Yu, T.C. Chai, M.L. Thew, Y.Y. Ong, V.S. Rao,
L.C. Wai, and J.H. Lau, Electromigration study of 50 m
pitch micro solder bumps using four-point Kelvin
structure, in Proc. 2009 Electronic Components and
Technology Conference (ECTC), IEEE, 2009, pp. 930
28.. Y. Wang, K. H. Lu, V. Gupta, L. Stiborek, D. Shirley, J.
Im, and P. S. Ho, Effect of Sn grain structure on
electromigration reliability of Pb-free solders, in Proc.
2011 Electronic Components and Technology Conference
(ECTC), 2011, pp. 711-716.
29. K. Lee, K.-S. Kim, Y. Tsukada, K. Suganuma, K.
Yamanaka, S. Kuritani, and M. Ueshima, Effects of the
crystallographic orientation of Sn on the electromigration
of Cu/SnAgCu/Cu ball joints, Journal of Materials
Research, vol. 26, pp. 467-474, 2011.