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MAQUINAMOORE.

vhd Thu Nov 03 20:22:47 2016
1 ----------------------------------------------------------------------------------
2 -- Company: INSTITUTO TECNOLOGICO DE LAZARO CARDENAS
3 -- Engineer: MARIO ALBERTO ALVAREZ VAZQUEZ
4 --
5 -- Create Date: 19:28:10 10/31/2016
6 -- Design Name: MAQUINA DE MOORE
7 -- Module Name: MAQUINAMOORE - Behavioral
8 ----------------------------------------------------------------------------------
9 library IEEE;
10 use IEEE.STD_LOGIC_1164.ALL;
11
12 entity MAQUINAMOORE is
13 Port ( clk : in STD_LOGIC;
14 rst : in STD_LOGIC;
15 w : in STD_LOGIC;
16 z : out STD_LOGIC);
17 end MAQUINAMOORE;
18
19 architecture Behavioral of MAQUINAMOORE is
20
21 type estados is (A,B,C);
22 signal actual, proximo:estados;
23 begin
24 prox: process(actual,w)
25 begin
26 case actual is
27 when A => case w is
28 When '0' => proximo <= A;
29 When others => proximo <= B;
30 end case;
31 When B => case w is
32 When '0' => proximo <= A;
33 When others => proximo <= C;
34 end case;
35 When C => case w is
36 When '1' => proximo <= C;
37 When others => proximo <= A;
38 end case;
39 end case;
40 end process prox;
41
42 sal: process(actual)
43 begin
44 case actual is
45 when A => z <= '0';
46 when B => z <= '0';
47 when C => z <= '1';
48 end case;
49 end process sal;
50
51 act: process(clk)
52 begin
53 if clk'event and clk ='1'
54 then if rst = '1'
55 then actual <= A;
56 else actual <= proximo;
57 end if;
58 end if;
59 end process act;
60 end Behavioral;

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