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# 5.

- Implementar un circuito que genere la siguiente forma de onda:
SEL DC
00 10%
01 25%
10 75%
11 90%
Sabiendo que la señal de reloj es de 48MHz y la salida tiene una
frecuencia de 1KHz.

Código:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity prob_1 is
Port (clk: in std_logic;
sel: in std_logic_vector(1 downto 0);
z: buffer std_logic);
end prob_1;
architecture Behavioral of prob_1 is
signal conta: std_logic_vector(8 downto 0);
signal a1,a2,a3,a4: std_logic;
begin
process(clk)
begin
if clk='1' and clk'event then conta<=conta+1;
if conta = 49 then a1<='1';
end if;
if conta = 124 then a2<='1';
end if;
if conta = 374 then a3<='1';
end if;
if conta = 449 then a4<='1';
end if;
if conta=499 then conta<=(others=>'0');
a1<='0';
a2<='0';
a3<='0';
a4<='0';
end if;
end if;
end process;
z<= a1 when sel="00" else
a2 when sel="01" else
a2 when sel="10" else a4;

end Behavioral;

end process. if cont10 = 9 then cont10 <= "0000". signal cont4: std_logic_vector(1 downto 0). . end if. entity div_8opc is port(clk: in std_logic. use ieee. end if. end process.6. if cont50 = 49 then cont50 <= "000000".. end if.std_logic_1164. end if. signal cont10: std_logic_vector(3 downto 0).all.all. architecture solucion of div_8opc is signal clk1. sel: in std_logic_vector(2 downto 0).std_logic_unsigned. use ieee. z: out std_logic). signal cont50: std_logic_vector(5 downto 0). use ieee. process(clk2) begin if clk2 = '1' and clk2'event then cont50 <= cont50 + 1.all.Implementar un circuito divisor de frecuencia programable SEL Fout 000 0 001 CLK/2 010 CLK/10 011 CLK/50 100 CLK/100 101 CLK/200 110 CLK/1000 111 1 library ieee.std_logic_arith.clk2: std_logic. process(clk1) begin if clk1 = '1' and clk1'event then cont10 <= cont10 + 1. end if. begin process(clk) begin if clk = '1' and clk'event then cont4 <= cont4+1. end div_8opc.

end timer. reset : in std_logic.all. end solucion. end if. '1' when "111". . ena : in std_logic. cont4(0) when "001". use ieee.end process. 7. z : out std_logic).std_logic_unsigned.reset) begin if reset = '1' then habilitado <= '0'. clk1 <= cont4(0) when sel = "110" else clk. process(clk. cont10(3) when "010". signal trigger : integer.reset) begin if reset = '1' then cuenta <= (others =>'0').std_logic_1164.all. begin process(clk. use ieee. architecture Behavioral of timer is signal cuenta : std_logic_vector(25 downto 0). elsif ena = '1' then habilitado <= '1'. clk2 <= cont4(0) when sel = "100" else cont4(1) when sel = "101" else cont10(3) when sel = "110" else clk. end process. entity timer is port ( sel : in std_logic_vector(1 downto 0). with sel select z <='0' when "000".all. signal habilitado : std_logic.Implementar un circuito para temporizar: SEL Tiempo 00 10ms 01 100ms 10 500ms 11 1000ms library ieee. use ieee. cont50(5) when others. clk : in std_logic..std_logic_arith.

signal x : std_logic_vector(2 downto 0). z <= '0'. esc : in std_logic_vector(2 downto 0). end if. hab : in std_logic. elsif clk = '1' and clk'event then if habilitado = '1' then cuenta <= cuenta + 1. z : out std_logic). signal clk2 : std_logic.all. 480000 when "01". with sel select trigger <= 48000 when "00". library ieee.. use ieee. entity pwm_prog is port ( clk : in std_logic. signal cuenta2 : std_logic_vector(9 downto 0).all. z <= '1'. end if. 8. DC : in std_logic_vector(10 downto 0). x16 ● El ciclo de trabajo (DC) se define con 110 bits de entrada. x4. use ieee. end Behavioral. signal clk1 : std_logic. architecture Behavioral of pwm_prog is signal cuenta1 : std_logic_vector(2 downto 0).std_logic_1164. 2400000 when "10". 4800000 when others. use ieee. if cuenta = trigger then cuenta <= (others => '0'). ● Tiene habilitador. end pwm_prog. end if.all.Implementar un circuito para generar una señal PWM con la siguiente característica: ● Resolución: Resolución: 10 bits.std_logic_arith. ● Escalador: x1. x8.std_logic_unsigned. begin process (clk) . x2. end process.

9. elsif cuenta2 = 1023 then cuenta2 <= (others => '0'). "001" when "010".hab) begin if hab = '0' then cuenta2 <= (others => '0').begin if clk = '1' and clk'event then cuenta1 <= cuenta1 + 1. "111" when others. z <= '0'. end process. end process.. clk1 when others. end if. end if.Implementar un reloj que cuente los segundos y minutos (MM:SS) y que muestre la información en 4 display a 7 segmentos del tipo ánodo común y comparten los mismos pines de los segmentos. "011" when "011". if cuenta1 <= x then cuenta1 <= (others => '0'). end Behavioral. with esc select x <= "000" when "001". . end if. if cuenta2 = DC then z <= '0'. z <= '1'. clk1 <= not clk1. with esc select clk2 <= clk when "000". Utilice el componente diseñado en la pregunta 3 como generador de reloj. elsif clk2 = '1' and clk2'event then cuenta2 <= cuenta2 + 1. process (clk2. end if.