CompE 271 Mid-term Exam #2 Fa16 NAME:______SOLUTIONS__________

Ken Arnold Red ID: .

1) Convert the C function below to IA-32 assembly language.

30 pts

void ComplementMemBit(long *address, int BitNumber)

// Complement the bit in specified memory location
{ *address ^= 1 << BitNumber; }

_ComplementMemBit:

push %ebp // setup

movl %esp, %ebp
push %ebx

movl 8(%ebp),%ebx // get address in ebx

movl (%ebx),%eax // fetch contents of mem in eax
movl 12(%ebp),%ecx // get bit number in ecx

movl $1,%edx // put a 1 in LSB of edx

shl %cl,%edx // shift the 1 left cl times
xorl %edx,%eax // XOR the 1 with mem content

movl %eax,(%ebx) // restore to original location

pop %ebx // clean up

pop %ebp

ret // return to caller

NOTE: This function can be done in many, many other ways,

such as using a loop to shift the 1 bit left one bit at a
time, etc. Credit is given for any plausible approach.

2) How does a semaphore differ from a simple flag?

10 pts
A semaphore is accessed using an indivisible test and set operation.
(A simple flag may be accessed in separate test and set operations.)

/40

1
CompE 271 Mid-term Exam #2 Fa16 NAME:______SOLUTIONS__________
Ken Arnold Red ID: .

3) Can software design affect interrupt latency? Why/why

not?
10pts

Yes! Because the maximum interrupt latency depends on how long the
interrupts are disabled (e.g.: in critical code segments), and the
priority of the interrupts in a nested interrupt system.

4) Make a state table for a 2-floor elevator FSM that has

the following state sequence: When UP button is pressed on
floor 1, elevator goes up to floor 2, when DOWN button is
pressed on floor 2, elevator goes down to floor 1, otherwise
elevator stays on the current floor.
10 pts

Current state Condition Next State Output

Floor 1 Up button Floor 2 Go UP
Floor 1 Not Up Floor 1 Stay put
Floor 2 Down button Floor 1 GO DOWN
Floor 2 Not Down Floor 2 Stay put

Any plausible state table is acceptable, partial credit for state bubble
diagram, depending on how complete it is.

5) What is the difference in the way SRAM and DRAM store

bits?
10 pts

SRAM (Static RAM) stores bits in flip-flops; 4 transistors/bit.

DRAM (Dynamic RAM) stores bits as charge on a cap; 1 transistor/bit.
Also DRAM charge leaks and must be refreshed, SRAM does not.

6) List 3 differences between CISC and RISC architectures:

15 pts

CISC
Variable length instructions
Multiple clocks/instruction
Many >100 instructions and
address mode combinations
More complex hardware/logic
Variable number of operands
Smaller object code due to
more complex instructions
Higher power consumption
RISC .
Fixed length instructions
Single clock/instruction
Few <<100 instructions and
address mode combinations
Simpler logic/hardware
Fixed number of operands
Larger object code due to
simpler instructions
Lower power consumption

/45

2
CompE 271 Mid-term Exam #2 Fa16 NAME:______SOLUTIONS__________
Ken Arnold Red ID: .

7) What are the three parts of an interrupt driven program,

and what does each part do?
15 pts
must have at least one item from each of 3 lists:

1) Initialization code (first part of main)

Sets up interrupt system, clear pending interrupts
Initialize vector table
Initializes any global variables

2) ISR - Interrupt Service Routine

Saves processor state (push regs on stack, etc.)
Processes the event that caused the interrupt
Interrupt return instruction

3) Main program Non-event driven code

After initialization:
perform any non-event driven functions
e.g.: main while(1), polling super-loop or sleep

8) List ALL memory characteristics (A-K) that apply to each

type of semiconductor memory:
20 total, 5 pts ea

SRAM _A D H J_(G)_ DRAM _A D F I J (G)

EEPROM _B C E G K_(A,J) FLASH _B C E J K L (A)

(Letters in parentheses are ok but not required)

Memory Characteristics that apply to above memories:

A) Read/Write B) Read-Mostly C) Must erase before write
D) Volatile E) Non-volatile F) Must be refreshed
G) Byte erasable H) Used for Cache memory
I) Multiplexed Addresses J) Used for Primary memory
K) Used for Secondary Memory L) Must erase blocks/sectors

9) A PC memory module contains 4GB of 64bit DRAM memory.

a) How many 1Gbit memory ICs, organized as 256Mx4, are used
on the module?
15 pts

The memory must have at least 16 memory ICs since each chip is 4 bits
wide, and 64bits/4bits/IC = 16 ICs. 256Mx64 = 256Mx(8x8) or 2Gx8= 2
GBytes. So 32 ICs are used to make up a total of 4 GBytes per module.

b) How many address pins are required on each memory IC?

10 pts

28=256 and 220=1M so

256M = 228 so 28 address bits, multiplexed row/col = 14 pins

/60

3
CompE 271 Mid-term Exam #2 Fa16 NAME:______SOLUTIONS__________
Ken Arnold Red ID: .

10) Which of the two functions below will execute faster on

a PC with cache memory:
sum_array_cols() or sum_array_rows()?
15 pts

int sum_array_cols(int a[M][N])

{
int i, j, sum = 0;

for (j = 0; j < N; j++)

for (i = 0; i < M; i++)
sum += a[i][j];
return sum;
}

int sum_array_rows(int a[M][N])

{
int i, j, sum = 0;

for (i = 0; i < M; i++)

for (j = 0; j < N; j++)
sum += a[i][j];
return sum;
}
sum_array_rows() is faster

Why?
25 pts
The spatial locality of the data: cache memory will store
adjacent array items in rows in cache memory location. The
array a[] is stored in row major order as follows:

addr content
0 a[0][0]
1 a[0][1]
2 a[0][2]
3 a[0][3]
4 a[0][4]
...
n a[1][0]
n+1 a[1][1]
n+2 a[1][2]
...

/40