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What Is ISA?

Lecture 3: Instruction set architecture is the structure of a


computer that a machine language programmer (or a
Instruction Set compiler) must understand to write a correct (timing
independent) program for that machine.
Architecture For IBM System/360, 1964

Assembly language
Appendix A
Contract between software and hardware
Software portability
Hardware flexibility

Classification of ISA Stack


Implicit operands on stack
Types
Ex. C = A + B
Stack
Push A
Accumulator
Push B
General-purpose register
Add
Reg-Mem
Reg-Reg Pop C
Good code density; used in
ISA is mature and stable 60s-70s; now in Java VM

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Accumulator Register-Memory
The accumulator provides an
implicit input, and is the There is no implicit operand
implicit place to store the One input operand is
result. register, and one in memory
Ex. C = A + B Ex. C = A + B
Load R1, A
Load A Add R3, R1, B
Add B Store R3, C
Store C Processors include VAX,
x86
Used before 1980

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Register-Register (Load-Store) General-Purpose Registers


Both operands are registers General-purpose registers are preferred by
Values in memory must be compilers
loaded into a register and Reduce memory traffic
stored back Improve program speed
Ex. C = A + B Improve code density
Load R1, A
Usage of general-purpose registers
Load R2, B
Add R3, R1, R2 Holding temporal variables in expression evaluation
Store R3, C Passing parameters
Holding variables
Processors: MIPS, SPARC

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Variants of GPR Architecture How Many Registers?
Number of operands in ALU instructions: two or If the number of registers increase:
three
Add R1, R2, R3 Add R1, R2 Allocating more variables in registers (fast accesses)
Maximal number of memory operands in ALU Reducing code spill
instructions: zero, one, two, or three Reducing memory traffic
Load R1, A Load R1, A
Load R2, B Add R3, R1, B Longer register specifiers (difficult encoding)
Add R3, R1, R2 Increasing register access time (physical registers)
Three popular combinations More registers to save in context switch
register-register (load-store): 0 memory, 3 operands
register-memory: 1 memory, 2 operands
MIPS64: 32 general-purpose registers
memory-memory: 2 memories, 2 operands; or 3 memories, 3
operands

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ISA and Performance Memory Addressing


CPU time = #inst CPI cycle time
Instructions see registers, constant values, and memory
RISC with Register-Register instructions (MIPS, PowerPC, UltraSPARC,
ARM, MIPS16) Addressing mode decides how to specify an object to access
Simple, fix-length instruction encoding Object can be memory location, register, or a constant
Simple code generation Memory addressing is complicated
Regularity in CPI

Higher instruction counts
Memory addressing involves many factors
Lower instruction density Memory addressing mode
Object size
CISC with Register-Memory instructions (IBM 360/370, VAX, and Byte ordering
Intel x86) Alignment
No extra load in accessing data in memory
Easy encoding

Operands being not equivalent
For a memory location, its effective address is calculated in a

Irregularity in CPI
certain form of register content, immediate address, and PC, as
specified by the addressing mode

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Little or Big: Where to Start? Addressing Modes
Register ADD R16, R8
Byte ordering: Where Number 0x5678 Immediate ADD R17, #100
is the first byte?
Little-endian Big-endian Displacement ADD R2, (100)R1
Big-endian: IBM, Direct (absolute) ADD R1, (1000)
SPARC, Motorola
Register indirect SUB R2, (R1)
Little-endian: Intel, DEC Indexed ADD R1, (R2 + R3)
Supporting both: MIPS, Scaled SUB R2, 100(R2)[R3]
PowerPC Autoincrement ADD R1, (R2)+
00000003 5 8
Issue: when they 00000002 6 7 Autodecrement SUB R2, -(R1)
exchange data 00000001 7 6 Memory indirect ADD R1, @(R3)
00000000 8 5 (see textbook pA-9)

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Choosing of Memory Addressing How Often Are Those Address


Modes Modes?
Choosing complex addressing modes
Close to addressing in high-level language
May reduce instruction counts
Increase implementation complexity (may increase
cycle time)
Increase CPI

RISC ISA comes with simple memory addressing, and


CISC ISA with complex ones
Usage of address modes, VAX machine, SPEC89
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Simple ones used most 16

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Instructions for Control Flow Issues in Control Flow
Conditional branch: change control flow based on a
Instructions
condition Memory addressing modes
Jump: unconditional change of control flow How to specify addresses to transfer
Procedure call Can be either PC-relative or register indirect
Procedure return Conditional branch options
What kind of conditions can be directly used
When and how to evaluate conditions
How to link branch instructions with conditions
Procedure invocation options
When to save and restore register contents
When to save global variables

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PC-relative Addressing Mode Bits in Displacement


Inst
The jump address is PC+d; d
can be negative
PC

d
Fewer bits in displacement
With position independence
e.g. loop

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Register Indirect Conditional Branch
Conditional code
Jump or branch to an address stored in a

Test special bits set by ALU operations
+ Sometimes condition is set for free
register

- CC is extra state, constraint on inst order
80x86, ARM, PowerPC, SPARC, SuperH
Condition register
Used for programming language with Test register (result of comparison)
+ Simple
Case or switch statements - Use up a register
Alpha, MIPS
Virtual function or methods Compare and branch
Compare is part of the branch
Function pointers
+ One inst for a branch
- Too much for the branch inst
Dynamically shared libraries
PA-RISC, VAX

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Procedure Invocation Options Caller Saving vs. Callee Saving


Saving return address P1() Caller Saving Ex. Callee Saving Ex.
P1: P2:
Use general-purpose c = a; Store R1, 200(SP)
register
Store R1, 100(SP) (R1 changes)
Use special link register Call P2 Load R1, 200(SP)
P2(); Load R1, 100(SP) Ret
Add R3, R2, R1
Saving register contents
Caller knows those regs it Callee knows those regs it
of caller procedure d = c + b; will use will change
Some regs may not to be Some regs may not needed
changed by callee by caller
Global variable in register

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Encoding Instruction Set Conflicting Desires
address address address
operation Encoding more registers and addressing
field 1 field 2 field 3
modes
Compiler needs, DSP needs, etc.
What to encode
Operation (opcode) Reducing size of instruction (program)
Address field (for operands)
Facilitating pipelining
Address specifier (for addressing modes) Align to byte boundary
Only for ISA with complex addressing modes Prefer fixed length

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Practical Choices Reduce Code Sizes in RISC


Hybrid of 16-bit and 32-bit instructions
ARM Thumb, MIPS MIPS16

Compression
IBM CodePack (full-size inst. in cache, compressed
inst. in main memory, disk)

Reduce 32-bit to 16-bit


Hitachi SuperH (32 regs -> 16 regs)

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MIPS ISA MIPS Addressing Modes
Register
Registers
DADDU R4, R2, R1
32 GPRs (integer registers) Immediate
DADDIU R4, R2, #3
R0, R1, , R31
Displacement


32 FPRs (floating-point registers) LW R4, 100(R1)
Register indirect
F0, F1, , F31 Place 0 as displacement
A few special registers
LW R4, 0(R1)
Absolute
e.g. FP status register Use R0 as base register (R0 is always 0)
LW R4, 100(R0)

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MIPS Instruction Types MIPS Instruction Format


Data transfer: Load and store Fixed-length instructions
LD R16, 100(R2) Regs[R16] <- Mem[100+Regs[R2]]

R-type
Integer arithmetic/logic
Register-register ALU operations
DADDIU R1, R2, #17 Regs[R1] <- Regs[R2] + 17
Floating point arithmetic I-type
ADD.D F0, F2, F0 Regs[F0] <- Regs[F2] + Regs[F0] Load/store, immediate, conditional branch,
Control instructions (branches and jumps) jump register
BEQZ R3, loop if (Regs[R3] == 0) PC <- loop J-type
Jump

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MIPS R-type Instructions R-type Example
op rs rt rd shamt funct op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

Instruction fields add $t0, $s1, $s2

op: operation code (opcode)


special $s1 $s2 $t0 0 add
rs: first source register number
rt: second source register number 0 17 18 8 0 32

rd: destination register number 000000 10001 10010 01000 00000 100000
shamt: shift amount
000000100011001001000000001000002 = 0232402016
funct: function code (extends opcode)

MIPS I-type Instructions MIPS J-type Instructions


op rs rt constant or address 6 26
6 bits 5 bits 5 bits 16 bits J-type opcode offset
Immediate arithmetic and load/store instructions
Immediate: rt <- rs op constant Jump
rt: destination (load) or source (store) register number Offset: offset added to PC for jumps
Constant: 215 to +215 1
Address: offset added to base address in rs Jump 26-bit offset
Conditional branch ((PC+4)-227) <= NPC < ((PC+4)+227)
rs, rt: comp., constant: displacement I-type 16-bit offset:
Jump register: rs: destination ((PC+4)-217) <= NPC < ((PC+4)+217)

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