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7401 4 quad 2-input NAND gate, open collector outputs

7402 4 quad 2-input NOR gate

7403 4 quad 2-input NAND gate, open collector outputs

7404 6 hex inverter

7405 6 hex inverter, open collector outputs

7406 6 hex inverter buffer/driver, 30 V open collector outputs

7407 6 hex buffer/driver, 30 V open collector outputs

7408 4 quad 2-input AND gate

7409 4 quad 2-input AND gate, open collector outputs

7410 3 triple 3-input NAND gate

7411 3 triple 3-input AND gate

7412 3 triple 3-input NAND gate, open collector outputs

7413 2 dual Schmitt trigger 4-input NAND gate

7414 6 hex Schmitt trigger inverter

7415 3 triple 3-input AND gate, open collector outputs

7416 6 hex inverter buffer/driver, 15 V open collector outputs

7417 6 hex buffer/driver, 15 V open collector outputs

7418 2 dual 4-input NAND gate, Schmitt trigger inputs

7419 6 hex Schmitt trigger inverter

7420 2 dual 4-input NAND gate

7421 2 dual 4-input AND gate

7422 2 dual 4-input NAND gate, open collector outputs

7423 2 expandable dual 4-input NOR gate, strobe

7424 4 quad 2-input NAND gate gates, Schmitt trigger line-receiver inputs.

7426 4 quad 2-input NAND gate, 15 V open collector outputs

7427 3 triple 3-input NOR gate

7428 4 quad 2-input NOR buffer

7430 1 8-input NAND gate

7431 6 hex delay elements

7432 4 quad 2-input OR gate

7433 4 quad 2-input NOR buffer, open collector outputs

7434 6 hex non-inverters

7435 6 hex non-inverters, open-collector outputs

7437 4 quad 2-input NAND buffer

7438 4 quad 2-input NAND buffer, open collector outputs

quad 2-input NAND buffer, open collector outputs,

7439 4

input and output terminals flipped, otherwise functionally identical to 7438

7440 2 dual 4-input NAND buffer

4001 - Quad 2-input NOR gate

4008 - 4-bit full adder

4011 - Quad 2-input NAND gate

4013 - Dual D Type Flip Flop

4017 - Decade counter / walking ring counter

4026 - 7-segment LED counter

4049 - Hex inverting buffer

4050 - Hex non-inverting buffer

4051 - 8-channel analog multiplexer / demultiplexer

4071 - Quad 2-input OR gate

4081 - Quad 2-input AND gate

GENERAL DECODER DIAGRAM

2-to-4-Line Decoder

The circuit operates with complemented

outputs and a complement enable input. The

decoder is enabled when E is equal to 0.

Only one output can be equal to 0 at any given

time, all other outputs are equal to 1.

The output whose value is equal to 0

represents the minterm selected by inputs A

and B

The circuit is disabled when E is equal to 1.

3-8 line decode (active-HIGH)

This decoder can be referred to in several

ways. It can be called a 3-line-to- 8-line decoder,

because it has three input lines and eight

output lines.

It could also be called a binary-octal decoder

or converters because it takes a three bit binary

input code and activates the one of the eight

outputs corresponding to that code. It is also

referred to as a 1-of-8 decoder, because only 1

of the 8 outputs is activated at one time.

Example of a 5 to 32 Bit Decoder

Logic symbol for a 4-line-to-16-line

(1-of-16) decoder . 74HC154

4-line-to-16 line Decoder constructed with

two 3-line-to-8 line decoders (1)

When w=0, the top decoder is enabled and

the other is disabled. The bottom decoder

outputs are all 0s , and the top eight outputs

generate min-terms 0000 to 0111.

When w=1, the enable conditions are

reversed. The bottom decoder outputs

generate min-terms 1000 to 1111, while the

outputs of the top decoder are all 0s.

BCD -to- Decimal decoders

The BCD- to-decimal decoder converts each BCD code

into one of Ten Positionable decimal digit indications. It

is frequently referred as a 4-line -to- 10 line decoder

The method of implementation is that only ten

decoding gates are required because the BCD code

represents only the ten decimal digits 0 through 9.

Each of these decoding functions is implemented with

NAND gates to provide active -LOW outputs. If an

active HIGH output is required, AND gates are used for

decoding

Logic diagram of BCD - decimal decoder

(Active LOW output)

Output Waveform for BCD Decoder

A Decoder Application - Counter -decoder combination used to

provide timing and sequential operations

Decoders are used whenever an output or a group

of outputs is to be activated only on the occurrence of

specific combination of input levels. These input

levels are often provided by the outputs of a counter

or register.

When the decoder inputs come from a counter that

is being continually pulsed, the decoder outputs will

be activated sequentially, and there can be used as

timing or sequencing signals to turn device on or off

at specific times

BCD-7SEGMENT

DECODERS/DRIVERS

Most digital equipment has some means

for displaying information in a form that

can be understood by the user. This

information is often numerical data but

also be alphanumeric.

One of the simplest and most popular

methods for displaying numerical digits

uses a 7-segment configuration to form

digital characters 0 to 9 and some times

the hex characters A to F

h

74LS47 ( BCDtoSevenSegment Decoder)

Lamp Test (LT)

segments in display are turned zero, LT is used to

verify that no segments are burned out

displays to blank out unnecessary zeros.

Example:

In a 6-digit display the number 6.4 may be displayed

as 006.400 if the zeros are not blanked out

Leading Zero Suppression

Blanking the zeros at the front of a numbers

Blanking the zeros at the back of the number

number 030.080 will be displayed as 30.08 (the

essential zeros remain)

7-SEGMENT DISPLAY

displays;

A) common - anode

B) common cathode

COMMON ANODE

In commonanode, the anode of all of the LEDs are tied

together to positive of the power supply (Vcc) as shown

Common Cathode

In commoncathode, the cathode of all of the LEDs are

tied together to ground as shown.

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