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Parity Bit Generator

Akhil Agrawal, Abhay Vinayak


B.Tech ECE, IIIT Hyderabad
akhil.agrawal@students.iiit.ac.in
B.Tech ECE, IIIT Hyderabad
abhaya.vinayak@students.iiit.ac.in

Abstract A new 3-Input XOR gate based upon the pass example in Table1.(a) helps in easily understanding the
transistor design methodology for low voltage, a low-voltage proposed circuit. In example we have assumed input bits to be
high-speed application is proposed to implement parity 1, 0, and 1 and accordingly checked which transistors are
generator. An even parity bit generator generates an output of 0 ON or OFF. The circuit has very short transition path and
if the number of 1s in the input sequence is even and 1 if the full-swing signal at output.
number of 1s in the input sequence is odd. The checker circuit
gives an output of 0 if there is no error in the parity bit P1 P2 P3 P4 P5 P6 N1 N2 N3 N4 N5 N6
generated. Thus it basically checks to see if the parity bit X=1
Y=0 Off On Off On Off On Off On On Off Off On
generator is error free or not. Z=1

Keywords Parity Bit; XOR Gate; Pass Transistor Logic;


Table1.(a)
CMOS Design; Power-Delay Product; Transistors; Power
Dissipation;

I. INTRODUCTION III. SIMULATION/COMPARISON RESULTS


At gate design level, a proper choice of a circuit style for
implementing combinational circuits is very important.
Depend on the applications, for example, a low power and low The proposed 3-input XOR gate is the best design as
voltage requirement or a high-speed and low power-delay compared to CMOS design and the other design which is too
product requirement, different types of circuits may be based on PTL. Fig1.(a),Fig1.(b),Fig1.(c) shows the schematic
adopted. The objective of this work is to propose a better of proposed parity bit generator circuit, design based on PTL
solution to fit various kinds of requirements including low and CMOS design respectively. The Design using Pass
voltage, low-power, power-delay product and operation speed Transistor Logic (PTL) is a good classical cascaded design
by implementing parity bit generator using 3-input exclusive- for minimizing no. of transistors used. It involves a least
or (XOR) logic. A parity bit is a bit that is added to ensure that number of transistors that are 12. It does not uses inverted
the number of bits with the value one in a set of bits is even or inputs which makes it much easier and beneficial design. Also
odd. Parity bits are used as the simplest form of error it is a good design for low voltage and low power applications.
detecting code. The simulation results and performance But at the same time it has some limitations like it does not
comparisons between two existed and one new proposed operate at high supply voltages. Also the power-delay product
circuit are shown in Table(a). The new proposed circuit has is much higher than the above proposed design. The CMOS
the best power-delay product at all supply voltages in all design is a complimentary logic design. It is a good design for
circuits. Finally some conclusions are shown in. The minimal low-voltage application but operates at low speed and a much
output equation is P X Y Z XY Z XYZ X Y Z X Y Z . area is wasted as it involves 26 transistors if inverted inputs
P is parity bit generated and X, Y, Z are input bits. Checker bit are not mentioned. Also power-delay product comes out to be
is defined as C= P P, which is XOR of two parity bits. Its highest for this design, leaving it to be the least-efficient
output or value of C remains 0 if parity bit is correctly design then.
generated else it outputs C=1. The parity bit generation
function can be implemented using three exclusive-or gates. The Schematic and Layout of the proposed circuit are
shown in Fig2.(a) and Fig2.(b) respectively. This is done on
Tanner Tool of VLSI Design. The technology followed here is
II. PROPOSED CIRCUIT w = 4 micron and l=0.5 micron. The layout rules used are
The new proposed 3-input XOR gate using the pass-transistor lambda rules and the aim is to optimise the area, Power
logic circuit is shown in Fig1.(a).The circuit uses 18 Consumption and Delays.
transistors overall if inverted inputs are not accounted and a
separate inverter is drawn for every inverted signal. An
Power Dissipation:
Design Supply Average Power Power No. of a) Layout = 0.025 nW (5V)
Voltage Time Dissipation(mw) Delay Transistors
0.004 nW (2V)
Delay(ns) Product(fJ)
Proposed 5 0.499 0.682 341 18 b) Schematic = 0.682 mW (5V)
2 0.704 0.0236 16.61 18 0.0236 mW (2V)
CMOS 5 0.681 0.536 362.97 12
2 0.371 0.0547 20.304 12
Area of Design (Acc. to tanner L-Edit) = 577.4 microne2
PTL 5 0.546 0.736 401.86 26 Normalized Power-Delay Product:
2 0.612 0.02769 16.96 26 At 5V supply: 341fJ

Table 1.(b) At 2V supply: 16.61 fJ

The average delay-time is calculated with the input signals The proposed 3-input XOR gate circuit has an excellent
(Gray code) varying from XYZ=000 to XYZ=100. The performance at power-delay product factor at all supply
simulated supply voltages are 5V, 3.3V, 2.5V, 2V, lV, voltages. So, this design proves to be better to generate parity
respectively. The simulation results for supply voltage to be bit and accordingly find if/any error are there or not in a bit
5V and 2V are shown in Table 1.(b). At high supply voltages train.
(5V), the new proposed circuit Fig2.(a) has at least 10-20%
improvement in power-delay product than the CPL structure
and 25-30% improvement than the CMOS structure. At low
supply voltage (2V) the new proposed circuit has at least 40%
improvement in power-delay product than the CPL structure
and 10-15% improvement than the CMOS structure.
Moreover the new proposed circuit could also be operated as
low as 1V. It is clear that although more transistors are used in
the proposed circuit, but it does not mean extra power
dissipation due to its passive transistor switches and full
output voltage swing property. So the proposed circuit can be
a well design for low-power and low-voltage applications.
And when it comes to low-voltage, row-power and high-speed
applications the new proposed circuit seems the best choice. Fig1.(a)

IV. RESULT AND CONCLUSIONS


Following are the various delays and Power Dissipation and
area of the proposed design. (Delay is visible in images too).

At 5V supply,
Rise Time Delay, tdr = 435.33ps
Fall Time Delay, tdf = 564.65ps
Total Delay (td = (tdr + t df)/2) = 499.99ps

At 2V supply,
Rise Time Delay, tdr = 830.85ps
Fall Time Delay, tdf = 577.46ps
Fig1.(b)
Total Delay (td = (tdr + t df)/2) = 704.09ps
Fig1.(c)

Waveforms obtained from the Tanner


The figures mentioned below shows various waveforms
obtained when T-Spice simulation is produced in Tanner.

REFERENCES

[I] Sung-Chuan Fang, Jyh-Ming Wang, and Wu-Shiung


Feng A New Direct Design for Three-Input XOR Function
on the Transistor Level in IEEE Transactions on Circuits and
Systems, vo1.43, no.4, April 1996.

[2] N. H. E. Weste and K. Eshraghian, Principle of CMOS


VLSI Design 2nd Edition, Addison Wesley, 1993.

[3] M. Suzuki, N. Ohkubo, T. Shinbo, T. Yamanaka et.


al.Al.5ns 32-b CMOS ALU in Double PASS-Transistor
Logic, IEEE J. Solid-state Circuits, vol. 28, no. 11, pp. 1145-
1 151, November 1993.

[4] Zan Xhuang and Haomin Wu, A New Design of the


CMOS Full Adder in IEEE J. Solid- State Circuits, vol. 27
no. 5, pp. 840-844, May 1992.

[5] http://en.wikipedia.org/wiki/Parity_bit.
Fig2.(a) Schematic of proposed Even Parity Bit Generator (made using Tanner S-Edit)

Fig2.(b) Layout of Proposed Circuit (made using Tanner L-Edit)


Fig. Output Waveform at 5V supply of Proposed Circuit

Fig. Rise and Fall Time Delays of Output at 5V supply


Fig. Output Waveform at 2V supply

Fig. Rise and Fall Time Delays of Output at 2V Supply