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Circuit Note

Devices Connected/Referenced

AD698 Universal LVDT Signal Conditioner
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analog, mixed-signal, and RF design challenges. For more AD8615
Operational Amplifier
information and/or support, visit
2-Channel, 12-Bit ADC with I2C-Compatible
Interface in 10-Lead MSOP

Universal LVDT Signal Conditioning Circuit

EVALUATION AND DESIGN SUPPORT This circuit uses the AD698 LVDT signal conditioner that contains
Circuit Evaluation Boards a sine wave oscillator and a power amplifier to generate the
CN-0301 Circuit Evaluation Board (EVAL-CN0301-SDPZ) excitation signals that drive the primary side of the LVDT. The
System Demonstration Platform (EVAL-SDP-CB1Z) AD698 also converts the secondary output into a dc voltage. The
Design and Integration Files AD8615 rail-to-rail amplifier buffers the output of the AD698 and
Schematics, Layout Files, Bill of Materials drives a low power 12-bit successive approximation analog-to-
digital converter (ADC). The system has a dynamic range of 82 dB
CIRCUIT FUNCTION AND BENEFITS and a system bandwidth of 250 Hz, making it ideal for precision
The circuit shown in Figure 1 is a complete adjustment-free linear industrial position and gauging applications.
variable differential transformer (LVDT) signal conditioning The signal conditioning circuitry of the system consumes only
circuit. This circuit can accurately measure linear displacement 15 mA of current from the ±15 V supply and 3 mA from the +5 V
(position). supply.
The LVDT is a highly reliable sensor because the magnetic core This circuit note discusses basic LVDT theory of operation and the
can move without friction and does not touch the inside of the design steps used to optimize the circuit shown in Figure 1 for a
tube. Therefore, LVDTs are suitable for flight control feedback chosen bandwidth, including noise analysis and component
systems, position feedback in servomechanisms, automated selection considerations.
measurement in machine tools, and many other industrial and
scientific electromechanical applications where long term reliability
is important.

0.01µF 2.7nF

E-100 –15V

Figure 1. Universal LVDT Signal Conditioning Circuit (Simplified Schematic: All Connections and Decoupling Not Shown)

Rev. A
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be required to add phase lead or lag to the A Channel to and because they operate without any built-in electronic circuitry. (B Channel). The output of the divider is a duty cycle.CN-0301 Circuit Note CIRCUIT DESCRIPTION The block diagram of the AD698 is depicted Figure 2. Figure 2. the AD698 converts the raw LVDT CHANNEL DUTY secondary output to a scaled dc signal. AD698 Block Diagram and a fixed input reference (primary or sum of secondaries or fixed input). the E-100 Economy Series LVDT sensor from BFILT1 BFILT2 +VS Measurement Specialties™. The output transfer function is thus: A V OUT = I REF × ×R2 B where IREF = 500 μA. A common problem with earlier solutions was Once both channels are demodulated and filtered a division that any drift in the amplitude of the drive oscillator corresponded circuit. B. Rev. the duty cycle will be equal to 100%. –ACOMP COMP The AD698 contains a low distortion sine wave oscillator to drive +ACOMP OFF2 OFF1 the LVDT primary. and the A reliability under severe environments are a required. The B channel monitors the drive excitation to the An LVDT is an absolute displacement transducer that converts LVDT. a phase compensation network may Instead. C2 For this circuit. In addition. The frequency of the sine wave is determined –AIN IREF 500µA V ±1 by a single capacitor and can range from 20 Hz to 20 kHz with V/I LPF +AIN amplitudes from 2 V rms to 24 V rms. Inc. V/I ±1 OUT C4 +BIN LPF It converts the transducer mechanical position of LVDTs to a FILTER FB VOUT unipolar dc voltage with a high degree of accuracy and COMP repeatability.) The duty cycle drives a circuit that modulates and it implements a different circuit transfer function and does not filters a reference current proportional to the duty cycle. The Theory of Operation inputs consist of two independent synchronous demodulation channels. Channel A is identical (or zero) into a proportional electrical signal containing phase except that the comparator’s pins are externally available. For this reason. military and aerospace applications. implemented with a duty cycle multiplier. is used to directly to a gain error in the output. CHANNEL –BIN R2 The AD698 is a complete. This (This signal can be used as is if a pulse width modulated output device differs from the AD598 LVDT signal conditioner in that is required. The require the sum of the LVDT secondaries (A + B) to be constant output amplifier scales the 500µA reference current converting with stroke length. to a voltage. it relies on electromagnetic coupling. such channel voltage is large enough to trigger the demodulator. DEMODULATOR AD698 The LVDT secondary output consists of two sine waves that drive 11607-002 AFILT1 AFILT2 –VS the AD698 directly. input excitation in order to cancel out any drift effects. The AD698 eliminates calculate the ratio A/B. All circuit functions are included on the chip. these errors by calculating the ratio of the LVDT output to its When A/B is equal to 1. The AD698 decodes LVDTs by synchronously C3 demodulating the amplitude modulated input (secondaries). The the A channel may reach 0 V output at the LVDT null. Since (for direction) and amplitude information (for distance). was used with the AD698. With a linearity of ±0. DUTY CYCLE With the addition of a few external passives components to DIVIDER A B A A/B = 1 = 100% set frequency and gain. A | Page 2 of 7 .5% of full range. the E Series is suitable for most B C5 applications with moderate operation temperature environments. The full wave rectified output is filtered by C2 before a linear displacement or position from a mechanical reference being sent to the computational circuit. the A LVDT operation does not require electrical contact between the channel demodulator is usually triggered by the primary voltage moving part (probe or core rod assembly) and the transformer. For LVDTs are widely used in applications where long life and high half-bridge circuits the phase shift in noncritical. LVDT signal conditioning subsystem. A. compensate for the LVDT primary to secondary phase shift.

has 12-bit resolution and a sampling rate of 188 kSPS per channel any single noise source that is at least three-to-four times larger when used with a 3.7 Bits The AD8615 is an ideal amplifier to buffer and drive the input = 13.4 mV = 12. and output voltage noise of the AD8615) are significantly smaller in comparison. however. Rev. When selecting capacitor values to set the bandwidth of the system. and its ability to swing rail-to-rail at both the input The total output dynamic range of the system can be calculated and output.6 Bits due to the extremely low input bias current of the AD8615 (1 pA) Noise-free code resolution can be obtained by subtracting which allows the use of larger resistors. Choosing smaller capacitors give higher RIPPLE (mV rms) system bandwidth but increase the amount of output voltage ripple. now be calculated by dividing the full-scale output by the total • It filters the output voltage ripple. In the case of the LVDT signal conditioning circuit. than any of the others dominates.39 µF capacitor value and with a 10 nF shunt capacitor across the found in the AD698 data sheet was followed to set the excitation feedback resistor shown in Figure 3. adds thermal noise. C4. 100 a trade-off is involved. C3.7 bits from the effective resolution. The ripple can be reduced by increasing the shunt capacitance 10 across the feedback resistor used to set the output voltage level.01 0. Noise-Free Code Resolution = Effective Resolution − 2. resolution needed to convert the signal must be determined.4 mV rms with a The design procedure for the dual supply operation (±15 V) 0.4 mV) = 82 dB As in most noise analyses. CSHUNT = 1nF AD698.5 kHz. Dynamic Range = 20 log(5 V/0. schematic in Figure 1. The other sources of noise (resistor noise. however. This is important because the output voltage of the AD698 can swing ±11 V with The effective resolution is found by taking the base 2 logarithm ±15 V supplies. The AD8615 operational amplifier buffers the output of the 1 10kHz. this also increases phase lag. system rms noise. by dividing the full-scale output signal (5 V) by the total output Noise Analysis rms noise (0.001 0.4 MHz serial clock. system bandwidth to 250 Hz.9 Bits protection. details can be found in the AD698 data sheet. It is normal for the AD698 internal oscillator to produce a small 1000 amount of ripple that feeds through to the output. the amount of approximately 82 dB. higher voltages can be applied to the input. This is primarily Effective Resolution = log2(12. The use of these resistors 2. yielding With all signal condition components selected. C2 = C3 = C4 (µF) The low-pass filter between the output of the AD698 and the Figure 3. Note that these components frequency to 2. Output Voltage Ripple vs.1 0. 0. the dominant source of the output noise is the output ripple of the AD698.6 Bits − 2.7 Bits of the AD7992 12-bit SAR ADC because of its input overvoltage = 10. A | Page 3 of 7 . which ensures that the AD7992 ADC is driven by a low 11607-003 impedance source (high source impedances significantly affect 10kHz. input voltage noise. which contributes to the overall output voltage noise of the amplifier. therefore. CSHUNT = 10nF the ac performance of the ADC). As long as the input current is limited to less than of the total rms counts. and an and related pin connections are not shown in the simplified output voltage from 0 V to 5 V.4 mV rms) and converting it to decibels. 5 mA. Filter Capacitance input of the AD8615 serves two purposes: The maximum number of rms counts that can be resolved can • It limits the input current to the AD8615. only the key contributors need to be The AD7992 is a good candidate for this application because it identified. 500 exceeding the supply to be applied at the input.Circuit Note CN-0301 Component Selection The output voltage ripple of the AD698 is 0.1 1 10 C2. Noise sources combine in an rss manner. The AD8615 has internal protective circuitry that allows voltages Total RMS Counts = 5 V/0.500) = 13. A passive low-pass filter is used to reduce this ripple to the required level.

They include roles such as aerial reconnaissance.01 µF) between the AD698 output When choosing component values for the appropriate network. or drones. Screenshot of the CN-0301 Evaluation Software Using a Measurement Specialties. Small amounts of phase shift can produce significant linearity error which is seen as undershoot in the output.CN-0301 Circuit Note Compensating for Phase Lag/Lead The AD698 uses demodulation to generate an output signal by multiplying the return signal with the reference oscillator fed to the primary. Applications in Flight Control Surface Position Feedback Unmanned autonomous vehicles (UAVs).000µs 11607-004 C D C D Figure 5. The end goal is to achieve the desired phase lag/lead on the ACOMP inputs of the AD698 with a small amplitude drop. The lag/lead circuitry also adds load collected from the EVAL-CN0301-SDPZ evaluation board. 1 The phase lead network compensates for the −3° of primary to secondary phase shift of the E-100 series LVDT. or unmanned in-flight refueling station. These high technology. E-100 Economy Series The ripple from the AD698 was attenuated to 2 mV p-p. the output of the AD698 found on J6 on the EVAL-CN0301- SDPZ evaluation board. complex aerial platforms are controlled by a crew miles away and are multimission capable. The amount of phase lag/lead can be calculated by using the following formulas: Phase Lag = tan −1 ( Hz × R × C )  1  Phase Lead = tan −1     Hz × R × C  where 1 1 R= + RS R S + RT 11607-006 Hz = Excitation Frequency Test Results Figure 6. as shown in Figure 6. data was needs to be much larger than RS. Output Voltage Ripple Before Low-Pass Filter Figure 4. A | Page 4 of 7 . found at http://www. mended. battlefield theater command and control oversight. PHASE LAG PHASE LEAD A B A B 11607-005 C RT RS RS RT RS C C CH1 2. Phase Lag/Lead Network The low-pass filter (3 kΩ. the actual output ripple found was A complete design support package for this circuit note can be 6. Inc. as is shown in Figure 5. divider that reduces the amplitude of the excitation signals before it With the low-pass filter installed between the output stage reaches the ±ACOMP inputs of the AD698. combat weapons platforms.6 mV and the AD8615 input has a −3 dB bandwidth of 5. Figure 4 shows two different phase compensation networks.analog.0mV M2. larger resistive values are recom. are playing an ever-increasing part in the national security of the United States. This suggests that RT of the AD698 and the input stage of the AD8615. to the excitation output therefore. and the LVDT connected to J3 and using a digital oscilloscope to monitor system was able to achieve 11 bits of noise-free code resolution.3 kHz and it is important to note that RS and RT effectively constitute a resistor reduces the ripple to 2 mV p-p. 0. Rev.

Use supply operation is required. The two boards have 120-pin mating connectors. and the EVAL-SDP-CB1Z (SDP-B) is used with the connect the USB cable from the PC to the Mini-USB connector on CN-0301 Evaluation Software to capture the data from the the EVAL-SDP-CB1Z. (EVAL-CFTL-LVDT) The sensors used to measure actuator position need to meet Getting Started three essential criteria: high accuracy. bipolar input. a large number of LVDTs are used in close proximity. The resulting beat notes may The PDF file can be found in the CN-0301 Design Support interfere with the accuracy of measurements made under these Package. controller board. the AD7321 is pins on the board. Inc. such as multiple gaging measurement. The AD7321 is a 2-channel. provided at the ends of the 120-pin connectors. locate the drive that contains the evaluation software. With power to the supply off. all LVDTs operate synchronously. When USB communications are established. other combinations BOARD SDP-B BOARD can be substituted. If dual. the EVAL-SDP- Equipment Needed CB1Z can send. All three of these attributes are found in the LVDTs Load the evaluation software by placing the CN-0301 Evaluation designed by Measurement Specialties. stray magnetic coupling can SDPZ-PADSSchematic. Inc. The precise measurement equivalent 6 V/1 A bench supply of the position of these actuators is crucial in maintaining the • Measurement Specialties. conditions. Each LVDT primary is driven from its own E-100 ECONOMY SERIES LVDT EVAL-CFTL-LVDT power amplifier. Figure 7. • A PC with a USB port and Windows® XP (32 bit). the ADA4638-1 or ADA4627-1 is nylon hardware to firmly secure the two boards. If these LVDTs See Figure 1 for the circuit block diagram and the EVAL-CN0301- operate at similar carrier frequencies. To avoid this situation. Test Setup Block Diagram Other suitable single-supply amplifiers are the AD8565 and Setup AD8601. connect a 6 V power supply to the +6 V and GND If the AD698 outputs ±10 V bipolar signals. If available. receive. Synchronous Operation of Multiple LVDTs Functional Block Diagram In many applications.pdf file for the complete circuit schematic. however. using the holes suggested. power supply. To control • The CN-0301 Evaluation Software the altitude (pitch. INC. Rev. a 6 V wall wart can be connected to suggested. Information regarding the EVAL- • The EVAL-CN0301-SDPZ circuit board SDP-CB1Z can be found in the UG-277 User Guide. actuators are used to • The EVAL-CFTL-6V-PWRZ dc power supply or exert forces on the flight control surfaces.Circuit Note CN-0301 The complex systems employed on UAVs use a myriad of • The EVAL-SDP-CB1Z SDP-B controller board electronic sensors for precise control and feedback. thus. high reliability. Launch the evaluation software and evaluated. Do not connect the USB This circuit uses the EVAL-CN0301-SDPZ circuit board and cable to the Mini-USB connector on the EVAL-SDP-CB1Z at the EVAL-SDP-CB1Z SDP-B system demonstration platform this time. Connect the USB cable supplied with the EVAL- CIRCUIT EVALUATION AND TEST SDP-CB1Z to the USB port on the PC. JP3 unpopulated. The EVAL-CN0301-SDPZ evaluation board can be configured EVAL-CFTL-6V-PWRZ PC 6V WALL WART to have one master oscillator between two LVDTs by populating MEASUREMENT Jumper JP1. and capture parallel data from the The following equipment is needed: EVAL-CN0301-SDPZ. 120 PINS COMMON VARIATIONS J1 J8 CON A The components selected were optimized for a maximum 5 V 11607-007 EVAL-CN0301-SDPZ EVAL-SDP-CB1Z unipolar output from the AD698. the CON A connector on the EVAL-SDP-CB1Z (SDP-B). 12-bit ADC the barrel connector on the board and used in place of the 6 V that can accept true bipolar analog input signals as large as ±10 V. cause beat notes to be generated. Figure 8 shows a photo of the EVAL-CN0301-SDPZ connected Windows Vista®. and JP4 with a shorting jumper and leaving SPECIALTIES. Software into the CD drive of the PC. the thermal load is shared between J4 USB the AD698 devices.. EVAL-CN0301-SDPZ. and yaw) of the UAV. These amplifiers are suitable replacements for the AD8615 because they have input overvoltage protection and the Connect the 120-pin connector on the EVAL-CN0301-SDPZ to ability to swing rail-to-rail at both the input and output. A | Page 5 of 7 . and. Using My Computer. Test allowing for the quick setup and evaluation of the performance Apply power to the 6 V supply (or wall wart) connected to the of the circuit. roll. JP2. The EVAL-CN0301-SDPZ contains the circuit to be EVAL-CN0301-SDPZ. or Windows 7 to the EVAL-SDP-CB1Z. E-100 Economy Series LVDT proper flight of path. and light weight.

The BeMicro SDK board from Altera can be used with the Connectivity for Prototype Development BeMicro SDK/SDP interposer using nios drivers. The EVAL-CN0301-SDPZ Board Connected to EVAL-SDP-CB1Z (SDP-B) Board and Measurement Specialties.CN-0301 Circuit Note Information and details regarding test setup and calibration. Imod interface specification. software must be developed by a third party. A | Page 6 of 7 . however. MEASUREMENT SPECIALTIES. E-100 Economy Series LVDT Rev. INC. found in the CN-0301 Software User Guide. another controller to be used with the EVAL-CN0301-SDPZ. any microprocessor can be used to interface to the I2C 2-wire serial interface of the AD7992. CB1Z. A photo of the system is shown in Figure 8. Any Xilinx evaluation board that features the FMC connector can be used The EVAL-CN0301-SDPZ is designed to use the EVAL-SDP- with the FMC-SDP interposer board. There are existing interposer boards that can be used to interface to and how to use the evaluation software for data capture can be the Altera and Xilinx field programmable gate arrays (FPGAs). In order for The EVAL-CN0301-SDPZ is also compatible with the Digilent. Inc. E-100 ECONOMY SERIES LVDT EVAL-CFTL-LVDT USB EVAL-CN0301-SDPZ EVAL-SDP-CB1Z EVAL-CFTL-6V-PWRZ 11607-008 Figure 8..

A | Page 7 of 7 . Analog Dialogue 39-09. implied. 1000 Lucas Way. A Practical Guide to High-Speed Printed-Circuit. Analog Devices. Measurement Specialties. 5 MT-036 Tutorial. Subminiature LVDTs Provide Accurate Flight Control Surface Position Feedback on UAVs. Measurement Specialties. Changes to Synchronous Operation of Multiple LVDTs Section . Analog Devices. Analog Devices.. express. Inc. Inc. Decoupling Techniques. However.. VA 23666. AD8615 Data Sheet MT-004 Tutorial. noninfringement or fitness for a particular purpose and no responsibility is assumed by Analog Devices for their use. REVISION HISTORY MT-035. 3/14—Rev.Circuit Note CN-0301 LEARN MORE Data Sheets and Evaluation Boards CN-0301 Design Support Package: CN-0301 Circuit Evaluation Board (EVAL-CN0301-SDPZ) http://www. Technical Paper. Inc. Measurement Specialties. (Continued from first page) Circuits from the Lab reference designs are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors. Hampton. Single-Supply. Analog Devices reserves the right to change any Circuits from the Lab reference designs at any time without notice but is under no obligation to do so. AD7992 Data Sheet Board Layout. Application Note. 1000 Lucas Way. and the Ugly Aspects of ADP1613 Data Sheet ADC Input Noise—Is No Noise Good Noise?. ADP7104 Data Sheet MT-031 Tutorial. Analog Devices. ©2013–2014 Analog Devices. All rights System Demonstration Platform (EVAL-SDP-CB1Z) SDP-B User Guide AD698 Data Sheet Ardizzoni. Analog Devices. and Rail-to. 0 to Rev. no other license is granted by implication or otherwise under any patents or other intellectual property by application or use of the Circuits from the Lab reference designs. Grounding Data Converters and Solving the Mystery of “AGND” and “DGND”. John. The LVDT: construction and principle of operation. Op Amp Inputs. but not limited to. September 2005.. or statutory including. Outputs. MT-068 Tutorial. Information furnished by Analog Devices is believed to be accurate and reliable. Analog Devices. Difference and Current Sense Amplifiers. VA 23666. While you may use the Circuits from the Lab reference designs in the design of your product. the Bad. A Rail Issues. Circuits from the Lab reference designs are supplied "as is" and without warranties of any kind. The Good. CN11607-0-3/14(A) Rev..analog. Inc. MT-101 Tutorial. Trademarks and registered trademarks are the property of their respective owners.. any implied warranty of merchantability.. An Improved Topology for Creating Split Rails from a Single Input Voltage. Op Amp Output Phase-Reversal and Input 5/13—Revision 0: Initial Version Over-Voltage Protection. Hampton. AN-1106 Application Note. E-100 Economy Series LVDT. Analog Devices. nor for any infringements of patents or other rights of third parties that may result from their use.