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November 2012

premier issue: high-speed design

Featured Content
THE NEED FOR SPEED Theres no escaping the challenges of high-speed design. After all, no design ex-
ists in a vacuum. No matter what type of board youre designing, whether its a single-sided commercial
board or a 24-layer backplane, high-speed design issues are likely to wreak havoc. But we have the cure
for your high-speed blues, right here in the inaugural issue of The PCB Design Magazine!

12 Designing a PCB Stackup, 26 Partner Early for HDI

Part 1 Board Design
by Lee W. Ritchey by John Levreault

38 A Chronicle of Speed and

Density: The TLA Design
Winners Through the Years
By Happy Holden

4 PCB Design Magazine November 2012

november 2012 The optimum

volume 1 TM magazine

number 1 dedicated to pcb design


Article Columns
50 Leveraging 8 Welcome to The PCB
the Cloud for Design Magazine
Automated by Andy Shaughnessy
by Iain Wilson 22 So You Want to be a Designer?
by Jack Olson

32 The Plain Truth About Plane Jumpers

by Barry Olney
36 SiSoft Releases Channel Designer
Kits for Intel 89xx Series 56 Trace Currents and Temperature,
Part 1: The Basic Model
49 Mentor Graphics Expands by Douglas Brooks, Ph.D.
HyperLynx Suite
64 The Elements of PCB Library
62 IPC APEX EXPO 2013 to Hold Construction
Design-Focused Activities by Tom Hausherr

96 Sunstone Highlights Expansion 74 How to Read the ESR Curve

with Open House by Istvan Novak

78 The Wrap Crack

by Paul Reid

84 Increasing Efficiency with PCB

by John Isaac

90 Non-Contact Interconnect:
When Crosstalk is Your Friend
top ten most-read News by Bert Simonovich
37 Design
Video Interviews
73 Mil/Aero007 24 Bruce Archambeault:
EMC Issues A Fact of Life
82 PCB007
31 MIA: The Next Generation of Designers?
Extras 49 Hartley: Design Education is
98 Events Calendar Your Responsibility

99 Advertiser Index & Masthead 62 HyperLynx: Not Just an SI Tool Anymore

6 PCB Design Magazine November 2012


the shaughnessy report

Welcome to The PCB Design Magazine

by Andy Shaughnessy

Summary: If youre reading this, youve made Design Magazine will take full advantage of our
it to the introductory issue of The PCB Design video and audio technology. Well be bringing
Magazine, the only magazine of its kind devoted you complete video coverage of DesignCon, as
entirely to PCB design. So, PCB designers and de- well as the Designers Forum at IPC APEX EXPO,
sign engineers, this is your magazine. Welcome with guest editors youve come to know and
home! trust like Mark Thompson and Kelly Dack, and
more. PCB designers are anything but boring,
Welcome to the first issue of The PCB Design and its my job to make every issue more excit-
Magazine the only magazine dedicated solely ing than the last. Each issue will be packed with
to PCB design. If youre a PCB designer or de- the news and technological information you
sign engineer, this need, and, almost as
is your magazine. importantly, each is-
Some of you are sue will be fun.
no doubt think- The response
ing, Its about from the design
time we had our community has
own publication! been overwhelming.
Through the Since we broke the
years, Ive asked news, designers and
myself why there engineers have been
are no magazines sending me articles
focused specifical- and columns from
ly on PCB design around the world. I
and design issues. field calls almost ev-
Why indeed? ery day from design-
So, we at I- ers who are interest-
Connect007 saw ed in writing for the
a need for a new magazine. I havent
PCB design publi- had to resort to the
cation, and decid- usual arm-twisting
ed to take action. to get good con-
The result is The tent. I cant think
PCB Design Maga- of a better way to
zine, a monthly, launch a PCB design
subscription-based magazine in the style of our magazine than with feature articles by long-
sister publications, SMT Magazine and The PCB time industry gurus like Lee Ritchey and Happy
Magazine. Readers can expect exhaustive cover- Holden. The PCB Design Magazine definitely has
age of the issues that are important to the PCB quite a buzz going now.
design community, in a digital format that al- I think were on the right track. Im fortu-
lows live-action animation, like the super cool nate to have quite a stable of fantastic colum-
cover of this issue. And because were a green nists and contributors, and together were go-
publication, were not killing any trees. ing to make this magazine the go-to place for
As an I-Connect007 publication, The PCB PCB designers. We do what we can to support

8 PCB Design Magazine November 2012

the shaughnessy report

welcome to the pcb design magazine continues

the industry, and I appreciate all of your sup- a single-sided commercial board fabricated in
port in return. You can be sure that we wont Asia, you can locate the right fabricator on The
take this responsibility lightly. PCB List.
The PCB List is just one more service that
One More Thing we provide to help make designers jobs a lit-
If you buy fabricated boards and you tle easier. Isnt it time someone made your job
havent already checked out The PCB List, now easier?
is the time. The PCB List is the single biggest Thanks for reading our first issue of The PCB
database of fabricators anywhere, and there are Design Magazine. If you havent subscribed yet,
enough search options that buyers can find ex- you can do so by clicking here.
actly what they need, from the part of the world Welcome home. PCBDESIGN
where they want to do business.
Set up an account its free for buyers and
start searching for the board types you need. Andy Shaughnessy is managing
You can restrict your search with dozens of cri- editor of The PCB Design Maga-
teria, such as country of manufacture, technol- zine. He has been covering PCB
ogy level, market segment served, volume level, design for 13 years. He can be
materials, average layer count, and much more. reached by clicking here.
Whether you need a mil/aero board built by an
ITAR-certified fabricator in North America or

10 PCB Design Magazine November 2012

Feature Article

Designing a PCB
Stackup, Part 1
more discipline in the choice of materials and
arrangement of the layers in the stackup both
of which are outside the skill set of virtually all
PCB fabricators. A common part of the vendor
selection process has been to submit each de-
sign for a quote to several fabricators and make
the choice based on price only. This is very of-
ten a fatal method of vendor selection because
the lowest bidder often takes shortcuts in order
to achieve the lowest price and/or may not pos-
sess the skills necessary to manufacture quality
PCBs of the given complexity.
Among the demands placed on stackup de-
sign are:

Providing enough signal layers to allow

successful routing of all signals to signal
integrity rules.
Creating copper thickness in planes and
signal layers that meets the conductivity
demands of signals and power and, at the
same time, be reasonable to manufacture.
Providing enough power and ground
layers to meet the needs of the power
delivery system.
by Lee W. Ritchey Specifying dimension trace widths and
Speeding Edge dielectric thicknesses that allow
impedance targets to be met.
Summary: The challenge in designing a PCB Ensuring that the spacing between signal
stackup is to satisfy its many demands. Informa- layers and their adjacent planes is thin
tion in this document is drawn from experience enough to satisfy crosstalk needs.
gained designing more than 2,000 PCB stackups Specifying dielectric materials that are
for products as simple as video games and as com- economical to manufacture and readily
plex as the highest-performance backplanes used available.
in supercomputers and routers. Avoiding the use of expensive techniques
such as blind and buried vias and build up
The practice that has worked in the past of processing if possible.
allowing the fabricator to design a PCB stackup Providing for prototype manufacture in
no longer works. Speeds have increased to the one factory or country and production
point where signal integrity and power delivery manufacture in another factory or
considerations make it necessary to employ far country.

12 PCB Design Magazine November 2012

Feature Article

designing a pcb stackup, part 1 continues

Information needed to design a successful number of layers. As a result, when additional

PCB stackup is scattered among many docu- layers are needed they will be added one pair at
ments and specifications, many of which are a time along with an additional pre-preg layer.
not in the public domain. This document is Designing a stackup with an odd number of
intended to bring all of the necessary informa- layers when only one additional layer is needed
tion into one document to improve the design does not result in a PCB that is cheaper than if
process. a pair of layers had been added. The reason for
this is that the fabricator will need to purchase
How a Typical Multilayer PCB is Built a piece of laminate for the added layer that has
In order to understand the choices that copper foil on both sides. The copper foil that is
must be made when designing a PCB stackup, not needed will be etched away when the nec-
it is useful to review how a typical multilayer essary foil side is etched.
PCB is fabricated. Figure 1 is a diagram showing As can be seen from Figure 1, three main com-
the components that make up a six-layer PCB. ponents make up a multilayer PCB. These are:
The manufacturing method shown in the fig-
ure is referred to as foil lamination. This refers Sheets of laminate that have a sheet of
to the fact that the two outer layers begin as copper foil bonded to each side which have the
sheets of foil copper with no images etched into patterns for either signal layers or plane layers
them. This is the most cost-effective way there etched into the copper foils. These are often re-
is to manufacture a multilayer PCB and should ferred to as details. (Laminate is a combination
be the objective of the stackup design process. of woven glass cloth and a resin system such as
There are other methods available, such as cap epoxy or polyimide.) The thickness of the cop-
lamination, that forms the outer layers as part per on each side of this laminate can vary from
of a two-sided piece of laminate and build up ounce to 2 ounces. (Copper foil thickness is
processing that involves blind and buried vias. specified in ounces per square foot of surface
These choices always result in more expensive area. 1 ounce is approximately 1.4 mil or 36 mi-
PCBs and should be considered only as a last crons thick.)
It should be noted that PCB layers are built Sheets of uncured laminate called pre-preg
in pairs. Therefore, PCBs normally have an even placed between the details and between details
and the outer foil sheets. This pre-preg is a wo-
ven glass material coated with the same resin
system that is used in the laminates. Unlike the
laminates, the resin is only partially cured. Dur-
ing lamination heat will cause this resin to melt
and flow into the voids in the adjacent copper
layers, serving as the glue to bond the layers to-
gether and then cure it to the same rigid state as
the resin in the laminate. After lamination pre-
preg is indistinguishable from laminate.

Sheets of copper foil to form the outer lay-

ers. The reason the two outer layers are solid
copper at this stage instead of etched with the
outer layer patterns is to provide a path for the
current required to plate copper into the holes
drilled through the PCB for vias and compo-
nent leads. The task of the stackup designer is to
Figure 1: A typical six-layer PCB stackup using select combinations of pre-preg, laminate and
foil lamination. foils that provide the desired electrical charac-

14 PCB Design Magazine November 2012

Feature Article

designing a pcb stackup, part 1 continues

teristics while satisfying cost and manufactur- a significantly more expensive PCB that takes
ability goals. longer to manufacture than either of the above
choices. (In some cases PCBs designed to use
Alternative PCB Fabrication Methods buried vias can cost as much as twice what the
Figure 2 is an illustration of the cap lami- same number of layers would cost using only
nation method of manufacturing a multilayer through-hole vias.)
PCB. As can be seen, there are three pieces of
laminate each with two conductor layers in Choosing a Fabricator as a Design Partner
this version of a six-layer PCB. The most obvi- One of the secrets to creating PCB stackups
ous difference between this and foil lamination that are right the first time is to select a PCB fab-
for this six-layer PCB is that only two pieces of ricator to work with while trading off manufac-
laminate or details must be processed using foil turability of the final PCB stackup against signal
lamination while three are required with cap integrity and cost goals. The right fabrication
lamination. This represents a cost increase over engineer can provide valuable insight into the
foil lamination. This was the method used to manufacturability of proposed stackups as well
fabricate PCBs in the early days of multilayer as advice on how to improve a stackup. Clearly,
fabrication. for this to work, the fabricator must have ex-
A third method for creating a multilayer PCB perience manufacturing PCBs of the complexity
is by the use of buried and blind vias. In one being designed. The design engineering depart-
version of this method, the internal n-2 layers ment must have a clear, direct path to the engi-
are fabricated using either of the two methods neering department of the fabricator. The classic
shown above, resulting in a complete sub-PCB method of allowing the purchasing or materials
with plated through holes running from layer department to select fabricators based on cost
2 to layer n-1. Then, a piece of pre-preg and a does not work well with modern designs.
piece of foil are added to each side and the com- My first criterion in choosing fabricators is
bination is laminated into a final PCB of n lay- Are they building PCBs like mine every day or
ers. After this second lamination step, holes are will my design represent a stretch for them? As
drilled through the entire stackup and plated. always, selecting fabricators that demonstrate
It is also common to drill blind vias from recent capability with the class of PCB being de-
layer 1 to layer 2 and layer n to layer n-1 as well. signed goes a long way toward ensuring success
It is easy to see that this method will result in on the first try. The best way to determine that
there is a match is to conduct a vendor survey
by visiting the factory and viewing the produc-
tion line itself. Look for PCBs of your complex-
ity being manufactured in real time. (It is com-
mon for fabricators to display complex PCBs
in conference rooms that do not represent the
actual capability of the fabrication process as a
way to impress customers.)
This is the standard method used by com-
panies such as Cisco to ensure suppliers are
matched to the need. These visits are conducted
by a team of people who represent manufactur-
ing, engineering and purchasing, to make sure
all areas are covered. Failing that, the next best
way is by checking references to see how sat-
isfied current customers are; ask for references
who are willing to discuss their experiences
Figure 2: Typical six-layer PCB using cap with the supplier. If no references are forthcom-
lamination. ing, it is well to beware.

November 2012 PCB Design Magazine 15

Feature Article

designing a pcb stackup, part 1 continues

Alternate Ways to
Stack Layers
Figure 4 shows two differ-
ent ways to arrange the layers
in a ten-layer PCB. The short
bars represent signal layers
and the long bars represent
planes. The stacking on the
left appears to have two more
signal layers than the one on
the right due to the fact that
the top and bottom layers on
the right are not available for
signals and this is true. The
disadvantages of the stackup
on the left are power deliv-
ery related. Most high-speed
designs require plane capaci-
tance to support fast switch-
ing edges. In order to create
plane capacitance, pairs of
Figure 3: A typical 10-layer PCB stackup.
planes must be close to each
other (less than 4 mils, 100
microns). The stackup shown in Figure 4 has
Types of Signal Layers only one plane pair close together while the
Figure 3 is a typical 10-layer PCB stackup. stackup on the right has two plane pairs.
This example has three types of signal layers: A second benefit of the stackup on the right
surface microstrip (L1 & L10), buried microstrip in Figure 4 is that the plane pairs are separated
(L2 and L9) and off-center or dual stripline (L5 by pre-preg which can be made very thin, less
& L6). than 3 mils, as shown in Figure 3. This is of sig-
There is a fourth type of signal layer-cen- nificant value when designing a power delivery
tered or symmetrical stripline: a single stripline system.
layer centered between two planes. The reason A third benefit of the stackup on the right
that dual stripline is used more often than sin- is that each signal layer is paired with a power
gle stripline is that each time a single stripline plane across a piece of laminate. The benefit
layer is added to a stackup, a plane must also here is that during lamination, the thickness of
be added to isolate signal layers from each oth- the laminate does not change and this makes
er, resulting in higher layer counts for a given it possible to achieve tightly controlled imped-
number of signal layers. The method used to ances on the transmission lines. When a signal
keep the two signal layers in the dual stripline layer is mated with a plane across a piece of pre-
configuration from interfering with each other preg, impedance control is more difficult as the
(crosstalk) is to route signals on one layer hori- pre-preg thickness can change significantly dur-
zontal and on the other vertical. ing the press cycle.
In this example, the two outer layers are For all the reasons given above, the layer
not used for signals. The reason is impedance stacking on the right in Figure 4 represents the
uniformity on these layers is difficult to control best compromise between power delivery and
accurately due to the uneven plating of copper impedance accuracy. If two more signal layers
that often results when plating is done to plate are needed, they would be added along with
copper in the holes that conduct current such two more planes resulting in a 14-layer PCB.
as vias and power leads. If four more signal layers are needed then four

16 PCB Design Magazine November 2012

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Feature Article

designing a pcb stackup, part 1 continues

Figure 4: Two ways to arrange plane and signal layers in a 10-layer PCB.

more signal and four more plane layers would Reference 1 explains how this impedance came
be added, resulting in an 18-layer PCB and so into existence and demonstrates that the PCI
on for 22 and 26 layers. bus works properly with 50-ohm transmission
lines. A similar analysis will show that the Ram-
Selecting an Impedance bus protocol also works properly with 50-ohm
The starting point for most PCB stackup de- transmission lines. (To make a 28-ohm line, the
sign is determining what impedance or imped- trace width must be so wide that it will not fit
ances to use in each signal layer. A number of between pins on a BGA.)
impedances have been used for controlled im- This leaves 72-ohm video and the various
pedance PCBs. Among these are 62 or 65 ohms differential protocols. In almost all cases, the
for PCI buses, 72 or 75 ohms for video signals, 72-ohm video requirement is to match 72-ohm
50 ohms for ECL and high-speed CMOS, 28 coaxial cable bringing a signal onto a PCB or
ohms for Rambus and an assortment of differ- taking it off the PCB. Building a stackup that
ential impedances for various differential sig- allows both 50 ohms and 72 ohms in the same
naling protocols. signal layer is very difficult, if not impossible.
Attempting to design stackups that accom- Is that really necessary? I have found that if the
modate more than one impedance value has IC using the video signal is located close to the
proven to be difficult. A reasonable question to edge of the PCB, as most are, a very short trace
ask is whether or not multiple impedances are of 50 ohms is not going to significantly degrade
really necessary. The most common impedance the video signal. This can be easily validated us-
found in multilayer PCBs is 50 ohms. It turns ing any good SI simulator.
out that this impedance represents a happy The 100-ohm differential impedance re-
medium between impedance value and ease of quirement is an artifact of the need to provide
manufacture when more than two controlled two 50-ohm lines each parallel terminated in 50
impedance signal layers are needed. Therefore, ohms[2]. It can be seen that the optimum way to
it is worth examining the protocols that specify route differential signals in a PCB is so that nei-
other impedance values to see if they will op- ther member of a pair interacts with the other.
erate successfully with a 50-ohm transmission This is achieved by separating them from each
line. other far enough so that one does not drive
The most common PCB impedance is 50 down the impedance of the other. When this is
ohms. This impedance is achieved on stripline done, it is no longer necessary to specify differ-
layers with a trace width that is about the same ential impedance. As a result, all of the signals
as the dielectric thickness. In order to make a that need controlled impedance can be routed
62-ohm line for the PCI bus, the trace width with the same impedance. The question is, what
has to be made very narrow in stripline layers. impedance?

18 PCB Design Magazine November 2012

Feature Article

designing a pcb stackup, part 1 continues

From all of this, it can be seen that 50 ohms For a detailed discussion of the merits and
is a very good compromise impedance. It also drawbacks of each of these resin systems, see
happens to be in the sweet spot of the PCB fab- Chapter 5[2].
rication process as well as of all the tools used to In the early years of PCB manufacture the
measure impedance and other characteristics of resin system choices were epoxy and polyimide.
transmission lines. Therefore, it is wise to con- Polyimide has very good high temperature
struct stackups that have a nominal impedance characteristics, but is very difficult to process
of 50 ohms. and absorbs moisture to a level that causes it to
In spite of what might be called out in some fail leakage tests unless it is baked dry and then
applications notes, every modern logic family waterproofed. Epoxy-based systems are very
fast enough to require controlled impedance easy to process and do not fail leakage tests,
and terminations is capable of driving a 50-ohm but dont tolerate the temperatures required to
transmission line so there is no need to design solder well. All of the other resin systems on
complex stackups that require complex routing the above list were developed in the hopes of
rules in order to make all of the nets fit into the achieving the ease of processing of epoxy and
space available in the signal layers. withstanding the high temperatures associated
with soldering and rework achieved with poly-
Making All Layers the Same Impedance imide. The results have been mixed. The work
Sometimes, in an attempt to provide more horses of PCB fabrication are still variations of
than one impedance on the same PCB, there is the epoxy and polyimide.
temptation to make some layers of the stackup In the United States, the resin systems of
one impedance and others a different impedance. choice have been Isola Corporations FR406 and
Examples of this are to make the PCI bus at 65 FR408 and Nelco Corporations N4000 series.
ohms and other signals 50 ohms. If this is done it When selecting a resin system for a project it
is likely that the layers containing one impedance is advisable to check with the probable fabrica-
may be used sparsely while layers containing the tors and determine which laminate system in
other impedance may be overcrowded. Therefore, their production inventory works best. It is also
it is wise to make all layers the same impedance so advisable to choose a resin system that has an
the task of routing is easy. equivalent with both suppliers in order to avoid
creating a single-source situation.
Selecting Laminates Most projects designed in the U.S. are des-
PCB material systems are defined by the res- tined for volume manufacture off shore in Chi-
in systems used to make the laminate and pre- na, Taiwan, Japan or South Korea. The resins
preg. To a lesser extent, the type of glass is also systems listed above are available in all of those
part of how a laminate system is differentiated countries. However, there are laminate manu-
from its competition. For the most part, a glass facturers in all four countries that manufacture
composition known as E glass is used. laminate locally. Among these are Mitsubishi,
Resin systems used to manufacture laminate Panasonic, Matsushita and TUC. All of these
include: suppliers have laminates that are equivalent
to the main stream laminates used in the U.S.
Epoxy-based systems (sometimes When designing a stackup that will be proto-
called FR-4) typed in the U.S. and manufactured in volume
Polyimide offshore it is advisable to obtain the materials
PPO-polyphenylene oxide information from the offshore supplier and
PPE-polyphenylene ester make sure the materials needed are available off
BT-bismalamine triazine shore.
CE-cyanate ester Laminate systems are created in two parts.
Phenolic cured epoxy These are the cured laminate with copper foil
Cyanate ester modified epoxy on each side and partially cured laminate (pre-
Filled phenolic cured epoxy preg) that will serve as the glue layers during

November 2012 PCB Design Magazine 19

Feature Article

designing a pcb stackup, part 1 continues

lamination. When creating a stackup, it is nec- both in order to achieve accurate impedance
essary to get the specifications for both types of calculations. It is easy to determine which er
material in order to create a stackup that can to use based on ratio of glass to resin. The big
be built with available materials. Figure 5 is question is what frequency should be used for a
this information for Isolas IS620i. Notice that given design. Virtually all modern designs will
each thickness of laminate is made with woven have components on them with 200 pSec or
glass cloth and resin. The standard construc- faster edges that must be properly controlled. It
tion column specifies what type of glass cloth has been shown that the equivalent frequency
is used for each thickness. These numbers refer for this rise time is approximately 2 GHz. There-
to a particular glass weave with precisely speci- fore, using the er value at 2-2.5 GHz will result
fied numbers of threads per inch and thread di- in accurate impedance calculations.
ameter. For more details on each glass style see As can be seen in the above tables, a wide
Chapter 5[4]. variety of glass styles are used to manufacture
Notice that the relative dielectric constant laminate and pre-preg. Prior to the advent of
(er) varies in two ways. First, it varies with the multigigabit differential signaling protocols,
ratio of glass to resin. Second, it varies with the glass style had little effect on signal quality.
frequency. Therefore, it is necessary to specify Since then, it has been shown that certain glass

Figure 5: Typical resin information.

20 PCB Design Magazine November 2012

Feature Article

designing a pcb stackup, part 1 continues

weaves can result in differential skew and exces- of the quality shown in Figure 5. There are two
sive jitter in differential signal paths operating places to get this information. These are the fab-
at or above 2.4 Gb/S[5]. ricator and the laminate manufacturer. My first
It has since been shown that three weaves choice is to ask the fabricator for this data. Of-
which exhibit this problem are 106, 1080 and ten, the engineering departments of fabricators
7628. Avoiding the use of these weaves in a do not have it. This is a sign that the fabricator
high-speed design obviates this problem. Of is not up to the skill level required to success-
all those listed, 3313 has been shown to be the fully participate in designs of this complexity.
most uniform weave. For this reason, I use this In the event the fabricator does not possess
weave between all my signal layers and their this information, the second choice is to contact
nearest planes. the materials manufacturer directly. Laminate
As mentioned earlier, all of the common manufacturers accustomed to supplying mate-
laminates use a glass known as E glass for- rials to the high performance market will have
mulated to spin well and allow good adherence their materials characterized in this manner and
of resin. This glass happens to have a relatively will openly share the data. There are laminate
high loss tangent. There is an alternate glass re- manufacturers who do not have this data. They
ferred to as S glass that has a lower loss tan- have been supplying materials to the low-per-
gent. At least one laminate supplier, Nelco, uses formance market and should be avoided.
this glass to create a low-loss laminate known as In Part 2, we will investigate methods
N4000-13SI. This material does have a low loss, for calculating and testing impedance, and
but at the expense of creating a single-sourced discuss the steps required for proper PCB
PCB design. The Isola IS620i shown here has stackup. PCBDESIGN
proven to be a drop-in replacement for N4000-
13SI if the need for lower-loss laminate is en- References
countered. 1. FAQ#1: Why is the PCI bus impedance
specification 65 ohms? Ritchey, Lee W., Speed-
Considerations When Selecting ing Edge, Jan. 2009
a Laminate System 2. A Treatment of Differential Signaling
There are a number of properties of lami- and Its Design Requirements, Ritchey, Lee W.,
nates that must be taken into account when Speeding Edge, Current Sources newsletter,
selecting a laminate system. Among these are: April 2008.
3. Right the First Time, A Practical Hand-
Does the PCB require lead free assembly? book on High Speed PCB and System Design,
Does the PCB require a high Tg (ability to Volume 1, Speeding Edge, August 2003.
withstand high temperatures)? 4. Right the First Time, A Practical Hand-
Does the design require a low-loss book on High Speed PCB and System Design,
laminate? Volume 2, Speeding Edge, April 2007.
Can the program tolerate a single-source 5. McMorrow, Scott, et al., Impact of PCB
laminate? Laminate Weave on Electrical Performance,
Will production volumes be DesignCon, Fall 2005.
manufactured in a different shop or
country than the prototypes?
Lee Ritchey is founder and presi-
When most of these conditions must be dent of Speeding Edge. A long-
met, many of the laminate types listed above time PCB design instructor and
will be eliminated from consideration. consultant, Ritchey is the author
of Right the First Time: A Prac-
Obtaining Laminate Information tical Handbook of High-Speed
In order to properly design a PCB stackup PCB and System Design.
it is necessary to obtain laminate information

November 2012 PCB Design Magazine 21


connecting the dots

So You Want to be a Designer?

by Jack Olson

Summary: Welcome to the first in a series of Welcome to the first in a series of short tu-
short tutorials on becoming a circuit board design- torials on becoming a circuit board designer. If
er. If youre new, theres a lot to learn. Well explore youre new, theres a lot to learn. Well explore
the PCB design process one step at a time, explain- the PCB design process one step at a time, ex-
ing the terminology and adding more pieces to the plaining the terminology and adding more piec-
puzzle from month to month. es to the puzzle from month to month. As we
go through it, Ill try to provide other
Your job as a circuit board de- resources where you can get more
signer is to convert ideas into help. So, lets get started
reality. Hows that for an
opening statement? What is a Circuit Board?
Maybe it sounds Most of you probably
too philosophical for wouldnt be reading this
a technical tutorial, if you didnt already
but think about it. know what a circuit
An engineer records board is, but my goal
ideas in the form of is to teach the basics,
a schematic. He does and assume you know
this by placing sym- nothing. Many costly
bols (which represent mistakes in this indus-
electronic components) try can be traced back
and connecting the to incorrect assump-
symbols together with tions and poor communi-
lines (which represent con- cation, and one habit you
ductive wires). Each connec- should develop early is that
tion point on the page corre- if you dont know, ask! None
sponds to a component pin in of us was born knowing any of
the real world. We will look at this, so well start from the be-
this in detail later, but the end ginning.
result is a schematic that can be A circuit board provides a
shared with others; anyone who mechanically stable substrate
understands electronics can inter- for mounting electronic compo-
pret the idea no matter what lan- nents, and provides conductive
guage he speaks. But a schematic connections between them. It is
is only a method of recording the constructed with layers of con-
idea. Someone has to convert it ductive material (usually copper)
into something physical that we separated by layers of insulating
can hold in our hands something material (usually a flame-retardant
we can test. epoxy reinforced with glass fibers).
The end result is a circuit board as- Connections between conductive lay-
sembly, and if you want to learn how to cre- ers are made through plated holes.
ate one from a schematic, youve come to the If I had to describe the job of a circuit board
right place! designer in a single sentence, it would look

22 PCB Design Magazine November 2012

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connecting the dots

so you want to be a designer? continues

Beyond that, if the design is to eventu-

ally become part of a product, it needs to be
manufacturable in some quantity. Feature
sizes are selected to be compatible with bare
board fabrication and test processes. Deci-
sions are made with automated assembly and
soldering methods in mind. There might be
cost constraints involved, and environmental
factors, and the final product needs to be ro-
bust enough to survive the customers use and
expected reliability.
Good design involves juggling many fac-
tors, and well look at each of these in detail in
like this: Circuit board designers create a board future columns. PCBDESIGN
shape that fits the physical size requirements,
position the mounting and tooling features,
determine the number of conductive layers Jack Olson, CID+, has been
(cost vs. performance), logically arrange circuits designing circuit boards full-
into functional areas (floor-planning), populate time for over 20 years. He
each area with appropriate land patterns (place- would like to thank Laser
ment), add planes and traces to connect every- Precision Analytical for giving
thing together (routing), and generate data to him his first design job.
fabricate, assemble and test the product.

Video Interview

Bruce Archambeault: EMC Issues A Fact of Life

by Real Time with...

Dr. Bruce Archambeault,

distinguished engineer with
IBM, discusses the state of
EMC, and why so many
designers and engineers of
all stripes attend DesignCon
for help with analysis.
To View

24 PCB Design Magazine November 2012

Feature Article

Partner Early for HDI Board Design

by John Levreault I think in terms of schematics. Over the
years, by the way, Ive designed many high-
Summary: When customers want to design power class-D amplifiers that are in wide use,
boards that are as compact as possible, there is with varying amounts of logic to support or
often very little reliable guidance from the chip control that function. Today, though, chip ven-
vendors. Heed the warnings of Texas Instruments: dors have made custom design unnecessary, for
Consult board manufacturers from the start of any the most part, for amplifiers with outputs up to
projects involving BGAs with a pin pitch of 0.4 mm 250 W or so. More power to them (!) and hats
and smaller. off, but I do have a bone to pick with them in
another regard. Ill get to that soon.
To preface this story about the design of my The first project I was contracted to design,
first HDI boards, let me point out Im primar- which led, inevitably, to an HDI board archi-
ily an analog design engineer whos been de- tecture, was a multimedia processor based on
signing mixed-signal boards for well beyond 25 a Texas Instruments OMAP. It was an upgrade
years. Theres nothing better than starting with of a product for which there was a lot of exist-
a fresh sheet of paper, or more recently a blank ing hardware and legacy peripherals, and my
screen, and developing a schematic that leads customer wanted to move to a new processor
to a board that performs exactly as intended. for improved audio and video performance and

Figure 1: The tiny (less than 2 in. diameter) six-layer board for multimedia processing holds the TI
OMAP processor (lower right quadrant), its companion power-management chip (upper right quadrant)
that drove the stackup, and a video-processing device on one side (a) with connectors and many of the
passive components on the other side (b).

26 PCB Design Magazine November 2012

Feature Article

partner early for hdi board design continues

speed, but still use the peripherals that had been The form factor was very small, only two
designed generations ago. There was a great deal inches in diameter. Implementing all the re-
of I/O: multiple USBs, WiFi, and much more. It quired functions involved several boards in a
was, in simple terms, a hub. stack spaced just 1 mm or so apart. Some of the

Figure 2: Routing to the inner pins of the TI PMIC could be accomplished only through microvias in
the pads for the device, which has a 0.4-mm pin pitch, though top-layer traces were navigated to a
few pins at the matrix perimeter.

28 PCB Design Magazine November 2012

Feature Article

partner early for hdi board design continues

cards were joined by board-to-board connec- fine-pitch board design is a team

tors; others that had tall components required effort. (Reference 1)
a flex connection. There was an audio board,
an interface board, a WiFi board which were Fortunately, I could learn a lot by essentially
fairly conventional four-layer boards and a reverse-engineering an open-source design by
central board designated the DSP board, incor- which I was able to develop my via stack. Even
porating the OMAP and its companion power- so, that was no picnic. While I was designing
management chip (TPS65950), as well as a vid- the DSP board, which was eventually routed in
eo processor. six layers with microvias, buried vias and there-
The OMAP in this case is packaged in a BGA fore multiple laminations, I didnt know who
with pins on a 0.5-mm pitch, yet there was a would build it. I took to heart the admonition
more difficult routing challenge. I knew no tac- from TI and other quarters to immediately open
tics to navigate traces from inside the pin ma- a dialog with a manufacturer. Several shops said
trix of the power-management chip, which has they could fab the board, but as discussions
209 pins on a 0.4-mm pitch. Clearly, this board progressed, they either couldnt do it or the
layout would be an education. Theres no way way they planned to do it was too complicated.
to fan out from the center clusters of pins on A diligent search led me to partner with Sierra
such a tight pitch without resorting to vias in Circuits, who built the board and along the way
pads. advised me how to architect it to achieve the
There are gaps among some of the pins most efficient, manufacturable design. The de-
along the matrix outer periphery through cision to use microvias in 10-mil pads resolved
which I could fan out from some of the pins in my routing issues for both the PMIC and the
the second row, and there is also a moat in the OMAP for that board.
middle of the matrix that could have permitted The next project I landed that would in-
me to use conventional vias for routing to some volve a BGA on a 0.4-mm pin pitch progressed
of the pins along its edges, but basically there is more easily. I sought advice from my contact
no practical way to get to most of the pins and at Sierra Circuits who had helped me architect
route the board except for blind vias in pads. the first HDI board. This project, a wearable per-
Texas Instruments agrees. sonal communication device, was less than half
I had the advantage of an open-source de- the size of the other board. The prototype had
sign, the BeagleBoard, whose documentation to be about 1 inch by 1.25 inch and include
includes Gerbers and the Allegro file, so I could debugging and programmer ports, but the pro-
study the via stackup stemming from an OMAP duction version would be only 0.7 inch by 1
and other devices packaged in BGAs with a 0.4- inch. My design was consolidated in six chips,
mm pin pitch. And TI has some white papers so clearly the board had to be double-sided to
with recommendations about what kind of contain those as well as a USB interface, all the
board designs might work with this pin geom- passives, and some additional elements. This
etry, which describe a couple of options. But I was a battery-powered system, so it also needed
suspect those responsible for the white papers a charger interface.
didnt actually design such boards. Its what I Obviously, I had to find the smallest pack-
call armchair engineering. However, they do ages available. For the MCU, my options in-
make good points: cluded QFNs and the BGA I selected, whose
80 pins have a 0.5-mm pitch. The available
1. The standard rules of thumb for board BGAs for another device, which has only 51
design do not apply when ball pitches pins, include one with a 0.65-inch pin pitch
of 0.4 mm or less are involved. and a smaller one with a 0.4-mm pitch. The
2. Close coordination and communication one with the looser pitch would not fit on the
between the device supplier, the PCB board, so I had no choice but to use the BGA
designer, the board fabricator, and the with the 0.4-mm pitch, and it was that pack-
assembly shop is mandatory because age that drove my stackup. There is a third

November 2012 PCB Design Magazine 29

Feature Article

partner early for hdi board design continues

tion. It was manually

routed, using Cadence
OrCAD Layout Plus.
The scheme en-
abled me to put the
two BGAs on opposite
sides of the board: the
MCU on the backside,
center top, and the
BGA with the 0.4-mm
pitch on the topside,
lower left. For the most
part, I was able to keep
the chips on one side
of the board from over-
lapping those on the
flip side. There was a
Bluetooth chip, which
made sense to locate
next to the antenna
along a board edge.
There was a require-
ment to put the USB
interface, which is also
the charger port, in a
particular spot, so that
told me where to put
the power-manage-
ment chip.
I needed five or six
different supply values
for the digital devices
Figure 3: HDI architecture made possible squeezing six ICs one with a and a supply for an an-
0.4-mm pad pitch onto a double-sided board whose long dimension is alog device. Everything
just 1.25 in. The top signal layer is shown. has a common ground.
Rarely do I split planes
for ground. I use fer-
major component in a QFN, and I also used rites and bulk capacitors for isolating the Vcc
a QFN for my power-management device. The or Vdd supplies from the bulk supply running
board also carries some flash memory in a re- through my power plane. I prefer to route pow-
ally big package. Most of the passives are 0402 er nets last and route the top signal layer first,
capacitors and there are two 0603 bulk capaci- which completes much of the job. Its easier, I
tors. find, to nudge a signal trace to make room for
My contact and I worked out a routing strat- a power via rather than the other way around.
egy resulting in a six-layer, double-sided board But if you ask 10 other people youll get a dozen
signal, ground, signal, signal, power, and other opinions. The trick is placing components
ground with microvias from layer 1 to 2, 1 to to minimize the rats nests of routing.
3, 6 to 4, and 6 to 5, and a standard via from Though the BGA with the 0.4-mm pitch has
layer 1 to 6. I embedded local copper pours into 51 pins, I needed only 26 of them, five of which
the inner routing layers to aid power distribu- are connected to the debug port in the proto-

30 PCB Design Magazine November 2012

Feature Article

partner early for hdi board design continues

type. Regarding the 80-pin MCU, six pins had But at the end of the day, when custom-
no function but I routed them to a debug port ers complete development and want to design
just in case. The project was designed for a cus- boards that are as compact as possible, there
tomer offshore who is still in development, so is very little reliable guidance from the chip
having those available should be handy. vendors. Take my advice and the recommenda-
Permit me to return to my issue with chip tion from TI: Early in the HDI design process,
vendors. The use of HDI board architecture in partner with a board manufacturer who knows
my experience is driven by the presence of BGAs what to do. PCBDESIGN
with a 0.4-mm pin pitch. Even tighter pitches
are soon to follow. I think the companies that References
build the dense chips that need such packag- 1. Texas Instruments Application Report
ing should have real documentation about real SPRAAV1B
things that have been built with those products.
Certainly, the designers who create those John Levreault is the presi-
chips with internal clock rates in the hundreds dent of Orvelle Technologies
of MHz want to avoid compromising signals, so in Boxford, Massachusetts.
things are not necessarily placed in locations He specializes in the design,
on the die that would result in the most con- development, and production
venient pinouts for customers. The evaluation of custom analog and mixed-
boards that are provided are not usually archi- signal products for OEMs. He
tected for very tight packing; theyre designed can be reached via and
so customers can easily get to test and debug 978-352-8235.

Video Interview

MIA: The Next Generation of Designers?

by Real Time with...
Designers Forum

San Diego design icon Mike

Creeden discusses the initial
presentations at the Designers
Forum, including his take on
the critical need for PCB design
education. He also outlines
plans for the Designers Council
meeting hosted by his com-
pany, San Diego PCB.
To View

November 2012 PCB Design Magazine 31


beyond design

The Plain Truth About Plane Jumpers

by Barry Olney
In-Circuit Design Pty Ltd, Australia

Summary: The key to building the optimum

board stackup is determining how and where the
return currents flow. But it is also just as important
to have the board constructed to your specifications
having engineering drive fabrication rather
than delegating impedance control and material
selection to the fab shop.

Moats, islands, cut-outs in the ground plane,

isolated power planes, floating ground regions,
and a host of other intricate layout techniques
are often used by PCB designers to reduce cross-
talk, EMI, and to otherwise improve overall cross a split in the power refer-
system performance. ence plane a plane jumper decou-
But a high-speed signal crossing a split pling capacitor (100nF) can be placed
in the plane causes problems along at least close to the offending signal(s) to provide a
three dimensions, including signal quality, path for the return current between the two
crosstalk, and EMI. The problem is the imped- supplies (e.g., 3.3V || 1.5V).
ance discontinuity in the signal path crossing In Figure 1, the gap totally isolates the pow-
the split. The discontinuity reflects energy back er reference planes, so a plane jumper capaci-
toward the source particularly the higher-fre- tor is used to allow the return current to bridge
quency components of the signal. At high fre- the gap in the planes from 3.3V to 1.5V. This
quencies, the return current follows the path of is quite effective, but should be only used as
least inductance which is directly below the a last resort, if you cannot avoid routing such
signal trace but that path is broken by the a signal across the gap. I must say that it does
split. The reason for this discontinuity is the look weird having a decap on the schematic
fact that the return current has to find an al- between 3.3V and 1.5V, where decaps are nor-
ternate path back to the source, creating a large mally placed between power and ground.
loop area and a nice little antenna for differen-
tial-mode radiation.
It is important to keep in mind that both
ground and power planes (any plane) can be
used as the reference plane and return current
path for a signal.
The key to a successful mixed digital/analog
design is functional partitioning, understand-
ing the current return path, and routing con-
trol and management not carving up ground
planes. It is always better to have just one single
reference (ground) plane for a system.
I mentioned plane jumpers briefly in my
recent column Mixed Digital Analog Technol- Figure 1: The return current path uses the ca-
ogies, where I said: If a digital signal(s) must pacitor to bridge power reference planes.

32 PCB Design Magazine November 2012


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Beyond design

the plain truth about plane jumpers continues

Figure 2 illus-
trates the correct
way to tackle this
situation control
signals crossing over
the bridge of a split
plane. The (blue)
traces are grouped to-
gether, with a contin-
uous ground plane
beneath, providing a
reliable return path
for these signals. The
trick is to always ref-
erence a signal to a
solid plane not to
split the reference
plane. The power
plane can be split
providing it is not
used as a reference
But that is the
most basic use of a
plane jumper. Lets
look at where else
in the design these
magic jumpers can
be employed.
ICD recently sim-
Figure 2: Control signals cross over the bridge of a split GND plane. ulated a board whose

Figure 3: Signal current flow (red) and return current flow (blue).

34 PCB Design Magazine November 2012

Beyond design

the plain truth about plane jumpers continues

designers intended to route high-speed signals at the fabricator to change the thickness of the
from a chip to a connector on top of the board. core and pre-preg materials to suit the dielectric
The routing fanned out from the BGA, went di- materials they had in stock.
rectly to layer 3, then popped back up through This is a classic case that we see all the time.
a via to a connector on the top layer. This seems It is the point where our design crosses over into
perfectly reasonable. the real world manufacturing. It represents a
But looking at the stackup in more detail, point beyond which many designers rarely dare
the signal was first referenced to the GND plane to venture, due to their lack of understanding
on layer 2; then, as it transitioned to layer 3, its of PCB fabrication processes. But, it is a fact that
reference plane changed to VCC (layer 4) due to the more awareness we have surrounding the
proximity. There is, in this case, only one way fabrication processes, the better our designs be-
for the return current to jump planes, and that come, and the better designers we become.
is by finding the nearest VCC to GND decou- The CAM professional looks at your board
pling capacitor which may be a long distance in purely physical terms. He, most likely, has
(relatively) from the signal transient, creating a no understanding of which signals are critical,
large loop area and undesirable common-mode and your current return paths. His window to
currents. This can all be avoided by placing a your world consists of layers of dielectric materi-
plane jumper (decap), close to the signal-via als, copper foils, PTH vias, and soldermasks. The
transition, between VCC and GND. standard Gerber file format transferred from
In the case, where there are multiple ground layout to fab is a rather primitive (based on the
planes on a PCB, we cannot simply assume that old X,Y plotters) but highly effective format for
ground is ground and be sure that the return describing two-dimensional graphical informa-
current will find its way back to the source. GND tion. It is well suited for representing the two
stitching vias should be placed next to each sig- major components of a PCB image: lines and
nal-via transition to stitch the GND planes to- dots. But this is all they are to the CAM engineer.
gether, providing a clear return path. The proverbial left shift in the design pro-
Now, the designer had good intentions: us- cess is to put control of the stackup build back
ing the GND plane on layer 2 as the common into the hands of engineers and PCB designers
reference plane. Everything would be fine, un- enabling them to collaborate with, if not con-
til a lack of communication (and understanding trol, the outcome of the fabrication. To do this,
of the design parameters) led the CAM engineer designers need a comprehensive list of standard

Figure 4: The return current path now uses a common GND plane (layer 2).

November 2012 PCB Design Magazine 35

Beyond design

the plain truth about plane jumpers continues

dielectric materials from popular manufacturers Plane jumpers (decaps) can be placed close
like Isola, Nelco, Rogers, etc., and the ability to to a via to allow the flow of return current
insert these into a prototype stackup, determin- from plane to plane.
ing the single-ended and differential impedanc-
es of these materials combined with PCB layout Where there are multiple ground planes,
design rules. The ICD Stackup Planner, shown ground-stitching vias should be placed
in Figures 3 and 4 (available for download at next to each signal-via transition. handles these tasks quite well,
in fact, providing an interface between CAM, The more knowledge PCB designers have
signal-integrity simulation, and PCB layout. of the fabrication processes, the better
Since layer 3 is now closer to the GND plane the outcome of our design, and the
on layer 2 in Figure 4, it will be used for the better designers we become.
current return path, rather than VCC, as be-
fore. And, there is no need for plane jumpers The left shift in the design process is to
in this case. This is by far the best scenario. The put control of the stackup back into the
PCB designer can pass this information on to hands of hardware designer so that
fabrication with confidence that his intended electrical design parameters dont get
stackup build will be manufactured to suit the pushed to the side. PCBDESIGN
designs electrical needs.
Plane jumpers can be used to easily resolve References
a return-current issue, but they are best avoid- 1. Advanced Design for SMT two-day
ed by taking control of the stackup back into course Barry Olney
the hands of the hardware engineer and PCB 2. Beyond Design: The Dumping Ground
designer, while streamlining communication Barry Olney
between the hardware-engineering team and 3. Intro to Board-Level Simulation and the
fabrication. PCB Design Process Barry Olney
4. PCB Design Techniques for DDR, DDR2 &
Points to Remember DDR3, Part 1 Barry Olney
5. PCB Design Techniques for DDR, DDR2 &
A split in a plane causes an impedance DDR3, Part 2 Barry Olney
discontinuity in the signal path crossing 6. Electromagnetic Compatibility Engineer-
the split, creating signal reflections, cross- ing Henry Ott
talk, and unwanted common-mode 7. High-Speed Digital Design Howard
currents that can lead to EMI problems. Johnson
8. The ICD Stackup Planner and PDN Plan-
Both ground and power planes (any plane) ner can be downloaded from
can be used as a reference plane and
return current-return path for a signal.
Barry Olney is managing
It is always better to have only one single director of In-Circuit Design
reference (ground) plane for a system. Pty Ltd (ICD), Australia. The
company developed the ICD
Plane jumpers (ceramic decaps) can
Stackup Planner and ICD
provide a path for the return current
PDN Planner software, is a
between the two supply planes.
PCB Design Service Bureau,
A bridge, provided by an adjacent plane, and specializes in signal integrity, cross-
is best used for control signals to cross a talk, and timing simulation, as well as EMC
split plane. analysis.

36 PCB Design Magazine November 2012

Most-Read Design News

Mentor Graphics Announces Zukens PCB Design Suites

TLA Program Winners Add Support for Xilinx Zynq-7000
Mentor Graphics Corporation has announced win- Zuken now supports the Xilinx Zynq-7000 All Pro-
ners of its 24th annual PCB Technology Leadership grammable SoCs within its CR-8000 and CR-5000
Awards. The Best Overall Design award went to PCB design suites.
Simon Hawkes, Mark Butt, and Kelly Perryman of
UK-based Selex Galileo. Judge Rick Hartley said, I Mentor Graphics Unveils
have never given a score to a design as high as the Next-Generation PADS Flow
one I ranked as the overall winner; its just unheard The scalable PADS 9.5 flow enables users to cost-
of, how good that design is! effectively design their products, from standard
PCBs to the industrys most complex, highest per-
Sunstone Launches formance, and densest PCBs. Enhancements in
Share Your Story Contest the PADS 9.5 release include the ability to switch
Sunstone Circuits has launched the Share Your to bottom view so the design can be viewed and
Story contest for design engineers. The contest modified from the bottom or top side.
will run through December 16, 2012, giving en-
gineers a chance to share their PCB-related design ICD Releases Japanese Version
successes online with their peers. of Stackup Planner
ICD Managing Director Barry Olney said, Due to the
Intercepts Pantheon popularity of the Stackup Planner, ICD has released a
Wins NPI Award Japanese version to respond to the huge CAM market
Intercept Technology won the 2012 New Product in Japan. The new release of ICD integrates the lat-
Introduction Award at PCB West in Santa Clara, est Boundary Element Method (BEM) 2D field solver
California. Intercepts Pantheon suite took home technology into the impedance planning software to
the award for the PCB Design Tools category. deliver the best functionality in its class.

DownStream Updates Allegro 16.6 Addresses Need

Post-Processing Solutions for Streamlined Solution
DownStream Technologies has announced new Allegro 16.6 accelerates timing closure for high-
versions of their industry-leading PCB post-pro- speed interfaces by 30-50%, through timing-aware
cessing solutions: DFMStream, CAM350, and Blue- physical implementation and verification delivered in
Print-PCB. The new releases will be available in Q4. the industrys first ECAD team collaboration environ-
ment for PCB design using Microsofts SharePoint.

SiSoft Releases Channel Designer Alliance, SiSoft has worked closely with Intel to
develop these design kits which offer ready-to-
Kits for Intel 89xx Series run setups, allowing designers to perform pre-
route design space exploration and verify their
Signal Integrity Software (SiSoft) announced PCB designs prior to fab-out, a huge advan-
the availability of three Quantum Channel De- tage over testing physical prototypes.Quantum
signer design implementation kits for the Intel Channel Designer enables designers to perform
platform for communications infrastructure with post-layout analysis on all serial links, allowing
the Intel Communications Chipset 89xx Series. designers to quickly analyze every link for volt-
As a member of the Intel Intelligent Systems age and timing margins.

November 2012 PCB Design Magazine 37

Feature Article

A Chronicle of Speed and Density:

The TLA Design Winners Through the Years
by Happy Holden Entries are accepted for six categories of
GENTEX Corporation applications. This is a fluid definition that
can change if new applications develop or
Summary: Since 1988, Mentors Technology existing categories are extinguished. The cat-
Leadership Awards have honored the PCB design- egories are:
ers working on the veritable edge of the cutting
edge. Happy Holden tracks some of the trends hes Computers, Blade & Servers,
seen in 12 years judging TLA designs. Memory Systems
Consumer Electronics & Handheld
Printed circuit design is a complex, chal- Industrial Controls, Instrumentation
lenging endeavor that often goes unrecognized. & Medical
There are no university degrees in PCB design, Military & Aerospace
but the skills required for modern, high-speed Telecom, Network Controllers &
electronics layout and design require just as Line Cards
much study and lab work as a university de- Transportation & Automotive
gree. Fortunately, Mentor Graphics sponsors an
ongoing program to recognize the best efforts The most hotly contested categories are
by printed circuit board designers and organiza- usually Industrial Controls, Instrumentation &
tions: the Technology Leadership Awards (TLA). Medical, Military & Aerospace, and Telecom.
The TLA was created in 1988 by Russ Henke, The majority comes from the U.S., the UK,
then GM of Mentors Board Station Division. China, and India. But 31 countries have sub-
For 24 years, Mentor has asked companies and mitted entries including Germany, South Af-
individuals to submit entries that they feel are rica, Finland, Israel, Hungary, Canada, Turkey,
examples of the best in technology of PCB de- Singapore, Austria, Poland, Belgium, Spain,
sign. The electronics world has responded with Norway, Sweden, Slovakia, France, the Russian
some of the most challenging PCBs ever seen. Federation, Japan, South Korea, Taiwan, Paki-
The TLA entries offer a unique look at the stan, Italy, the Netherlands, Poland, Switzer-
evolution of PCB designs over nearly a quarter land, Mexico, Egypt, Italy and Portugal. This
century, particularly in the ever-changing areas list includes entries from universities in those
of speed and density. countries.

38 PCB Design Magazine November 2012
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Feature Article

a chronicle of speed and density continues

A Brief History of
TLA Entries
I have been a judge for TLA
since 2001, and in that time I
have seen enormous changes
in design complexity. Figure
1 tracks the TLA designs over
this period. Each point was an
entry from 2001 through 2012,
with the larger triangles and
squares showing the average
for that year. The two diagonal
dashed lines are the minimum
HDI entries and the maxi-
mum through-hole multilayer
entries. This is a logarithmic
chart, with dispersal showing
the enormous variety of entries
over the years.
Figure 2 offers another way
to look at these entries. I have
plotted the average number of Figure 1: Individual board entries for the TLA from 2001
pins per square inch of substrate through 2012, with averages for each year. Shown are
over the years for through-hole minimums for HDI and maximum for TH.
multilayers and microvia HDI.
There has been a steady growth
in the density of components
from 52 (TH) and 173 (HDI)
average connections per square
inch in 2001 to the peak occur-
ring in 2010 at 187 (TH) and
413 (HDI) average connections
per square inch. And 2012 fol-
lows the general trend, with
180 (TH) and 330 (HDI) average
connections per square inch.
The wide variations of MAX
and MIN are due to the diver-
sity of designs; typical entries
range from single-sided boards
to 42-layer telecom backplanes
with only connectors. In 2001,
only 18% of entries were HDI,
but there was a steady increase
of HDI entries to a level of over
Figure 2: Average board density (in connections per square
40% for the last three years.
inch) for entries to the TLA from 2001 through 2012, separated
HDI is also increasingly rep-
for TH multilayers and microvia HDI (solid lines) with dashed
resented among the winning
lines marking MAX entries and dash-dot lines being the MIN
design, with 30% in 2001 to
greater than 70% by 2010.

40 PCB Design Magazine November 2012

Feature Article

a chronicle of speed and density continues

Mentor has automated

much of the technical data
for submission with EDA tool
scripts. These scripts collect
the physical information from
the design database much like
a standard design report would
do. Information such as size,
thickness, layers, number of
nets, design rules, vias, rout-
ing distances, etc., provide data
needed for Mentor to create a
large spreadsheet of these tech-
nical details for the judges.
When screen captures of Figure 3: Entry averages from 2007 and 2012 are compared to
layers routed, 3D images, ther- averages from 2000 and 1995.
mal maps, SI and PI simula-
tions, and photos of the finished board or as- just coming out and there were no HDI entries.
sembly are provided, the judges have a much By 2000, there were 750MHz processors with
clearer understanding of the challenges the de- 100MHz clocks and rise times at 0.5ns. BGAs
signers and engineers faced, as well as their solu- were small at 100-200 pins, and 18% were HDI.
tions. These are important parts of an entry that To make the judging as unbiased as possible,
cannot be found in the design tool database Mentor removes the identity of each entrys de-
the problems that this team faced in terms of signers. Each design is given an entry number,
high-speed logic, critical nets, placement issues, and until the winners are announced, judges
signal integrity and noise challenges, as well as have no idea who is responsible for the design,
power integrity, PDN, thermal, manufacturing or even where it originated. We are, however,
and cost issues. provided with the designers written explana-
The entry statistics for the 2012 TLA pro- tions of challenges they faced, which can be
gram are typical: very interesting when dealing with non-English
speaking design teams.
Biggest board: 16.75 x 14.0 Figure 4 is typical of the drawings, figures
Smallest board: 2.67 x 2.11 and photos attached to a design entry. A verbal
Most layers: 28 HDI (5+16+5)
Average traces/spaces: 4/4
Most vias: 45,673
Most nets: 8,057
Most connections: 23,316
Most components: 8,635
Most FPGAs: 45
Largest percentage of high-speed nets: 88%
Highest passive/active ratio: 205:1

To better view some of the average charac-

teristics, Figure 3 compares some averages of
2012 and 2007 with 2000 and 1995 entries. In
1995, clocks were around 66MHz and signals
had nanosecond edge rates, and RAM averaged Figure 4: One of the 2012 TLA submissions
64MB. DIP through-hole still predominated, featuring additional details about the power
but SMT was increasing. Mobile phones were integrity of the design.

November 2012 PCB Design Magazine 41

Feature Article

a chronicle of speed and density continues

description is essential, as well as all the techni- Placement and routing was done in an
cal data and layer routings, but a finished board orthogonal fashion, then rotated to
and a 3D image can be very helpful in putting the proper 3D angle.
it all into perspective! EDA Tools: Expedition PCB, Dx Designer,
DMS, IO Designer & Valor NPI.
Recent TLA Winners
To help us better gauge the caliber and trend The 2011 Best Overall Design winner (Figure
lines of the winning designs over the years, Fig- 6): Wipro Technologies, for its single-box BTS
ures 5-10 offer a summary of the winners of the housing transport, baseband and RF circuits:
Best Overall Design awards for the last six years,
followed by each teams details of the challeng- Digital & RF circuits tight constraints;
es associated with that design. managed within limited board space.
The 2012 Best Overall Design winner (Figure High-speed routing is done using HDI
5): Selex-Galileos semi-active laser system: and needed strict length matching
and verified using SI and timing (pre-
Complex due to unique shape and and post-layout) simulations.
reliability concerns during use. 210 diff pairs.
Connecting two fine-pitch parts Multiple DDR3 devices.
(LQFP @ 0.4 mm) without the use of Serial interfaces: SGMII, SRIO-II, RP3,
microvias and large power module. USB2.0.
Plated-through and cap-plated via-in-pad Power integrity: 12 major rails; 20 minor
employed with close fabricator rails (lots of split planes).
involvement. Dissipate 280W temperature-sensitive

Figure 5: The 2012 TLA Best Overall Design from UK-based Selex-Galileo.

42 PCB Design Magazine November 2012

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Feature Article

a chronicle of speed and density continues

Figure 6: The 2011 TLA Best Overall Design from India-based Wipro Technologies.

devices resolved using heat towers & The 2010 Best Overall Design winner (Fig-
thermal ground vias ure 7): General Electric Intelligent Platforms
Managed tight component & routing SBC612 rugged 6U VPX single-board computer:
density while minimizing crosstalk.
Tight DFx constraints broad test Aimed at high-performance mil/aero
coverage required. applications. 6U form factor.
SI and timing analysis on parallel buses; Complexity: 3,500+ nets; 20,000+
SI/timing and channel analysis on connections; 11,600+ vias; total 20 BGAs
SERDES/differential lines placed on both sides several quad flat
Power integrity on power distribution packs with 0.4mm pitch also used.
planes. Thermal management: Processor was low
EDA Tools: Agilent ADS RF circuit power (30W), but still needed to be placed
analysis and simulations; Ansoft HFSS close to a cold wall due to operation at
3D EM simulation for RF resonance temperatures up to 85C. All components
analysis; Flotherm board-level and had to be rated for -45C to 85C for
system-level thermal simulations; ruggedization.
Valor DFx review; XtremePCB Mechanical: Mezzanine plug-in cards
Concurrent PCB layout work. dictated low profile placement regions.
Concurrently, designers were working on Buried vias: Reduced buried via pairs to cut
the single database across different costs, which increased routing challenge.
locations. We were able to change/modify High-speed signaling: Serial Rapid I/O,
the constraints online and work on PCI-X, DDR3 significant constraints
different sections. Since the data is with tight tolerances. Placed solid
updated dynamically, all the designers continuous ground layers on either side
were able to see the progress and plan of over 500 diff pairs to minimize
accordingly. impedance discontinuities.

44 PCB Design Magazine November 2012

Feature Article

a chronicle of speed and density continues

Figure 7: 2010 TLA Best Overall Design, UK-based GE Intelligent Platforms.

Power: Managed trade-offs between power Designer was used extensively to manage
consumption and thermal management. the unraveling of these connections. By
Ensured that the PCB could deliver the maintaining consistency between the PCB
required 30A current. and schematic data the team could
Significant effort taken in placement to quickly perform the necessary pin-swaps
ensure thermal efficiency, effective power to optimize the routing without
delivery, and sufficient routing channels compromising the FPGA internal design.
including tuning space.
14 power rails placed on two internal The 2009 Best Overall Design winner (Fig-
layers shielded signals from power noise ure 8): Tellabs Operations, for its sonnet switch
with ground plane on either side. module for an optical transport product:
Manually increased power trace widths
wherever possible to increase current Tight timing margins requiring extensive
capacity for critical devices. constraint formulas with tons of diff
The stackup created for this design has pairs, ground shielding and curved traces.
been successfully used for other designs Constraints evolved as the layout was
and has become the new standard. underway.
Design was completed two weeks under 120+ power rails supplying filtered
schedule. power throughout the design.
EDA tools: Expedition PCB; I/O Designer: Time constraints, so two layout designers
The major design challenge was routing worked simultaneously with XtremePCB.
the processor and connecting components. Also worked concurrently with
Because the number of routing channels engineering.
and layers was limited, it was important EDA tools: ExpeditionPCB, XtremePCB,
to reduce the number of crossover CES, DXDesigner, FablinkXE. The use of
connections between the devices. I/O XtremePCB and cluster attributes to group

November 2012 PCB Design Magazine 45

Feature Article

a chronicle of speed and density continues

Figure 8: 2009 TLA Best Overall Design, U.S.-based Tellabs Operations.

components quickly to finalize the design autorouted using both hard and soft
floorplan, and the ability to cross-probe routing fences.
between the design and schematic or CES
database was crucial to our success. We The 2008 Best Overall Design winner (Figure
utilized XtremePCB to double-team 9): Alcatel-Lucent, for its optical router telecom
during the entire layout design phase, switch module:
including floorplan, placement, fanout,
defining power layers, routing and trace Blind vias, eight power planes, two 4-layer
tuning. During the layout phase we TH MULT laminated to a 10-layer.
maintained a design source for 4/4 geometry, 0.010 FHS with 18:1 AR.
engineering changes, and if running Signal and noise problems for 1,900
XtremePCB was not feasible we worked high-speed nets.
through design copies and utilized the
export/import functions to work in The 2007 Best Overall Design winner (Figure
tandem throughout the floorplan and 10): Siemens, for its reconfigurable FPGA-based sig-
placement phase. This was instrumental nal processing platform on PCI-X (1.5 TeraMAC/s):
in reducing the time-to-market of this
product. Concurrent design techniques According to Xilinx, this is the most
were followed which allowed for powerful signal processing board in the
seamless engineer changes to the design; world. With 16 Virtex 4 SX55 (BGA
HyperLynx Simulation was run to model 1148 pins), DDR2-533 DRAM
design considerations. Static signals were (BGA 0.8 mm pitch).

46 PCB Design Magazine November 2012

Feature Article

a chronicle of speed and density continues

Figure 9: 2008 TLA Best Overall Design winner, Alcatel-Lucent of France.

Board dimensions and board thickness is badly when we added the power layers
limited to the PCI-X standard. The and area fills, so we decided to switch from
manufacturer was undefined at project Solaris to Linux computers and to use a
start, so we needed a very common PCB faster HW platform.
technology definition. Huge estimated When we started our design, the Mentor
power dissipation (220W, 100A@1.2V, I/O-Designer did not support the Xilinx
30A transients) requires thermo Virtex-4, so an experimental patch was
simulations. added. To avoid voids during the soldering
One of the challenges was the time process, we found a completely new
schedule; we had only 10 weeks for the solution to via-in-pads by placing the
first layout. microvias concentric to the BGA pads.
All 16 FPGAs on the board had to be EDA Tools: Boardstation, HiSpeed Option,
connected to the 128-bit cascade bus Boardstation RE (partially autorouting,
and each FPGA had its own DDR2 fanout generation), HyperLynx;
memory bus. AutoTherm, 3D Thermal analysis
PCI specification allows a maximum of (FloTherm/Flomerics); Power integrity
1.6 mm board thickness, and it was very (PowerSI/Sigrity).
difficult to keep the layers low!Each
FPGA also has to be connected to Challenges of the Future
four DDR2-533 DRAMs. Each section of A study of TLA design winners reveals sever-
the buss had 3,406 high-speed nets. al trends. More functionality is being supplied
The system performance went down by semiconductor integration, with ever-in-

November 2012 PCB Design Magazine 47

Feature Article

a chronicle of speed and density continues

Figure 10: 2007 TLA Best Overall Design, Siemens of Germany.

creasing finer-pitch BGAs featuring more pins, and engineers, while recognizing the best de-
busses and memory channels with their associ- signers for that work. For information about the
ated problems of signal and power integrity, and 2013 program, click here.
more passives, with thermal and manufacturing I hope to see one of your designs next
issues. Time-to-market pushes schedules, while year! PCBDESIGN
cost controls are driving more design planning
and DFM. Fortunately, there seem to be more
simulation tools being used to optimize designs Happy Holden, Mr. HDI, is
and solve tricky problems. Director of Electronics Engineer-
How does your work compare? If your de- ing and Innovations at Gentex
signs are challenging, or if you have a more in- Corporation and a veteran PCB
novative solution to these design challenges, technologist and author. He can
then you should enter the Technology Leader- be reached at happy.holden@
ship Awards next year. There are few programs
that show the work of our best PCB designers

48 PCB Design Magazine November 2012

Video Interview

Hartley: Design Education is Your Responsibility

by Real Time with...
Designers Forum

Guest Editors Kelly Dack and Rick Hart-

ley go over Ricks Designers Forum
message regarding who is responsible
for a designers education. Rick makes
a great point: Education is empower-
ment, but it is up to you, not your
company or anyone else, to make sure
you are educated! Like many successful
designers, Rick has never allowed his
education to be snuffed by a companys
lack of training budget and he minces To View
no words when explaining why.

Mentor Graphics Expands One example: Sony Mobile, based in Lund,

Sweden, is faced with very compressed engineer-
HyperLynx Suite ing schedules to reach time-to-market windows
in the mobile phone market. To ensure design
Mentor Graphics Corporation has released quality, Sony Mobile performs design reviews to
a major new product in the HyperLynx suite, identify electrical issues related to signal integ-
the market-leading, high-speed analysis prod- rity, EMC, and power integrity prior to building
uct line. a board; however, these review meetings can be
HyperLynx DRC efficiently performs best very time consuming.
practice design rule checking (DRC) on PCB By using HyperLynx DRC we get a structured
layout databases. Driven by customizable rules, approach where all nets are equally checked by
the HyperLynx DRC product can be executed the tool. We can then focus the review meet-
by engineers and designers during the PCB lay- ing on the critical nets where the tool finds the
out process to quickly highlight potential high- violations, said Anders Olsson, senior manager,
speed design issues pertaining to signal integri- Lund DevelopmentElectronics System Design
ty, power integrity, and EMI, at Sony Mobile. Valuable
without running detailed, time can thus be spent on
time-consuming analysis. problem solving instead of
Not only will designs be of problem finding. This makes
improved quality, but cor- us more efficient in our de-
recting problems earlier in sign process, extending our
the design process can avoid review coverage, and en-
re-design and shorten time- sures higher design quality
to-market. for our customers.

November 2012 PCB Design Magazine 49


the Cloud for
by Iain Wilson
Iron Atom

Summary: Significant advances in PCB pre-

CAM with automated DFM solutions now offer
unprecedented levels of automation and advanced
features. Cloud computing is an enabling technol-
ogy offering a new way for users to access busi-
ness-critical processes like DFM. In 10 years, users
will be accessing business-critical applications on a
browser via a Cloud-based provider.

We know that optimizing a PCB design pri-

or to manufacturing speeds time to market and
minimizes time-consuming and costly rework
cycles. With the advent of Cloud computing,
powerful pre-CAM solutions can be leveraged
in a new way to provide a quicker, easier and
more cost-effective way to ensure designs are
ready for the manufacturers. This article will
explain how Cloud computing and pre-CAM
software have been married and are now acces-
sible to everyone, regardless of company size or

50 PCB Design Magazine November 2012


DFM: Whats Not Working Today Effective interpretation of the DFM results
At PCB West 2012, I attended a seminar ti- requires manufacturing knowledge.
tled A CAM Engineers Perspective on Improv- The automation provided by the more
ing the CAD-to-CAM Flow. The presenter made expensive tools is unavailable in the
a sincere effort to educate the audience on mak- cheaper ones. The less you spend, the less
ing the CAD-to-CAM (or design-to-manufactur- you get.
ing) flow smoother, quicker and with minimal
errors. A significant portion of the seminar was A new breed of DFM solutions in the form
dedicated to the topic of DFM. of pre-CAM and recent advances in worldwide
The speaker offered numerous tips and ad- IT infrastructure (specifically, the Cloud) has
vice on typical DFM issues that caused delays opened the door to improvements that were
prior to manufacture. These issues required the impossible, until now.
job to be put on hold while the issues were re-
solved and often required some design rework. The Emergence of Pre-CAM
While listening, I reflected that these were the Fabricators need to get design files loaded
same issues I dealt with as a PCB CAM engineer and checked as quickly as possible has driven
20 years ago. CAM vendors to develop a dedicated solution:
In short, nothing has changed. Pre-CAM. Youve likely heard of CAM, but these
That begs the question: If its to everyones pre-CAM tools offer the following key features:
advantage to have the DFM bugs ironed out
first, how come we, as an industry, still have to Automated input, using some method to
hear tips on how to prevent issues that should automatically load multiple file sets.
not, by now, be an afterthought? Shouldnt Automated file recognition of PCB CAD
there be a solution that becomes part of the system outputs, e.g., Gerber files, ODB++,
natural flow and can be adopted by anybody, drill files, netlists drawings, etc.
regardless of the size of the company and their Automated layer ordering. The correct
financial means? sequencing of all the various PCB layers
Certainly, there are numerous DFM prod- including pastes, legends, masks and
ucts available today. Most are very good at what the copper layers, of course.
they do. They range from relatively affordable, A CAM system engine.
downloadable desktop applications to high- Automated DFM processing.
end, sophisticated (but expensive) solutions in- Automated CAM tasks. The ability to
tegrated with CAD tools. perform standard CAM tasks, like unused
Yet, the majority (if not all) of these prod- pad removal, increasing soldermask
ucts suffer from these problems: clearances to minimums.

The implicit approach that designers will These tools crunch through design files
actually run DFM tools. Some will and like there is no tomorrow. Most file sets pass
some wont. through completely automatically, or require
Designers will focus on completing the just a nudge of information confirmation. Fab-
design. This is rather obvious, of course, ricators can use these types of tools up front at
but it needs to be stated. the quotation process. Its hugely advantageous
Manual DFM tools are only as good as the for them to know critical manufacturing crite-
user. They require product knowledge to ria: layer & drilling structures; minimum lines,
get the best out of them. Unless used spaces, annular ring; SMD pad densitythese
frequently, time will be required to are the factors that drive the cost of the PCB and
refamiliarize with the product. can determine the required tooling and manu-
Manual DFM takes time, which designers facturing processes. If the quote is won, a signif-
dont necessarily have. Im sure they are icant amount of the front-end work is already
itching to get working on the next design. done, reducing the load on the engineering

November 2012 PCB Design Magazine 51


leveraging the cloud for automated dfm continues

team and total engineering time required, thus tions and data storage. There are many well es-
getting the board into manufacturing quicker. tablished companies offering pure Cloud com-
You may be thinking, Where can I get my puting today.
hands on one of these things? Notice the word Youve likely heard of, a
automated in my bullet list above. These venture that initially provided a Cloud CRM
tools are highly sophisticated, incorporating (customer relationship management) offering

years, even decades, of industry (notably, their slogan is No Soft-
knowledge translated into al- ware!). They have since gone
gorithms and computing on to expand into services,
processes. This kind of tech- marketing, social network-
nology doesnt come cheap.
To us, Cloud computing is
ing and HR. They also offer
Further, these tools required a new way to look at hard- a platform where a user can
processing power a high- ware, network and software build custom applications
end workstation or server to ensure a good fit into a
resources that lets people
which means $$$. particular market. There are
develop, or use, better and many other companies of-
The Traditional more scalable software for fering Cloud solutions: SAP,
(On-Premises) Software significantly less money. Oracle, Google, and Micro-

Business Model soft, to name a few. Perhaps
Certainly those who can surprisingly, is
afford pre-CAM will buy it. But considered the worlds most im-
what about light-to-medium users, smaller fab- portant Cloud company today.
ricators, and designers? The traditional model So what is Cloud computing exactly? Ill
for business or engineering solution of buying start by saying what its not: 1) The Internet,
the software and hardware is not a good fit for and 2) A website. Certainly, the term Cloud is
pre-CAM or other sophisticated (read expen- being bandied about all over the place. Many
sive) solutions. Heres why: companies are misusing the term by slap-
ping Cloud onto their Internet product offer-
The up-front cost can simply go beyond ing. OK, I suppose it doesnt really matter for
the budget. all intents and purposes the Cloud is the
Inevitable software maintenance fees catchword of the day and most end-users dont
add recurring cost. really care.
Pay-as-you-go schemes cost less to get Wikipedia describes Cloud computing as fol-
going but cost the same long-term, lows: Cloud computing is the use of comput-
and can ultimately cost more. ing resources (hardware and software) that are
Hardware and associated IT support delivered as a service over a network (typically
add more cost. the Internet).
Users need to be trained, costing To us, Cloud computing is a new way to look
more time and money. at hardware, network and software resources
that lets people develop, or use, better and more
So, what to do? Lets look to the skies scalable software for significantly less money.
How is this possible? Well, if you look at an Am-
Cloud Computing azon Web Services (AWS) proposal, you will see
The ubiquitous Cloud is the software indus- that they offer computing power for rent and
trys latest big thing. In software, anyone who is many other products that tie into this. Specifi-
anyone is either heading to the Cloud, or wants cally, they rent the use of one, 10, or 100 serv-
to (because they need to). If not, someones ers, that they own and maintain, for a certain
going to take their place. Cloud computing per-hour cost which depends on the hardware
offers a financially compelling model for specs required by the user.
access to computing power, software applica- For instance, a dual-core, 4GB server will

52 PCB Design Magazine November 2012


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including quick-turn prototype, mid-volume and
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We will support your NPI team transition seamlessly from

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Our goal using the latest DFM tools is to achieve

manufacturing excellence by assisting in design
optimization, helping to reduce, lead time, cost and
improving reliability.

We can meet your certification requirements including

commercial, Military and Aerospace.

To learn more about how our capabilites, facilities and

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leveraging the cloud for automated dfm continues

cost a few cents per hour while an 8-core, 16GB If you ask them if its on their roadmap, most
server will cost a few cents more. For this fee, will assure you it is. Or if its not in the road-
you get premium hardware, patched OS, and map, then they will likely espouse security
the ability to run in a highly secure environ- concerns (more on that later) or some other
ment for which you had to do precisely noth- excuse.
ing. No up-front costs, no IT personnel, and no Heres a question to consider: Do organi-
continuous maintenance: Nothing. zations want to spend any time, money and
Users get load balancers, firewalls, message resources maintaining software, hardware and
queuing software as part of the per-hour cost networks to support business-critical appli-
and, in practical terms, an infrastructure that cations, or just have users access them with a
lets you build software that can scale massively, browser?
without prior investment. So, why are business-software companies so
Cloud software takes advantage of all these eager to migrate their traditional, on-premises
new capabilities and makes all those hardware product to the cloud? Heres three key items:
and software infrastructure parts cooperate.
This new type of software is engineered to run Instant customer access to their product.
in the Cloud and is not the old website-based Customers dont require new hardware,
or browser-based app. Its way more: Cloud OS licenses and all the associated IT
software runs with an infinitely scalable back- time and costs its cheap and easy to
end, and it was designed to take advantage of begin.
all those elements. Very little software is specifi- The software company can maintain its
cally designed for the Cloud today. software; new patches, service packs,
While many vendors stamp their software new releases, new modules and new
with the label runs in the Cloud, features can be applied easily and
most of them do just that: They quickly to its entire customer base
run software that is not in a controlled and
designed to take advan- predictable fashion.
tage of the cloud, in Heres the de-facto
the cloud. software company
Companies who support persons
currently only offer first question to a
the traditional model customer with an
solutions are desperate issue: What version
to get to the Cloud. are you on?

54 PCB Design Magazine November 2012


leveraging the cloud for automated dfm continues

Traditional software companies can only and passwords are never shared. And when I
make fixes available to their customers. Most say the server they work on, I mean one of
software users do not run the latest and greatest, their servers, for their jobs. They cannot ever
and some even neglect to apply critical patches. log onto a rented server without permission,
I dont have a concrete figure at hand, but af- since they have no way to access passwords.
ter working for a traditional software company Only you have that information. When a com-

for 16 years, I can say that supporting puter is thrown away, the hard disks
multiple versions of a product are demagnetized and shredded
was probably our single big- to pieces so that none of your
gest workload. Software up- data can ever be recovered.
grades put a burden on the While the Cloud provider For more information on
end-user too, of course. cannot help a user write security, AWS
outlines its multipoint secu-
Cloud Security
better software, it can rity strategy, click here. Am-
A very common reaction certainly ensure that the azon also features a special
to a discussion on Cloud software platform is rock zone that meets the require-
computing is, Is it secure? ments for ITAR-controlled
solid. In other words, more
My perhaps trite response is data, available here.
usually, Its at least as secure than half the equation
as your e-mail server or FTP about security (the more Cloud Computing Meets
site, but likely several orders complex and ever-changing Pre-CAM DFM
of magnitude greater. Significant advances in
Cloud providers are, of part) is handled; the user PCB pre-CAM with auto-
course, extremely conscious need only focus on software. mated DFM solutions now

of security concerns. Its offer unprecedented levels
fundamental to their success. of automation and advanced
There have been many news features. Cloud computing is
stories during the last few years an enabling technology that of-
about companies suffering from data breaches fers a new way for users to access business-crit-
and having critical information stolen. Some of ical processes like DFM and new markets are
these stories related to poor software implemen- opening up for software vendors who can offer
tation (e.g., clear text passwords sent over the on-demand usage of their sophisticated and ex-
network) while others could be linked to an im- pensive products to those who cant afford to buy
proper infrastructure setup (e.g., firewalls not in them or only need ad-hoc or light-medium usage.
place or not restrictive enough, unpatched SSL There are, in fact, already Cloud-based
implementations, missing OS patches). pre-CAM applications available today, so go
While the Cloud provider cannot help a check them out. Stick around another 10 years
user write better software, it can certainly en- and you will likely be accessing most, if not
sure that the software platform is rock solid. In all, of your business-critical applications on
other words, more than half the equation about your browser via a Cloud-based provider. PCBDESIGN
security (the more complex and ever-changing
part) is handled; the user need only focus on
software. Iain Wilson is a co-founder and
For instance, Amazons internal security president of Iron Atom. He and
policies could be seen as straight from a sci- Alessandro Federici founded Iron
fi movie. Employees cannot access any of the Atom in 2011 after seeing an op-
AWS servers without authentication, and the portunity to utilize Cloud comput-
ing to offer on-demand usage of
authentication is always bound to a real per-
highly automated, expensive soft-
son. Logging-on goes from the server they work
ware applications to the mass market.
on to the office door they opened. User names

November 2012 PCB Design Magazine 55


brooks bits

Trace Currents and Temperature, Part 1:

The Basic Model
by Douglas Brooks, Ph.D.
UltraCAD Design Inc.

Summary: This first of a four-part series on website[1]. Individual electrons really flow very
trace currents and temperature covers the role of slowly down a copper conductor. More accu-
resistance and then formulates a basic model for rately, they jump from one atom to another,
analysis. Subsequent parts will explore various re- displacing an electron in that atom. That elec-
sults that have been empirically obtained, how we tron then jumps to another atom, displacing
can use the melting temperature of a trace to our an electron in that atom, and so on. The in-
advantage, and how to deal with vias. dividual electrons do not travel at the speed of
light, but the displacement of electrons from
Role of Resistance one atom to another does progress at the speed
Traces heat up (increase temperature) be- of light.
cause of power dissipation within the trace it- Heat (or temperature) is movement[2]. As the
self. If no current flows, there is no heating. If temperature of a material increases, atomic and
current does flow, then the power dissipated in molecular motion within that material speeds
the trace is equal to i2R, where i is the current up. In particular, there is random motion at the
down the trace and R is the resistance of the electron level, which also speeds up with tem-
conductor. perature. This results in random collisions be-
In my column What Is Current And Why tween electrons in conductors. If we try to push
Do We Care, I provide the fundamental defi- a signal down a conductor with many such col-
nition in electronics: Current is the flow of lisions going on, we must overcome (at least to
electrons. I develop that definition in that col- some extent) the effects of the collisions. We
umn and in more detail in an article on our do that with a force that, in our world, equates
to voltage. It is the effect of
these collisions, impeding
the flow of the electrons, that
we call resistance.
The resistance that a sig-
nal sees as it propagates down
a conductor is primarily the
result of these collisions.
There are fewer collisions
at lower temperatures than
at higher temperatures, and
therefore the resistance of a
conductor is smaller at lower
temperatures and increases
with temperature. The num-
ber of available electrons for
current flow increases with
cross-sectional area, making
it easier for a signal to find a
path through the collisions
(i.e., there are more paths

56 PCB Design Magazine November 2012


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brooks bits

trace currents and temperature, part 1: the basic model continues

available with bigger cross-sectional areas). Where:

Therefore, as a general rule, the resistance of a (rho) is the resistivity of the conductor
conductor decreases with increasing cross-sec- A is the cross-sectional area of the conductor
tional area and increases with increasing tem- L is the length of the conductor.
So as we pass a signal down a conductor, a And since resistivity is given relative to a
small amount of the energy in the signal is dis- specific temperature, then the resistance of a
sipated within the conductor as power dissipa- trace calculated with Equation 1 applies at a
tion: i2R. It is this power dissipation that heats specific temperature.
up the conductor. There is generally higher en-
ergy lost at higher temperatures, and lower en- Thermal Coefficient of Resistivity
ergy lost with larger conductors (i.e., those with The thermal coefficient of resistivity is
larger cross-sectional areas). usually represented by the symbol alpha, . It is
the factor that resistance increases with increas-
Resistivity ing temperature. Its usage is shown in Equation
The characteristic of a material that reflects 2. Take the resistance of a conductor at some
its electrical resistance is a property called re- reference temperature (usually, but not neces-
sistivity. All materials have resistivity and there sarily 20oC) and multiply it by one plus alpha,
are numerous tables in printed media and on times the change in temperature from the refer-
the Web that provide resistivity information for ence:
various materials. Silver, copper, and gold, re-
spectively, have the lowest resistivity of all ele- [Eq. 2] R = Rref(1+ *T)
ments. It is typically given by the values:
Silver 1.6x10-8 ohm*m R = Resistance at the desired temperature
Copper 1.7x10-8 ohm*m Rref = Resistance at the reference temperature
Gold 2.2x10-8 ohm*m = thermal coefficient of resistivity, and
T = desired temperature reference
Note: Units are ohm-meters. temperature (oC).
Since resistivity increases with temperature
(see discussion above), electrical resistivity must The thermal coefficient of resistivity for sil-
be specified at a particular temperature. This is ver, copper, and gold is[4]:
usually specified as ambient, or room tempera-
ture, at 20oC. Silver 0.003819 per degree C
As noted, the units of resistivity are ohms- Copper 0.004041 per degree C
length. If we divide resistivity by the cross-sec- Gold 0.003715 per degree C
tional area of a conductor, we get units of:
The thermal coefficient of resistivity is very
Ohms-length/area = ohms/unit length. roughly 0.4% per degree C.

Now, if we multiply that by the length of Resistance of Copper Wires and Traces
the conductor, the units become: The resistance of copper wires of arbitrary
size is readily available in standard texts and
Ohms/unit length X length = ohms Web pages. The standard table of resistance is
(or, simply, resistance). usually based on the American Wire Gauge table
which itself is based on what was known as the
So, the standard formula for the resistance Brown and Sharpe Wire Gauge table first for-
of a conductor, based on its resistivity, is[3]: mulated in 1857[5]. While these types of tables
readily equate resistance and wire size for some
[Eq. 1] R = (/A) * L 44 different wire sizes (gauges) they are not

58 PCB Design Magazine November 2012

brooks bits

trace currents and temperature, part 1: the basic model continues

particularly useful for determining resistance [Eq. 3]

vs. size for PCB traces. UltraCAD has created a
freeware calculator for conveniently converting Since R is inversely proportional to the area,
between trace size and wire gauge, available on A, we can rewrite this as:
our website[6].
An illustration of this calculator is shown [Eq. 4]
in Figure 1.
The top portion of the calculator allows And rearranging terms leads to:
the user to enter any two of three parameters
(wire gauge, trace thickness, and trace width) [Eq. 5]
and solve for the third. Then if the user enters a
trace length and a specific environmental tem-
perature, the calculator will solve for the trace [Eq. 6]
resistance at that temperature. Finally, if the
user enters the current flowing down the trace,
the calculator provides the voltage drop across [Eq. 7]
the trace (a simple Ohms Law calculation).
Note that each successive equation
Model for Trace Temperatures (Equations 6 and 7) gets progressively
We now have everything we need to more general.
develop a model for trace current/tempera-
ture relationships. Such a model is shown in There are two reasons for the more general
Figure 2.
Figure 2 il-
lustrates a trace
on a substrate.
The trace is sub-
jected to heating
as a result of the
power dissipated
in the trace (i.e.,
the i2R loss). The
trace will cool
as a result of
conduction and
convection. A
stable tempera-
ture is reached
when the heat-
ing effect and
the cooling ef-
fect are equal
and cancel.
Therefore, we
can start with
the idea that the
change in tem-
perature (of the
trace) is propor-
tional to i2R, or: Figure 1: UltraCADs Wire Gauge Calculator, v3.

60 PCB Design Magazine November 2012

brooks bits

trace currents and temperature, part 1: the basic model continues

equation. The first is that the area of the trace Equation 8, then, becomes an appropriate
is involved in both the heating of the trace and model for investigation of the relationship be-
the cooling of the trace. Therefore, one would tween trace currents and trace temperatures. We
expect it to have a different exponent than the will look at some empirical results of this model
T term. The other reason for a more general in Part 2 of this series. PCBDESIGN
approach is because the resistivity changes with
temperature. Assume the only important factor References
is power dissipation. Then it would intuitively 1. For a more extensive discussion of current
seem that 0.5 would be the correct exponent and its relationship to Maxwells Equations, see
for T. But as the trace heats up the resistivity my article What is This Thing Called Current:
changes. Therefore, for a given current, there is Electrons, Displacement, Light, or What?
more heating at higher temperatures than there 2. For example, the definition of absolute
is at lower temperatures. Consequently, we zero temperature is when ALL motion at the
would expect the exponent of T to be slightly atomic level stops.
different from 0.5. 3. It is really easy to mix up units when us-
In an article in 1997, McHardy and Gan- ing this formula. Make sure that resistivity, area,
dhi attempted to fit Equation 7 to the original
and length are all expressed in the same length
IPC data we all know and love; more on that in units or errors will result!
Part 2 of this series. They concluded that the 4. The thermal coefficient of resistivity is
form factor of a trace may be important in the very sensitive to a particular alloy. Therefore dif-
relationship. That is, the temperature rise may ferent sources may give different values, based
be different for a wide, relatively skinny trace on different alloy assumptions.
than it would be for a narrow, thicker one of 5. For a good discussion of this, as well as a
the same cross-sectional area. This would be be- complete table, visit Wikipedia.
cause a wider trace may cool better than a nar- 6. See
row trace would. Thermal stability would occur 7. Empirical Equation for Sizing PWB Trac-
when the heating of the trace (caused by i2R) es, John McHardy, Mahendra Gandhi. Pre-
equaled the cooling of the trace (related to the sented at IPC Works 97 October 5 - 9, 1997,
surface area, or more directly to the width, W). IPC Technical Paper S06-2.
We may be able to improve the model in Equa-
tion 7, therefore, by looking at the form factor
of the trace (i.e., the width and the thickness) Douglas Brooks has an MS/EE
instead of just the cross-sectional area. We can from Stanford University and
modify the model in Equation 7 to adjust for a Ph.D. from the University
this by breaking the area term into its width of Washington. He has spent
and thickness components, as in Equation 8: most of his career in the elec-
tronics industry in positions
[Eq. 8] of engineering, marketing, general manage-
ment, and as CEO of several companies. He
has owned UltraCAD Design Inc. since 1992.
He is the author of numerous articles in sev-
eral disciplines, and has written articles and
given seminars all over the world on signal
integrity issues since founding UltraCAD.
His book,Printed Circuit Board Design
and Signal Integrity Issueswas published
Figure 2: Model for trace current/ by Prentice Hall in 2003. Visit his website
temperature effects.

November 2012 PCB Design Magazine 61

Video Interview

HyperLynx: Not Just an SI Tool Anymore

by Real Time with...

Steve McKinney of Mentor

Graphics describes the
evolution of the HyperLynx
tool. In a few years,
HyperLynx has gone from
a signal integrity tool to
a full PCB design analysis
To View

IPC APEX EXPO 2013 to Hold on roadmapping efforts in the area of design.
Other subject matter experts presenting at
Design-Focused Activities the Designers Forum include: Edward Acheson,
Cadence Design Systems Inc., who will discuss
With expertise on the latest design technolo- efficient design data transfer to manufacturing
gies, techniques and roadmapping efforts, the using IPC-2581; Daniel DiTuro, DiTuro Consult-
IPC Designers Forum, design-focused courses ing, will cover design for high-reliability applica-
and Designer Certification sessions will be held tions; Happy Holden, Gentex Corporation, will
at IPC APEX EXPO, February 15-18, 2013, at the review the increasing complexity of PCB de-
San Diego Convention Center. Leaders in design signs; Vern Solberg, Solberg Technical Consult-
from L-3 Avionics Systems, Plexus, Gentex, and ing, will tackle embedded circuits; and Rick Hart-
other leading companies will ley, L-3 Avionics Systems,
share insights on design chal- will cover professional
lenges and processes for the design technology and
next generation of electronics. techniques. Mark Finstad,
For engineering staff and Flexible Circuit Technolo-
managers in design, sales, pur- gies and Mark Verbrugge,
chasing and quality, the IPC Pica Manufacturing Solu-
Designers Forum on February tions, will host the popu-
18 is a full-day educational and lar Ask the Flexperts
technical exchange program fo- session.
cused on critical design issues. To view design-fo-
Dieter Bergman, IPC, will kick cused activities at IPC
off the Forum with a discussion APEX EXPO, click here.

62 PCB Design Magazine November 2012


from the pcb library

The Elements of PCB Library Construction

by Tom Hausherr
PCB Libraries Inc.

Summary: There are many elements of PCB li- units for all PCB library creation and layout, but
brary construction. Measurement units, pad shapes, I find this scenario primarily in the U.S. Others
terms, rotations, line widths, text height, IPCs three- use millimeters for CAD library construction,
tier environment, manufacturers recommended part placement, via fanout, and trace routing;
patterns, and many other issues can quickly become even their mechanical data for the board out-
confusing, even for experienced designers. The good line, mounting and tooling holes, text heights,
news: It doesnt have to be this way. title blocks, drill chart and dimensions are based
in metric units.
There are many elements of PCB library In order for the PCB designer to completely
construction. Measurement units, pad shapes, transition to metric units, the EE, mechanical
terms, rotations, line widths, text height, IPC drafters, component manufacturers, fabricators
3-Tier environment, manufacturers recom- and assembly shops must all transition togeth-
mended patterns, and many other issues can er. Component manufacturers have done an
quickly become confusing, even for experi- outstanding job at transitioning to the metric
enced designers. The purpose of this article is system. However, there is one issue regarding
to help clear up confusion about why these fea- chip component names that I dont see chang-
tures exist. At the end, a short survey will help ing in the near future.
identify how prevalent these features are in the When EIAJ in Japan introduced the stan-
design community. The results of the survey dard dimensioning for chip components in
will be published next month in this magazine the 1980s, in the PDP-100 publication, every
and at, so you can see how component dimension and name was in metric
commonly used your PCB library construction units. The most popular resistors and capacitors
preferences are. were dimensioned 3.2 mm X 1.6 mm and right-
This information will empower design- fully named 3216. Under the pressure of the
ers with the information needed to make sure American imperial unit system, it didnt take
designs use the best construction. Are the fea- long for the American-based EIA PDP-100 to be
tures being used driven by converted to inch units so that
standards organizations, Americans could better under-
or by CAD vendors? How stand the sizes and names
do these affect the final of all chip components.
design? Read on to Therefore, the 3.2 mm
find out. X 1.6 mm discrete
components were
Measurement changed to 0.125
Units X 0.062 and renamed
Lets look at work- 1206. Note that the 5
ing units first. Some and 2 were dropped.
PCB designers build EIA did not round num-
all their CAD libraries bers when creating foot-
in metric units, but print naming conven-
do the PCB layout tions, but rather they
in inches. Is this dropped numbers.
you? Some still How consistent
cling strictly to mil has this been? Well,

64 PCB Design Magazine November 2012

From the pcb library

the elements of pcb library construction continues

the 2.0 mm X 1.2 mm chip component was in- been a CAD tool option in enterprise CAD
troduced and quickly changed by EIA to 0.078 tools but rarely used in PCB library construc-
X 0.047, but in this case they rounded the tion. The rounded rectangle is a new concept in
numbers to create the 0805. Next came the 1.6 pad shape and has not been adopted by most
mm X 0.8 mm component, which was changed PCB designers due to the lack of guidance from
to 0.062 X 0.031, and the 0603 was born. The standards organizations regarding the corner ra-
1.0 mm X 0.5 mm component became 0.039 X dius values. And the CAD vendor libraries and
0.019, and the 0402 was created. component manufacturers who provide recom-
mended solder patterns always use a rectangu-
Terms and Definitions lar pad shape.
There is enough history and facts surround- Figure 1 illustrates the pad shape variations
ing terms and definitions to write an entire ar- for a standard quad flat no-lead (QFN) package,
ticle. In brief, IPC has used the term land pat- but note that even though the terminal leads
tern to describe CAD library parts since the are both rectangle and D-shaped, the compo-
introduction of the IPC-SM-782 in March 1987. nent manufacturers recommendations are
But during that same time period, OrCAD Cap- rectangle pad shape. I have never seen a com-
ture introduced footprint to describe a CAD ponent manufacturer recommend oblong or D-
library part. The IPC-T-50 Terms and Definitions shaped pad shape for the terminal leads. And
included footprint, and for 20 years the defini- even though component manufacturers form
tion was See Land Pattern. Just recently, the the thermal tab with a corner chamfer by Pin
IPC-T-50 committee redefined the term foot- 1 and radius corners in the other three corners,
print as The area projected onto the printed the recommended thermal pad is usually sharp
board, described by the component body, in- corners with no chamfers or radius. If the physi-
cluding the lead terminations. So IPC now de- cal component thermal tab has a chamfer, I per-
scribes the footprint as the component package sonally prefer to add a chamfered corner in the
outline that attaches to a land pattern. Depend- thermal pad as a visible Pin 1 indicator in cop-
ing on the CAD software you use, you may have per etch.
also become familiar with CAD vendor-specific Most CAD tools now support the rounded
terms such as cell and decal. rectangle pad shape. The rounded rectangle
The terms pad and
land have also been used in-
terchangeably. The IPC-7351
standard refers to a PCB library
part solder area as a land, but
CAD vendors refer this as a
pad. In your everyday com-
munication with other PCB
designers and EE, what term
do you use?

Pad/Land Shape
Since the introduction
of the IPC-SM-782 in 1987,
IPC has always promoted
the oblong (full radius) pad
(or land) shape. However,
an industry poll indicates
that 70% of PCB designers
use a rectangle pad shape.
Figure 1: Pad shape variations for a standard QFN package.
The D-shaped pad shape has

66 PCB Design Magazine November 2012

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From the pcb library

the elements of pcb library construction continues

Figure 2: Solder rounded off at corners.

IPC J-STD-001 assembly standard), which illus-

trates assembled parts after reflow. Notice that
the lead and lead-free solder move away from
the corners of the pad, therefore creating use-
less copper on the PCB. In this case, a rounded
rectangle pad shape would conform closer to
Figure 3: Rounded rectangle. the final solder joint than the rectangle shape.
Figure 3 is a rounded rectangle concept of
how the rounded corners are calculated using
could become the universal pad shape of the the pad width and a known percentage of the
future as a 100% replacement for oblong, rect- width to determine the corner radius. Also, the
angle and D-shape. Some CAD vendors claim calculation includes a round-off factor for the
that the rounded rectangle is the best option for radius and a maximum radius. The calculation
lead-free solder, and others claim it improves is automated by free tools such as the PCB Foot-
fabrication and assembly. See Figure 2 (from the print Expert from PCB Libraries. This method

68 PCB Design Magazine November 2012

From the pcb library

the elements of pcb library construction continues

Figure 4: (left) Rounded rect-

angle for a chip capacitor.

Figure 5: (middle) IPC-7351

Figure 6: (right) IEC 61188-7

of calculation creates a consistent known pat- shop which rotation you used by identifying
tern throughout the entire CAD library. the standard your PCB library was built to.
The rounded rectangle shape can be used To solve this issue, the IPC-2581 CAD tool
for every surface-mounted component pack- export format is designed to replace Gerber data.
age with the exception of bottom-only termi- IPC-2581 supports fabrication and assembly. In
nations such as the ball grid array (BGA), land the future, if you use IPC-2581 to provide your
grid array (LGA) and column grid array (CGA) assembly shop with pick-and-place data, your as-
due to the round component lead shape. The sembly drawing should indicate zero component
rounded rectangle shape is even acceptable orientation Level A or Level B, which will
for chip capacitors and resistors as shown in provide valuable information to accelerate the
Figure 4. assembly process and reduce errors. Until every-
one uses this standard terminology and orienta-
Zero Component Orientation tion technique for their PCB libraries, assembly
The world standards organizations know shops are forced to check and double-check every
that one of the key elements in electronic prod- rotation to verify the rotation accuracy.
uct development automation is the implemen-
tation of a single zero component orientation Silkscreen Outlines
for all CAD library parts. IPC introduced zero Silkscreen outlines continue to be debated
component orientation in 2007 with the IPC- as everybody seems to have different ideas and
7351A in Figure 5, as Pin 1 left or upper left for recommendations regarding them. Should the
all PCB library parts. Then in 2009, IEC intro- silkscreen outline be outside the component
duced zero component orientation in the IEC package as represented in Figure 7 or under
61188-7 in Figure 6 as Pin 1 left or lower left for the component package as shown in Figure 8?
all PCB library parts. Should the silkscreen outline perform any use-
Table 1 illustrates various component fami- ful function or simply represent a box to define
lies and the various rotations recommended for where each component is assembled? Here are
PCB library construction. Also included is the some basic silkscreen guidelines that should be
EIA-481D which publishes the recommended used for all PCB library construction:
rotation of the component in the tape and reel,
tube, or tray. However, not all component man- 1. No silkscreen outline under the compo-
ufacturers adhere to the EIA-481D standard. nent; these are covered up during assembly,
The primary purpose of creating all of your dont provide any useful purpose, and are a
PCB library parts with a known zero compo- waste of expensive inkjet cartridges.
nent orientation is to easily alert your assembly 2. All silkscreen outlines visible after assem-

November 2012 PCB Design Magazine 69

From the pcb library

the elements of pcb library construction continues

4. All silkscreen out-

lines are mapped to the
maximum component
body with one exception,
the silkscreen-to-pad spac-
ing rule overrides the
component body map-
5. Silkscreen outlines
should map the compo-
nent body and not go
around pads. Excess silk-
screen outlines should be
avoided to make room for
ref des locations. Silkscreen
outlines should perform a
hatch outline along the
component package body.
6. Pin 1 is identified by
extending the silkscreen
along Pin 1 length to in-
dicate polarity when the
package cannot be placed
inverted (the only compo-
nents that can be inverted
are non-polarized 2-pin
7. No silkscreen on any
exposed pad (land). The
ideal pad/silkscreen gap
should be 0.05 mm (2 mils)
+ solder mask annular ring.
So if your solder mask an-
nular ring is 0.07 mm (3
mils) + 0.05 (2 mils) = 1.2
mm (5 mils) minimum
silkscreen to pad gap.
Some companies do
not use silkscreen outlines
when creating the PCB li-
brary. Others put a silk-
screen outline in the PCB
library part to aid part
Table 1: Rotation by standard note: The EIA-481-D rotations marked in
placement, but do not in-
red conflict with both IPC and IEC.
clude it in the Gerber out-
put data for the board fab-
bly provide a functional use as alignment mark- rication. Others put the silkscreen outline only
ing for assembly registration accuracy. on the prototype boards but not in production,
3. All silkscreen outlines must be inside while others use silkscreen outlines on every
placement courtyard. board. Silkscreen outline line widths are also a

70 PCB Design Magazine November 2012

From the pcb library

the elements of pcb library construction continues

Figure 7: Silkscreen outside Figure 8: Silkscreen under Figure 9: Missing polarity marker.
component body. component body.

user preference, ranging from 0.1 mm (4 mils) aries to guide part placement, to aid the assem-
to 0.25 mm (10 mils). bly process and also rework for unsoldering bad
On components with bottom-only termi- components. This boundary as seen in Figure
nals, its difficult to meet the silkscreen rules to 10 is referred to as the courtyard excess. In IPC-
keep the silkscreen and polarity marking out- 7351, there are three tiers for the gap between
side the component and inside the placement the outer perimeter of the library part and the
courtyard. In these cases, the lack of silkscreen placement courtyard. The least courtyard excess
outlines indicates the polarity. Figure 9 shows is 0.12 mm (5 mils) and the nominal is 0.25 mm
the three distinct silkscreen outline corners; (10 mils), while the most is 0.50 mm (20 mils).
note the silkscreen corner by Pin 1 has a miss- There is also a manufacturing zone to allow ad-
ing silkscreen outline to clearly indicate the ditional clearance if the assembly shop requires
location of Pin 1. The surface mount compo- it. If your assembly shop requests an additional
nent families affected are DFN, QFN, SON, BGA, manufacturing zone, then the PCB designer
LGA, and CGA. sets a component body space rule to define the
clearance between the placement courtyards.
Courtyard If no manufacturing zone is required by your
The IPC-7351 standard features a three-tier assembly shop, then you can place the library
library system: least for handheld devices, parts bumper-to-bumper against each court-
nominal for desktop or con-
trolled environment, and most
for ruggedized military, space,
and medical devices. Sometimes,
the component manufactur-
ers datasheets also offer recom-
mended solder patterns. Anoth-
er option is the user preference,
where neither the IPC-7351 nor
the manufacturers recommen-
dation is used, and the PCB de-
signer invents a unique solder
pattern based on experience.
IPC-7351 promotes the use
of placement courtyard bound- Figure 10: Courtyard boundaries.

November 2012 PCB Design Magazine 71

From the pcb library

the elements of pcb library construction continues

Figure11: 3D models.

yard boundary, but the boundaries should nev-

er overlap each other. Overlapping courtyard
boundaries could compromise the assembly
3D modeling is an upcoming technology
that many companies are adding to their PCB
design flow. It used to be that PCB design tools
had to export IDF data and import IDF data
into 3D mechanical drafting tools like PRO-E or
SolidWorks. But now, CAD vendors such as Al-
tium are adding 3D modeling directly into their
CAD tool software. Eventually 3D modeling
will be a must-have feature in the PCB design
Figure 12: Fiducial placement. flow, but no one knows when that will hap-
pen. Many people say they cant live without it,
while others are asking, Why do I need it? I
believe the industry will adapt to 3D modeling
concepts as seen in Figure 11 when 3D model
libraries become abundant and affordable.
Some assembly shops require local fiducials
on fine-pitch quad flat packages and ball grid
arrays as seen in Figure 12. Local fiducials are
used by assembly to optically bombsite (locate)
the center of the fiducial in each corner of the
component to compensate for any skew or mis-
alignment in the panel as it travels down the
assembly conveyor belt. This improves pick-
and-place accuracy for fine-pitch components
that require special handling during assembly.
If there is no room in the corners of the compo-
nent to place two fiducials, one fiducial in the
center of the part is a second option. But as as-
sembly technology improves, the need for local
fiducials could diminish.

Post-Assembly Inspection Dots

Finally, well take a look at the post-assem-
Figure 13: Post-assembly inspection line or dot. bly inspection dots or lines. These are intended

72 PCB Design Magazine November 2012

Most-Read Mil/Aero007
News Highlights

AT&S Certified for EN9100/AS9100 avoidance measures at a time when U.S. defense
AT&S Hinterberg has successfully passed the cer- representatives are scheduled to update acquisi-
tification audit for the EN9100/AS9100 standard. tion rules, according to information and analytics
After having successfully implemented the man- provider IHS.
agement system requirements for ISO 9001, ISO/
TS 16949 and ISO 13485, AT&S Hinterberg has Report: Global Aerospace and
achieved another landmark in certification process. Defense Market 2011-2015
Commenting on the report, an analyst from Tech-
Viasystems Boosts Military Navios Automotive team said: The Civil Avia-
Offerings with AS9100C Cert tion industry in the U.S. has recorded significant
Viasystems Group, Inc., a leading provider of growth over the past few years. The Aerospace
complex multilayer PCBs and electromechanical industry in the U.S. has emerged as an industry
solutions, today announced the achievement of with high potential across the world, despite the
AS9100C certification at its Denver, Colorado and negative impact of the global financial crisis. The
North Jackson, Ohio facilities. AS9100C certifica- aerospace industry in the US is showing an up-
tion is an internationally recognized aerospace in- trend in line with strong market developments. It
dustry standard for the development and produc- is expected that the U.S. will buy a huge amount
tion of aviation, space and defense products. Via- of airplanes by 2028.
systems facilities in Forest Grove, Oregon; Milpitas,
California; Sterling, Virginia; and Toronto, Canada Military Fighter Aircraft Market
attained their re-certification to the AS9100C stan- at $34.37B in 2012
dards in 2011. The Military Fighter Aircraft Market 2012-2022,
Visiongains latest defence report, values the mar-
DOD Set to Update Component ket for fighter jets at $34.37bn in 2012. Major
Acquisition Rules programme developments are expected over the
Reported incidents of counterfeit electronic com- coming decade, with the F-35 joint strike fighter
ponent parts this year are maintaining the re- (JSF) leading a host of influential procurement
cord pace set in 2011, highlighting the need for projects, spanning both Western and emerging
continued vigilance and improved detection and nations such as India, Saudi Arabia, and China.

for the EE or bench technician to visually see requirements. I think many PCB designers will
the location of Pin 1 after assembly to verify if benefit from knowing how other designers cre-
any components were inverted during the as- ate their libraries.
sembly process. Using the silkscreen marking Toward this end, I urge you to consider
located by Pin 1 and the polarity marking on taking this three-minute survey to voice your
the physical package, the inspector should be opinion about PCB library issues. My next ar-
able to visually verify if the Pin 1 silkscreen ticle will show the results of this survey.
mark and component polarity marking match See you next month. PCBDESIGN
up. A good example of this is the QFP in Figure
13, where there are four different assembly rota-
Tom Hausherr, CID+, is president
tions to attach the component to the board.
of PCB Libraries Inc. He can be
I hope you found this article useful in iden-
reached at Tom.Hausherr@
tifying various parts of PCB library develop-
ment. This is the first article of a series that is
intended to identify how your requirements
for a PCB library compare to other designers

November 2012 PCB Design Magazine 73


quiet power

How to Read the ESR Curve

by Istvan Novak

Summary: To use bypass capacitors properly, ESR curve in measured or simulated plots. That
any designer must understand ESR effective se- is the focus of this column.
ries resistance. A designer must understand what it A real-world capacitor, whether it is a dis-
means and how to read the ESR curve in measured crete capacitor or the capacitance of a power-
or simulated plots. ground plane pair, is never ideal. It always has
parasitic resistance and inductance. The induc-
The most widely used power distribution tance is associated with the shape and size of
component is undoubtedly the bypass capaci- the capacitor electrodes as well as the shape and
tor. After the nominal capacitance, its next size of external connections the pads, vias and
most important parameter is its effective se- planes closing the current loop around the ca-
ries resistance, or ESR. To use bypass capacitors pacitor. The size of the current loop, which de-
properly, designers must need to understand termines the inductance, depends only partly
exactly what ESR means and how to read the on the capacitor itself. It is a widely recognized

Figure 1: Equivalent circuit of a capacitor with separate conductive and dielectric losses on the left
and combined effective series losses on the right. ESR is the sum of the Rs(f) conductive and Rps(f) di-
electric losses.

74 PCB Design Magazine November 2012

quiet power

how to read the esr curve continues

may be true for many appli-

cations, there are cases (to be
shown in a future column)
where even the ESR of a ca-
pacitor depends on the exter-
nal connection geometry. To
get to that interesting case,
we need first to understand
the contributors to ESR.
The resistance of a capac-
itor comes from two sources:
conductor losses and dielec-
tric losses. For instance, in a
multilayer ceramic capacitor,
the capacitor plates and the
connecting terminals have
finite resistance and they
make up the series losses.
Figure 2: Typical frequency dependence of conductive losses in a The dielectric layers, espe-
ceramic capacitor. cially if we have high dielec-
tric constant materials, have
a finite loss tangent and will
create a parallel loss conduc-
tance. When we use a series
C-R-L equivalent circuit for
the capacitor, the series and
parallel losses combine into a
single series resistance, called
effective series resistance, or
ESR. This is shown in the
equivalent circuits of Figure
The conductive loss fol-
lows the frequency depen-
dence of skin loss: Starting
from a DC resistance value,
the resistance rises with the
square root of frequency. In
some cases, it may be impor-
tant that different contribu-
Figure 3: Parallel conductance and capacitive susceptance as a tors of conductive losses,
function of frequency. such as terminal and capac-
itor-plate losses have differ-
ent DC resistances and knee
and accepted fact that the loop inductance of a frequencies. Figure 2 shows a simple example:
capacitor also depends on how we connect it to the Rs(f) conductive resistance with 10 mOhm
our board. DC resistance and 1 MHz knee frequency.
In contrast, we tend to assume that the ESR The parallel losses are described by a DC
of the capacitor depends only on the capacitor, leakage current and a dielectric loss tangent,
and not on its external connections. While this D(f). For AC modeling, we can usually ignore

76 PCB Design Magazine November 2012

quiet power

how to read the esr curve continues

the DC leakage. In a sim-

plified model we can also
assume that the dielectric
loss tangent is frequency-
independent; therefore, the
parallel conductance is G =
wC Df. If we want a causal
model, the slight frequency
dependence of C and Df has
to be taken into account.
Figure 3 shows the conduc-
tance (G) and the capacitive
susceptance (B) for a 1 uF
capacitor with 1% Df using
the causal wideband Debye
model. Figure 4 shows the
series equivalent of the same
lossy capacitance.
We notice that the two Figure 4: Series equivalent of the parallel conductance and series
contributors of the equiva- capacitive reactance for the capacitor from Figure 3.
lent series resistance vary
with frequency the opposite
way: The resistance of con-
ductor losses increases, and
the resistance of the dielec-
tric losses decreases with in-
creasing frequency. The sum
of the two creates a typical
basin-like plot (Figure 5).
With reasonably low Df val-
ues and at low frequencies,
the ratio of the magnitude
of capacitive reactance |X(f)|
and ESR(f) is constant and
equals the (approximately
frequency independent) loss
tangent. We can see that in
Figure 5, in the 100 Hz to 10
kHz frequency range, the red
ESR curve is approximately
100 times smaller than the Figure 5: Capacitive reactance and effective series resistance (ESR)
green |X(f)| curve, which cor- of a 1 uF capacitor with 1% Df and 10 mOhm DC series resistance.
responds to a 1% Df loss.
You can try different in-
put numbers, plot the result Dr. Istvan Novak is a distinguished engineer at Oracle, working on signal
and power integrity designs of mid-range servers and new technology de-
and see all the expressions velopments. Novak received his M.S. degree from the Technical University
behind these calculations in of Budapest, Hungary and his Ph.D. degree from the Hungarian Academy
the bypass capacitor model, of Sciences in 1976 and 1989, respectively. With 25 patents to his name,
available at www.electrical- Novak is co-author of Frequency-Domain Characterization of Power Distri- PCBDESIGN bution Networks. To contact Istvan, click here.

November 2012 PCB Design Magazine 77


reid on reliability

The Wrap Crack

by Paul Reid
PWB Interconnect Solutions

Summary: In the process of plating copper to have the holes filled with epoxy or have the
on the initial core, we produce a wrap of copper B-stage epoxy fill the hole during lamination.
that goes through the barrel of the hole, and over Frequently, the B-stage epoxy is used to auto-
the copper foil on its surface, producing what is matically fill the microvia or buried via. There
called the wrap. A wrap crack is similar to a corner are occasions when the buried via is too large or
crack in a plated through-hole, and the focus of too long for the B-stage epoxy to adequately fill
this column. the buried via during the lamination process. In
those cases, a third-party epoxy may be used to
Buried vias and microvias are created by a fill the drilled holes. The third-party fill may be
sequential lamination process, which is the conductive epoxy or not, as the electrical cur-
number of lamination steps that the board is rent is carried by the copper plating in the wall
exposed to during fabrication. The first lamina- of the buried via.
tion is used to make the core that includes the If a copper cap is required, as in stacked
buried via. It is processed just like a normal cir- microvias, then the core may be put through
cuit board, by making internal layers with dis- a process called planarization or skiving. Some-
creet innerlayer circuits, laminating the stack times the copper on the surface of the core is
together, and drilling the laminated stack. The so thick that, with the copper cap, the dielec-
board is then subjected to desmear and hole tric spacing between the top of the buried via
preparation, electroless and electrolytic copper and the layer above is reduced. With -ounce
plating in the hole and etching to produce dis- copper foil, the thickness is typically 15.2 m
creet circuits. After that, the board is subjected (.0006) of copper, 30.5 m (.0012) of plating
to one or more lamination steps in which other in the hole on the surface of the plated hole
structures, like microvias,
are formed.
In the process of plat-
ing copper on the initial
core, we produce a wrap of
copper that goes through
the barrel of the hole, and
over the copper foil on the
surface around the hole.
This copper produces what
is called the wrap. A wrap
crack is similar to a corner
crack in a PTH.
There are two styles of
microvias or buried vias:
those with copper caps and
those without copper caps.
If there is no need for a cop-
per cap, say with staggered
microvias, the core is ready Figure 1: Planarization of the cap, wrap and glass compression.

78 PCB Design Magazine November 2012

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reid on reliability

the wrap crack continues

lamination step. The com-

pression of the glass fibers
makes an area between
layers that has reduced
amount of resin. This com-
pression of the glass fibers
can be described as glass
lock or in extreme cases can
produce a glass crack.
To eliminate this con-
dition of glass lock or
glass crack, the fabricator
frequently planarizes, or
skives, the copper circuits
before the cap is plated. This
is done to reduce the copper
thickness of the wrap and
produce a smooth surface.
Figure 2: Planarization of the cap and wrap. Planarization is done on
both sides of the core. The
and 30.5 m of copper for the copper cap. In problem is that the core may have variation in
this case, we have a total of 76.2 m (.003) of the copper plating thicknesses due to current
copper sticking up into the dielectric. If we use distribution problems. Although the copper is
127 m (.005) of dielectric after lamination, a supposed to be 30.5 m (.0012) thick, it may
post of copper sticks up into the dielectric 76.2 be as low as 20.3 m (.00079) thick in some
m, thus reducing the dielectric spacing down areas or on the opposite site of the board. So
to 50.8 m (.002). This means that the glass the planarization step needs to be controlled to
in the dielectric will be compressed during the skive aggressively on the 30.5 m (.0012) cir-
cuit and less aggressively on
the circuit that has 17.8 m
(.0007) of copper plating.
Next, the core is sub-
jected to electroless and
electrolytic copper plating
and the cap is produced. Af-
ter etching, the core may be
planarized or skived again
to produce a smooth sur-
face and reduce the thick-
ness of the cap.
One study showed
that a wrap that is 5.0
m (.0002) thick is ro-
bust where as a wrap of
less than 5.0 m is prone
to early failure. Based on
this, I think a wrap of 10.1
m (.0004) is adequate to
provide a guard band. The
Figure 3: Photo showing wrap crack. same is true for the cap. A

80 PCB Design Magazine November 2012

reid on reliability

the wrap crack continues

cap of 5.0 m seems to

be robust in most appli-
cations, so I would make
the requirement to be
10.1 m as a guard band.
IPC-6012 specifies that
the wrap and cap will
be a minimum of 12 m
(.00047) and the cap
will be 12 m. Add to
that the thickness of the
foil, in this case 15.2 m
(.0006). This makes the
minimum copper stick-
ing up into the dielec-
tric a total of 38.1 m
To understand the
role of the cap in circuits
we have to understand
how the electricity flow Figure 4: Animation of a wrap crack. Click here for animation.
through the buried via
(see Reid on Reliability:
Lifted Pad Stacked Microvia Failure). What we via. Unlike the dielectric the fill is not con-
find is that if the cap forms the target pad for a strained with X- or Y-axis glass fibers. The fill
microvia, it becomes an integral part of the cir- is expanding to all directions, X, Y and Z. Be-
cuit and a crack between the cap and the wrap cause there is more dielectric in the Z-axis the
will produce an open. A cap that is not part of amount of pressure pushing up on the cap is
a stacked microvia can have a crack and it will greater than the X- and Y-axis pressure.
not cause an open. If the cap is not part of a One of the factors of concern is the coeffi-
stacked structure it can come completely off cient of thermal expansion of the fill as com-
of the microvia or buried via and the electrical pared to the dielectric. While this is an impor-
path will still be intact. tant factor I believe the Tg of the fill is a bigger
factor. With a Tg mismatch, the dielectric in the
A microvia or buried via which has a wrap
hole of the buried via can expand at a signifi-
crack type of failure presents itself as an acceler-
cantly higher rate than the surrounding dielec-
ated or a wear out type damage accumulation.
tric until the Tg of the surrounding dielectric is
Usually the cycles to failure are reduced to be-
tween 100 to 200 cycles. This failure mode starts
The best fill is the A-stage fill of the dielec-
with a crack from the corner of the dielectric.
tric. If one can get the A-stage dielectric and use
The crack progresses up the face of the copper
this as the fill, the Tg will be matched and the
foil and then across the knee of the wrap, usual-
whole buried via will have the same thermal ex-
ly at a 45 angle. The crack can then propagate
pansion at a given temperature. PCBDESIGN
horizontally between the wrap and the cap. In
Figure 4, note that the crack has trapped mois-
ture, resulting in oxidation between the cap Paul Reid is program coordinator
and the wrap. at PWB Interconnect Solutions,
The fill in the buried or microvia is very where his duties include reliability
important. The cap on top of the buried via testing, failure analysis material
analysis and PWB reliability con-
produces what can be best described as a pipe
bomb. The cap traps the fill inside the buried

November 2012 PCB Design Magazine 81

Most-Read News Highlights
from PCB007 this Month

Basista Banks on Continuous
Capability Enhancements c

Fire at Viasystems
Guangzhou China Facility
Basista Leiterplatten GmbH, based in Bottrop, Early on the morning of September 5, 2012, Via-
Germany, specializes in the production of circuit systems experienced a fire contained in part of one
board prototypes and small production runs of the building on the campus of its PCB manufacturing
highest quality. The circuit board manufacturer facility in Guangzhou City, China.
enjoys an outstanding reputation among its large
client base. With the continual modernization of
his company, Peter Basista not only guides the de-
velopment of the market, he anticipates it. d

TTM Technologies Becomes
First Certified Zeta


Italys Somacis Buys
San Diegos Hallmark Circuits PCB manufacturer TTM Technologies of Santa
Ana, California, will be the first factory certified to
produce PCBs using Integral Technologys revolu-
Hallmark has outstanding employees and with tionary Zeta dielectric films.
our plans to make further investments, we will be
expanding Hallmarks capability and capacity to
meet our customers growing requirement, said
Giovanti Tridenti, Somacis Spa CEO.

82 PCB Design Magazine November 2012


AT&S to Build New Factory
in Chongqing, China i

Schweizers PCB Segment
Sees 41% Growth in 1H

China and coastal industries globally are rapidly Schweizer Electronic AG announced its financial
developing their businesses in inland China, with figures for the first half of 2012. Within this pe-
Chongqing Liangjiang New Area one of three riod the company could achieve sales revenues of
national developments becoming an investment 53.7 million, compared to 58 million the previ-
highland for European enterprises. ous year. The EBIT margin amounted to 6.9% (pre-
vious year 9.8%). Hence Schweizer confirms the
revised forecast for the full financial year published

Graphic Plc Acquires
Printca Denmark
on July 5 and, in view of the economic framework
conditions, considers themselves well on target.

This acquisition will reinforce the position of

Graphic Plc as a global leader in manufacturing
complex advanced technology PCBs in the high-

eXception Strengthens
Capabilities, Boosts
reliability segment of defence, aerospace, medical, Investments
industrial, telecommunications, and other special
markets. Despite evidence that the UK manufacturing sec-
tor is shrinking, eXception Group, a UK-based PCB
and contract electronic manufacturer, is seeing

Invotec Achieves Record
Sales in July
continued growth. Increased investment in staff,
processes, and equipment is allowing the com-
pany to weather the eurozone crisis, and buck the
Sales output figures for Invotec reached a record downward trend that has blighted the manufac-
high of over 2.7 million in July. New Managing turing sector to date.
Director Tim Tatton said, These figures are great
news and they demonstrate our proven ability in
supplying time critical, high-technology PCBs. This
is very encouraging against the back-drop of pes-
simism and uncertainty that continues to weigh
heavily on the global economy.


Advanced Circuits Expands
Colorado Facility
The additional space will provide for the introduc-
tion of additional capital equipment investment
and not only provide for cost efficiencies, but also
enable the expansion of current capabilities at the
Aurora location which is well-known in the indus-
try for its expedited turn-time capabilities and reli-
able early and on-time shipments.
For the latest PCB news
anywhere, anytime.
November 2012 PCB Design Magazine 83

six keys to pcb design excellence

Increasing Efficiency with PCB

Design-Through-Manufacturing Automation
by John Isaac
Mentor Graphics Corp.

Summary: Many companies are struggling to The typical electronics company is not
keep up while using traditional PCB design and organized as a continuum. Rather, there is
manufacturing techniques, and treating PCB de- often a mysterious chasm between design
sign and manufacturing as two separate entities. and manufacturing, as illustrated in Figure
But the design-through-manufacturing process, 1. PCB design is performed following ba-
when automated properly, can increase efficiency sic manufacturing rules and then the data is
and cut waste throughout the product develop- passed to the target manufacturer. The de-
ment cycle. sign may have followed these basic rules but
may not be ready for high-volume, high-yield
The high-tech world is under increasing production. The manufacturer will test the
pressure to deliver more differentiated products design data and if they identify changes that
faster, and at reduced cost. Many companies could improve the yields or the cost of fab-
are struggling to keep up while using tradition- rication/assembly, they may request the de-
al PCB design and manufacturing techniques. signer to re-design. This process costs time
And I mean this as two separate entities, PCB and money.
design and PCB manufacturing, because they Lack of automated production line optimi-
often seem to be completely disconnected. In- zation and real-time management of the assem-
stead, the design-through-manufacturing pro- bly line is another problem in todays design-
cess should be thought of as a continuum, be- through-manufacturing continuum. Without
cause thats exactly what it is. Only by chang- automation, you will likely see higher-cost
ing thinking to see this as a continuum with products and lower profits because of excess
feedback can companies compete in the near material inventories and inefficient production-
future. line equipment utilization.

Figure 1: Lack of a continuum between design and manufacturing can lead to higher costs and longer
time-to-market volumes.

84 PCB Design Magazine November 2012

six keys to pcb design excellence

increasing efficiency with pcb design-through manufacturing automation continues

Design-Through-Manufacturing sult in high yields without the need for design

Automation re-spins or significant changes by the manufac-
The first opportunity for automation should turer. Figure 2 illustrates this.
start with design for manufacturability (DFM)
analysis right at schematic entry and continue Design Transfer to Manufacturing
through the entire design process. During sche- DFM checking during the design process
matic entry, DFM requires communication with should have taken us a long way to accelerating
procurement and manufacturing organizations. the setup for short time to volume production
As the schematic is created and parts are cho- levels. Design now passes the data to manufac-
sen, a bill of material (BOM) is generated from turing. In the past, the only method for passing
the design system and passed to procurement this data was in the form of several separate files
and manufacturing. Procurement then analyzes like Gerber, Excellon drill, NC routing, assembly
the BOM to make sure that the parts used can drawings, etc. This method took the intelligent
be procured in the volumes necessary and at CAD data, where all of the inter-relationships
the target costs. Likewise, manufacturing can were intact, and transformed it into disjointed
assure that the chosen parts can be efficiently segments, thus losing all of the intelligence.
assembled and tested on the production line, If the manufacturer wanted to optimize their
thus reducing the cost of the product. manufacturing process for higher yields, they
The next step is to ensure that the PCB can had to reverse engineer the data, and add the
be fabricated, assembled and tested with high intelligence back in prior to any changes. This
yields. The goal is to perform extensive check- is an expensive and time-consuming process.
ing during the PCB design process that not But intelligent data transfer protocols such
only highlights manufacturing violations that as ODB++ maintain the inter-relationships of
will cause hard failures, but also employs the the data as it existed in the PCB CAD system.
manufacturers best practices to ensure that the The manufacturer no longer has to reverse-en-
design data passed to the manufacturer will re- gineer the data to reinstate the intelligence.

Figure 2: DFM checks can discover a variety of possible problems. These are just a few examples.

86 PCB Design Magazine November 2012

six keys to pcb design excellence

increasing efficiency with pcb design-through manufacturing automation continues

greatly improved with

the right software sup-
port. Many elements of
this complex process
can be managed in real
time by MES (manufac-
turing execution sys-
tem) software.
Some parts will fail,
and by capturing and
analyzing this data,
we can determine and
correct the causes, thus
increasing the line ef-
ficiency and product
quality. One of the key
benefits of this type of
software is the ability
to relate, in real time,
the test and/or inspec-
tion failures with the
Figure 3: Optimizing the production line means most effective use of pro- specific machine(s)
duction machines and increased revenue. and process parameters
used in assembly and
the specific material
Planning the Assembly Process vendors and lot codes used in the exact failure
As a new assembly line is being configured locations on the PCB. This data correlation and
in preparation for future cost-efficient produc- real-time visibility is crucial to maintaining a
tion for either high mix, high volume or finely tuned manufacturing flow.
both simulation software (Figure 3) can aid
in this process. This software can be utilized to Feedback
simulate various line configurations combined At the beginning of this article we allud-
with different product volumes and/or product ed to feedback being critical to the design-
mixes. The result is an accurate what if? sim- through-manufacturing automation process.
ulation that lets process engineers try various Operating in a design-through-manufacturing
machine types, feeder capacities and line con- continuum is a learning process. We can learn
figurations to find the best machine mix and by actually manufacturing this or similar de-
utilization to meet their needs. Using line con- signs, and determine what additional best prac-
figuration tools, line balancers, and cycle time tices we might apply to DFM that could incre-
simulators, they can try a variety of machine mentally improve our process with increased
platforms before deciding on the best line con- yields or more optimum use of our manufac-
figurations to target for the specific product or turing assets.
family of products to be assembled. Once the Data captured during the manufacturing
line is set up, this same software maintains an process and during product failure analysis
internal model of each line for future design- can be translated into improved best practices
specific or process-specific assembly operations. (Figure 4) and used to improve the effective-
ness of DFM rules used by the designer. Contin-
The Production Line uous improvement of the DFM rule set based
Configuring and monitoring the running on real-world results can positively influence
assembly line is a complex process but can be the design of the next product or, if the cost

November 2012 PCB Design Magazine 87

six keys to pcb design excellence

increasing efficiency with pcb design-through manufacturing automation continues

Figure 4: A design-through-manufacturing continuum, with the ability for improvement, can help an
electronics company meet their goals.

change is significant enough, the yields of the we can feed that back to previous steps
current product. (including design) to further cut unnecessary
costs and produce more competitive products
The Design-Through-Manufacturing and enable a culture of real, continuous im-
Continuum provement. PCBDESIGN
Design-through-manufacturing should be
treated as a continuum and supported with
integrated manufacturing execution software. John Isaac is director of market
Start with the manufacturers DFM rules, fol- development. He has worked in
lowed and checked by the designers software, the EDA industry with PCB and
followed in turn by the transfer of data in in- IC technology for more than 40
telligent form to the manufacturer. Then come years. His career started with IBM
the automated setup and optimization of the where he managed the develop-
production line; the real-time monitoring and ment of EDA systems for IBMs internal design
visibility of equipment; process and material of their high-end ICs and PCBs. He then joined
performance; and finally, the capture, analysis Mentor Graphics where he has held marketing
and correlation of all failure data. positions in both PCB and IC product areas.
But the process does not end with product Isaac is currently responsible for worldwide
delivery, or even after the sale support. The market development for the Systems Design
idea of continuum is that there is no end. By Division.
capturing information from the shop floor,

88 PCB Design Magazine November 2012


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How did you find the Yes, THE PCB List

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berts practical design notes

Non-Contact Interconnect:
When Crosstalk is Your Friend
by Bert Simonovich

Summary: In normal PCB designs, crosstalk layer count of the backplane would have to
is due to electromagnetic coupling of two or more grow exponentially.
traces routed in close proximity to one another. No, something else was definitely needed.
We usually consider crosstalk to be our enemy in Fortunately, Bell Northern Research (BNR), the
any high-speed design, and go to great lengths to R&D lab of Nortel where I was working at the
avoid it. So how, you may ask, can crosstalk ever time, had an advanced technology group that
be your friend? liked to play in the sand. I remember going to a
meeting to see some presentations on the neat
In normal PCB designs, crosstalk is due to technology they were playing with.
electromagnetic coupling of two or more traces One particular presentation they gave was
routed in close proximity to one another. We of a unique non-contact interconnect technol-
usually consider crosstalk to be our enemy in ogy. I immediately saw the practical application
any high-speed design, and go to great lengths that technology offered for our architecture; it
to avoid it. So how, you may ask, can crosstalk instantly became my friend. It allowed us to
ever be your friend? eventually invent a patented, proprietary point
To answer that question, I would like to start
by taking you back to the fall of 1994. This was
the era of wide parallel busses running up to
33 MHz across backplanes. High-speed serial,
point-point interfaces, and SERDES technology,
as we know and love today, were just a twinkle
in some bright young engineers eye.
Nortel, a.k.a. Northern Telecom, at the time,
was looking to replace the computing module
shelf of the DMS Supernode platform because
it was projected to run out of steam a few years
later. In order to address the issue, the system
architects decided that a scalable, multiprocess-
ing, shared memory computing architecture
was needed to replace it.
My job was to develop a concept to pack-
age all these cards in a shelf, and then design
a backplane to interconnect everything. It
quickly became evident that a single shared
bus could not support the bandwidth re-
quired for multiprocessing. Nor could multiple
parallel buses solve the problem, because of the
lack of high-density backplane connector tech-
nology needed for all the I/O. Even if we had Figure 1: High-level block diagram illustrating
a suitable connector, and it could magically fit the non-contact, point-to-multipoint interconnect
within the confines of the card slot, then the concept.

90 PCB Design Magazine November 2012



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berts practical design notes

non-contact interconnect: when crosstalk is your friend continues

to multipoint interconnect solution, running at line rate of 1 GB/s was achieved using simple,
1 GB/s per pair . inexpensive 2 mm connectors; the same ones
The non-contact technology actually relied chosen for compact PCI standard.
on controlled electro-magnetic coupling, or Figure 2 is a photograph of an innerlayer,
simply, crosstalk (Figure 1). In this simple high- double-sided core of the backplane, prior to
level block diagram example, each card on the lamination and drilling. It shows the couplers
shelf would transmit their data differentially in more detail. The round pads are for the con-
across the backplane. As the differential pairs nector vias, and are used to attach the coupler
traversed through the connector fields of the traces to the connector pins. Differential receiv-
card slots, the transmit signal was edge-coupled ers are connected to these pins on a plug-in
to adjacent small traces called couplers, which card. The rows of pads on the left are for one
were about three quarters of an inch long. They card slot, while the rows of pads on the right
were connected to their respective receiver pins are for another.
on the plug-in cards. After the last card slot, If we look at the two traces, entering the pic-
they switched layers and returned back to the ture from the bottom, left side, they are part of
originating plug-in card, where they were ter- a differential pair, connected to a transmitter.
minated. Each pair was routed using single-ended traces
The beauty of this architecture was that each (i.e., with no coupling to one another). As these
card only needed one transmitter to broadcast traces approach the first row of pads, they jog
its data to all the other cards. Since each card had down to ensure close coupling to the coupler
enough receivers to listen to the other cards, the traces attached to the pads. The close coupling
point-to-multipoint interconnect achieved the continues to the next set of pads, and the pat-
equivalent of a multipoint-to-multipoint archi- tern starts all over again, as the pair exits the
tecture, but without the overhead of additional picture at the bottom right (Figure 2). This pat-
pins and PCB layers. Furthermore, an effective tern repeats all the way up the photo for each
differential pair.
You may be astute
enough to notice that
the bottom coupler trace
connects to a grounded
pad at the farend, while
the mate coupler above it
does not. Obviously this
was intentional, but why
was it done? The follow-
ing explains some of the
physics behind this pat-
ented technology .
When two coplanar
parallel traces are in
close proximity to one
another, there are two
types of crosstalk gener-
ated: backward, or near-
end crosstalk (NEXT),
and forward, or far-end
crosstalk (FEXT). Gen-
erally speaking, traces
Figure 2: Photograph of an innerlayer, double-sided core of the back- routed in stripline are
plane, prior to lamination and drilling showing the routing of the couplers. only susceptible to

92 PCB Design Magazine November 2012

berts practical design notes

non-contact interconnect: when crosstalk is your friend continues

NEXT, while in microstrip, they are susceptible By leaving one far-end coupler open, and
to both. Since non-contact technology relies on shorting the other one to ground, any second-
NEXT, all routing was done in stripline. ary noise that is reflected will have the same
As the transmit signal propagates, from left phase (even-mode). When they arrive back at
to right in Figure 2, the rising and falling edges the receiver, they will cancel, thereby eliminat-
of the transmit signal initiates NEXT at the be- ing the inter-symbol interference, and increas-
ginning of the coupled length (near-end). The ing the eye amplitude, as shown in Figure 3B.
NEXT voltage saturates after a critical length You will notice that the eye waveforms do
equal to the risetime (tr) divided by twice the not resemble the traditional eye diagram we
propagation delay (2tpd), where the rise time is are used to seeing. Instead we observe a typical
in seconds, and propagation delay is in seconds NEXT eye, when the coupled length is short,
per unit length. It stays saturated for twice the compared to the bit time. There is also a line
time delay (2TD) of the coupled length. Because right in the middle.
of differential signalling, NEXT voltages have Figure 4 can help to explain the reason. The
opposite phase on the respective couplers (odd- blue waveform is the NEXT voltage, seen at the
mode). near-end of the coupler, in response to the red
At the coupler via, there is a reflection caused transmitted waveform. Notice that there are
by the impedance discontinuity of the via and only pulses at an edge transition of the trans-
connector pin. This reflection propagates to- mitted waveform. A rising edge creates a posi-
wards the far end of the coupler (left to right). tive pulse, and a falling edge generates a nega-
If both couplers at the far end are left open, any tive pulse. The duration of each pulse is twice
secondary reflections reflect back towards the the time delay of the coupler length.
receiver again in odd-mode. When both reflec- The receiver uses simple peak-detectors and
tions arrive back at the receiver, they will add latch to regenerate the signal back to the origin-
together and combine with the received signal. al waveform. A positive going pulse is detected
This causes inter-symbol interference, as seen by the positive peak-detector. When it crosses
by the shoulder on the trailing edges, on the the positive voltage threshold (+Vth), it sets the
eye waveform in Figure 3A. latch output to logic high. The output remains

Figure 3: Simulated PRBS eye diagrams at the receiver when both couplers are left open at the end
(A), vs. one coupler being shorted to ground and the other left floating (B). Reflections from the coup-
ler via cause the inter-symbol interference and reduced amplitude in (A) compared to (B). Simulated
and plotted with Agilent ADS.

November 2012 PCB Design Magazine 93

berts practical design notes

non-contact interconnect: when crosstalk is your friend continues

Figure 4: Near-end coupled waveform (blue) in response to the transmitted waveform (red) at the
coupler. The green dashed markers are the positive and negative voltage thresholds of the respective
peak detectors in the receiver. Simulated and plotted with Agilent ADS.

high until a negative pulse crosses the negative 3. Alexandre Guterman, Robert J.Zani,
threshold (-Vth), of the negative peak-detector, Point-to-Multipoint Gigabit Backplane De-
and resets the latch to logic low. sign, IEEE International Symposium on EMC,
And that is how crosstalk can be your friend! May 11-16, 2003.
Of course the small coupled crosstalk signal
means we have to guard against crosstalk from
other digital signals on board. But thats noth- Bert Simonovich is the founder
ing that mixed-signal layout design rules cant of Lamsim Enterprises Inc.,
where he continues to provide
Wait a minute! We both share the same
enemy? Who would have thought the old Prov- innovative signal integrity and
erb The enemy of my enemy is my friend backplane solutions to clients as
[sic], would apply here too? PCBDESIGN a consultant. With three pat-
ent applications and two patent grants to his
References name, he has also (co)authored several publi-
1. L. Simonovich et al, U.S. Patent 6,091,739,
cations, including an award-winning Design-
High-speed data bus utilizing point to multi-
point interconnect non-contact coupler tech- Con2009 paper related to PCB via modeling.
nology achieving a multi-point to multi-point His current research interests include signal
interconnect. integrity, high-speed characterization, and
2. J. Williamson et al, U.S. Patent 6,016,086, modeling of high-speed serial links associated
Noise cancellation modification to non-con- with backplane interconnects.
tact bus.

94 PCB Design Magazine November 2012

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Highlights Expansion
With Open House Ethologys Kent Schnepp and Amy Simpson visit with
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Sunstone Circuits celebrated the comple-
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The new building, which houses Customer
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For the estimated 80 guests on hand, Sun-
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tended, including Columbia Helicopters, IEC,
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Copious, Xenium, ethology, ServiceMaster,
Molalla Telecommunications, Arrowhead Golf
Visitors to the open house toured the manufacturing Club and law firm Tonkon Corp. rounded out
plant to see how printed circuit boards are made. the guest list.

96 PCB Design Magazine November 2012

Exclulsive Publications for
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2012 International Printed Circuit
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NCEDAR 2012: National Conference

For the IPCs Calendar of Events, click here.
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For a complete listing of events, check out December 4-5, 2012
San Jose, California, USA
PCB007 full events calendar here.

Printed Electronics USA 2012
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Defence IQs Military Radar Conference
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November 27-29, 2012

Portland Place, London, UK
Renewable Energy World Conference
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6th International Symposium
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November 2012 PCB Design Magazine 99