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TRNG AI HOC S PHAM KY THUAT TP.

HCM
KHOA IEN T
BO MON VIEN THONG

Bien soan: Nguyen nh Phu

TP.HCM 2007
TRNG AI HOC S PHAM KY THUAT TP.HCM
KHOA IEN T
BO MON VIEN THONG

Bien soan: Nguyen nh Phu

TP.HCM 2007
LI NOI AU

Cac he thong so lap trnh ngay cang hien dien trong nhieu thiet b ien t dan dung cung nh
trong cac thiet b ieu khien cong nghiep.
u iem cua thiet b so lap trnh la lam cho mach ien ngay cang nho gon do mat o tch hp
cao, khong mat nhieu thi gian cho viec ket noi va th nghiem so vi IC ri, de thay oi yeu cau ieu
khien cua mach, chiem t dien tch khong gian, toc o hay tan so lam viec cao ap ng c cac
ng dung oi hoi ve toc o hoac x ly khoi lng d lieu ln.
Noi dung cuon sach nay c bien soan gom 4 chng nham phuc vu cho mon hoc 2 tn ch,
trong o chng 1 gii thieu ve cac thiet b so lap trnh c, chng 2 trnh bay ngon ng VHDL
dung e lap trnh cho he thong so, chng 3 trnh bay cach lap trnh cho cac mach ien to hp,
chng 4 trnh bay cach lap trnh cho cac mach ien tuan t.
Noi dung trong cuon sach nham trang b cac kien thc c ban ve ky thuat PLD va ASIC cho
sinh vien nganh ien ien t.
Trong qua trnh bien soan co tham khao nhieu tai lieu nen van con sai sot nen mong s ong
gop xay dng e bai giang c hoan thien hn xin hay gi ve tac gia theo a ch
phu_nd@yahoo.com - xin chan thanh cam n.
MUC LUC
LI NOI AU
CHNG 1. GII THIEU CAC CAU TRUC LAP TRNH C
I. GII THIEU PLD 4
1. HOAT ONG CUA SPLD C BAN LA PAL 4
2. HOAT ONG CUA SPLD C BAN LA GAL 5
3. K HIEU N GIAN CHO S O CUA PAL/GAL 5
4. S O KHOI TONG QUAT CUA PAL/GAL 7
5. MACROCELL 7
6. CAC SPLD THC TE 9
7. CAC CPLD 10
II. CPLD CUA HANG ALTERA 12
1. CPLD MAX 7000 12
2. MACROCELL 13
3. KHOI M RONG CHIA SE 13
4. KHOI M RONG SONG SONG 15
5. CPLD MAX I 16
III. CPLD CUA HANG XILINX 18
1. PLA (PROGRAMMABLE LOGIC ARRAY) 18
2. COOLRUNNER I 19
IV. LOGIC LAP TRNH FPGA 22
1. CAC KHOI LOGIC CO THE NH CAU HNH CLB 23
2. CAC MODULE LOGIC 24
3. FPGA DUNG CONG NGHE SRAM 25
4. CAC LOI CUA FPGA 26
V. FPGA CUA ALTERA 27
1. KHOI MANG LOGIC (LAB: LOGIC ARRAY BLOCK) 27
2. MODULE LOGIC THCH NGHI ALM 28
3. CAC CHC NANG TCH HP 30
VI. FPGA CUA XILINX 31
1. CAC KHOI LOGIC CO THE NH CAU HNH CLB (CONFIGURABLE LOGIC BLOCK) 31
2. CHUOI LIEN TIEP SOP 32
3. CAU TRUC FPGA TRUYEN THONG VA CAU TRUC ASMBL 35
VII. PHAN MEM LAP TRNH 37
1. CACH THIET KE 39
2. MO PHONG CHC NANG 43
3. TONG HP 44
4. LIET KE LI (NETLIST) 45
5. PHAN MEM THI HANH 46
6. MO PHONG THI GIAN 47
7. LAP TRNH CHO THIET B HAY NAP CHNG TRNH CHO THIET 47
VIII. CAU HOI ON TAP VA BAI TAP 48

CHNG 2. NGON NG LAP TRNH VHDL 51


I. S RA I NGON NG VHDL 55
II. CAC THUAT NG CUA VHDL 55
III. MO TA PHAN CNG TRONG VHDL 53
1. ENTITY (THC THE ) 53
2. ARCHITECTURE 54
3. CAC THIET KE CO CAU TRUC 56
4. HOAT ONG TUAN T 57
5. LA CHON KIEN TRUC 58
6. CAC CAU LENH CAU HNH 59
7. TOM TAT 60
IV. GII THIEU VE MO HNH HANH VI 60
1. DELAY QUAN TNH VA DELAY TRUYEN 63
2. MO PHONG DELTA 65
3. DRIVER 68
4. GENERIC 69
5. CAC PHAT BIEU KHOI 71
6. TOM TAT 76
V. X LY TUAN T 76
1. PHAT BIEU 76
2. GAN BIEN KHAC VI GAN TN HIEU 78
3. CAC PHAT BIEU TUAN T 81
4. PHAT BIEU IF 81
5. PHAT BIEU CASE 82
6. PHAT BIEU LOOP 83
7. PHAT BIEU ASSERT 87
8. PHAT BIEU WAIT 88
VI. CAC KIEU OI TNG TRONG VHDL 91
1. KHAI BAO TN HIEU 91
2. KHAI BAO BIEN 92
3. KHAI BAO HANG SO 93
VII. CAC KIEU D LIEU TRONG VHDL 93
1. LOAI SCALAR 94
2. KIEU VAT LY 103
3. CAC THUOC TNH 103
VIII. CAC TOAN T C BAN TRONG VHDL 106
1. CAC TOAN T LOGIC 106
2. CAC TOAN T QUAN HE 107
3. CAC TOAN T SO HOC 108
4. CAC TOAN T CO DAU 108
5. CAC TOAN NHAN CHIA 109
6. CAC TOAN T DCH 106
7. CAC TOAN T HON HP 107
IX. CHNG TRNH CON VA GOI 107
1. CHNG TRNH CON 107
2. GOI 122
X. CAU HOI ON TAP VA BAI TAP 126

CHNG 3. THIET KE MACH TO HP BANG VHDL 129

I. GII THIEU 129

II. THIET KE MACH GIAI MA MACH MA HOA 129


1. THIET KE MACH GIAI MA 129
2. THIET KE MACH MA HOA 131
3. THIET KE MACH GIAI MA LED 7 OAN LOAI ANODE CHUNG 132
III. THIET KE MACH A HP MACH GIAI A HP 134
1. THIET KE MACH A HP 134
2. THIET KE MACH GIAI A HP 135
IV. CAU HOI ON TAP VA BAI TAP 137

CHNG 4. CAC THANH GHI BO EM TRON VHDL 119

I. GII THIEU 141

II. THIET KE CAC LOAI FLIP FLOP 141


1. THIET KE FLIP FLOP JK 141
2. THIET KE FLIP FLOP D CO ENABLE 144
III. THIET KE THANH GHI DCH N 146
1. THIET KE THANH GHI DCH 4 BIT 146
2. THIET KE THANH GHI DCH 8 BIT 148
3. THIET KE MACH EM JOHNSON 8 BIT 149
4. THIET KE MACH EM VONG 8 BIT 151
5. THIET KE MACH IEU KHIEN 8 LED SANG DAN TAT DAN 153
IV. THIET KE MACH EM 155
1. THIET KE MACH EM NH PHAN 4 BIT EM LEN 155
2. THIET KE MACH BCD EM LEN 156
3. THIET KE MACH EM BCD VA GIAI MA HIEN TH LED 7 OAN 157
4. THIET KE MACH EM BCD T 00 EN 59 HIEN TH TREN 2 LED 7 OAN 159
5. THIET KE MACH EM BCD T 000 EN 999 HIEN TH TREN 3 LED 7 OAN 161
V. CAU HOI ON TAP VA BAI TAP 163

Tai lieu tham khao. 166


Chng 1
GII THIEU CAC CAU TRUC LAP TRNH
C

GII THIEU PLD


HOAT ONG CUA SPLD C BAN LA PAL
HOAT ONG CUA SPLD C BAN LA GAL
K HIEU N GIAN CHO S O CUA PAL/GAL
S O KHOI TONG QUAT CUA PAL/GAL
MACROCELL
CAC SPLD THC TE
CAC CPLD
CPLD CUA HANG ALTERA
CPLD MAX 7000
MACROCELL
KHOI M RONG CHIA SE
KHOI M RONG SONG SONG
CPLD MAX I
CPLD CUA HANG XILINX
PLA (PROGRAMMABLE LOGIC ARRAY)
COOLRUNNER I
LOGIC LAP TRNH FPGA
CAC KHOI LOGIC CO THE NH CAU HNH CLB
CAC MODULE LOGIC
FPGA DUNG CONG NGHE SRAM
CAC LOI CUA FPGA
FPGA CUA ALTERA
KHOI MANG LOGIC (LAB: LOGIC ARRAY BLOCK)
MODULE LOGIC THCH NGHI ALM
Kieu hoat ong bnh thng
Kieu hoat ong LUT m rong
CAC CHC NANG TCH HP
FPGA CUA XILINX
CAC KHOI LOGIC CO THE NH CAU HNH CLB (CONFIGURABLE LOGIC BLOCK)
CHUOI LIEN TIEP SOP
CAU TRUC FPGA TRUYEN THONG VA CAU TRUC ASMBL
Cau truc truyen thong
Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu
Cau truc ASMBL
PHAN MEM LAP TRNH
CACH THIET KE
MO PHONG CHC NANG
TONG HP
LIET KE LI (NETLIST)
PHAN MEM THiI HANH
MO PHONG THI GIAN
LAP TRNH CHO THIET B HAY NAP CHNG TRNH CHO THIET B
CAU HOI ON TAP VA BAI TAP
CAU HOI ON TAP
Hnh 1-1. Cau truc cua PAL.
Hnh 1-2. PAL sau khi lap trnh e tao ham.
Hnh 1-3. Cau truc cua GAL.
Hnh 1-4. K hieu n gian cho PAL/GAL.
Hnh 1-5. Hnh cho v du 1-1.
Hnh 1-6. S o khoi cua PAL/GAL.
Hnh 1-7. S o mach cac Macrocell.
Hnh 1-8. S o khoi va hnh dang vo cua PAL16V8.
Hnh 1-9. S o khoi va hnh dang vo cua GAL22V10.
Hnh 1-10. S o khoi cua CPLD tong quat.
Hnh 1-11. Cau truc CPLD MAX 7000
Hnh 1-12. S o khoi mcrocell n gian cua MAX 7000.
Hnh 1-13. V du cach m rong.
Hnh 1-14. Minh hoa cho viec chia se.
Hnh 1-15. Minh hoa cho bo m rong song song.
Hnh 1-16. Minh hoa cho bo m rong song song t macrocell khac.
Hnh 1-17. S o khoi cua MAX II.
Hnh 1-18. Phan biet 2 kieu xay dng ham.
Hnh 1-19. Phan biet 2 kieu ket noi.
Hnh 1-20. So sanh PAL vi PLA.
Hnh 1-21. S o cau truc cua Coolrunner II.
Hnh 1-22. Cau truc cua mot khoi chc nang FB.
Hnh 1-23. Minh hoa cho v du 1-2.
Hnh 1-24. Cau truc c ban cua FPGA.
Hnh 1-25. Cac khoi CLB cua FPGA.
Hnh 1-26. S o khoi c ban cua 1 module logic trong FPGA.
Hnh 1-27. Khai niem c ban cua LUT c lap trnh e tao SOP ngo ra .
Hnh 1-28. Minh hoa cho v du 1-3.
Hnh 1-29. Khai niem ve FPGA bay hi.
Hnh 1-30. Khai niem chc nang loi phan cng trong FPGA.
Hnh 1-31. S o khoi cua cau truc LAB cua Stratix II va ALM
Hnh 1-32. S o khoi ALM cua Stratix II.
Hnh 1-33. Cac cau hnh co the co cua LUT trong ALM kieu bnh thng.
Hnh 1-34. M rong ALM e tao ra ham SOP 7 bien trong kieu LUT m rong.
Hnh 1-35. Minh hoa cho v du 1-4.
Hnh 1-36. S o khoi cua FPGA Stratic II.
2 Ky thuat PLD va ASIC
Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu
Hnh 1-37. Minh hoa cac cap logic nh cau hnh t te bao logic cho en CLB.
Hnh 1-38. V du cach dung chuoi noi tiep e m rong bieu thc SOP.
Hnh 1-39. Minh hoa cho v du 1-5.
Hnh 1-40. Tch hp nhieu chc nang IP ket qua lam giam CLB va/hoac phai tang kch thc
chip.
Hnh 1-41. Minh hoa cau truc ASMBL cua FPGA platform.
Hnh 1-42. S o dong thiet ke tong quat e lap trnh cho SPLD, CPLD hoac FPGA.
Hnh 1-43. Cac thiet b c ban e lap trnh cho SPLD, CPLD hoac FPGA.
Hnh 1-44. Minh hoa cho 2 kieu lap trnh.
Hnh 1-45. Minh hoa cho kieu lap trnh tng oan.
Hnh 1-46. Lu thanh khoi logic 3.
Hnh 1-47. Man hnh soan thao dang song tong quat .
Hnh 1-48. Thiet lap cac dang song ngo vao.
Hnh 1-49. Dang song ngo vao va ra khi chay mo phong.
Hnh 1-50. Minh hoa cho chc nang tong hp.
Hnh 1-51. S o mach va danh sach liet ke.
Hnh 1-52. Minh hoa cho mo phong thi gian.
Hnh 1-53. Download thiet ke vao thiet b lap trnh.

Ky thuat PLD va ASIC 3


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu

I. GII THIEU PLD:


Hai thanh phan chnh cua thiet b logic lap trnh n gian SPLD (Simple Programmable
Logic Device) la PAL va GAL. PAL tng trng cho logic mang lap trnh (Programmable
Array Logic) va GAL tng trng cho logic mang tong quat (Generic Array Logic). Thng
th PAL ch lap trnh 1 lan con GAL th cho phep lap trnh lai, tuy nhien co nhieu loai SPLD lap
trnh lai van con c goi la PAL.
Thuat ng GAL la ten do hang Lattice Semeconductor at va sau o th c cap phep cho
cac nha san xuat khac.
Cau truc c ban cua PAL va GAL la mang AND cho phep lap trnh va mang OR co nh to
chc theo phng phap tong cua cac tch SOP (Sum-Of-Product). Vi CPLD (Complex
Programmable Logic Device) c tch hp t nhieu SPLD e co chc nang manh hn cho cac
thiet ke phc tap.
Trong phan nay chung ta se khao sat hoat ong cua SPLD, phng phap tong cua cac tch
c dung trong PAL va GAL, giai thch c s o logic cua PAL/GAL, mo ta macrocell c
ban cua PAL/GAL, khao sat PAL16V8 va GAL22V10, mo ta CPLD c ban.
1. HOAT ONG CUA SPLD C BAN LA PAL
PAL cha mang cong AND lap trnh va c noi vi mang cong OR co nh. Thng th
PAL dung cong nghe x ly cau ch nen ch cho phep lap trnh 1 lan OTP (One-time-
Programmable).
Cau truc PAL cho phep thc hien tat ca cac ham tong cua cac tch vi cac bien a c
xac nh. Cau truc cua mot PAL n gian c trnh bay nh hnh 1-1 cho 2 bien ngo vao va 1
bien ngo ra:

Hnh 1-1. Cau truc cua PAL.


Mot mang lap trnh la mot ma tran cac day dan gom cac hang va cac cot va chung co the
lap trnh e noi vi nhau tai iem giao nhau. Moi iem noi lap trnh co cau tao la cau ch oi
vi loai PAL va c goi la mot te bao cell. Moi hang co the noi vi mot ngo vao cua cong
AND va moi cot la mot bien ngo vao hoac bien phu nh. Bang cach lap trnh gi nguyen cau
ch hay pha hong cau ch th co the tao ra bat ky ham to hp nao t cac bien ngo vao e a

4 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu
en cong AND tao ra cac thanh phan tch mong muon. Cac cong AND c ket noi vi cong
OR e tao nen cac ham ngo ra tong cua cac tch.

V du 1: Mot PAL c lap trnh nh hnh 1-2 e tao ra thanh phan AB , AB va AB .


Trong hnh 1-2 ta co the nhn thay mot so cau ch b pha hong va mot so cau ch con nguyen e
ket noi cac bien ngo vao vi cac ngo vao cua cac cong AND tao ra ham tch theo yeu cau va
sau cung la ham tong cua cac tch:
X = AB + AB + AB

Hnh 1-2. PAL sau khi lap trnh e tao ham.


2. HOAT ONG CUA SPLD C BAN LA GAL
GAL ve c ban chnh la PAL co the lap trnh c, GAL co to chc AND/OR giong nh
PAL nhng s khac nhau c ban la GAL dung cong nghe x ly cho phep lap trnh lai giong nh
EEPROM thay cho cau ch c trnh bay nh hnh 1-3.

Hnh 1-3. Cau truc cua GAL.


3. K HIEU N GIAN CHO S O CUA PAL/GAL

Ky thuat PLD va ASIC 5


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu
Cac thiet b lap trnh PAL va GAL co cac cong logic AND va OR va them mot so phan t
khac cung vi cac bien ngo vao va cac bien phu nh. Hau het cac PAL va GAL eu co s o k
hieu n gian nh hnh 1-4:

Hnh 1-4. K hieu n gian cho PAL/GAL.


Cac bien ngo vao cua PAL hoac GAL thng co mach em e ngan chan qua tai khi co
qua nhieu cong AND noi ti ngo vao o. Trong s o, khoi em la khoi tam giac va em tn
hieu ngo vao va ao tn hieu e tao ra bien phu nh cua tn hieu o.
PAL va GAL eu co mot lng rat ln cac ng lap trnh ket noi ben trong va moi cong
AND co nhieu ngo vao. Thng th trong s o mach cua PAL va GAL thay cong AND nhieu
ngo vao bang cong AND ch co mot ng ngo vao cho gon nhng tren o co ghi so lng ngo
vao thc cho cong AND o. Trong hnh 1-4 th moi cong AND eu co 2 ngo vao.
iem noi lap trnh nam trong ma tran c xac nh bang dau nam tren cac ng giao
nhau va cau ch se c gi nguyen, con cac iem khong co anh dau th cau ch se b pha
hong. Hnh 1-4 cua v du tren c lap trnh e tao ra ham X = AB + AB + AB .

V du 1-2: Hay ve s o mach cho mot PAL a lap trnh e tao ra ham co 3 bien ngo vao
nh sau: X = A BC + ABC + A B + AC
Giai: S o mach cua PAL nh hnh 1-5:

6 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu

Hnh 1-5. Hnh cho v du 1-1.


4. S O KHOI TONG QUAT CUA PAL/GAL
S o khoi cua PAL hoac GAL c trnh bay hnh 1-6. Nen nh rang s khac nhau c
ban la GAL co mang cho phep lap trnh lai con PAL th ch lap trnh mot lan. Cac ngo ra cua
mang cong AND lap trnh c a en cac cong OR co nh a c ket noi e tao cac ham
logic ngo ra. Cong OR ket hp vi ham logic ngo ra thng c goi la macrocell.

Hnh 1-6. S o khoi cua PAL/GAL.


5. MACROCELL
Mot macrocell gom mot cong OR va cac ham logic ngo ra ket hp. Mc o phc tap cua
macrocell tuy thuoc vao thiet b cu the PAL hoac GAL. Mot macrocell co the c nh cau
hnh cho mot ham to hp, ham thanh ghi hoac cho ca hai.

Ky thuat PLD va ASIC 7


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu
Ham thanh ghi co lien quan en flip flop chnh v the trong macrocell cung co flip flop e
tao ra cac ham tuan t.
Hnh 1-7 trnh bay 3 loai macrocell c ban vi cac ham to hp.

(a)

(b)

(c)
Hnh 1-7. S o mach cac Macrocell.
Hnh 1-7a trnh bay mot macrocell n gian vi mot cong OR va mot cong ao ba trang
thai. Ngo ra cua cong ao ba trang thai co the hoat ong tao ra mc HIGH, mc LOW va trang
thai tong tr cao xem nh h mach.
Hnh 1-7b trnh bay mot macrocell co the hoat ong nh ngo vao hoac ngo ra. Khi ngo vao
c dung nh ngo ra th cong ao phai trang thai tong tr cao e h mach va tn hieu t ben
ngoai a en bo em va ket noi vi mang cong AND ben trong.
Hnh 1-7c trnh bay mot macrocell co the lap trnh e co ngo ra tch cc mc HIGH hoac
mc tch cc mc LOW va cung co the s dung nh ngo vao. Mot ngo vao cua cong XOR (ex-
or) co the c lap trnh mc HIGH hoac mc LOW. Khi lap trnh ngo vao cong XOR mc
HIGH th tn hieu ngo ra cua cong OR se b ao v : 0 1 = 1 va 1 1 = 0 . Tng t khi lap trnh

8 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu
ngo vao cong XOR mc LOW th tn hieu ngo ra cong OR khong b ao v: 0 0 = 0 va
1 0 = 1.
6. CAC SPLD THC TE
Thng th hnh dang vo cua SPLD co cau hnh chan nam trong khoang t 20 en 28 chan.
Co 2 thanh phan giup chung ta xac nh PAL hoac GAL mot cach thch hp cho cac thiet ke
logic a cho la so lng ngo vao va ngo ra cung vi so lng cong logic. Mot vai thong so khac
can phai xem xet la tan so hoat ong cc ai, thi gian tre va nguon ien ap cung cap.
Cac nha san xuat Lattice, Actel, Atmel va Cypress la cac cong ty san xuat SPLD.
Cac loai PAL va GAL thng s dung la PAL16V8 va GAL22V10. Cac ma so cho biet so
lng ngo vao, so lng ngo ra va loai ngo ra logic. V du: PAL16V8 se cho biet thiet b nay co
16 ngo vao, 8 ngo ra va ngo ra la bien (V: variable). Ch H hoac ch L co ngha la ngo ra tch
cc mc HIGH hoac mc LOW tng ng. S o khoi cua PAL16V8 va hnh dang vo c trnh
bay hnh 1-8.

Hnh 1-8. S o khoi va hnh dang vo cua PAL16V8.


Moi macrocell co 8 ngo vao lay t mang cong AND nen co the co ti 8 thanh phan tch
cho moi ngo ra. Co 10 ngo vao k hieu la I, 2 ngo ra k hieu la O va 6 chan co the c dung
Ky thuat PLD va ASIC 9
Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu
nh la ngo vao hoac ngo ra va k hieu la I/O. Moi ngo ra tch cc mc LOW. PAL16V8 co mat
o tch hp khoang 300 cong.
S o khoi cua GAL 22V10 va hnh dang vo nh hnh 1-9. GAL nay co 12 ngo vao va 10
chan co the s dung nh ngo vao hoac ngo ra. Cac macrocell co cac ngo vao ket noi vi mang
cong AND co the thay oi so lng ket noi t 8 en 16. GAL 22V10 co mat o tch hp khoang
500 cong.

Hnh 1-9. S o khoi va hnh dang vo cua GAL22V10.


7. CAC CPLD
Mot CPLD cha nhieu mang SPLD vi ket noi ben trong cho phep lap trnh nh hnh 1-10.

10 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu
Chung ta xem moi mang SPLD trong CPLD la mot khoi mang logic LAB (Logic Array
Block). Mot ten khac oi khi cung c dung la khoi chc nang, khoi logic hoac khoi tong
quat.
Cac ket noi lap trnh ben trong thng c goi la PIA (Programmable Interconnect
Array) nhng mot so nha che tao nh Xilinx dung thuat ng AIM (Advance Interconnect
Matrix) hoac cac thuat ng tng t.
Cac LAB va cac ket noi ben trong c lap trnh bang phan mem. Mot CPLD co the c
lap trnh cho cac chc nang phc tap da vao cau truc tong cua cac tch cho moi LAB oc lap
hay chnh xac hn la moi SPLD. Cac ngo vao co the ket noi ti bat ky khoi LAB nao va cac
ngo ra cung co the ket noi ti bat ky LAB nao thong qua PIA.

Hnh 1-10. S o khoi cua CPLD tong quat.


Hau het cac nha che tao ra mot chuoi CPLD c sap xep theo mat o tch hp, cong
nghe x ly, cong suat tieu thu, nguon cung cap va toc o. Cac nha che tao thng cung cap mat
o CPLD theo cac thanh phan macrocell hoac LAB. Mat o tch hp co the sap xep t 10
macrocell en 2000 macrocell trong mot vo co the len en vai tram chan.
PLD cang phc tap th mat o tch hp cang cao. Mot vai CPLD co the lap trnh lai va
dung cong nghe x ly EEPROM hoac SRAM cho cac iem ket noi lap trnh. Cong suat tieu tan
co the nam trong khoang t vai mili watt en vai tram mili watt. Nguon cung cap DC thng th
nam trong khoang t 2,5V en 5V tuy thuoc vao cac ch nh cua thiet b. Co nhieu nha san
xuat CPLD nh Altera, Xilinx, Lattice va Cypress.
Trong phan tiep theo chung ta se khao sat cac CPLD cua hai nha san xuat la Altera va
Xilinx bi v hai cong ty nay ang chiem lnh th trng. Cac nha che tao khac th cung san xuat
thiet b va phan mem tng t.

Ky thuat PLD va ASIC 11


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu
II. CPLD CUA HANG ALTERA
Altera san xuat ra nhieu ho CPLD nh MAX II, MAX 3000 va MAX 7000. Trong phan
nay ch trnh bay chu yeu ho MAX 7000.
Sau khi hoan tat phan nay th ban co the: mo ta c ho CPLD MAX, thao luan ve cau
truc cua CPLD MAX 7000 va CPLS MAX II, giai thch cach tao cac thanh phan tch c tao ra
trong CPLD.
1. CPLD MAX 7000
Cau truc cua CPLD la cach thc ma cac thanh phan ben trong c to chc va c sap
xep. Cau truc cua ho CPLD MAX 7000 th giong nh s o khoi cua CLPD tong quat c trnh
bay hnh 1-11.

Hnh 1-11. Cau truc CPLD MAX 7000.


CPLD MAX 7000 co cau truc lp PAL/GAL e tao ra cac ham SOP. Mat o nam trong
khoang t 2 LAB en 16 LAB tuy thuoc vao CPLD cu the. Nen nh la mot LAB tng ng
vi mot SPLD dung cong nghe x ly EEPROM. Kieu lap trnh trong he thong ISP (In-System
Programmable) dung giao tiep chuan JTAG.
Hnh 1-11 trnh bay s o khoi tong quat CPLD ho MAX 7000 cua Altera. Bon khoi LAB
c trnh bay nhng so lng co the len en 16 khoi LAB. Moi khoi LAB co 16 macrocell,

12 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu
nhieu khoi LAB c ket noi vi nhau thong qua PIA, PIA la cau truc bus lap trnh toan cuc
(cho tat ca cac LAB) bao gom cac ngo vao co cung chc nang, I/O va cac macrocell.
2. MACROCELL
S o khoi macrocell n gian cua ho MAX 7000 c trnh bay trong hnh 1-12.
Macrocell cha mot mang cong AND lap trnh gom 5 cong AND, mot cong OR, mot ma tran la
chon thanh phan tch e ket noi cac ngo ra cua cong AND vi cong OR, va logic ket hp e co
the lap trnh cho ngo vao, ngo ra logic tong hp hoac ngo ra thanh ghi dch.

Hnh 1-12. S o khoi macrocell n gian cua MAX 7000.


Mac du van dung cung mot khai niem nhng macrocell nay khac vi macrocell a trnh
bay phan SPLD bi v no co mang cong AND lap trnh va ma tran la chon thanh phan tch.
Trong hnh 1-12 co 5 cong AND tao ra cac thanh phan tch t PIA vao ma tran la chon thanh
phan tch. Thanh phan tch t cong AND nam di cung co the c hoi tiep tr lai ma tran lap
trnh xem nh phan m rong chia se e s dung bi cac macrocell khac.
Cac ngo vao m rong song song cho phep mn cac thanh phan tch khong dung t cac
macrocell khac e m rong bieu thc SOP. Ma tran la chon thanh phan tch la mot ma tran cua
cac ket noi lap trnh c dung e ket noi cac ngo ra a la chon t mang cong AND va t ngo
vao m rong en cong OR.
3. KHOI M RONG CHIA SE
Bu cua thanh phan tch c dung e tang so lng thanh phan tch trong bieu thc SOP
th co the dung c cho moi macrocell trong LAB. Hnh 1-13 minh hoa cach thc thanh phan
m chia se t macrocell khac co the c dung e thiet lap them cac thanh phan tch.
Trong trng hp nay mot trong 5 cong AND trong 1 mang macrocell b gii han, ch co 4
ngo vao va do o co the tao ra 1 thanh phan tch co 4 bien khac nhau c minh hoa trong hnh
(a). Hnh (b) trnh bay phan m rong cho 2 thanh phan tch.

Ky thuat PLD va ASIC 13


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu

a. Cong AND 4 ngo vao tao ra b. Cong AND c m rong e


thanh phan tch 4 bien. tao ra 2 thanh phan tch.

Hnh 1-13. V du cach m rong.


Moi macrocell cua MAX 7000 co the tao ra 5 thanh phan tch t mang cong AND. Neu 1
macrocell can nhieu hn 5 thanh phan tch cho ham ngo ra SOP th no phai dung them thanh
phan m rong t macrocell khac. Gia s thiet ke can bieu thc SOP cha 6 thanh phan tch.
Hnh 1-14 trnh bay cach thanh phan tch t macrocell khac co the c dung e tang bieu thc
SOP ngo ra.

Hnh 1-14. Minh hoa cho viec chia se.


14 Ky thuat PLD va ASIC
Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu
Macrocell th 2 tao ra thanh phan m rong chia se ( E + F ) c noi en cong AND th 5
trong macrocell th 1 e tao ra bieu thc SOP vi 6 thanh phan tch. Cac dau ket noi c tao
ra trong phan cng t chng trnh thiet ke va phan mem bien dch roi nap vao chip.
4. KHOI M RONG SONG SONG
Mot phng phap khac e tang so lng cac thanh phan tch cho mot macrocell bang cach
dung bo m rong song song trong no cac thanh phan tch m rong c OR vi cac thanh
phan c tao ra macrocell thay v dung ket hp trong ma tran AND nh bo m rong chia se.
Mot macrocell a cho co the mn cac thanh phan tch khong dung t cac macrocell lan can (co
the len en 5 thanh phan t cac macrocell khac oi vi MAX 7000). Khai niem nay c minh
hoa nh hnh 1-15 trong o mach ien n gian c tao ra t 2 thanh phan tch mn them 3
thanh phan tch m rong.

Hnh 1-15. Minh hoa cho bo m rong song song.

Ky thuat PLD va ASIC 15


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu

Hnh 1-16. Minh hoa cho bo m rong song song t macrocell khac.
Hnh 1-16 trnh bay cach mot macrocell co the mn cac thanh phan m rong song song t
macrocell khac e tang bieu thc ngo ra SOP. Macrocell th 2 dung 3 thanh phan tch t
macrocell th 1 e tao ra bieu thc SOP gom 8 thanh phan.
5. CPLD MAX I
Cau truc cua CPLD MAX II khac vi hoc MAX 7000 va c Altera goi la CPLD Post-
macrocell. Nh a trnh bay trong s o khoi hnh 1-17, thiet b nay cha cac khoi LAB cung
vi nhieu thanh phan logic LE (Logic Elements). Mot LE la mot n v thiet ke logic c ban va
tng t nh macrocell. Ket noi ben trong co the lap trnh c sap xep theo hang va cot chay
gia cac LAB va cac phan t ngo vao/ngo ra (IOE: Input/Output Elements) c nh hng
xung quanh. Cau truc cua ho CPLD nay giong nh FPGA co the xem MAX II la FPGA co mat
o thap.
S khac nhau gia CPLD MAX II va cac CPLD thiet ke t SPLD la cach xay dng mot
ham logic. CPLD MAX II s dung cac bang tra LUT (Look-Up Tables) thay cho ma tran
AND/OR. Mot LUT ve c ban la loai bo nh co the lap trnh e tao ra cac ham SOP. Hai
phng phap nay c minh hoa nh hnh 1-18.

16 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu

Hnh 1-17. S o khoi cua MAX II.

Loai dung LUT. Loai dung logic mang AND/OR

Hnh 1-18. Phan biet 2 kieu xay dng ham.

Ky thuat PLD va ASIC 17


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu
Nh a e cap CPLD MAX II co cach sap xep hang/cot cua cac ket noi ben trong thay
cho cach ket noi ben trong theo loai kenh co trong hau het cac CPLD. Co 2 phng phap c
minh hoa trong hnh 1-19.

Ket noi ben trong dung hang/cot Ket noi theo kieu kenh
Hnh 1-19. Phan biet 2 kieu ket noi.
Hau het cac CPLD dung cong nghe x ly khong bay hi cho cac iem noi lap trnh. Tuy
nhien MAX II dung cong nghe x ly nh SRAM nen chung co the bay hi tat ca cac logic a
lap trnh se mat het khi mat ien. Bo nh c gan vao ben trong chip e lu tr d lieu chng
trnh dung cong nghe bo nh khong bay hi va se nh cau hnh lai cho CPLD khi co ien.
III. CPLD CUA HANG XILINX:
Cung giong nh Altera, Xilinx san xuat ra cac ho CPLD c sap xep theo mat o tch
hp, cong nghe x ly, ien ap nguon cung cap va toc o. Xilinx che tao ra nhieu ho CPLD nh
Cool Runner II, Cool Runner XPLA3 va XC9500. Ho XC9500 th co cau truc giong nh ho
CPLD MAX 7000 cua Altera s dung cau truc loai PAL/GAL. Trong phan nay chung ta ch
phan tch Cool Runner II.
Sau khi ket thuc phan nay ban co the: mo ta PLA va so sanh vi PAL, thao luan ve cau
truc CPLD Cool Runner II va mo ta cac khoi chc nang.
1. PLA (PROGRAMMABLE LOGIC ARRAY)
Nh a trnh bay, cau truc cua CPLD la cach ma cac thanh phan ben trong c to chc
va sap xep. Cau truc cua ho Cool Runner II cua Xilinx th da vao cau truc mang logic lap trnh
PLA (Programmable Logic Array) tot hn cau truc PAL (Programmable Array Logic). Hnh 1-
20 so sanh cau truc PAL vi cau truc PLA n gian.

18 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu

Hnh 1-20. So sanh PAL vi PLA.


Nh a trnh bay, PAL co mang cong AND lap trnh va theo sau la mang cong OR co nh
e tao ra cac bieu thc SOP nh hnh 1-20a. PLA co mang cong AND lap trnh va theo sau la
mang cong OR lap trnh nh hnh 1-20b.
2. COOLRUNNER I
CPLD Cool Runner II dung loai cau truc PLA. Cool Runner II co nhieu khoi chc nang FB
(Function Block) tng t nh LAB trong CPLD MAX 7000 cua Altera. Moi khoi chc nang FB
cha 16 macrocell. Cac khoi chc nang c ket noi ben trong bi mot ma tran ket noi ben
trong cai tien AIM tng t nh PIA trong MAX 7000. S o cau truc c ban cho Cool Runner II
c trnh bay hnh 1-21.

Ky thuat PLD va ASIC 19


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu

Hnh 1-21. S o cau truc cua Cool runner II.


S o khoi CPLD cua Xilinx va cua Altera gan nh la giong nhau tuy nhien ben trong th
khac nhau.
CPLD ho Cool Runner II cha t 32 macrocell en 512 macrocell. Do co 16 macrocell cho
moi khoi chc nang, so lng khoi chc nang nam trong khoang t 2 en 32. S o khoi cua
mot khoi chc nang FB c trnh bay nh hnh 1-22.

20 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu

Hnh 1-22. Cau truc cua mot khoi chc nang FB.
Mang cong AND co 56 cong AND va mang cong OR lap trnh co 16 cong OR. Vi cau
truc PLA th bat ky thanh phan tch nao cung co the noi ti cong OR e tao nen bieu thc SOP
cho ngo ra. Vi kha nang cc ai moi khoi chc nang co the tao ra 16 ngo ra va moi ngo ra co
bieu thc SOP cha 56 thanh phan tch.
V du 1-2: Hay lap trnh ket noi ben trong khoi FB cua hnh 1-22 e tao ra ham chc nang
SOP t macrocell th 1 la: ABCD + A BC D + ABC D va ham cho macrocell th 2 la:
ABC D + ABCD + A BCD + ABC D
Giai: ket qua nh hnh 1-23:

Ky thuat PLD va ASIC 21


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu

Hnh 1-23. Minh hoa cho v du 1-2.

IV. LOGIC LAP TRNH FPGA


Nh a trnh bay tren, cau truc phan loai CPLD bao gom cac khoi logic loai PAL/GAL
hoac PLA vi cac ket noi ben trong co the lap trnh. Ve c ban FPGA (Field Programmable
Gate Array) co cau truc khac khong dung mang loai PAL/PLA co mat o tch hp cao hn
nhieu so vi CPLD. Cac phan t dung e tao ra cac ham logic trong FPGA thng th nho hn
nhieu so vi cac thanh phan trong CPLD. Tng t trong FPGA th cac ket noi ben trong c
to chc theo hang va cot.
Sau khi ket thuc phan nay ban co the: mo ta cau truc c ban cua FPGA, so sanh FPGA vi
CPLD, thao luan ve LUT, thao luan ve FPGA dung cau truc SRAM va nh ngha loi cua
FPGA.
Co 3 thanh phan c ban trong FPGA la khoi logic co the nh cau hnh logic CLB
(Configurable Logic Block), cac ket noi ben trong va cac khoi ngo vao/ra c minh hoa nh
hnh 1-24.

22 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu

Hnh 1-24. Cau truc c ban cua FPGA.


Cac khoi co the nh cau hnh logic CLB trong FPGA th khong phc tap bang cac khoi
LAB hoac FB trong CPLD nhng thng th co nhieu thanh phan hn. Khi CLB kha n gian th
cau truc FPGA c goi la fine grained. Cac khoi IO nam xung quanh cua cau truc tao ra s
truy xuat ngo vao, ngo ra hoac ca hai chieu co the la chon mot cach oc lap en the gii ben
ngoai.
Ma tran phan loai cua cac ket noi ben trong co the lap trnh tao ra cac ket noi ben trong
cua CLB va ket noi en cac ngo vao va cac ngo ra. Cac FPGA ln co the co 10000 CLB va co
them bo nh va cac nguon tai nguyen khac.
Hau het cac nha che tao cac thiet b logic lap trnh thng sap xep thanh chuoi FPGA
phan loai theo mat o, cong suat tieu tan, ien ap nguon cung cap, toc o va mot vai mc o
khac nhau ve cau truc. FPGA la thiet b co the lap trnh lai va s dung cong nghe x ly SRAM
hoac ban cau ch e lap trnh cho cac iem noi. Mat o co the nam trong khoang t vai tram
module logic en sap x khoang 180000 module logic trong 1 vo vi so lng chan len en
1000. Nguon cung cap DC thng nam trong khoang 1,2V en 2,5V tuy thuoc vao loai chip.
1. CAC KHOI LOGIC CO THE NH CAU HNH CLB
Thng th khoi logic cua FPGA cha mot vai module logic kha nho tng t nh
macrocell trong CPLD. Hnh 1-25 trnh bay cac khoi CLB c ban nam trong cac ket noi ben
trong co the lap trnh hang/cot toan cuc c dung e ket noi cac khoi logic. Moi CLB c
Ky thuat PLD va ASIC 23
Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu
thiet lap t nhieu module logic nho hn va cac ket noi ben trong co the lap trnh cuc bo c
dung e ket noi cac module logic vi CLB.

Hnh 1-25. Cac khoi CLB cua FPGA.


2. CAC MODULE LOGIC
Mot module logic trong mot khoi logic cua FPGA co the c nh cau hnh cho ham logic
to hp, ham logic thanh ghi hoac cho ca 2. Flip flop la thanh phan logic ket hp va c dung
cho cac ham logic thanh ghi. S o khoi cua module logic tieu bieu dung cau truc LUT c
trnh bay nh hnh 1-26.

Hnh 1-26. S o khoi c ban cua 1 module logic trong FPGA.


Thng th to chc cua mot LUT bao gom mot so cac o nh bang vi 2 n , trong o n la so
lng cac bien ngo vao. V du: 3 ngo vao co the la chon en 8 o nh, do o LUT vi bien ngo
vao co the tao ra bieu thc SOP len en 8 thanh phan tch. Mot mo hnh mau cua 1 va 0 co the
c lap trnh vao trong cac o nh cua LUT c minh hoa nh hnh 1-27 e tao ra ham SOP
theo ch nh. Cac o nh cha so 1 co ngha la thanh phan tch c ket hp trong bieu thc
SOP cua ngo ra va o nh cha so 0 co ngha la thanh phan tch ket hp khong xuat hien trong
bieu thc SOP cua ngo ra.

24 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu
Ket qua bieu thc SOP ngo ra la A2 A1 A0 + A2 A1 A0 + A2 A1 A0 + A2 A1 A0

Hnh 1-27. Khai niem c ban cua LUT c lap trnh e tao SOP ngo ra.
V du 1-3: Hay thiet lap LUT co 3 bien c ban c lap trnh e tao ra bieu thc SOP theo
sau: A2 A1 A0 + A2 A1 A0 + A2 A1 A0 + A2 A1 A0 + A2 A1 A0

Giai: ket qua nh hnh 1-28:

Hnh 1-28. Minh hoa cho v du 1-3.


3. FPGA DUNG CONG NGHE SRAM
Cac FPGA cung co the la khong bay hi neu dung cong nghe ban cau ch hoac co the bay
hn neu dung cong nghe SRAM. Khai niem bay hi co ngha la tat ca cac d lieu a lap trnh
Ky thuat PLD va ASIC 25
Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu
vao trong cac khoi CLB se b mat het khi mat ien. Do o, cac FPGA dung cong nghe SRAM
cha ca bo nh khong bay hi tch hp ben trong chip e lu tr chng trnh va d lieu va nh
cau hnh lai cho thiet b moi khi co ien tr lai hoac chung dung bo nh ben ngoai vi viec
chuyen d lieu c ieu khien vi x ly chu. Khai niem bo nh tch hp trong chip c minh
hoa nh hnh 1-29a va khai niem nh cau hnh lai dung vi x ly c trnh bay nh hnh 1-29b.

a. FPGA bay hi nh lai cau hnh dung bo nh khong bay hi ben trong.

b. FPGA bay hi nh lai cau hnh dung bo nh khong bay hi va vi x ly.


Hnh 1-29. Khai niem ve FPGA bay hi.
4. CAC LOI CUA FPGA
Cac FPGA ve c ban giong nh cac phien trang ma ngi dung co the lap trnh cho cac
thiet ke logic. Cac FPGA tien li khi ma no cha cac mach logic loi phan cng (hard core).
Mot mach logic loi phan cng la mot phan logic trong FPGA c at vao ben trong bi nha
che tao e cung cap cac chc nang at biet va khong the lap trnh lai. V du neu khach hang
can mot vi x ly nho nh la mot phan cua thiet ke he thong th no co the c lap trnh vao
trong FPGA cho khach hang hoac no co the c cung cap nh la mot loi phan cng bi nha
che tao. Neu chc nang c tch hp vao ben trong co vai cau truc co the lap trnh c th no
c xem nh la chc nang loi mem (soft core).
u iem cua phng phap dung loi phan cng la cung mot thiet ke co the thc hien ay
u dung kha nang cua FPGA t hn neu so vi cach ngi dung s dung cach lap trnh, ket qua
la khong gian tren chip nho hn va thi gian thiet ke ngan hn.
26 Ky thuat PLD va ASIC
Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu
Khuyet iem cua phng phap dung loi phan cng la cac thong so ky thuat la co nh
trong qua trnh che tao va khach hang phai co kha nang dung c chc nang o. No khong the
thay oi ve sau.
Cac loi phan cng thng co tac dung cho cac chc nang ma chung c s dung pho bien
trong cac he thong so nh vi x ly, giao tiep ngo vao/ngo ra va x ly tn hieu so (Digital Signal
Processor). Co nhieu chc nang loi phan cng co the lap trnh trong FPGA. Hnh 1-30 minh hoa
cho khai niem loi phan cng c bao quanh bi CLB c lap trnh bi ngi s dung.

Hnh 1-30. Khai niem chc nang loi phan cng trong FPGA.
Viec thiet ke cac loi phan cng thng c xay dng bi nha che tao FPGA va chung
thuoc s hu cua nha che tao. Cac thiet ke rieng bi nha che tao c at ten la Intellectual
Property (IP) s hu tr tue. Mot cong ty thng liet cac loai s hu tr tue ma chung co hieu
lc tren cac website. Nhieu s hu tr tue la s ket hp cua loi phan cng va loi phan mem. Vi
x ly la mot v du minh hoa co vai tnh nang mem deo trong la chon va ieu chnh mot vai
thong so bi ngi dung.
Cac FPGA cha cac vi x ly tch hp mot trong hai hoac ca hai loi phan cng va loi phan
mem va nhieu chc nang khac th c at ten la Platform FPGA bi v chung co the c
dung e ieu khien mot he thong ay u ma khong can them mot thiet b ho tr nao.
V. FPGA CUA ALTERA
Altera san xuat ra nhieu ho FPGA bao gom Stratix II, Stratix , Cyclone va ACEX. Trong
phan nay chung ta ch khao sat ho Stratix II e minh hoa cho cac khai niem.
Sau khi ket thuc phan nay chung ta co the:
Thao luan ve cau truc c ban cua FPGA ho Stratix II, giai thch cach thanh phan c tao
ra trong FPGA, thao luan ve cac chc nang c tch hp.
1. KHOI MANG LOGIC (LAB LOGIC ARRAY BLOCK)
S o khoi cua FPGA tong quat a c trnh bay nh hnh 1-24; cau truc cua Stratix II
va cac ho Altera khac th giong nhau. Chung eu co cau truc loai LUT cho cac module logic
c goi la module logic thch nghi ALM (Adaptive Logic Module) c trnh bay trong thiet
b tong quat LAB. Mat o c phan loai t 2000 LAB cho en 22000 LAB tuy thuoc vao cac
ho cu the va moi LAB co 8 ALM. Kch thc vo thay oi t 314 chan en 1173 chan. Thiet b

Ky thuat PLD va ASIC 27


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu
yeu cau s dung nguon DC cung cap t 1,2V; 1,5V va 2,5V. Ho FPGA Stratix II s dung cong
nghe cua SRAM.
Hnh 1-31 trnh bay s o khoi cua cau truc LAB cua Stratix II. Moi LAB cha 8 ALM,
cac LAB c lien ket vi nhau thong qua cac ket noi hang va cot ben trong. Cac iem ket noi
cuc bo ben trong lien ket cac ALM vi moi LAB.

Hnh 1-31. S o khoi cua cau truc LAB cua Stratix II va ALM
2. MODULE LOGIC THCH NGHI ALM
ALM la n v thiet ke c ban trong FPGA Stratix II. Moi ALM cha mot phan to hp
logic dung cau truc LUT va mach logic ket hp co the c lap trnh cho 2 ngo ra logic to hp
hoac hai ngo ra thanh ghi dch. Ben canh o, ALM co mach cong logic, cac flip flop va cac
mach logic khac cho phep thc hien chc nang tnh toan so hoc, chc nang em va thanh ghi
dch. S o khoi ALM cua Stratix II c trnh bay nh hnh 1-32.
Hoat ong cua ALM:
Mot ALM co the c lap trnh cho ra nhieu kieu hoat ong nh sau:
Kieu hoat ong bnh thng.
Kieu hoat ong LUT m rong.
Kieu tnh toan so hoc.
Kieu tnh toan so hoc dung chung.
Ngoai 4 kieu hoat ong th ALM co the c dung nh la 1 chuoi thanh ghi e xay dng
bo em va thanh ghi dch. Trong phan nay chung ta se khao sat kieu hoat ong bnh thng va
kieu hoat ong LUT m rong.

28 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu

Hnh 1-32. S o khoi ALM cua Stratix II.


a. Kieu hoat ong bnh thng
c s dung au tien e tao cac ham logic to hp. Mot ALM co the thc hien mot hoac
hai ham ngo ra to hp vi hai LUT cua no. V du ve 4 cau hnh LUT c minh hoa hnh 1-33.

Hnh 1-33. Cac cau hnh co the co cua LUT trong ALM kieu bnh thng.
Hai ham SOP moi ham co 4 bien hoac t hn co the c thc hien trong mot ALM
ma khong can dung cac ngo vao chia se. V du ban co the co 2 ham 4 bien, mot ham co 4
bien va mot ham 3 bien hoac hai ham 3 bien. Bang cach chia se cac ngo vao, ban co the co
bat ky to hp nao cua 8 ngo vao len en toi a 6 ngo vao cho moi LUT. Trong kieu hoat ong
bnh thng th ban b gii han la cac ham SOP ch co toi a la 6 bien.
Ky thuat PLD va ASIC 29
Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu
b. Kieu hoat ong LUT m rong
Cho phep m rong ham len en 7 bien c minh hoa hnh 1-34. Mach ien AND OR
vi ngo vao ao la mot v du n gian cua mach don kenh. Mach don kenh la mot phan cua
mach logic dung rieng trong ALM.

Hnh 1-34. M rong ALM e tao ra ham SOP 7 bien trong kieu LUT m rong.

V du 1-4: Mot ALM trong FPGA Stratix II c nh cau hnh hoat ong kieu LUT m
rong c trnh bay hnh 1-35. Hay xac nh bieu thc ngo ra SOP.

Hnh 1-35. Minh hoa cho v du 1-4.


Giai: bieu thc ngo ra tren th AND vi bien ngo vao A0 va bieu thc ngo ra ben di th
AND vi A0 . Bieu thc sau cung nh sau:

A5 A4 A3 A2 A1 A0 + A5 A4 A3 A2 A1 A0 + A5 A4 A3 A2 A1 A0 + A6 A5 A4 A3 A2 A0 + A6 A5 A4 A3 A2 A0 + A6 A5 A4 A3 A2 A0

3. CAC CHC NANG TCH HP

30 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu
S o khoi tong quat cua FPGA Stratix II c trnh bay hnh 1-36. FPGA cha cac
thanh phan bo nh va chc nang x ly tn hieu so DSP. Chc nang cua DSP nh cac mach loc
so thng c s dung nhieu trong cac he thong. Khi quan sat s o khoi, cac khoi tch hp
ben trong c sap xep khap ni trong ma tran ket noi ben trong cua FPGA va cac phan t
ngo vao/ngo ra c at xung quanh chu vi FPGA.

Hnh 1-36. S o khoi cua FPGA Stratix II.


VI. FPGA CUA XILINX
Xilinx co 2 ho FPGA chnh la Spartan va Virtex va co nhieu loai khac nhau trong moi ho.
V du Spartan 3 va Spartan IIE, Virtex-4, Virtex II va Virtex II Pro X. Xilinx nh ro Virtex-4,
Virtex II va Virtex II Pro X la cac FPGA loai platform (nen) bi v chung tch hp nhieu chc
nang nh bo nh, vi x ly, bo thu phat va cac phan cng khac va cac loi phan mem IP. Cac ho
FPGA thng th khac ve mat o tch hp va cac thong so ky thuat. Hau het cac thiet b cua
Xilinx co cau truc FPGA truyen thong, tuy nhien Virtex II Pro X co cai goi la cau truc khoi
module ch nh ng dung ASMBL (Application Specific Modular Block c phat am la
assemble) co tren 1 t transistor trong 1 chip n.
1. CAC KHOI LOGIC CO THE NH CAU HNH CLB (CONFIGURABLE LOGIC BLOCK)
Vung logic nh cau hnh cua hau het cac FPGA ho Xilinx c chia thanh nhieu khoi
logic co the nh cau hnh CLB vi moi CLB cha nhieu n v logic c ban c la cac te bao
logic (logic cell - LC). Moi te bao logic LC s dung mach logic LUT truyen thong co 4 ngo vao
va them mach logic cong va mot flip flop. Mot LUT co 4 ngo vao co the tao ra t mot thanh
phan tch cho en ham SOP cha 16 thanh phan tch. Hai te bao logic LC giong nhau c goi
la slice (lat mong). Hnh 1-37 minh hoa cac cap logic nh cau hnh t te bao logic cho en

Ky thuat PLD va ASIC 31


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu
CLB. Mat o tch hp nam trong khoang t 2000 en 74000 te bao logic LC trong mot thiet b
Virtex n.

Hnh 1-37. Minh hoa cac cap logic nh cau hnh t te bao logic cho en CLB.
2. CHUOI LIEN TIEP SOP
Slice n gian (hai te bao logic LC) vi logic chuoi lien tiep c trnh bay hnh 1-38.
Co mach a hp (MUX) danh rieng nam trong mach logic ket hp cua moi LC c dung
trong chuoi lien tiep va mot cong OR danh rieng nam trong slice.

32 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu
Hnh 1-38a trnh bay v du cach ma mot slice trong CLB co the c nh cau hnh nh la
mot cong AND e tao ra thanh phan tch 8 bien. Hai slice co the c nh cau hnh e tao ra
mot ham SOP vi 2 thanh phan tch 8 bien c trnh bay hnh 1-38b. Toan bo CLB cua 4
slice co the c nh cau hnh thanh mot chuoi lien tiep e tao ra mot ham SOP vi 4 thanh
phan tch co 8 bien c trnh bay nh hnh 1-38c. Bieu thc SOP dai hn na co the c thc
hien dung them cac CLB m rong.

(a)

(b)

Ky thuat PLD va ASIC 33


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu

(c)
Hnh 1-38. V du cach dung chuoi noi tiep e m rong bieu thc SOP.

V du 1-5: Hay trnh bay cach cong AND co 16 ngo vao co the tao ra bieu thc trong CLB.
Giai: Hai slice c nh cau hnh c trnh bay hnh 1-39 la ket qua cua cong AND co
16 ngo vao.

34 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu

Hnh 1-39. Minh hoa cho v du 1-5.


3. CAU TRUC FPGA TRUYEN THONG VA CAU TRUC ASMBL
a. Cau truc truyen thong
Nh a biet, cau truc FPGA truyen thong xuat hien nh la mot mang cua cac khoi logic
(CLB hoac LAB) c bao boc xung quanh bi cac te bao ngo vao/ngo ra co the nh cau hnh.
So LCB trong FPGA tuy thuoc vao so lng cac phan t IO co the at xung quanh. Khi loi IP
nh DSP va bo nh tch hp ben trong khi c yeu cau th mot lng logic nh cau hnh phai
mat i va tai mot vai v tr c thay the bang IO neu co yeu cau. Khi nhieu loi IP c them
vao th kch thc vat ly cua FPGA phai tang len e am bao so lng logic cau hnh can thiet
va tang them so lng IO. Khai niem nay c minh hoa bang hnh 1-40.

(a) FPGA vi logic nh hnh ay u. (b) FPGA cung kch thc vi bo nh


va loi IP (DSP) nen co t CLB hn.

Ky thuat PLD va ASIC 35


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu

(c) FPGA co nhieu bo nh, them loi DSP va loi vi x ly se yeu cau kch thc ln hn.

Hnh 1-40. Tch hp nhieu chc nang IP ket qua lam giam CLB va/hoac phai tang kch
thc chip.
Logic cau hnh trong FPGA cang phc tap th cang dung nhieu IO. Moi lien he rang buoc
gia logic va IO se dan en tang kch thc chip va tang gia thanh. Ngoai ra mot van e khac
vi FPGA platform la khi them cac chc nang loi IP tch hp ben trong neu co yeu cau th phai
thiet ke lai thanh phan chnh hoac thiet ke lai mot phan trong cach bo tr chip (layout) co the
c yeu cau se lam tang them gia thanh.
a. Cau truc ASMBL
Xilinx a xay dng mot phng phap mem deo cho FPGA platform chip Virtex II Pro X
e khac phuc mot vai han che xuat hien trong cau truc truyen thong. Cau truc ASMBL la cau
truc s dung cot thay v dung cau truc hang/cot. Cac IO c at rai rac khap ni tot hn la at
xung quanh, dan en so lng IO cua no tang ma khong can lam tang kch thc chip. Moi cot
ve c ban la mot dai logic co the c thay the bang dai logic khac ma khong can thiet ke lai
cach bo tr chip. Cac v du ve cac loai cua cac dai logic la cac khoi logic nh cau hnh CLB,
khoi IO, bo nh va cac loi phan cng va phan mem nh DSP va vi x ly.
So lng khac nhau cua moi loai dai logic co the c tron lai e tng thch vi cac yeu
cau ng dung rieng biet. V du, trong cau hnh n gian nhat th co the pha tron cac dai CLB va
cac dai khoi IO c minh hoa nh hnh 1-41a. Nhieu hoac t hn cua ca 2 cung co the c s
dung tuy thuoc vao cac yeu cau.

36 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu
Neu can nhieu bo nh th mot hoac nhieu dai CLB co the c thay the nh hnh 1-41b.
Neu vung rieng biet trong ng dung la x ly tn hieu so th co the them vao cac loi IP DSP tron
vi bo nh nh hnh 1-41c. Hnh 1-41d trnh bay cac loi vi x ly c them vao.

(a) (b)

(c) (d)
Hnh 1-41. Minh hoa cau truc ASMBL cua FPGA platform.

VII. PHAN MEM LAP TRNH


e s dung thiet b logic lap trnh th phai co phan cng va phan mem ket hp vi nhau.
Tat ca cac nha che tao SPLD, CPLD va FPGA cung cap phan mem ho tr cho moi thiet b phan
cng. Cac goi phan mem nam trong danh sach phan mem c dung e thiet ke di s giup
cua may tnh CAD. Trong phan nay phan mem lap trnh c gii thieu mot cach tong quat.
Sau khi ket thuc phan nay ban co the: giai thch quy trnh lap trnh cho cac thanh phan cua
thiet ke, mo ta giai oan thiet ke, mo ta giai oan mo phong chc nang, mo ta giai oan tong
hp, mo ta giai oan thi hanh, mo ta mo phong theo thi gian, mo ta cach tai chng trnh.

Ky thuat PLD va ASIC 37


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu
Quy trnh lap trnh thiet ke c xem nh la dong thiet ke (design flow). Gian o dong
thiet ke c ban dung e thc hien thiet ke logic cho thiet b lap trnh c trnh bay nh hnh 1-
42. Hau het cac goi phan mem rieng le se ket hp cac cong oan cua quy trnh lai vi nhau va
qua trnh x ly hoan toan t ong. Thiet b e c lap trnh thng c xem la thiet b ch
(target device)

Hnh 1-42. S o dong thiet ke tong quat e lap trnh cho SPLD, CPLD hoac FPGA.
Phai co 4 thiet b e co the lap trnh cho thiet b la: may tnh, phan mem lap trnh, thiet b
logic lap trnh (SPLD, CPLD hoac FPGA) va thiet b ket noi may tnh vi thiet b lap trnh (cap
hoac mach nap). Tat ca cac thanh phan nay c minh hoa nh hnh 1-43.

38 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu

Hnh 1-43. Cac thiet b c ban e lap trnh cho SPLD, CPLD hoac FPGA.
1. CACH THIET KE
Gia s rang chung ta co mot thiet ke mach ien logic muon ieu khien bang thiet b lap
trnh th chung ta co the thiet ke tren may tnh bang mot trong hai cach c ban: thiet ke dung s
o nguyen ly (schematic entry) va cach dung ngon ng (text entry).
e dung cach thiet ke bang ngon ng th phai lam quen vi ngon ng HDL nh VHDL,
Verilog, ABEL hoac AHDL. Hau het cac nha che tao thiet b lap trnh cung cap cac goi phan
mem ho tr ngon ng VHDL va Verilog bi v chung la ngon ng HDL chuan. Nhieu nha che
tao con cung cap them ngon ng ABEL, AHDL.
Kieu thiet ke dung s o mach cho phep chung ta at cac k hieu cua cac cong logic va
cac chc nang logic khac t th vien len man hnh va ket noi chung theo yeu cau cua thiet ke.
Vi kieu thiet ke nay th can biet cac ngon ng HDL. Hnh 1-44 minh hoa cho ca 2 kieu thiet ke
cho mot mach ien logic AND-OR n gian.

Ky thuat PLD va ASIC 39


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu

Hnh 1-44. Minh hoa cho 2 kieu lap trnh.


Xay dng s o logic:
Khi xay dng mach ien logic ay u tren man hnh th no c goi la s o phang flat.
Cac mach ien logic phc tap hn th kho ma tng thch vi man hnh. Chung ta co the thiet ke
mach ien logic thanh nhieu oan (segment), lu tr moi oan nh la mot k hieu khoi va sau
o ket noi cac k hieu khoi lai vi nhau e tao thanh mot mach ien hoan chnh c goi la
thiet ke co th t.
V du thiet ke mach ien co bieu thc SOP nh sau:
( ) (
Z = A3 A2 A1 A0 + A3 A2 A1 A0 + A3 A2 A1 A0 + A3 A2 A1 A0 + A3 A2 A1 A0 )
Chung ta dung phng phap thiet ke co th t va xay dng mach logic cho 2 thanh phan
tong trong phng trnh, lam n gian moi mach ien logic bang mot k hieu duy nhat, sau khi
thiet ke xong ca 2 mach ien th at chung len man hnh va ket noi cac ngo ra vi cong OR e
tao thanh mach hoan chnh tat ca c minh hoa bang hnh 1-45.

a. Thiet ke thanh phan th 1 gom tong cua 2 tch.

40 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu

b. Lam n gian khoi mach ien bang k hieu logic 1.

c. Thiet ke thanh phan th 2 gom tong cua 3 tch.

d. Lam n gian khoi mach ien bang k hieu logic 2.

Ky thuat PLD va ASIC 41


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu

e. Ket noi 2 khoi logic 1 va logic 2 bang cong OR.


Hnh 1-45. Minh hoa cho kieu lap trnh tng oan.
Toan bo mach ien tren co the at len man hnh nhng phng phap thiet ke theo trnh t
rat tien li khi mach ien logic ln va phai chia ra thanh nhieu phan.
hnh 1-46e, mach ien logic co the lam n gian bang 1 k hieu khac va c s dung
e thiet ke mach ien ln hn hoac co the lu va dung lai cho cac thiet ke khac c minh hoa
nh hnh 1-46.

42 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu

Hnh 1-46. Lu thanh khoi logic 3.


2. MO PHONG CHC NANG
Muc ch cua chc nang mo phong trong dong thiet ke la e am bao chac chan thiet ke
hoat ong ung theo yeu cau trc khi tong hp thanh thiet ke phan cng. Ve c ban sau khi
mach ien logic c bien dch th sau o co the mo phong bang cach cung cap cac dang song
au vao va kiem tra dang song ngo ra cho cac to hp ngo vao co the co dung trnh soan thao
dang song.
Trnh soan thao dang song cho phep la chon cac nut (cac ngo vao va cac ngo ra) muon
kiem tra. Ten cac ngo vao va ngo ra a chon xuat hien tren man hnh soan thao dang song bang
k hieu hoac ten khac e xac nh cho moi mot ngo vao hoac mot ngo ra c trnh bay hnh
1-47. Khi bat au th tat ca cac ngo vao mac nhien mc 0 va cac ng cheo song song tng
trng cho tn hieu cha xac nh. Co the la chon cac khoang thi gian e hien th.

Hnh 1-47. Man hnh soan thao dang song tong quat .
Bc tiep theo chung ta xay dng dang song cho moi ngo vao bang cach nhap vao 1 hoac
0 cho moi khoang thi gian. Hnh 1-48 trnh bay cac dang song ngo vao.

Ky thuat PLD va ASIC 43


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu

Hnh 1-48. Thiet lap cac dang song ngo vao.


Sau khi thiet lap cac dang song ngo vao th m ca so ieu khien mo phong e thiet lap
thi gian bat au va thi gian ket thuc cho viec mo phong va ch nh cac khoang thi gian hien
th. Khi bat au mo phong th dang song cua tn hieu Z se c hien th tren man hnh dang
song nh hnh 1-49.
Ket qua dang song ngo ra Z cua v du nay se cho chung ta biet thiet ke hoat ong ung
hay khong ung. Trong trng hp nay dang song ngo ra la ung vi dang song ngo vao a
chon. Khi dang song ngo ra khong ung th phai quay lai kiem tra thiet ke ban au cho en khi
mach hoat ong ung.

Hnh 1-49. Dang song ngo vao va ra khi chay mo phong.


3. TONG HP
Moi khi mach logic c xay dng va c mo phong chc nang e kiem tra ung sai cua
mach logic thiet ke th phan mem bien dch a t ong thc hien mot vai cong oan e chuan b
cho viec nap thiet ke vao cho thiet b lap trnh.
Trong cong oan tong hp cua dong thiet ke th thiet ke c toi u theo cac thanh phan
e lam giam so lng cong, thay the cac phan t logic bang cac phan t logic khac ma chung co
the thc hien cung mot chc nang nhng hieu qua hn va loai tr cac thanh phan logic tha.

44 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu
Ngo ra cuoi cung t cong oan tong hp la liet ke ket noi (netlist) chung dien ta trang
thai toi u cua mach ien logic.
4. LIET KE LI (NETLIST)
Liet ke li ve c ban la mot danh sach liet li ma chung mo ta cac thanh phan va cach
ket noi vi nhau. Tong quat, liet ke li cha cac tham chieu mo ta cac thanh phan va cac phan
t c s dung.
Moi lan mot thanh phan nh cong logic c s dung trong liet ke li th no c goi la
instance. Moi instance co xac nh liet ke cac ket noi. Cac iem ket noi c goi la cac cang
(port) hoac cac chan (pin).
Thng th moi instance se co mot ten duy nhat, v du nh neu co 2 instance cua cac cong
AND th mot la and1 va cong con lai la and2. Ngoai ten ra con co ten khac, cac li la cac
ng day noi vi nhau trong mach ien. Bang liet ke cac li thng mo ta tat ca cac
instance va cac thuoc tnh cua chung, sau o mo ta tng li va at biet la cac port noi vi moi
instance.
Mach ien logic AND-OR a thiet ke tren c trnh bay hnh 1-50a co the c toi
u thanh mach ien hnh 1-50b. Trong phan minh hoa nay, trnh bien dch thay the cac cong OR
va bang mot cong OR co 5 ngo vao, bo hai cong ao tha trong mach.

(a). Mach ien thiet ke (b). Mach toi u sau khi tong hp
Hnh 1-50. Minh hoa cho chc nang tong hp.
Phan mem tong hp tao ra danh sach liet ke li. e minh hoa cho khai niem tao ra danh
sach li th hnh 1-51a se trnh bay cach gan ten cho li, gan ten cho instance va gan ten cho
IO. Danh sach liet ke li c trnh bay hnh 1-51b khong can thiet phai giong bat ky danh
sach liet ke nao ve cu phap va khuon kho. Danh sach liet ke nham xac nh cac loai thong tin
can e mo ta mach ien. Mot khuon kho c dung cho bang liet ke cac li la EDIF
(Electronic Design Interchange Format).

Ky thuat PLD va ASIC 45


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu

(a) (b)
Hnh 1-51. S o mach va danh sach liet ke.
5. PHAN MEM THI HANH
Sau khi thiet ke a c tong hp th trnh bien dch thi hanh thiet ke ve c ban cong
viec nay chnh la sap xep thiet ke e no co the tng thch vi thiet b lap trnh a chon bang
cach da vao cau truc va cau hnh chan.
Qua trnh x ly nay goi la lam cho tng thch (fitting). e ket thuc cong oan thi hanh
cua dong thiet ke th phan mem phai biet thiet b ro rang va co ay u cac thong tin chi tiet ve
chan. D lieu ay u cho tat ca cac thiet b thng c lu trong th vien cua bo nh va ngi
thiet ke ch can chon ung thiet b lap trnh.
6. MO PHONG THI GIAN
Phan nay nam trong dong thiet ke c thc hien sau khi phan mem thi hanh bien dch va
trc khi nap chng trnh vao thiet b. Mo phong theo thi gian e kiem tra mach ien hoat
ong tai tan so thiet ke va khong co thi gian tre hoac cac van e ve thi gian khac lam anh
hng en hoat ong cua mach.
Phan mem thiet ke dung cac thong tin cua thiet b lap trnh nh thi gian tr hoan cua cac
cong e thc hien mo phong theo thi gian cua thiet ke.
Khi mo phong chc nang a c thc hien th mach ien se hoat ong ung theo quan
iem logic. Khi mo phong chc nang th cac thong so ch nh ve thiet b ch la khong can thiet
nhng khi mo phong ve thi gian th phai la chon thiet b ch. Phan mem soan thao dang song
co the c dung e xem ket qua mo phong cung nh mo phong chc nang c minh hoa nh
hnh 1-52.

46 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu
Neu khong co van e g vi ket qua mo phong nh c trnh bay hnh 1-52a th thiet ke
co the nap vao thiet b lap trnh. Tuy nhien, gia s rang cac khoang mo phong thi gian phat
hien khong eu hay khong giong nhau phu thuoc vao thi gian tre nh c trnh bay hnh 1-
52b.

Hnh 1-52. Minh hoa cho mo phong thi gian.


Viec thc thi khong giong nhau ch xay ra trong mot khoang thi gian rat ngan trong dang
song. Trong trng hp nay can phai phan tch thiet ke mot cach can than e tm ra nguyen
nhan va sau o hieu chnh lai thiet ke va lap lai cac bc thiet ke.
7. LAP TRNH CHO THIET B HAY NAP CHNG TRNH CHO THIET B
Sau khi kiem tra mo phong chc nang va mo phong theo thi gian va thiet ke a hoat
ong ung th co the tien hanh download. Chuoi bit nh phan c tao ra tng trng cho thiet
ke va c gi en thiet b ch e t ong nh cau hnh cho thiet b. Sau khi thc hien xong th
thiet ke co the c kiem tra bang mach ien thc te. Hnh 1-53 trnh bay khai niem cho qua
trnh download.

Ky thuat PLD va ASIC 47


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu

Hnh 1-53. Download thiet ke vao thiet b lap trnh.


VIII. CAU HOI ON TAP VA BAI TAP
Cau 1-1. PAL tng trng cho cai g ?
Cau 1-2. GAL tng trng cho cai g ?
Cau 1-3. S khac nhau gia PAL va GAL la g ?
Cau 1-4. Mot macrocell c ban cha cac thanh phan nao?
Cau 1-5. CPLD la g?
Cau 1-6. LAB tng trng cho cai g ?
Cau 1-7. Mo ta LAB trong CPLD MAX 7000 ?
Cau 1-8. Muc ch ca bo m rong chia se la g ?
Cau 1-9. Muc ch ca bo m rong song song la g ?
Cau 1-10. CPLD MAX II khac vi MAX 7000 iem nao ?
Cau 1-11. S khac nhau c ban cua CPLD hang Altera va hang Xilinx la g?
Cau 1-12. Hay mo ta PLA ?
Cau 1-13. PLA khac vi PAL la g ?
Cau 1-14. FB tng trng cho cai g ?
Cau 1-15. FPGA khac vi CPLD nh the nao ?
Cau 1-16. CLB tng trng cho cai g ?
Cau 1-17. Mo ta LUT va cho biet chc nang cua no ?
Cau 1-18. S khac nhau gia ket noi ben trong toan cuc va cuc bo trong FPGA la g ?
Cau 1-19. Loi FPGA la g ?
Cau 1-20. nh ngha thuat ng IP co lien en nha san xuat FPGA ?

48 Ky thuat PLD va ASIC


Chng 1. Gii thieu cac cau truc lap trnh c. SPKT Nguyen nh Phu
Cau 1-21. n v thiet ke logic c ban trong FPGA Stratix II la g?
Cau 1-22. Co bao nhieu ALM trong LAB?
Cau 1-23. Cai g tao ra cac ham logic to hp trong ALM?
Cau 1-24. Co bao nhieu ham SOP co the c tao ra t mot ALM ?
Cau 1-25. Hay cho biet ten cua 2 loai chc nang tch hp trong Stratix II ?
Cau 1-26. CLB trong FPGA cua Xilinx cha cai g ?
Cau 1-27. LC cha cai g ?
Cau 1-28. Hay mo ta slice trong FPGA cua Xilinx ?
Cau 1-29. Chuoi noi tiep SOP la g ?
Cau 1-30. ASMBL tng trng cho cai g ?
Cau 1-31. Hay liet ke cac cong oan cua dong thiet ke cho mot thiet b lap trnh ?
Cau 1-32. Hay liet ke cac phan t c ban e lap trnh cho CPLD va FPGA?
Cau 1-33. Hay cho biet chc nang cua bang liet ke ca li ?
Cau 1-34. Co bao nhieu ham SOP co the c tao ra t mot ALM ?
Cau 1-35. Hay cho biet ten cua 2 loai chc nang tch hp trong Stratix II ?

end

Ky thuat PLD va ASIC 49


Chng 1. Gii thieu cac cau truc lap trnh c SPKT Nguyen nh Phu

50 Ky thuat PLD va ASIC


Chng 2
NGON NG LAP TRNH VHDL
S RA I NGON NG VHDL
CAC THUAT NG CUA VHDL
MO TA PHAN CNG TRONG VHDL
ENTITY (THC THE )
ARCHITECTURE
Gan Cac Tn Hieu ong Thi
Thi gian tre
ong bo lenh
CAC THIET KE CO CAU TRUC
HOAT ONG TUAN T
Cac phat bieu qua trnh
Vung khai bao qua trnh
Thanh phan phat bieu qua trnh
Thc hien qua trnh
Cac phat bieu tuan t
LA CHON KIEN TRUC
CAC CAU LENH CAU HNH
TOM TAT
GII THIEU VE MO HNH HANH VI
DELAY QUAN TNH VA DELAY TRUYEN
Delay quan tnh
Delay truyen tn hieu
Mo hnh Delay quan tnh
Mo hnh Delay truyen
MO PHONG DELTA
DRIVER
Tao driver
Mo hnh nhieu driver xau
GENERIC
CAC PHAT BIEU KHOI
TOM TAT

Ky thuat PLD va ASIC 51


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu
X LY TUAN T
PHAT BIEU
Danh sach nhay
V du ve qua trnh
GAN BIEN KHAC VI GAN TN HIEU
V du mo hnh mach a hp khong ung
V du mo hnh mach a hp ung
CAC PHAT BIEU TUAN T
PHAT BIEU IF
PHAT BIEU CASE
PHAT BIEU LOOP
Phat bieu vong lap LOOP c ban
Phat bieu vong lap While LOOP
Phat bieu vong lap FOR LOOP
Phat bieu Next va Exit
PHAT BIEU ASSERT
PHAT BIEU WAIT
CAC KIEU OI TNG TRONG VHDL
KHAI BAO TN HIEU
KHAI BAO BIEN
KHAI BAO HANG SO
CAC KIEU D LIEU TRONG VHDL
LOAI SCALAR
Kieu so nguyen INTEGER
Kieu d lieu a nh ngha
Kieu d lieu do ngi dung nh ngha
Kieu d lieu SUBTYPE
Kieu d lieu mang ARRAY
Kieu d lieu mang port
Kieu d lieu bang ghi record
Kieu d lieu SIGNED va UNSIGNED
Kieu so thc REAL
Kieu liet ke
KIEU VAT LY
CAC THUOC TNH
Thuoc tnh tn hieu
Thuoc tnh d lieu scalar
Thuoc tnh mang
CAC TOAN T C BAN TRONG VHDL
CAC TOAN T LOGIC
CAC TOAN T QUAN HE
CAC TOAN T SO HOC
CAC TOAN T CO DAU
CAC TOAN NHAN CHIA

52 Ky thuat PLD va ASIC


CAC TOAN T DCH
CAC TOAN T HON HP
CHNG TRNH CON VA GOI
CHNG TRNH CON
Ham
Ham chuyen oi
Ham phan tch
Thu tuc
GOI
Khai bao goi
Khai bao chng trnh con
CAU HOI ON TAP VA BAI TAP
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu
Hnh va bang

Hnh 2-1. Cong A co 2 ngo vao.


Hnh 2-2. K hieu cua mux co 4 ngo vao.
Hnh 2-3. Bang trang thai cua mux co 4 ngo vao.
Hnh 2-4. Dang song co delay quan tnh cua bo em.
Hnh 2-5. Dang song co delay truyen cua bo em.
Hnh 2-6. So sanh 2 c cau anh gia.
Hnh 2-7. So sanh 2 c cau anh gia.
Hnh 2-8. C cau anh gia delay delta.
Hnh 2-9. K hieu mach a hp va bang trang thai.
Hnh 2-10. Gian o cac loai d lieu trong VHDL.
Hnh 2-11. Cac kieu mang d lieu.

Bang 2-1. Thuoc tnh tn hieu.


Bang 2-2. Thuoc tnh d lieu scalar.
Bang 2-3. Thuoc tnh mang.
Bang 2-4. Tat ca cac toan t.
Bang 2-5. Cac toan t quan he.
Bang 2-6. Cac toan t so hoc.
Bang 2-7. Cac toan t co dau.
Bang 2-8. Cac toan t nhan chia.
Bang 2-9. Cac toan t dch.
Bang 2-10. Cac toan t hon hp.

54 Ky thuat PLD va ASIC


I. S RA I NGON NG VHDL
VHDL (Very high speed integrated circuit Hardware Description Language) la mot trong cac
ngon ng mo ta phan cng c s dung rong rai hien nay. VHDL la ngon ng mo ta phan cng
cho cac vi mach tch hp co toc o cao, c phat trien dung cho chng trnh VHSIC (Very High
Speed Integrated Circuit) cua bo quoc phong My.
Muc ch cua viec nghien cu va phat trien la tao ra mot ngon ng mo phong phan cng
chuan va thong nhat, cho phep th nghiem cac he thong so nhanh hn, hieu qua hn, va nhanh
chong a cac he thong o vao ng dung.
Thang 7 nam 1983, ba cong ty Internetic, IBM, Texas Instruments bat au nghien cu. Sau
mot thi gian, phien ban au tien cua ngon ng VHDL c cong bo vao thang 8 nam 1985.
Vao nam 1986, VHDL c cong nhan nh mot chuan IEEE. VHDL a qua nhieu lan kiem
nghiem va chnh sa cho en khi c cong nhan nh mot chuan IEEE 1076 vao thang 12 nam
1987.
VHDL c nghien cu phat trien nham giai quyet toc o phat trien, cac thay oi va xay
dng cac he thong ien t so. Vi mot ngon ng phan cng tot th viec xay dng cac he thong ien
t so co tnh linh hoat, phc tap tr nen de dang hn. Viec mo ta he thong so bang ngon ng cho
phep xem xet, kiem tra toan bo hoat ong cua he thong trong mot mo hnh thong nhat.
II. CAC THUAT NG CUA VHDL
Cau truc cua mot chng trnh VHDL nh sau:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07:52:37 09/26/2007
-- Design Name:
-- Module Name: mux - Behavioral
-- Project Name:
-- Target Devices:
Comment -- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------

package typedef IS
package SUBTYPE byte IS bit_vector (7 downto 0);
END ;
Use clause USE work.typedef.all

Ky thuat PLD va ASIC 51


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu
ENTITY data_path IS
PORT (clk, rst, s_1: IN BOOLEAN;
s0, s1: IN BIT;
Entity d0, d1, d2, d3: IN BYTE;
q: OUT BYTE);
END data_path;

ARCHITECTURE behavior OF data_path IS


SIGNAL reg, shft: BYTE;
SIGNAL sel: BIT_VECTOR (1 DOWNTO 0):
BEGIN
PROCESS (CLK, RST)
BEGIN
IF rst THEN -- async reset
Reg <= x 00;
shft <= x 00;
ELSIF clk and clkevent THEN -- define a clock
Architecture sel <= s1 & s0;
CASE sel IS
WHEN b 00 => reg <= d0;
Process WHEN b 01 => reg <= d1;
statement WHEN b 10 => reg <= d2;
Sequential WHEN b 11 => reg <= d3;
Statement END CASE;
IF s_1 THEN
shft <= shft (6 downto 0) & shft(7);
ELSE clk and clkevent THEN
shft <= reg;
END IF;
END PROCESS;
q <= shft;
END behavior;

e tm hieu chng trnh th chung ta can nh ngha mot so thuat ng c s dung trong
ngon ng VHDL.
Entity (thc the) tat ca cac thiet ke eu c bieu dien dang cac thuat ng thc the (entity).
Mot thc the la mot khoi xay dng c ban nhat trong thiet ke. Mc cao nhat cua thc the la mc
nh. Neu thiet ke co th bac th mo ta mc cao nhat se cha cac mo ta mc thap hn nam ben
trong. Nhng mo ta mc thap hn nay se cha cac thc the mc thap hn na. Trong VHDL th
thc the dung e khai bao cac cong input_output cua cac thanh phan va ten cua no.
Architecture (kien truc) tat ca cac thc the co the c mo phong eu co mot mo ta kien truc.
Kien truc mo ta hanh vi cua thc the. Mot thc the n co the co nhieu kien truc. Mot kien truc co
the mo ta hanh vi (behavioral description) trong khi o mot kien truc khac co the mo ta cau truc
(structural description).
Configuration (cau hnh) phat bieu cau hnh c s dung e rang buoc mot the hien
(instance) thanh phan vi mot cap thc the - kien truc. Mot cau hnh co the c khao sat giong
nh mot danh sach cac thanh phan cua mot thiet ke. Danh sach cac thanh phan mo ta hanh vi e
s dung cho moi thc the, giong nh danh sach liet ke cac phan mo ta s dung cho moi thanh phan
trong thiet ke.

52 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Package (goi) mot goi la mot tap hp cac loai d lieu c dung pho bien va cac chng
trnh con (subprogram) c s dung trong thiet ke. Xem package nh la mot hop cong cu cha
nhieu cong cu c dung e xay dng cac thiet ke.
Driver (nguon kch) la nguon kch cua mot tn hieu. Neu mot tn hieu c kch bi hai
nguon, th ca hai nguon eu mc tch cc, khi o ta xem tn hieu co 2 driver.
Bus (nhom tn hieu) thuat ng bus xem mot nhom cac tn hieu hoac mot phng phap
truyen thong ac biet c s dung trong thiet ke phan cng. Trong VHDL, bus la loai tn hieu ac
biet co nhieu nguon kch trang thai tat.
Attribute (thuoc tnh) la d lieu c gan cho cac oi tng VHDL hoac d lieu a nh
ngha trc lien quan en cac oi tng VHDL. V du la kha nang kch dong cua mot mach em
hoac nhiet o hoat ong cc ai cua linh kien.
Generic la thuat ng cua VHDL dung cho mot thong so, thong so nay chuyen thong tin en
mot thc the. Th du, neu mot thc the la mot mo hnh cong co tr hoan canh len va tr hoan canh
xuong, cac gia tr cua cac tr hoan len va xuong co the c chuyen vao trong thc the bang cac
dung generic.
Process (qua trnh) qua trnh la mot n v thc thi c ban trong VHDL. Tat ca cac hoat ong
c thc hien trong mo phong cua mot mo ta VHDL th c chia ra thanh mot hoac nhieu
qua trnh x ly.
III. MO TA PHAN CNG TRONG VHDL
Cac mo ta VHDL cha nhieu n v thiet ke s cap va nhieu n v thiet ke th cap.
n v thiet ke s cap la thc the (Entity) va goi (Package).
n v thiet ke th cap la cau hnh (Configuration) va than goi (Package Body).
Cac n v thiet ke th cap th luon co moi lien he vi n v thiet ke s cap. Cac th vien
cha nhieu cac n v thiet ke s cap va th cap.
1. ENTITY (THC THE )
Entity dung e khai bao ten cua thc the, cac port cua thc the va cac thong tin lien quan en
thc the. Tat ca cac thiet ke c xay dng dung mot hoac nhieu thc the.
V du 2_1: Khai bao n gian ve thc the:
ENTITY mux IS
PORT (a, b, c, d: IN BIT;
s0, s1: IN BIT;
x: OUT BIT);
END mux;
T khoa ENTITY bao cho biet bat au mot phat bieu thc the.
Trong cac mo ta c trnh bay trong toan bo tai lieu, cac t khoa cua ngon ng va cac loai
d lieu c cung cap cho goi chuan (STANDARD) th c trnh bay dang ch hoa. V du:
trong v du a trnh bay th cac t khoa la ENTITY, IS, PORT, IN, INOUT, Loai d lieu chuan
la BIT. Ten cua cac oi tng do ngi dung nh ngha v du nh mux trong v du tren la dang
ch thng.

Ky thuat PLD va ASIC 53


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Ten cua thc the la mux. Thc the co 7 port trong cau lenh khai bao PORT 6 port cho kieu
IN va 1 port cho kieu OUT. 4 port d lieu ngo vao (a, b, c, d) la dang BIT. Hai ngo vao la chon
mach a hp (s0, s1) cung thuoc kieu d lieu BIT. Ngo ra cung la BIT.
Thc the mo ta giao tiep vi the gii ben ngoai. Thc the ch nh ro bao nhieu port, hng
tn hieu cua port va loai d lieu cua port.
2. ARCHITECTURE (KIEN TRUC)
Thc the mo ta giao tiep vi mo hnh VHDL.
Kien truc mo ta chc nang c ban cua thc the va cha nhieu phat bieu mo phong hanh vi
cua thc the. Kien truc luon luon co lien quan en thc the va cac mo ta hanh vi cua thc the.
Mot kien truc cua bo a hp tren co dang nh sau:
ARCHITECTURE dataflow OF mux IS
SIGNAL select: INTEGER;
BEGIN
Select <= 0 WHEN s0 = 0 AND s1= 0 ELSE
1 WHEN s0 = 1 AND s1= 0 ELSE
2 WHEN s0 = 0 AND s1= 1 ELSE
3;
x <= a AFTER 0.5 NS WHEN select = 0 ELSE
b AFTER 0.5 NS WHEN select = 1 ELSE
c AFTER 0.5 NS WHEN select = 2 ELSE
d AFTER 0.5 NS ;
END dataflow;
T khoa ARCHITECTURE cho biet phat bieu nay mo ta kien truc cho mot thc the. Ten
cua kien truc la dataflow. Kien truc cua thc the ang c mo ta c goi la mux.
Ly do cho ket noi gia thc the va kien truc la mot thc the co the co nhieu kien truc mo ta
hanh vi cua thc the. V du mot kien truc co the la mot mo ta hanh vi va mot kien truc khac co the
la mo ta cau truc.
Vung ky t nam gia t khoa ARCHITECURE va t khoa BEGIN la ni khai bao cac phan
t va cac tn hieu logic cuc bo e sau nay dung. Trong v du tren bien tn hieu select c khai bao
la tn hieu cuc bo.
Vung cha cac phat bieu cua kien truc bat au vi t khoa BEGIN. Tat ca cac phat bieu
nam gia cac cau lenh BEGIN va END c goi la cac phat bieu ong thi bi v tat ca cac phat
bieu c thc hien cung mot luc.
a. Gan Cac Tn Hieu ong Thi
Trong ngon ng lap trnh thong thng nh C hoac C++ th moi phat bieu gan thc hien mot
lan sau mot phat bieu gan khac va theo mot th t c ch nh. Th t thc hien c xac nh
bi th t cua cac phat bieu trong file chng trnh nguon.
Trong kien truc VHDL th khong co th t ch nh nao cho cac phat bieu gan. Th t thc
hien c ch nh ro bi s kien xay ra tren tn hieu ma phat bieu gan hng en.
Khao sat phat bieu gan au tien c trnh bay nh sau:

54 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Select <= 0 WHEN s0 = 0 AND s1= 0 ELSE


1 WHEN s0 = 1 AND s1= 0 ELSE
2 WHEN s0 = 0 AND s1= 1 ELSE
3;
Gan tn hieu c thc hien bang k hieu <=. Tn hieu select se c gan gia tr da vao gia
tr cua s0 va s1. Phat bieu gan nay c thc hien bat ky luc nao khi mot hoac hai tn hieu s0 va s1
co thay oi.
Mot phat bieu gan tn hieu c xem la nhay vi cac thay oi tren bat ky tn hieu nao nam
ben phai cua k hieu gan <=. Phat bieu gan tn hieu cua v du tren th nhay vi s0 va s1. Phat bieu
gan tn hieu khac trong kien truc dataflow nhay vi tn hieu la chon.
Chung ta se khao sat cach hai phat bieu tren hoat ong thc s ra sao. Gia s rang chung ta
co ieu kien on nh khi s0 va s1 eu co gia tr la 0 va cac tn hieu hien hanh a, b, c va d eu co
gia tr la 0. Tn hieu x se co gia tr la 0 v no c gan cho gia tr cua tn hieu a.
Bay gi gia s: chung ta tao ra mot s kien thay oi tren tn hieu a t gia tr 0 len 1.
Khi s kien tn hieu a xay ra th phat bieu gan au tien khong c thc hien bi v phat bieu
nay khong nhay vi s thay oi cua tn hieu a v tn hieu a khong nam ben phai cua toan t.
Phat bieu gan th 2 se c thc hien bi v no nhay vi s kien xay ra tren tn hieu a. Khi
phat bieu gan th 2 c thc hien th gia tr mi cua a se c gan cho tn hieu x. Ngo ra x bay
gi se thay oi sang 1.
Tiep theo chung ta se khao sat trng hp khi tn hieu s0 thay oi. Gia s cho s0 va s1 eu
mc 0 va cac port a, b, c va d co gia tr theo th t la 0, 1, 0 va 1. Cho tn hieu S0 thay oi gia tr t
0 len 1.
Phat bieu gan tn hieu au tien nhay vi s0 nen no se c thc hien.
Khi cac phat bieu ong thi thc hien, viec tnh toan gia tr bieu thc se dung gia tr hien
hanh cho tat ca cac tn hieu cha trong phat bieu.
Khi phat bieu au tien thc hien se tnh gia tr mi e c gan cho select t gia tr hien
hanh cua bieu thc tn hieu nam ben phai cua k hieu gan <=. Viec tnh toan gia tr bieu thc se
dung gia tr hien hanh cho tat ca cac tn hieu cha trong phat bieu.
Vi gia tr cua s0 bang 1 va s1 bang 0 th tn hieu select se nhan gia tr mi la 1. Gia tr mi
cua tn hieu select c xem nh s kien xay ra tren tn hieu select, lam phat bieu gan th 2 cung
c thc hien theo. Phat bieu gan th 2 se dung gia tr mi cua tn hieu select e gan gia tr cua
port b cho ngo ra x va x se thay oi gia tr t 0 len 1.
b. Thi gian tre
Viec gan tn hieu cho tn hieu x khong xay ra ngay lap tc. Moi mot gia tr c gan cho tn
hieu x eu cha phat bieu AFTER. Gia tr cua x trong cac phat bieu gan tren ch c nhan gia
tr sau khoang thi gian 0,5 ns.
c. ong bo lenh
Phat bieu gan au tien ch c thc hien khi cac s kien xay ra cac port s0 va s1. Phat
bieu gan tn hieu th 2 se khong thc hien tr khi s kien xay ra tren tn hieu select hoac s kien
xay ra tren cac tn hieu a, b, c, d.

Ky thuat PLD va ASIC 55


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Hai phat bieu gan tn hieu trong kien truc behave hnh thanh mo hnh hanh vi (behavioral
model), hoac kien truc cho thc the mux.
Kien truc dataflow th khong co cau truc.
3. CAC THIET KE CO CAU TRUC (STRUCTURAL DESIGNS)
Mot cach khac e viet thiet ke mux la xay dng cac thanh phan phu ma chung thc hien cac
hoat ong nho hn cua mo hnh ay u. Vi mo hnh n gian nhat cua mach a hp 4 ngo vao
nh chung ta a dung la mo ta cap o cong n gian.
Kien truc c trnh bay sau ay la mo ta cau truc cua thc the mux.
ARCHITECTURE netlist OF mux IS
COMPONENT andgate
PORT(a, b, c: IN BIT; x: OUT BIT);
END COMPONENT;
COMPONENT inverter
PORT(in1: IN BIT; x: OUT BIT);
END COMPONENT;
COMPONENT orgate
PORT(a, b, c, d: IN BIT; x: OUT BIT);
END COMPONENT;
SIGNAL s0_inv, s1_inv, x1, x2, x3, x4: BIT;
BEGIN
U1: inverter (s0, s0_inv);
U2: inverter (s1, s1_inv);
U3: andgate (a, s0_inv, s1_inv, x1);
U4: andgate (b, s0, s1_inv, x2);
U5: andgate (c, s0_inv, s1, x3);
U6: andgate (d, s0, s1, x4);
U7: orgate (x2 => b, x1 => a, x4 => d, x3 => c, x => x);
END netlist;
Mo ta nay s dung mot so cac thanh phan mc thap hn e mo hnh hoa hanh vi cua thiet b
mux. Co mot thanh phan cong ao inverter, mot thanh phan cong andgate, va mot thanh phan
orgate. Mot trong cac thanh phan nay c khai bao trong phan khai bao kien truc nam gia cau
lenh kien truc va BEGIN.
Mot so cac tn hieu c dung e ket noi mot trong cac thanh phan e thanh lap mo ta kien
truc. Cac loai tn hieu nay c khai bao dung khai bao SIGNAL.
Vung cha phat bieu kien truc c thiet lap tai v tr ngay sau t khoa BEGIN. Trong v du
nay co mot so phat bieu cua cac thanh phan. Cac thanh phan nay c at ten la U1U7.
Phat bieu U1 la phat bieu cho cong ao. Phat bieu nay noi port s0 vi port ngo vao cua thanh
phan cong ao va tn hieu s0_inv vi port ngo ra cua thanh phan cong ao.
Ket qua la port in1 cua cong ao th c noi ti port s0 cua thc the mux va port x cua cong
ao c noi ti tn hieu cuc bo s0_inv. Trong phat bieu nay th cac port c noi ti theo th t
ma chung xuat hien trong phat bieu.

56 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Chu y phat bieu thanh phan U7 phat bieu nay dung cac k hieu nh sau:
U7: orgate (x2 => b, x1 => a, x4 => d, x3 => c, x => x);
Phat bieu nay ket hp cac ten e tng thch vi cac port. V du port x2 cua cong orgate th
c noi ti port b cua thc the cua phat bieu ket hp au tien. S ket hp va th t co the khong
theo th t nhng khong nen thc hien.
4. HOAT ONG TUAN T (SEQUENTIAL BEHAVIOR)
Co mot cach khac e mo ta chc nang cua thiet b mux trong ngon ng VHDL. Thc ra ngon
ng VHDL co nhieu cach trnh bay cho chc nang vi ket qua tng t. Cach th 3 e mo ta chc
nang cua mux la s dung phat bieu qua trnh (process) e mo ta chc nang trnh bay theo thuat
toan. Cach nay c dung cho kien truc sequential nh sau:
ARCHITECTURE sequential OF mux IS
PROCESS (a, b, c, d, s0, s1)
VARIABLE sel: INTEGER;
BEGIN
IF s0 = 0 and s1 = 0 THEN sel:= 0 ;
ELSIF s0 = 1 and s1 = 0 THEN sel:= 1 ;
ELSIF s0 = 0 and s1 = 1 THEN sel:= 2 ;
ELSE sel:= 3 ;
END IF;

CASE sel IS
WHEN 0 => x <= a ;
WHEN 1 => x <= b ;
WHEN 2 => x <= c ;
WHEN OTHERS => x <= d ;
END CASE;
END PROCESS;
END sequential;
Kien truc nay ch cha 1 phat bieu duy nhat c goi la phat bieu qua trnh (process). c
bat au vi hang co t khoa PROCESS va ket thuc vi hang co t khoa END PROCESS. Tat ca
cac phat bieu nam gia hai hang tren c xem thanh phan cua phat bieu qua trnh.
a. Cac phat bieu qua trnh
Phat bieu qua trnh cha nhieu thanh phan.
Thanh phan th nhat c goi la danh sach cac phan t nhay.
Thanh phan th hai c goi la thanh phan khai bao qua trnh.
Thanh phan th 3 la cac phat bieu.
Trong v du tren th danh sach liet ke cac tn hieu nam trong dau ngoac sau t khoa
PROCESS c goi la danh sach nhay. Danh sach nay liet ke chnh xac nhng tn hieu lam cho
phat bieu qua trnh c thc hien. Trong v du nay th danh sach cha cac tn hieu la a, b, c, d, s0
va s1. Ch co nhng s kien xay ra tren cac tn hieu nay lam cho phat bieu qua trnh c thc
hien.

Ky thuat PLD va ASIC 57


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

b. Vung khai bao qua trnh


Phan khai bao qua trnh la vung nam gia: sau danh sach nhay va t khoa BEGIN. Trong v
du tren phan khai bao cha khai bao bien cuc bo sel. Bien nay la bien cuc bo ch c dung e
tnh toan gia tr da vao port s0 va s1.
c. Thanh phan phat bieu qua trnh
Thanh phan phat bieu qua trnh bat au vi t khoa BEGIN va ket thuc vi hang co t khoa
END PROCESS. Tat ca cac phat bieu nam trong vung qua trnh la nhng phat bieu tuan t. ieu
nay co ngha la phat bieu nay c thc hien xong th cau lenh tiep theo se c thc hien giong
nh mot ngon ng lap trnh bnh thng. Chu y: th t cac phat bieu trong kien truc (architecture)
th khong can v chung thc hien ong thi, tuy nhien trong qua trnh (process) th can phai theo
th t th t thc hien trong qua trnh la th t cac phat bieu.
d. Thc hien qua trnh
Chung ta xem cach hoat ong qua trnh bang cach phan tch hoat ong cua v du sequential
trong kien truc theo tng hang phat bieu. e phu hp chung ta gia s s0 thay oi ve 0. Bi v s0
nam trong danh sach nhay cua phat bieu qua trnh.
Moi phat bieu trong qua trnh c thc hien theo trnh t. Trong v du tren, phat bieu if c
thc hien au tien va tiep theo la phat bieu case.
Kiem tra th nhat xem s0 co bang 0 hay khong. Phat bieu nay se khong thc hien neu s0
bang 1 va s1 bang 0. Phat bieu gan tn hieu theo sau phat bieu kiem tra th nhat se khong c
thc hien. Thay vao o phat bieu ke c thc hien. Phat bieu nay kiem tra ung trang thai va
phat bieu gan theo sau lenh kiem tra s0 =1 va s1 = 0 c thc hien. Gia tr sel:=1.
e. Cac phat bieu tuan t
Phat bieu se thc hien tuan t. Khi mot phat bieu kiem tra thoa ieu kien th phat bieu c
thc hien thanh cong va cac bc kiem tra khac se khong c thc hien. Phat bieu IF a thc
hien xong va bay gi th en phat bieu case se c thc hien.
Phat bieu case se can c vao gia tr cua bien sel a c tnh toan trc o cau lenh IF va
thc hien ung phat bieu gan tng ng vi gia tr cua bien sel. Trong trng hp nay th gia tr
cua sel = 1 nen cau lenh gan x<= b se c thc hien.
Gia tr cua port b se c gan cho port x va qua trnh thc hien se cham dt bi v khong con
phat bieu nao trong kien truc.
5. LA CHON KIEN TRUC
Cho en bay gi 3 kien truc a c dung e mo ta cho mot thc the. Kien truc nao se c
dung e xay dng mo hnh cho thc the th tuy thuoc vao o chnh xac mong muon va neu thong
tin ve cau truc c yeu cau.
Neu mo hnh se c dung e ieu khien cong cu layout th kien truc netlist la la chon hp
ly.
Neu mo hnh cau truc khong c yeu cau v nhieu ly do th mo hnh hieu suat cao c s
dung. Mot trong 2 phng phap con lai (kien truc dataflow va sequential) th co the at hieu suat
cao hn ve yeu cau khong gian bo nh va toc o thc hien.

58 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Cach e la chon gia 2 phng phap nay co the lam nay sinh mot cau khoi ve kieu lap
trnh. Ngi xay dng mo hnh thch viet chng trnh VHDL theo kieu ong thi hay theo kieu
trnh t?
Neu ngi xay dng mo hnh muon viet ma VHDL kieu ong thi th phai chon kieu kien
truc dataflow, ngc lai th chon kieu kien truc sequential. Thng th ngi xay dng mo hnh
quen vi kieu lap trnh tuan t nhng kieu ong thi la nhng cong cu manh e viet cho cac mo
hnh nho hieu suat cao.
6. CAC PHAT BIEU CAU HNH
Mot thc the co the co nhieu hn mot kien truc nhng lam the nao e ngi xay dng mo
hnh chon kien truc nao e s dung trong mo phong a cho. Phat bieu cau hnh sap xep cac thuyet
minh thanh phan cho thc the. Vi kha nang manh cua cau hnh ngi xay dng mo hnh co the
c la chon dung xay dng mo hnh cho thc the tai moi cap o trong thiet ke.
Chung ta se xem xet phat bieu cau hnh dung kien truc liet ke cua thc the mux.
V du 2-2: Phat bieu hnh nh sau:
CONFIGURATION muxcon1 OF mux IS
FOR netlist
FOR U1, U2: Inverter USE ENTITY WORK.myinv (version1);
END FOR;

FOR U3, U4, U5, U6: andgate USE ENTITY WORK.myand (version1);
END FOR;

FOR U7: orgate USE ENTITY WORK.myor (version1);


END FOR;

END muxcon1;
Chc nang cua phat bieu cau hnh la dien ta chnh xac kien truc nao dung cho moi thanh
phan trong mo hnh. ieu nay xay ra kieu he thong co cap bac. Thc the co cap bac cao nhat
trong thiet ke can co kien truc e s dung cho cac ch nh cung nh bat ky thanh phan nao can
c thuyet minh trong thiet ke.
Bat au phat bieu cau hnh la ten cua cau hnh muxcon1 cho thc the mux. S dung kien
truc netlist nh la kien truc cho thc the cap cao nhat o la mux.
oi vi 2 thanh phan U1 va U2 cua cong ao inverter c thuyet minh cho kien truc
netlist, s dung thc the myinv, kien truc version1 t th vien c goi la WORK.
oi vi cac thanh phan U3 U6 cua and andgate, dung thc the myand, kien truc version1
t th vien WORK.
oi vi thanh phan U7 cua cong orgate s dung thc the myor, kien truc version1 t th
vien WORK.
Tat ca cac thc the bay gi eu co cac kien truc c ch nh cho chung. Thc the mux co
kien truc netlist va cac thanh phan khac co kien truc c at ten ch nh version1.
SC MANH CUA CAU HNH

Ky thuat PLD va ASIC 59


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Khi bien dch cac thc the, cac kien truc va cau hnh a ch nh trc th co the xay dng mo
hnh co the mo phong. Nhng ieu g se xay ra neu khong muon mo phong cap o cong? Va neu
muon dung kien truc BEHAVE thay the. Sc manh cua cau hnh cho phep ban khong can bien
dch lai toan bo thiet ke ma ch can bien dch lai cau hnh mi.
V du 2-3: Cho cau hnh nh sau:
CONFIGURATION muxcon2 OF mux IS
FOR dataflow
END FOR;
END muxcon2;
Cau hnh nay co ten la muxcon2 cho thc the mux. S dung kien truc dataflow cho thc the
cap cao nhat la mux. Khi bien dch cau hnh nay th kien truc dataflow c la chon cho thc the
mux trong mo phong.
Cau hnh nay khong can thiet trong VHDL chuan nhng cung cap cho ngi thiet ke s t do
e ch nh chnh xac kien truc nao se c dung cho thc the. Kien truc mac nhien c dung cho
thc the la kien truc sau cung c bien dch cho vao th viec lam viec.
7. TOM TAT
Trong phan nay a gii thieu c ban ve VHDL va cach s dung ngon ng e xay dng mo
hnh hanh vi cua thiet b va thiet ke. V du th nhat a trnh bay cach xay dng mo hnh dataflow
n gian trong VHDL c ch ro. V du th 2 trnh bay cach mot thiet ke ln co the c thc
hien t nhng thiet ke nho hn trong trng hp nay bo a hp 4 ngo vao a c xay dng
dung cac cong AND, OR, va INVERTER. V du nay cung cap tong quan cau truc cua VHDL.
IV. GII THIEU VE MO HNH HANH VI
Phat bieu gan tn hieu la dang c ban nhat cua mo hnh hanh vi trong VHDL.
V du 2-4: Phat bieu gan tn hieu nh sau:
a <= b;
Phat bieu nay c oc nh sau: a co gia tr cua b. Ket qua cua phat bieu gan nay la gia tr
hien tai cua b c gan cho tn hieu a. Phat bieu gan nay c thc hien bat ky luc nao tn hieu b
thay oi gia tr. Tn hieu b nam trong danh sach nhay cua cau lenh nay. Bat ky tn hieu nao trong
danh sach nhay cua phat bieu gan tn hieu thay oi gia tr th phat bieu gan tn hieu c thc
hien.
Neu ket qua thc hien co gia tr mi khac vi gia tr trc o th sau mot thi gian tre th tn
hieu se xuat hien tai tn hieu ch.
Neu ket qua thc hien co cung gia tr th se khong co thi gian tre tn hieu nhng s chuyen
trang thai van c tao ra. S chuyen trang thai luon c tao ra khi mo hnh c anh gia nhng
ch nhng tn hieu co gia tr thay oi mi co s kien tre.
Phat bieu sau se gii thieu ve phat bieu gan tn hieu sau mot thi gian tre:
a <= b AFTER 10 ns;
Phat bieu nay c oc la a co gia tr cua b sau thi gian tre 10 ns

60 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Ca hai phat bieu eu la cac phat bieu gan tn hieu ong thi, va nhay vi s thay oi gia tr
cua tn hieu b. Khi b thay oi gia tr th cac phat bieu gan thc hien va gia tr mi c gan cho gia
tr cua tn hieu a.
V du 2-5: Phat bieu gan tn hieu ong thi cho mo hnh cong AND nh sau:
ENTITY and2 IS
PORT (a, b: IN BIT;
c: OUT BIT);
END and2;
ARCHITECTURE and2_behav OF and2 IS
BEGIN
c <= a AND b AFTER 5 ns;

Hnh 2-1. Cong A co 2 ngo vao.


Cong AND co 2 ngo vao a, b va mot ngo ra c nh hnh 2-1. Gia tr cua tn hieu c co the c
gan cho gia tr mi khi mot hoac ca hai tn hieu a va b thay oi gia tr.
n v thiet ke thc the mo ta cac port cua cong and2: co 2 ngo vao a va b, mot ngo ra c.
Kien truc and2_behav cho thc the and2 cha mot phat bieu gan tn hieu ong thi. Phat bieu gan
nay nhay vi ca 2 tn hieu a va tn hieu b.
Gia tr cua bieu thc a and vi b c tnh toan trc, ket qua tnh toan c a en ngo ra
sau khoang thi gian tre 5 ns t luc tnh toan xong.
V du 2-6: trnh bay phat bieu gan tn hieu phc tap hn nhieu va minh hoa cho khai niem
ong thi mot cach chi tiet hn.
Hnh 2-2 trnh bay s o khoi cua bo a hp 4 ngo vao va mo hnh hanh vi cho mux nh sau:

Hnh 2-2. K hieu cua mux co 4 ngo vao.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY mux4 IS
PORT (I0, I1, I2, I3, a, b: IN STD_LOGIC;
q: OUT STD_LOGIC);
END mux4;
Ky thuat PLD va ASIC 61
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

ARCHITECTURE mux4 OF mux4 IS


SIGNAL sel: INTEGER;
BEGIN
WITH sel SELECT
q <= I0 AFTER 10 ns WHEN 0
I1 AFTER 10 ns WHEN 1
I2 AFTER 10 ns WHEN 2
I3 AFTER 10 ns WHEN 3
X AFTER 10 ns WHEN OTHERS;

sel <= 0 WHEN a = 0 AND b = 0 ELSE


1 WHEN a = 1 AND b = 0 ELSE
2 WHEN a = 0 AND b = 1 ELSE
3 WHEN a = 1 AND b = 1 ELSE
4 ;
END mux4;
Thc the entity cho mo hnh nay co 6 port ngo vao va 1 port ngo ra. 4 port ngo vao (I0, I1, I2,
I3) tng trng cho cac tn hieu se c gan cho tn hieu ngo ra q. Ch 1 trong cac tn hieu c
gan cho tn hieu ngo ra q da vao ket qua cua 2 tn hieu ngo vao khac la a va b. Bang s that cho
bo a hp c trnh bay nh hnh 2-3.
e ng dung chc nang a mo ta tren, chung ta dung phat bieu gan tn hieu ieu kien va
phat bieu gan tn hieu co la chon.
Phat bieu th 2 trong v du c goi la phat bieu gan tn hieu co ieu kien. Phat bieu nay gan
gia tr cho tn hieu ch da vao cac ieu kien c anh gia cho moi lenh. Cac ieu kien WHEN
c thc hien mot lan tai mot thi iem theo th t tuan t cho en khi gap ieu kien tng thch.
Phat bieu th 2 gan gia tr cho tn hieu ch khi tng thch ieu kien, tn hieu ch la sel. Tuy
thuoc vao gia tr cua a va b th cac gia tr t 0 en 4 se c gan cho sel.
Neu co nhieu ieu kien cua mot phat bieu tng thch th phat bieu au tien ma no tng
thch se c thc hien va cac gia tr cua phat bieu tng thch con lai se b bo qua.
Phat bieu th 1 c goi la gan tn hieu co la chon va la chon gia so lng cac tuy chon
e gan gia tr ung cho tn hieu ch trong v du nay tn hieu ch la q.

B A Q
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Hnh 2-3. Bang trang thai cua mux co 4 ngo vao.
Bieu thc (gia tr sel trong v du nay) c anh gia va phat bieu ma no tng thch vi gia
tr cua bieu thc c gan gia tr cho tn hieu ch. Tat ca cac gia tr co the co cua bieu thc phai
co s la chon tng thch trong cach gan tn hieu a la chon.

62 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Moi mot tn hieu ngo vao co the c gan cho ngo ra q tuy thuoc vao cac gia tr cua 2 ngo
vao a va b. Neu cac gia tr cua a va b khong xac nh th gia tr sau cung X (khong xac nh)
c gan cho ngo ra q. Trong v du nay, khi cac ngo vao la chon gia tr khong xac nh th ngo
ra c gan cho gia tr khong xac nh.
Phat bieu th hai nhay vi cac tn hieu a va b. Bat ky luc nao khi a hoac b thay oi gia tr,
phat bieu gan th hai c thc hien va tn hieu sel c cap nhat. Phat bieu th 1 nhay vi tn
hieu sel. Khi tn hieu sel thay oi gia tr th gan tn hieu tn hieu th nhat c thc hien.
Neu v du nay c x ly bi cong cu tong hp, th ket qua cau truc cong c xay dng
giong nh mot bo a hp 4 ng sang 1 ng. Neu th vien tong hp cha bo a hp 4 ng
sang 1 ng th bo a hp nay co the c cap phat da vao s phc tap cua cong cu tong hp va
at vao trong thiet ke.
1. DELAY QUAN TNH VA DELAY TRUYEN
Trong VHDL co 2 loai delay co the dung cho mo hnh hanh vi. Delay quan tnh th c s
dung pho bien, trong khi delay truyen c s dung nhng ni ma mo hnh delay day dan c
yeu cau.
a. Delay quan tnh:
Delay quan tnh la mac nhien trong VHDL. Neu khong co kieu delay c ch nh th delay
quan tnh c s dung. Delay quan tnh la delay mac nhien bi v trong hau het cac trng hp th
no thc hien giong nh thiet b thc.
Gia tr cua delay quan tnh bang vi delay trong thiet b.
Neu bat ky xung tn hieu co chu ky vi thi gian cua tn hieu ngan hn thi gian delay cua
thiet b th gia tr tn hieu ngo ra khong thay oi.
Neu thi gian cua tn hieu c duy tr mot gia tr ac biet dai hn thi gian delay cua thiet
b th delay quan tnh se c khac phuc va thiet b se thay oi sang trang thai mi.
Hnh 2-4 la mot v du ve k hieu bo em rat n gian co 1 ngo vao A va mot ngo ra B, dang
song c trnh bay cho tn hieu ngo vao A va ngo ra B.
Tn hieu A thay oi t 0 sang 1 tai moc thi gian 10ns va t 1 sang 0 tai moc thi gian
20ns. Vi cac khoang thi gian nay cho phep xay dng mot xung hoac xung nhon co thi gian nho
hn 10ns. Cho bo em co thi gian tre la 20ns.
Chuyen trang thai t 0 sang 1 tren tn hieu A lam cho mo hnh bo em c thc hien va
theo d kien th gia tr 1 xuat hien ngo ra B tai moc thi gian 30ns.
moc thi gian 20ns, s kien tiep theo tren tn hieu A xay ra (tn hieu a xuong mc 0) th
mo hnh bo em d kien mot s kien mi se xay ra tren ngo ra B co gia tr 0 tai moc thi gian
40ns. Trong khi o s kien a d kien ngo ra B cho moc thi gian 30ns van cha xay ra. S kien
mi c d oan bi mo hnh bo em xung ot vi s kien trc va trnh mo phong u tien cho s
kien co moc thi gian 30ns.
Ket qua cua viec u tien la xung b nuot (mat). Ly do xung b nuot la tuy thuoc vao mo hnh
delay quan tnh, s kien th nhat tai moc thi gian 30ns cha co u thi gian e hoan thanh delay
quan tnh cua tn hieu ngo ra.

Ky thuat PLD va ASIC 63


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Mo hnh thi gian delay quan tnh thng c s dung trong tat ca cac trnh mo phong.
Trong hau het cac trng hp mo hnh delay quan tnh u chnh xac cho cac yeu cau cua ngi
thiet ke. Mot trong nhng ly do cho viec m rong s dung thi gian delay quan tnh la no ngan
chan thi gian tr hoan cua xung xuyen qua thiet b.

Hnh 2-4. Dang song co delay quan tnh cua bo em.


b. Delay truyen tn hieu
Delay truyen tn hieu khong phai la delay mac nhien cua VHDL ma phai c ch nh.
Delay truyen tng trng cho delay day dan, bat ky xung nao c truyen en ngo ra eu c
delay vi mot gia tr delay theo ch nh. Delay truyen rat co ch e xay dng mo hnh thiet b co
tre tren ng day, tren day dan cua bo mach.
Neu chung ta xem mach em a c trnh bay hnh 2-4 nhng thay the cac dang song
delay quan tnh bang cac dang song delay truyen th chung ta co ket qua nh hnh 2-5. Cung dang
song cua ngo vao nhng dang song ngo ra B th hoan toan khac. Vi delay truyen th cac xung
nhon se xuat hien nhng cac s kien xep theo th t trc khi truyen i.
Tai moc thi gian 10ns, mo hnh bo em c thc hien va d kien mot s kien ngo ra se len
mc 1 tai moc thi gian 30ns. Tai moc thi gian 20ns mo hnh bo em b kch va d oan mot gia
tr mi se xuat hien ngo ra tai moc thi gian 40ns. Vi thuat toan delay truyen th cac s kien
c at theo th t. S kien cho moc thi gian 40ns c at trong danh sach cac s kien nam sau
s kien cua moc thi gian 30ns. Xung khong b nuot nhng c truyen nguyen ven sau thi gian
delay cua thiet b.

64 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Hnh 2-5. Dang song co delay truyen cua bo em.

c. Mo hnh Delay quan tnh


Mo hnh tiep theo trnh bay cach viet mot mo hnh delay quan tnh. Giong nh nhng mo hnh
khac ma chung ta a khao sat, delay mac nhien la delay quan tnh do o khong can thiet phai ch
nh kieu delay la delay quan tnh:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY buf IS
PORT (a: IN STD_LOGIC;
b: OUT STD_LOGIC);
END buf;

ARCHITECTURE buf OF buf IS


BEGIN
b <= a AFTER 20 ns ;
END buf;

d. Mo hnh Delay truyen


V du cho mo hnh delay truyen c trnh bay nh sau:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY delay_line IS
PORT (a: IN STD_LOGIC;
b: OUT STD_LOGIC);
END delay_line;

ARCHITECTURE delay_line OF delay_line IS


BEGIN
b <= TRANSPORT a AFTER 20 ns ;
END delay_line;
Giong nh mo hnh delay quan tnh ch khac la co them t khoa TRANSPORT trong lenh
gan tn hieu cho tn hieu b. Khi t khoa nay ton tai, kieu delay c dung trong phat bieu la delay
truyen.
2. MO PHONG DELTA
Mo phong delta c dung e xep th t cho nhieu loai s kien trong mo phong thi gian.
ac biet cac s kien delay bang 0 phai c xep theo th t e tao ra cac ket qua thch hp. Neu
cac s kien delay zero khong theo th t hp ly th ket qua co the khac nhau gia cac lan mo
phong khac nhau. Mot v du cho kieu nay c trnh bay hnh 2-6. Mach ien nay la mot phan
cua s o mach ong ho.

Ky thuat PLD va ASIC 65


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Mach ien gom co mot cong ao, mot cong NAND va mot cong AND thuc ngo vao ong ho
cua thanh phan flip flop. Cong NAND va cong AND c dung e gac ngo vao xung clock en flip
flop.
Chung ta se khao sat hoat ong cua mach dung c cau delay delta va c cau khac. Bang cach
kiem tra 2 c cau delay chung ta se hieu ro hn cach delay delta sap xep cac s kien.

Hnh 2-6. So sanh 2 c cau anh gia.


e dung delay delta th tat ca cac thanh phan cua mach ien phai co delay zero theo ch
nh. Delay cho ca 3 cong c ch nh la zero. (cac mach ien thc te th khong co ac tnh nh
the).
Khi co canh xuong xay ra tren tn hieu A, ngo ra cua cong ao thay oi ung thi iem 0.
Chung ta gia s rang s kien xay ra tai moc thi gian 10ns. Tn hieu ra B cua cong ao thay oi
ngc vi gia tr mi cua ngo vao.
Khi gia tr B thay oi, ca hai cong AND va NAND c anh gia lai. Trong v du nay gia s
ngo vao xung clock la 1. Neu cong NAND c anh gia trc th gia tr mi ngo ra cong
NAND la 0.
Khi cong AND c anh gia th tn hieu B co gia tr la 1 va tn hieu C co gia tr la 0, do
o cong AND d oan ket qua mi la 0.
Nhng ieu g se xay ra neu cong AND anh gia trc. cong AND se co gia tr 1 tn
hieu B va gia tr 1 tn hieu C (cong NAND cha anh gia). Ngo ra cong AND co gia tr mi la
1.
Bay gi cong NAND mi c anh gia va gia tr mi ngo ra la 0. S thay oi ngo ra
NAND lam cho cong AND anh gia lai lan na. Cong AND co gia tr cua B la 1 va gia tr mi
cua tn hieu C la 0. Ngo ra cong AND bay gi se co gia tr la 0. Qua trnh nay c tom tat nh
hnh 2-7.
Ca hai tn hieu en ngo vao D. Tuy nhien khi cong AND c anh gia trc th co xung
canh len vi o rong delta xuat hien ngo ra D. Canh len nay co the kch flip flop, tuy thuoc vao
cach mo hnh flip flop c xay dng.

66 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

AND FIRST NAND FIRST


Evaluate inverter Evaluate inverter
B <= 1 B <= 1
Evaluate AND (C = 1) Evaluate NAND
D <= 1 C <= 0
Evaluate NAND Evaluate AND
C <= 0 D <= 0
Evaluate AND
D <= 0
Hnh 2-7. So sanh 2 c cau anh gia.
Trong tam cua van e la neu khong co c cau ong bo delta th ket qua cua mo phong co the
tuy thuoc vao cach cac cau truc d lieu mo phong c xay dng. V du, khi bien dch mach ien
lan th nhat th co the cong AND c anh gia trc, neu bien dch lai lan na th co the cong
NAND c anh gia trc cho ra ket qua khong mong muon, mo phong delta se ngan chan
hanh vi nay xay ra.
Cung mot mach ien c anh gia dung c cau delay delta VHDL se anh gia nh hnh 2-8.

Time Delta
10 ns (1) A <= 0
Evaluate inverter
(2) B <= 1
Evaluate AND
Evaluate NAND
(3) D <= 1
C <= 0
Evaluate AND
(4) D <= 0
11 ns
Hnh 2-8. C cau anh gia delay delta.
iem thi gian delta au tien cua 10ns, tn hieu A nhan gia tr 0. Gia tr nay lam cho cong
ao c anh gia lai vi gia tr mi. Tn hieu ngo ra cong ao B co gia tr la 1. Gia tr nay
khong truyen ngay lap tc ma ch cho en iem thi gian delta th 2.
Sau o trnh mo phong bat au thc hien iem thi gian delta th 2. Tn hieu B c cap nhat
gia tr la 1 va cong AND va cong NAND c anh gia lai. Ca hai cong AND va NAND phai
ch cac gia tr mi iem thi gian delta th 3.
Khi iem thi gian delta th 3 xay ra, tn hieu D nhan gia tr la 1 va tn hieu C nhan gia tr
la 0. Do tn hieu C cung thuc cong AND, cong AND c anh gia lai va ch ket qua ngo ra
iem thi gian delta th 4. Cuoi cung ngo ra D bang 0.
Tom lai mo phong delta la lng thi gian vo cung nho c dung nh mot c cau ong bo
khi cac s kien delay zero xuat hien. Delay delta c dung khi delay zero c ch nh va trnh
bay nh sau:
Ky thuat PLD va ASIC 67
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

a <= b after 0 ns;


Mot trng hp khac dung delay delta la khi delay zero c ch nh.
V du 2-7: Phat bieu hnh nh sau:
a <= b ;
Trong ca 2 trng hp, tn hieu b thay oi gia tr t 1 s kien, tn hieu a c gan tn hieu sau
khoang thi gian delay delta.
Mot mo hnh VHDL tng ng cua mach ien c trnh bay nh hnh 2-6:
ENTITY reg IS
PORT (a, clock: IN BIT;
d: OUT BIT);
END reg;

ARCHITECTURE test OF reg IS


SIGNAL b,c: BIT;
BEGIN
b <= NOT (a); -- no delay
c <= NOT (clock AND b);
d <= c AND b;
END test;
3. DRIVER
VHDL co mot phng phap duy nhat e x ly cac tn hieu co nhieu nguon kch. Cac tn hieu
co nhieu nguon kch rat hu ch cho mo hnh bus d lieu, bus hai chieu, Mo hnh chnh xac cac
loai mach ien nay trong VHDL yeu cau phai biet cac khai niem ve mach kch (thuc) tn hieu.
Moi mot driver cua VHDL xem nh mot tn hieu gop phan cho gia tr tong the cua mot tn hieu.
Mot tn hieu co nhieu nguon kch se co nhieu driver. Cac gia tr cua tat ca cac driver c
phan tch cung nhau e tao ra gia tr duy nhat cho tn hieu nay. Phng phap phan tch tat ca cac
tn hieu gop phan thanh mot gia tr duy nhat la thong qua ham phan tch. Mot ham phan tch la
ham do ngi thiet ke viet, se c goi moi khi mot driver cua tn hieu thay oi gia tr.
a. Tao driver:
Cac driver c tao ra bang cac phat bieu tn hieu. Mot phep gan tn hieu ong thi ben
trong mot kien truc tao ra mot driver cho mot phep gan tn hieu. Do o nhieu phep gan tn hieu se
tao ra nhieu driver cho mot tn hieu. Hay khao sat kien truc sau ay
ARCHITECTURE test OF test IS
BEGIN
a <= b AFTER 10ns;
a <= c AFTER 10ns;
END test;
Tn hieu a se c kch t hai nguon b va c. Moi phat bieu gan tn hieu ong thi se tao ra
mot driver cho tn hieu a.
Phat bieu th nhat tao ra mot driver cha gia tr cua tn hieu b c tr hoan 10 ns.
68 Ky thuat PLD va ASIC
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Phat bieu th hai tao ra mot driver cha gia tr cua tn hieu c c tr hoan 10 ns.
Nhng ngi thiet ke s dung VHDL khong muon tuy y them vao cac rang buoc ngon ng
oi vi hanh vi cua tn hieu. Khi tong hp v du tren se noi tat b va c vi nhau.
b. Mo hnh nhieu driver xau:
Ta hay khao sat mot mo hnh thoat nhn co ve ung nhng lai khong thc hien chc nang nh
ngi s dung d nh. Mo hnh nay s dung mot mach a hp 4 ng sang 1 ng a thao luan:
USE IEEE.std_logic_1164.ALL;
ENTITY mux4 IS
PORT (i0, i1, i2, i3, a, b: IN STD_LOGIC;
q: OUT STD_LOGIC);
END mux4;

ARCHITECTURE bad OF mux4 IS


BEGIN
q <= i0 WHEN a = 0 AND b = 0 ELSE 0
q <= i1 WHEN a = 1 AND b = 0 ELSE 0
q <= i2 WHEN a = 0 AND b = 1 ELSE 0
q <= i3 WHEN a = 1 AND b = 1 ELSE 0
END bad;
Mo hnh nay gan: i0 cho q khi a bang 0 va b bang 0;
i1 khi a bang 1 va b bang 0;
Thoat nhn, mo hnh nay co ve hoat ong ung. Tuy nhien moi phep gan cho tn hieu q tao ra
mot tn driver mi cho tn hieu q. Bon driver cho tn hieu q c tao ra trong mo hnh nay.
Moi driver se kch gia tr cua mot trong cac ngo vao i0, i1, i2, i3 hoac 0. Gia tr c kch
phu thuoc vao cac tn hieu a va b.
Neu a bang 0 va b bang 0, phat bieu gan au tien at gia tr cua i0 va mot trong cac driver
cua q. Ba phat bieu gan khac khong thoa ieu kien va do vay se kch gia tr 0. Nh vay, ba driver
se kch gia tr 0 va mot driver se kch gia tr cua i0.
Cac ham phan tch ien hnh kho ma d oan ket qua ngo ra q mong muon, nhng gia tr thc
cua no chnh la i0. Cach tot hn e viet cho mo hnh nay la ch xay dng mot mach driver (kch)
cho tn hieu q nh c trnh bay sau ay
ARCHITECTURE better OF mux4 IS
BEGIN
q <= i0 WHEN a = 0 AND b = 0 ELSE
i1 WHEN a = 1 AND b = 0 ELSE
i2 WHEN a = 0 AND b = 1 ELSE
i3 WHEN a = 1 AND b = 1 ELSE
X;
END better;
4. GENERIC

Ky thuat PLD va ASIC 69


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Generic la mot c cau tong quat c dung e chuyen thong tin en thc the. Thong tin c
chuyen en thc the la mot trong cac kieu c VHDL cho phep.
Generic cung co the c dung e chuyen cac kieu d lieu bat ky do ngi thiet ke nh
ngha bao gom cac thong tin nh ien dung tai, ien tr, Cac thong so tong hp nh o rong
ng d lieu, o rong tn hieu, co the chuyen c di dang cac generic.
Tat ca d lieu c chuyen en mot thc the la cac thong tin ro rang. Cac gia tr d lieu co
lien quan en instance ang c truyen d lieu. phng phap nay, ngi thiet ke co the truyen
cac gia tr khac nhau en cac instance khac nhau trong thiet ke.
D lieu c truyen en instance la d lieu tnh. Sau khi mo hnh c cho them chi tiet (lien
ket vi trnh mo phong), d lieu se khong thay oi trong thi gian mo phong. Cac generic khong
the c gan thong tin cho cac thanh phan chay chng trnh mo phong. Thong tin cha trong cac
generic c chuyen en instance thanh phan hoac mot khoi co the c s dung e thay oi cac
ket qua trong mo phong, nhng cac ket qua khong the sa oi cac generic.
V du 2-8: thc the cong AND co 3 generic ket hp:
ARCHITECTURE load_dependent OF and2 IS
SIGNAL internal BIT;

BEGIN
internal <= a AND b;
c <= Internal AFTER (rise + (load*2 ns)) Internal = 1 ELSE Internal
AFTER (rise + (load*3 ns));
END load_dependent;
Kien truc nay khai bao mot tn hieu cuc bo goi la internal e lu gia tr cua bieu thc a va b.
Cac gia tr tnh toan trc dung cho nhieu instance la mot phng phap rat hieu qua cho viec xay
dng mo hnh.
Cac generic rise, fall va load cha cac gia tr a c chuyen vao bi phat bieu cua instance
thanh phan. Ta hay khao sat mot phan cua mo hnh ma no the hien cac thanh phan loai AND2
trong mot cau truc khac:
ENTITY test IS
GENERIC (rise, fall: TIME; load: INTEGER);
PORT (ina, inb, inc, ind: IN STD_LOGIC;
Out1, out2: OUT STD_LOGIC);
END test;

ARCHITECTURE test_arch OF test IS


COMPONENT and2
GENERIC (rise, fall: TIME; load: INTEGER);
PORT(a, b: IN BIT; c: OUT BIT);
END COMPONENT;
BEGIN
U1: and2 GENERIC MAP (10 ns, 12 ns, 3) PORT MAP (ina, inb, out1);
U2: and2 GENERIC MAP (9 ns, 11 ns, 5) PORT MAP (inc, ind, out2);
END test_arch;
Phat bieu kien truc au tien khai bao cac thanh phan se c s dung trong mo hnh. Trong
v du nay thanh phan AND2 c khai bao.

70 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Tiep theo, than cua phat bieu kien truc cha hai phat bieu the hien thanh phan cua cac thanh
phan U1 va U2. Port a cua thanh phan U1 c anh xa en tn hieu ina, port b c anh xa en tn
hieu inb va port c c anh xa en tn hieu out1. Cung phong phap nh vay thanh phan U2 c
anh xa en cac tn hieu inc, ind va out2.
Generic rise cua the hien U1 c anh xa en 10ns, generic fall c anh xa en 12ns va
generic load c anh xa en 3. Cac generic cua thanh phan U2 c anh xa en cac gia tr 9 ns,
11ns va gia tr 5.
Cac generic cung co the co gia tr mac nh, cac gia tr nay c ghi e neu cac gia tr thc
te c anh xa en cac generic. V du tiep theo trnh bay hai the hien thanh phan loai AND2.
Trong thanh phan U1, gia tr thc te c anh xa en generic va cac gia tr nay c dung e
ieu khien hanh vi mo phong neu c ch nh ro, ngc lai se phat sinh loi.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY test IS
GENERIC (rise, fall: TIME; load: INTEGER);
PORT (ina, inb, inc, ind: IN STD_LOGIC;
Out1, out2: OUT STD_LOGIC);
END test;

ARCHITECTURE test_arch OF test IS


COMPONENT and2
GENERIC (rise, fall: TIME: = 10 ns; load: INTEGER := 0);
PORT(a, b: IN BIT; c: OUT BIT);
END COMPONENT;
BEGIN
U1: and2 GENERIC MAP (10 ns, 12 ns, 3) PORT MAP (ina, inb, out1);
U2: and2 PORT MAP (inc, ind, out2);
END test_arch;
Nh a nhn thay, cac generic co nhieu cach dung. Viec s dung generic ch b gii han bi
s sang tao cua ngi viet mo hnh.
5. CAC PHAT BIEU KHOI
Cac khoi la c cau tng phan trong VHDL cho phep ngi thiet ke cac khoi trong mo hnh.
V du neu ban thiet ke CPU th co the chia ra thanh nhieu khoi nh khoi ALU, khoi bank thanh ghi
va cac khoi khac.
Moi khoi co the khai bao cac tn hieu cuc bo, kieu d lieu, hang so, Bat ky oi tng nao
ma no co the c khai bao trong phan khai bao kien truc th co the c khai bao trong phan
khai bao khoi.
V du 2-9: dung cac phat bieu khoi:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

Ky thuat PLD va ASIC 71


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

package bit32 IS
TYPE tw32 IS ARRAY ( 31 downto 0 ) OF std_logic;
END bit32;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.bit32.ALL;

ENTITY cpu IS
PORT (clk, interrupt: IN STD_LOGIC;
addr: OUT tw32;
data: INOUT tw32;);
END cpu;

ARCHITECTURE cpu_blk OF cpu IS


SIGNAL ibus, dbus: tw32;
BEGIN
ALU: BLOCK
SIGNAL qbus: tw32;
BEGIN
-- alu behavior stataments
END BLOCK ALU;

REG8: BLOCK
SIGNAL zbus: tw32;
BEGIN
REG1: BLOCK
SIGNAL qbus: tw32;
BEGIN
-- REG1 behavior stataments
END BLOCK REG1;
-- more REG8 stataments

END BLOCK REG8;


END cpu_blk;
Thc the cpu co khai bao thc the ngoai cung trong mo hnh (mo hnh cho v du nay cha
hoan chnh). Thc the cpu khai bao 4 port dung cho giao tiep mo hnh. Cac port clk va interrupt
la cac port ngo vao, addr la port ngo ra va data la port hai chieu inout. Tat ca cac port nay c
nhn thay bat ky khoi nao, c khai bao trong kien truc cho thc the nay. Cac port ngo vao co
the oc va cac port ngo ra co the c gan gia tr.
Cac tn hieu ibus va dbus la cac tn hieu cuc bo c khai bao trong kien truc cpu_blk. Cac
tn hieu nay la cuc bo oi vi kien truc cpu_blk va do o cac khoi ben ngoai khong c truy xuat
cac tn hieu nay.
Tuy nhien, bat ky khoi nam nao ben trong kien truc o eu co the truy xuat cac tn hieu nay.
Cac khoi co cap mc o thap th co the truy xuat en cac tn hieu co cap mc o cao hn, nhng

72 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

cac khoi co cap mc o cao hn th khong the truy xuat en cac tn hieu cuc bo cua khoi cap thap
hn.
Tn hieu qbus c khai bao trong phan khai bao khoi cua khoi ALU. Tn hieu nay la tn hieu
cuc bo cho khoi ALU va cac khoi ben ngoai khong the truy xuat. Tat ca cac phat bieu nam ben
trong khoi ALU co the truy xuat qbus, nhng cac phat bieu ben ngoai khoi ALU th khong the
dung qbus.
Tng t, tn hieu zbus cho khoi REG8. Khoi REG1 nam ben trong khoi REG8 co the truy
xuat tn hieu zbus va tat ca cac phat bieu khac trong khoi REG8 cung co the truy xuat tn hieu
zbus.
Trong phan khai bao cua khoi REG1 con khai bao mot tn hieu khac goi la qbus. Tn hieu
nay co cung ten vi tn hieu qbus c khai bao trong khoi ALU ieu nay co gay ra xung ot g
khong ? oi vi chng trnh chng trnh bien dch th hai tn hieu nay la oc lap. Hai tn hieu nay
c khai bao trong hai vung khac nhau va ch co hieu lc cho vung o.
Mot trng hp khac long vao nhau nh sau:
BLK1: BLOCK
SIGNAL qbus: tw32;
BEGIN
BLK2: BLOCK
SIGNAL qbus: tw32;
BEGIN
-- blk2 stataments
END BLOCK BLK2;
-- blk1 stataments
END BLOCK BLK1;
Trong v du nay, tn hieu qbus c khai bao trong 2 khoi. Cau truc long vao nhau trong mo
hnh nay la mot khoi co cha mot khoi khac.
Khoi BLK2 truy xuat 2 tn hieu c goi la qbus: tn hieu qbus th nhat khai bao trong BLK2
va tn hieu qbus th 2 khai bao trong BLK1. Khoi BLK1 la cha cua khoi BLK2. Tuy nhien, khoi
BLK2 xem tn hieu qbus nam trong chnh no, nhng tn hieu qbus cua khoi BLK1 se b ghi e bi
khai bao cung ten cua tn hieu khoi BLK2.
Tn hieu qbus t BLK1 co the c nhn thay ben trong khoi BLK2, neu ten cua tn hieu
qbus c bo sung them bang ten cua khoi. Cu the cho v du tren, e truy xuat tn hieu qbus t
khoi BLK1 th dung BLK1.qbus.
Nh a e cap tren, cac khoi cha cac vung cua mo hnh ben trong no. Nhng cac khoi la
duy nhat bi v mot khoi co the cha cac port va cac generic. ieu nay cho phep ngi thiet ke
anh xa lai cac tn hieu va cac generic ben ngoai en cac tn hieu va generic nam ben trong khoi.
Nhng tai sao ngi thiet ke muon lam ieu nay.
Dung lng cua cac port va cac generic trong mot khoi cho phep ngi thiet ke dung lai cac
khoi a viet cho muc ch khac trong thiet ke mi.
Gia s ta muon cai tien thiet ke CPU va can m rong them chc nang cho khoi ALU, va ta
gia s rang mot ngi thiet ke khac co khoi ALU mi co the thc hien c cac chc nang ma ta

Ky thuat PLD va ASIC 73


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

can th van e ch con la hieu chnh lai ten cua cac port va cac generic cho tng thch vi khoi
mi la xong. Phai anh xa cac ten cua tn hieu va cac thong so generic trong thiet ke ang cai tien
vi cac port va cac generic a xay dng cua khoi ALU mi.
V du 2-10: minh hoa cho s cai tien:
package math IS
TYPE tw32 IS ARRAY ( 31 downto 0 ) OF std_logic;
FUNCTIOB tw_add(a,b; tw32) RETURN tw32;
FUNCTIOB tw_sub(a,b; tw32) RETURN tw32;
END math;
USE WORK.math.ALL;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY cpu IS
PORT (clk, interrupt: IN STD_LOGIC;
addr: OUT tw32;
cont : IN INTEGER;
data: INOUT tw32);
END cpu;

ARCHITECTURE cpu_blk OF cpu IS


SIGNAL ibus, dbus: tw32;
BEGIN
ALU: BLOCK
PORT (abus, bbus: IN tw32;
D_out: OUT tw32;
ctbus: IN INTEGER);
PORT MAP (abus => ibus, bbus => dbus, d_out => data, ctbus => cont);
SIGNAL qbus: tw32;
BEGIN
D_out <= tw_add (abus, bbus) WHEN ctbus = 0 ELSE
tw_add (abus, bbus) WHEN ctbus = 1 ELSE
abus;
END BLOCK ALU;
END cpu_blk;
Ve c ban mo hnh nay giong nh mo hnh a trnh bay ngoai tr port va cac phat bieu anh
xa port trong phan khai bao khoi ALU. Phat bieu port khai bao so lng c dung cho khoi,
hng cua port va loai d lieu cua port. Phat bieu anh xa port se anh xa port mi vi cac tn hieu
hoac cac port ton tai ben ngoai khoi. Port abus c anh xa cho tn hieu cuc bo ibus cua kien truc
CPU_BLK, port bbus c anh xa cho dbus. Cac port d_out va ctbus c anh xa cho cac port ben
ngoai cua thc the.

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Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Anh xa co ngha la ket noi gia port va tn hieu ben ngoai chang han nh khi co mot s thay
oi gia tr tren mot tn hieu noi en 1 port th port se thay oi sang gia tr mi. Neu s thay oi xay
ra trong tn hieu ibus th gia tr mi cua ibus c truyen vao khoi ALU va port abus se co gia tr
mi. Tng t cho tat ca cac port.
Cac khoi co bao ve
Cac phat bieu khoi co khoi hanh vi long vao ben trong c xem nh nhng khoi co bao ve.
Mot khoi co bao ve cha mot bieu thc bao ve co the cho phep va khong cho phep cac driver
ben trong khoi.
Bieu thc bao ve la bieu thc ai so boolean: neu bang true th cac driver ben trong khoi
c phep va neu bang false th cac driver b cam.
Chung ta se khao sat v du 2-11:
V du 2-11: co khoi bao ve
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY latch IS
PORT (d, clk: IN STD_LOGIC;
q, qb: OUT STD_LOGIC);
END latch;

ARCHITECTURE latch_guard OF latch IS


BEGIN
G1: BLOCK (clk = 1)
BEGIN
q <= GUARDED d AFTER 5 ns;
qb <= GUARDED NOT (d) AFTER 7 ns;
END BLOCK G1;
END latch_guard;
Mo hnh nay minh hoa cach thc mo hnh mach chot co the c viet dung khoi co bao ve.
Thc the khai bao 4 port can thiet cho mach chot va ch co mot phat bieu trong kien truc. Phat bieu
chnh la phat bieu khoi co bao ve.
Phat bieu khoi co bao ve giong nh phat bieu khoi bnh thng, ngoai tr bieu thc bao ve
nam sau t khoa BLOCK. Bieu thc bao ve trong ve trong v du nay la (clk=1). ay la bieu
thc luan ly va tra ve ket qua la true khi gia tr cua clk bang 1 va se co gia tr la false khi clk co
gia tr khac.
Khi bieu thc bao ve la true th tat ca driver cua cac phat bieu gan tn hieu bao ve c phep
hoac c m. Khi bieu thc bao ve la false th tat ca cac driver cua cac phat bieu gan tn hieu
bao ve b cam hoac b tat.
Co 2 phat bieu gan tn hieu bao ve trong mo hnh: phat bieu th nhat la gan gia tr q va cau
lenh gan con lai la gan gia tr qb. Phat bieu gan tn hieu co bao ve c nhan ra bang t khoa
GUARDED nam gia <= va thanh phan cua bieu thc.

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Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Khi port clk cua thc the co gia tr la 1 th bieu thc bao ve co gia tr la true va khi gia tr
cua ngo vao d se xuat hien ngo ra q sau khoang thi gian tre 7ns.
Khi port clk co gia tr la 0 hoac bat ky gia tr nao khac hp le cua kieu d lieu th ngo ra q
va qb chuyen sang tat va gia tr ngo ra cua tn hieu c xac nh bi gia tr c gan cho mot gia
tr mac nh bi ham phan giai. Khi clk khong bang 1 th cac driver c xay dng cho cac lenh
gan tn hieu q va qb trong kien truc se chuyen sang tat. Cac driver khong tham gia vao gia tr tong
the cua tn hieu.
Gan tn hieu co the c bao ve bang cach dung t khoa GUARDED. Tn hieu mi c
khai bao hoan toan trong khoi khi khoi co bieu thc bao ve. Tn hieu nay c goi la GUARD.
Gia tr cua no la gia tr cua bieu thc bao ve. Tn hieu nay co the c dung e cac x ly khac xay
ra.
Cac khoi rat tien li e chia nho thiet ke thanh cac khoi nho hn, cac n v de quan ly hn.
Chung cho phep ngi thiet ke s mem deo e xay dng nhng thiet ke ln t nhng khoi nho hn
va cung cap phng phap thuan tien cho ieu khien cac driver oi vi tn hieu.
6. TOM TAT
Cach gan tn hieu la dang c ban nhat cua mo hnh hanh vi.
Phat bieu gan tn hieu co the c la chon tuy vao ieu kien.
Phat bieu gan tn hieu co the cha thi gian tre.
VHDL cha tr hoan tre quan tnh va tr hoan truyen.
Cac iem thi gian mo phong delta dung e cac s kien hoat ong ung thi gian.
Cac driver cho mot tn hieu c xay dng bi cac phat bieu gan tn hieu.
Generic c dung e truyen d lieu cho thc the.
Cac phat bieu khoi cho phep xay dng nhom trong cung mot thc the.
Cac phat bieu khoi bao ve cho phep kha nang tat cac driver trong mot khoi.
V. X LY TUAN T
phan trc chung ta a khao sat mo hnh hanh vi dung cac phat bieu ong thi. Chung ta
a thao luan cac phat bieu gan ong thi cung nh cac phat bieu khoi va the hien thanh phan.
Trong phan nay chung ta tap trung cho phat bieu tuan t. Cac phat bieu tuan t la cac phat
bieu thc hien noi tiep nhau.
1. PHAT BIEU
Trong mot kien truc cua mot thc the, tat ca cac phat bieu la ong thi. Vay th cac phat bieu
tuan t ton tai au trong VHDL ?
Co mot phat bieu c goi la phat bieu qua trnh ch cha cac phat bieu tuan t. Phat bieu
qua trnh cung chnh la phat bieu ong thi. Phat bieu qua trnh co the ton tai trong kien truc va
nhng vung xac nh trong kien truc ni cha cac lenh tuan t.
Phat bieu qua trnh co phan khai bao va phan phat bieu. Trong phan khai bao th cac kieu,
cac bien, cac hang so, cac chng trnh con, , co the c khai bao. Phan phat bieu ch cha cac
phat bieu tuan t. Cac phat bieu tuan t cha cac phat bieu CASE, phat bieu IF THEN ELSE,
phat bieu LOOP,

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Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

a. Danh sach nhay


Phat bieu qua trnh co the co mot danh sach nhay ro rang. Danh sach nay nh ngha cac tn
hieu ma chung lam cho cac phat bieu ben trong phat bieu qua trnh thc hien khi co mot hoac
nhieu phan t trong danh sach thay oi gia tr. Danh sach nhay la danh sach cua cac tn hieu ma
chung se lam cho qua trnh thc hien.
b. V du ve qua trnh
Chung ta hay quan sat v du 2-12 cua phat bieu qua trnh trong kien truc
V du 2-12:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY nand2 IS
PORT (a, b: IN STD_LOGIC;
c: OUT STD_LOGIC);
END nand2;

ARCHITECTURE nand2 OF nand2 IS


BEGIN
PROCESS (a,b)
VARIABLE temp : STD_LOGIC;
BEGIN
temp := NOT (a AND b);
IF (temp = 1 ) THEN c <= temp AFTER 6 ns;
ELSIF (temp = 0 ) THEN c <= temp AFTER 5 ns;
ELSE c <= temp AFTER 6 ns;
END IF;
END PROCESS;
END and2;
Trong v du nay trnh bay cach viet mo hnh cho mot cong NAND n gian co 2 ngo vao
dung phat bieu tuan t.
Phat bieu USE khai bao goi VHDL e cung cap nhng thong tin can thiet cho phep xay dng
mo hnh cho cong NAND. Phat bieu USE c dung e cho mo hnh co the c mo phong vi
trnh mo phong VHDL ma khong can them bc hieu chnh nao.
Thc the khai bao 3 port cho cong nand2. Port a va port b la ngo vao va port c la ngo ra. Ten
cua kien truc cung ten vi thc the.
Kien truc ch cha mot phat bieu, mot phat bieu qua trnh ong thi.
Phan khai bao qua trnh bat au tai t khoa PROCESS va ket thuc tai t khoa BEGIN.
Phan phat bieu qua trnh bat au tai t khoa BEGIN va ket thuc tai t khoa END
PROCESS. Phan khai bao qua trnh co hai phat bieu tuan t: mot phat bieu gan bien:
temp := NOT (a AND b);

Ky thuat PLD va ASIC 77


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Va mot phat bieu IF THEN ELSE


IF (temp = 1 ) THEN c <= temp AFTER 6 ns;
ELSIF (temp = 0 ) THEN c <= temp AFTER 5 ns;
ELSE c <= temp AFTER 6 ns;
END IF;
Qua trnh cha danh sach nhay ro rang vi 2 tn hieu cha ben trong:
PROCESS (a,b)
Qua trnh ang thc hien (nhay) vi 2 tn hieu a va b. Trong v du nay, a va b la 2 port ngo
vao cua mo hnh. Cac port ngo vao xay dng cac tn hieu co the c dung nh cac ngo vao, cac
port ngo ra xay dng cac tn hieu co the c dung nh cac ngo ra, cac port inout xay dng cac tn
hieu co the c dung cho ca 2 vao ra.
Khi port a hoac b thay oi gia tr th phat bieu ben trong qua trnh c thc hien. Moi phat
bieu c thc hien theo th t noi tiep bat au vi phat bieu tren cung cua phat bieu qua trnh va
thc hien t tren xuong di. Sau khi tat ca cac phat bieu a c thc hien mot lan, qua trnh i
cho en khi co s thay oi tn hieu hoac port nam trong danh sach nhay.
2. GAN BIEN KHAC VI GAN TN HIEU
Phat bieu th nhat trong phat bieu qua trnh la gan bien gan gia tr cho bien temp. phan
trc chung ta a thao luan ve cach cac tn hieu nhan gia tr sau thi gian tr hoan hoac sau thi
gian tr hoan delta. Gan bien xay ra ngay lap tc khi phat bieu c thc hien. V du: trong mo
hnh nay, phat bieu th nhat phai gan gia tr cho bien temp e phat bieu th hai s dung. Gan bien
khong co thi gian tr hoan, xay ra ngay lap tc.
Chung ta se khao sat hai v du minh hoa e phan biet cac lenh gan tn hieu va gan bien. Ca
hai v du eu la mo hnh cua mach a hp 4 ng sang 1 ng. K hieu va bang trang thai nh
hnh 2-9. Mot trong 4 ngo vao c truyen en ngo ra tuy thuoc vao gia tr cua A va B.

B A Q
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Hnh 2-9. K hieu mach a hp va bang trang thai.
Mo hnh th nhat la mo hnh khong ung va mo hnh th hai la mo hnh ung.
a. V du mo hnh mach a hp khong ung

78 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Mo hnh khong ung cua bo a hp co thieu sot lam cho mo hnh hoat ong khong ung. Mo
hnh nay c trnh bay nh sau:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY mux IS
PORT (i0, i1, i2, i3, a, b: IN STD_LOGIC;
q: OUT STD_LOGIC);
END mux;

ARCHITECTURE wrong OF mux IS


SIGNAL muxval: INTEGER;
BEGIN
PROCESS (i0, i1, i2, i3, a, b)
BEGIN
muxval <= 0;
IF (a = 1 ) THEN muxval<= muxval + 1;
END IF;
IF (b = 1 ) THEN muxval<= muxval + 2;
END IF;

CASE muxval IS
WHEN 0 => q <= I0 AFTER 10 ns;
WHEN 1 => q <= I1 AFTER 10 ns;
WHEN 2 => q <= I2 AFTER 10 ns;
WHEN 3 => q <= I3 AFTER 10 ns;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END wrong;
Khi co 1 trong cac tn hieu ngo vao nam trong danh sach nhay thay oi gia tr th cac phat
bieu tuan t c thc hien.
Phat bieu qua trnh trong v du nay cha 4 phat bieu tuan t.
Phat bieu th nhat khi tao tn hieu cuc bo muxval vi gia tr 0. Cac phat bieu tuan t con
cong gia tr cho tn hieu tuy thuoc vao cua cac tn hieu vao a va b.
Phat bieu case cuoi cung la chon mot ngo vao e truyen en ngo ra tuy thuoc vao gia tr
cua tn hieu muxval. Mo hnh nay co mot thieu sot nghiem trong vi phat bieu: muxval <=0; lam
cho gia tr 0 c sap xep nh mot s kien oi vi tn hieu muxval. Thc te th gia tr 0 c sap
xep trong mot s kien cho thi gian tre delta e mo phong bi v khong co thi gian tr hoan.
Khi phat bieu th 2:
IF (a = 1 ) THEN muxval <= muxval + 1;
END IF;

Ky thuat PLD va ASIC 79


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

c thc hien, gia tr cua tn hieu muxval la gia tr c truyen lan cuoi cung. Gia tr mi
a sap xep t phat bieu th nhat cha c truyen en. Trong thc te th khi nhieu phep gan cho
tn hieu xay ra trong cung phat bieu qua trnh th gia tr gan sau cung la gia tr c truyen.
Tn hieu muxval co gia tr vo ngha (khong xac nh) khi bat au qua trnh. Gia tr cua
muxval khong thay oi cho en khi cac phat bieu nam trong qua trnh c thc hien xong. Neu
tn hieu b co gia tr la 1 th sau o gia tr vo ngha c cong them vi 2.
V du tiep theo se chat che hn. S khac nhau gia 2 mo hnh cua 2 v du la khai bao muxval
va phep gan cho mulval. Trong mo hnh v du trc, muxval la tn hieu va phat bieu gan tn hieu
c dung e gan gia tr cho muxval. Trong mo hnh v du nay th muxval la bien va phep gan
bien c dung e gan gia tr cho muxval.
b. V du mo hnh mach a hp ung
Trong v du nay th mo hnh khong ung tren c viet lai e cho thay cach giai quyet van
e cua mo hnh khong ung:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY mux IS
PORT (i0, i1, i2, i3, a, b: IN STD_LOGIC;
q: OUT STD_LOGIC);
END mux;

ARCHITECTURE better OF mux IS


BEGIN
PROCESS (i0, i1, i2, i3, a, b)
VARIABLE muxval : INTEGER;
BEGIN
muxval := 0;
IF (a = 1 ) THEN muxval := muxval + 1;
END IF;
IF (b = 1 ) THEN muxval := muxval + 2;
END IF;

CASE muxval IS
WHEN 0 => q <= I0 AFTER 10 ns;
WHEN 1 => q <= I1 AFTER 10 ns;
WHEN 2 => q <= I2 AFTER 10 ns;
WHEN 3 => q <= I3 AFTER 10 ns;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END better;
Khi phat bieu th nhat muxval:=0; c thc hien th gia tr 0 c at vao cho bien muxval
ngay lap tc. Gia tr khong c sap xep v muxval trong v du nay la bien, khong phai la tn hieu.
Cac bien tng trng cho o nh lu tr cuc bo khac vi tn hieu tng trng cho ket noi mach

80 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

ien ben trong. O nh lu tr cuc bo c cap nhat ngay lap tc va gia tr mi co the c dung
sau o trong mo hnh cho cac tnh toan sau o.
Do bien muxval c khi tao gia tr 0 ngay lap tc nen hai phat bieu gan trong qua trnh
dung gia tr 0 nh gia tr khi tao va cong vi cac con so thch hp tuy thuoc vao tuy thuoc vao gia
tr cua tn hieu a va b. Cac phat bieu gan nay cung c thc hien ngay lap tc va do o khi phat
bieu case c thc hien th bien muxval a cha gia tr ung. T gia tr nay tn hieu ngo vao
ung co the c truyen en ngo ra.
3. CAC PHAT BIEU TUAN T
Cac phat bieu tuan t nam ben trong phat bieu qua trnh va nam trong cac chng trnh con.
Trong phan nay chung ta se khao sat cac phat bieu tuan t nam ben trong phat bieu qua trnh.
Cac phat bieu tuan t se c trnh bay la: IF, CASE, LOOP, EXIT, ASSERT, WAIT.
4. PHAT BIEU IF
Phat bieu IF cho phep chon mot trong cac cau lenh e thc hien. Ket qua tra ve cua menh e
ieu kien la gia tr kieu BOOLEAN. Da vao ket qua tra ve cua menh e ieu kien e cho phep
mot lenh co c thc thi hay khong.
Cu phap cua phat bieu IF nh sau
if condition then sequential statements;
[elsif condition then sequential statements;]
[else sequential statements;]
end if;
V du 2-13: cho phat bieu IF
IF (x < 10 ) THEN a:= b;
END IF;
Phat bieu c bat au bang t khoa IF. Theo sau t khoa IF la menh e ieu kien (x < 10).
ieu kien tra ve true khi x nho hn 10, ngc lai th co gia tr false. Khi ieu kien la true th phat
bieu gia THEN va END IF c thc hien. Trong v du nay th lenh phat bieu gan (a:=b) c
thc hien bat ky luc nao x nho hn 10.
V du 2-14: cho phat bieu IF THEN ELSE:
IF (day = sunday ) THEN weekend := true;
ELSIF (day = saturday ) THEN weekend := true;
ELSE weekday := true;
END IF;
Trong v du nay co hai bien weekend va weekday c thiet lap gia tr tuy thuoc vao
gia tr cua tn hieu day. Bien weekend c thiet lap la true khi day bang Saturday hoac Sunday.
Ngc lai bien weekday c thiet lap la true.
Thc hien phat bieu IF bat au kiem tra xem bien day co bang vi Sunday hay khong.
Neu ket qua la true th phat bieu ke c thc hien va ieu khien c chuyen ti phat bieu
nam sau t khoa END IF.

Ky thuat PLD va ASIC 81


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Ngc lai ieu khien c chuyen ti phan phat bieu ELSIF va kiem tra day co phai la
Saturday hay khong. Neu bien day la Saturday th phat bieu ke c thc hien va ieu khien
c chuyen ti phat bieu nam sau t khoa END IF.
Cuoi cung neu day khong bang Sunday va Saturday th phan phat bieu ELSE c thc
hien. Phat bieu IF co the co nhieu phan phat bieu ELSIF nhng ch co duy nhat mot lan phat bieu
ELSE.
5. PHAT BIEU CASE
Phat bieu CASE c s dung khi gia tr cua bieu thc duy nhat co the c dung e la
chon mot trong so hoat ong. Cu phap cho phat bieu CASE nh sau:
case expression is
when choices => sequential statements;
when choices => sequential statements;
-- branches are allowed
[ when others => sequential statements ];
end case;
Ket qua bieu thc la so nguyen, hoac kieu liet ke cua mang mot chieu chang han nh
bit_vector. Phat bieu case anh gia bieu thc va so sanh gia tr cua bieu thc vi moi gia tr cua
cac la chon. Menh e when tng ng vi la chon trung hp se c thc hien. Cac nguyen tac
sau phai nh:
Khong co 2 la chon trung lap (la chon nay bao phu la chon kia).
Neu phat bieu la chon when others khong hien dien th tat ca gia tr co the co cua
bieu thc phai bao phu het bi cac la chon.
Phat bieu CASE cha t khoa CASE theo sau la bieu thc va t khoa IS. Bieu thc co gia tr
tng thch vi CHOICES nam trong phat bieu WHEN hoac tng thch vi phat bieu WHEN
OTHERS.
Neu bieu thc tng thch vi phan CHOICES cua cac phat bieu WHEN choices => th
sequence_of_statement theo sau se c thc hien. Sau khi cac phat bieu nay c thc hien
xong th ieu khien chuyen ti phat bieu nam sau t khoa END CASE.
V du 2-15: phat bieu case :
CASE instruction IS
WHEN load_accum => accum <= data;
WHEN store_accum => data_out <= accum;
WHEN load|store => process_IO (addr) ;
WHEN OTHERS => process_error (instruction);
END CASE;
Phat bieu CASE thc hien phat bieu tng ng tuy thuoc vao gia tr cua bieu thc ngo vao.
Neu gia tr cua bieu thc la mot gia tr nam trong cac gia tr c liet ke trong cac menh e
WHEN th sau o phat bieu theo sau menh e WHEN c thc hien. Ngc lai th phat bieu theo
sau menh e OTHERS c thc hien.
Trong v du nay khi gia tr cua bieu thc la load_accum th phat bieu gan au tien c thc
hien. Neu gia tr cua bieu thc la load hoac store th thu tuc process_IO c goi.

82 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Neu gia tr cua bieu thc nam ngoai day la chon a cho th sau o menh e OTHERS tng
thch vi bieu thc va phat bieu theo sau menh e OTHERS c thc hien. Se phat sinh loi neu
khong co menh e OTHERS va cac la chon a cho khong bao trum gia tr co the co cua bieu
thc.
V du 2-16 vi bieu thc co ket qua tra ve phc tap hn. Phat bieu CASE dung kieu d lieu
nay e la chon mot trong cac phat bieu.
V du 2-16:
TYPE vectype IS ARRAY (0 TO 1) OF BIT;
VARIABLE bit_vector: vectype;

CASE bit_vector IS
WHEN 00 => RETURN 0;
WHEN 01 => RETURN 1;
WHEN 10 => RETURN 2;
WHEN 11 => RETURN 3;
END CASE;
V du nay trnh bay mot phng phap chuyen oi mot mang bit thanh mot so nguyen.
Khi hai bit cua bien bit_vec co gia tr 0 th la chon 00 tng thch va gia tr tra ve la 0.
Khi hai bit cua bien bit_vec co gia tr 1 th la chon 11 tng thch va gia tr tra ve la 3.
Phat bieu CASE khong can menh e OTHERS v tat ca cac gia tr cua bien bit_vec c liet
ke bi cac la chon.
6. PHAT BIEU LOOP
Phat bieu LOOP c s dung e lap lai chuoi cac lenh tuan t. Cu phap cho phat bieu
LOOP nh sau:
[ loop_label :]iteration_scheme loop
sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop [loop_label];

Phat bieu next va exit la cac phat bieu tuan t ch co the c s dung ben trong vong lap.
Phat bieu next cham dt phan con lai cua vong lap hien tai va sau o se lap lai vong
lap ke.
Phat bieu exit bo qua phan con lai cua phat bieu, cham dt hoan toan vong lap va
tiep tuc vi phat bieu ke sau vong lap v thoat.
Co 3 loai vong lap:
Vong lap loop c ban
Vong lap while loop
Vong lap for loop
a. Phat bieu vong lap LOOP c ban

Ky thuat PLD va ASIC 83


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Vong lap thc hien lien tuc cho en khi bat gap phat bieu exit hoac next. Cu phap nh sau:
[ loop_label :] loop
sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop [ loop_label];

Vong lap c ban phai co t nhat mot phat bieu wait. V du mot bo em 5 bit em t 0 en 31.
Khi bo em at gia tr 31 th bo em bat au tran ve 0. Phat bieu wait co cha trong chng trnh
e cho vong lap se thc hien moi khi xung clock thay oi t 0 sang 1.
V du 2-17: s dung vong lap c ban cho mach em t 0 en 31.
ENTITY count31 IS
PORT (CLK: IN STD_LOGIC;
Count: OUT INTEGER);
END count31;

ARCHITECTURE behav_count OF count31 IS


BEGIN
P_COUNT: PROCESS
VARIABLE intern_value : INTEGER :=0;
BEGIN
Count <= intern_value;
LOOP
WAIT UNTIL CLK = 1;
intern_value := (intern_value + 1) mod 32;
Count <= intern_value;
END LOOP;
END PROCESS P_COUNT;
END behav_count;

b. Phat bieu vong lap While LOOP


Vong lap while loop anh gia ieu kien lap dang Boolean. Khi ieu kien la TRUE, vong
lap thc hien, ngc lai vong lap thc hien lien tuc cho en khi bat gap phat bieu exit hoac next.
Cu phap nh sau:
[ loop_label :] while condition loop
sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop[ loop_label ];

ieu kien lap c kiem tra trc moi lan lap ke ca lan lap au tien. Neu ieu kien la false
th vong lap cham dt.
c. Phat bieu vong lap FOR LOOP:
Vong lap for loop dung gian o lap so nguyen e xac nh so lan lap. Cu phap nh sau:
[ loop_label :] for identifier in range loop
sequential statements
[next [label] [when condition];
[exit [label] [when condition];

84 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu
end loop[ loop_label ];

Ch so lap c khai bao t ong bi chnh vong lap do o khong can khai bao rieng le. Gia
tr cua ch so ch co the c oc ben trong vong lap va khong co hieu lc ngoai vong lap.
Khong the gan hoac thay oi gia tr cua ch so lap. Ch so lap nay oi ngc vi vong lap while
loop khi ieu kien cua vong lap while-loop co cha bien va c hieu chnh ben trong vong lap.
Day so cua vong lap phai la mot day so nguyen co the tnh toan c mot trong cac dang
sau, trong moi dang th integer_expression phai la mot so nguyen:
o integer_expression to integer_expression
o integer_expression downto integer_expression
d. Phat bieu Next va Exit:
Phat bieu next bo qua viec thc hien e en thc hien vong lap ke cua phat bieu vong lap.
Cu phap nh sau:
next [label] [when condition];

T khoa when la tuy chon va se c thc hien phat bieu ke khi ieu kien anh gia la true.
Phat bieu exit bo qua phan con lai cua phat bieu, cham dt hoan toan vong lap va tiep tuc
vi phat bieu ke sau khi vong lap b thoat. Cu phap nh sau:
exit [label] [when condition];

T khoa when la tuy chon va se c thc hien phat bieu ke khi ieu kien anh gia la true.
Chu y: s khac nhau gia phat bieu next va exit la phat bieu exit cham dt vong lap.
V du 2-18: Minh hoa cho vong lap next
PROCESS (A, B)
CONSTANT max_limit: INTEGER :=255;
BEGIN
FOR i IN 0 TO max_limit
LOOP
IF (done(i) = true ) THEN next;
ELSE done(i) = true;
END IF;
q(i) <= a(i) and b(i);
END LOOP;
END PROCESS;
Phat bieu qua trnh cha mot phat bieu vong lap LOOP. Phat bieu LOOP la and cac bit cua
mang a va mang b va at ket qua vao mang q. Mo ta hanh vi tiep tuc cho en khi nao c trong
mang done la false.
Neu gia tr cua c done la true vi ch so i th phat bieu next c thc hien. Viec thc hien
tiep tuc vi phat bieu au tien cua vong lap va ch so i bay gi co gia tr la i + 1.
Neu gia tr cua c done la false th phat bieu next khong c thc hien va viec thc hien
tiep tuc vi phat bieu cha trong menh e ELSE cho phat bieu IF.

Ky thuat PLD va ASIC 85


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Phat bieu next cho phep ngi thiet ke kha nang ngng viec thc hien cac lenh cua vong lap
va tiep tuc vi vong lap tiep theo. Co mot so trng hp khac th can thoat khoi vong lap th kha
nang nay c thc hien bi phat bieu EXIT.
Trong thi gian thc thi mot phat bieu LOOP, co the ta can nhay ra khoi vong lap. ieu nay
co the xay ra do mot loi quan trong xuat hien trong thi gian thc thi mo hnh hoac toan bo viec x
ly ket thuc sm.
Phat bieu EXIT cua VHDL cho phep ngi thiet ke thoat hoac nhay ra khoi mot phat bieu
LOOP hien ang thc thi. Phat bieu EXIT lam cho viec thc thi dng v tr cua phat bieu nay.
Viec thc thi se tiep tuc phat bieu theo sau phat bieu LOOP.
V du 2-19: Minh hoa cho vong lap exit
PROCESS (A)
CONSTANT int_a: INTEGER;
BEGIN
Int_a := a;
FOR i IN 0 TO max_limit
LOOP
IF (int_a <0 ) THEN exit;
ELSE (int_a := int_a - 1);
q(i) <= 3.14 / REAL (int_a* i); -- signal assign
END IF;
END LOOP;
y <= q;
END PROCESS;
Ben trong phat bieu cua qua trnh nay, gia tr cua int_a luon luon c gia nh la gia tr
dng ln hn 0. Neu gia tr cua int_a am hoac bang 0 th sinh ra loi va viec tnh toan se khong
c hoan tat. Neu gia tr cua int_a nho hn hoac bang 0 th phat bieu IF la ung va phat bieu
EXIT se c thc thi. Vong lap ket thuc ngay lap tc va phat bieu ke tiep c thc thi chnh la
phat bieu gan cho y sau phat bieu LOOP.
Phat bieu EXIT co 3 loai c ban. Loai th nhat yeu cau phat bieu EXIT khong co nhan vong
lap hoac WHEN condition. Neu cac ieu kien nay ung, phat bieu EXIT se hoat ong nh sau:
phat bieu EXIT ch thoat khoi phat bieu LOOP hien tai. Neu phat bieu EXIT ben trong mot phat
bieu LOOP va phat bieu LOOP nay c long trong mot phat bieu LOOP khac, phat bieu EXIT
ch thoat khoi phat bieu LOOP ben trong. Viec thc thi van duy tr trong phat bieu LOOP ben
ngoai. Phat bieu EXIT ch thoat khoi phat bieu LOOP gan nhat.
V du 2-20: Minh hoa
PROCESS (a)
BEGIN
First_loop: FOR i IN 0 TO 100 LOOP
second_loop: FOR j IN 0 TO 10 LOOP
.
Exit second_loop; -- exit the second loop only
.
Exit first_loop; -- exit the first loop and second loop
END LOOP;
86 Ky thuat PLD va ASIC
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

END LOOP;
END PROCESS;
Neu phat bieu co them ieu kien WHEN th phat bieu EXIT ch thoat khoi vong lap khi ieu
kien la TRUE. Phat bieu ke c thc hien tuy thuoc vao ieu kien cua phat bieu EXIT co nhan
ch nh hay khong.
Neu nhan cua vong lap c ch nh th phat bieu ke c thc hien th cha trong phat bieu
LOOP ch nh bi nhan vong lap.
Neu khong co nhan th phat bieu ke c thc hien th nam vong lap ke ben ngoai.
V du 2-21: cho phat bieu EXIT vi ieu kien WHEN
Exit first_loop WHEN (i < 10);
Phat bieu nay ket thuc viec thc hien cua vong lap co nhan la first_loop khi bieu thc i <
10.
Phat bieu EXIT cung cap mot phng phap de dang va nhanh chong e thoat khoi phat bieu
LOOP khi toan bo cong viec x ly ket thuc hoac mot loi hay canh bao xay ra.
7. PHAT BIEU ASSERT
Phat bieu ASSERT la phat bieu rat hu ch e bao cao chuoi van ban en ngi thiet ke.
Phat bieu ASSERT kiem tra gia tr cua mot bieu thc logic xem ung hay sai. Neu gia tr la ung,
phat bieu nay khong lam g ca. Neu gia tr la sai, phat bieu ASSERT xuat mot chuoi dang van ban
c ch nh bi ngi s dung en ngo ra chuan cua thiet b au cuoi.
Ngi thiet ke cung co the ch ra mc o nghiem trong e xuat chuoi dang van ban. Theo
trnh t tang dan cua mc o nghiem trong ta co 4 mc: chu y, canh bao, loi va that bai. Mc o
nghiem trong cung cap cho ngi thiet ke kha nang phan loai thong iep thanh cac loai thch hp.
Phat bieu ASSERT c s dung chu yeu e quan ly khi viet mo hnh, khong co phan cng
nao c xay dng.
Cu phap:
assert_statement ::=
ASSERT condition
[REPORT expression];
T khoa ASSERT c theo bi mot bieu thc co gia tr logic c goi la mot ieu kien
(condition). ieu kien nay xac nh bieu thc dang van ban c phep xuat ra hay khong bi phat
bieu REPORT. Neu sai, bieu thc dang van ban c xuat, con neu ung, bieu thc dang van ban
khong c xuat.
Chung ta khao sat v du thc te cho phat bieu ASSERT, v du nay thc hien viec kiem tra
thiet lap d lieu gia hai tn hieu ieu khien flip flop D. Hau het cac flip flop yeu cau d lieu ngo
vao din phai gia tr on nh vi mot khoang thi gian xac nh trc khi co canh xung clock xuat
hien. Thi gian nay c goi la thi gian thiet lap va am bao rang d lieu vao din se c chot
vao ben trong flip flop. V du 2-22 ve phat bieu ASSERT tao ra thong bao loi cho ngi thiet ke
biet neu thi gian thiet lap khong u hay b vi pham.
V du 2-22:
PROCESS (clk, din)
Ky thuat PLD va ASIC 87
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

VARIABLE last_d_change: TIME :=0 ns;


VARIABLE last_d_value : STD_LOGIC :=X;
VARIABLE last_clk_value: STD_LOGIC :=X;
BEGIN
IF (last_d_value /= din) THEN -- /= is not equal
last_d_change : = NOW;
last_d_value : = din;
END IF;
IF (last_clk_value /= clk) THEN
last_clk_value: = clk;
IF (clk= 1) THEN
ASSERT (NOW last_d_change >= 20ns)
REPORT setup violation
SEVERITY WARNING;
END IF;
END IF;
END PROCESS;
Qua trnh dung 3 bien cuc bo e ghi lai thi gian va gia tr sau cung cua tn hieu din cung nh
gia tr cua tn hieu clk. Do lu tr gia tr sau cung cua clk va din nen chung ta co the xac nh xem
tn hieu co thay oi gia tr hay khong.
Bang cach ghi lai thi gian sau cung ma tn hieu din thay oi nen chung ta co the o c
thi gian hien tai so vi lan chuyen trang thai sau cung cua din, t o chung ta se biet c thi
gian thiet lap co b vi pham hay khong.
Bc th nhat trong qua trnh la kiem tra xem tn hieu din co thay oi hay khong. Neu co
thay oi th thi gian cua chuyen oi c lu lai dung ham NOW. Ham nay tra ve thi gian mo
phong hien tai. Tng t, gia tr sau cung cua din cung c lu tr cho viec kiem tra sau nay.
Bc tiep theo la kiem tra xem tn hieu clk co chuyen trang thai hay khong. Neu bien
last_clk_value khong bang vi gia tr hien tai cua clk th se co s chuyen trang thai xay ra. Neu
tn hieu clk la 1 th xem nh a co canh len cua xung clk.
Khi co canh len cua xung clk th chung ta can kiem tra xem thi gian thiet lap co b vi pham
hay khong. Neu lan chuyen sau cung cua tn hieu d nho hn 20 ns th bieu thc:
NOW last_d_change
Tra ve gia tr nho hn 20ns. Phat bieu ASSERT b kch va gi ra thong tin thi gian thiet lap
b vi pham canh bao en ngi thiet ke.
Neu lan chuyen trang thai sau cung tren tn hieu d xay ra dai hn 20 ns th bieu thc tren se
tra ve ket qua vi gia tr ln hn 20 ns va phat bieu ASSERT khong b kch.
8. PHAT BIEU WAIT
Phat bieu WAIT cung cap cho ngi thiet ke kha nang dng tam thi viec thc thi tuan t cua
mot qua trnh hoac mot chng trnh con. Cac ieu kien e tiep tuc viec thc thi qua trnh hoac
chng trnh con tam dng co the c thc hien bang mot trong 3 cach nh sau:
WAIT ON (ch) cac thay oi tn hieu.
WAIT UNTIL (ch cho en khi) mot bieu thc la ung.

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Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

WAIT FOR (ch trong) mot khoang thi gian cu the.


Cac phat bieu WAIT co the c s dung cho mot so muc ch khac nhau. Hien nay lenh
WAIT c dung pho bien nhat la dung e ch ra cac ngo vao xung clock cho cac cong cu tong
hp. Phat bieu WAIT ch nh xung clock cho phat bieu qua trnh c oc bi cac cong cu tong
hp nham tao ra mach logic tuan t chang han nh cac thanh ghi va cac flip flop.
Cac cong dung khac la tr hoan viec thc thi qua trnh trong mot khoang thi gian hoac hieu
chnh danh sach nhay cua mot qua trnh.
Chung ta khao sat phat bieu qua trnh s dung phat bieu WAIT c dung e tao mc logic
tuan t:
PROCESS (clock, d)
BEGIN
WAIT UNTIL clock = 1 AND clockEVENT;
q <= d;
END PROCESS;
Qua trnh nay dung e phat hien xung clock canh len cua flip flop. Thuoc tnh EVENT i
cung vi xung clock la true khi ngo vao xung clock co thay oi. To hp cua 2 ieu kien la xung
clock co gia tr 1 va xung clock co thay oi nen co the xem nh xung clock va xuat hien xung
canh len. Ket qua cua qua trnh nay la i hoac ch phat bieu WAIT cho en khi xuat hien xung
clock canh len va gia tr cua d c gan cho ngo ra q.
Them chc nang reset ong bo cho v du tren nh sau:
PROCESS (clock, d)
BEGIN
WAIT UNTIL clock = 1 AND clockEVENT;
IF (reset = 1) THEN q <= 0;
ELSE q <= d;
END IF;
END PROCESS;
Trong v du tren th khi co xung clock th tn hieu reset c kiem tra trc: neu tn hieu
reset tch cc th gan gia tr 0 cho ngo ra q, ngc lai th gan tn hieu d.
Chc nang reset khong ong bo cung c thc hien nh sau:
PROCESS (clock, d)
BEGIN
IF (reset = 1) THEN q <= 0;
ELSE clockEVENT AND clock = 1 THEN q <= d;
END IF;
WAIT ON reset, clock;
END PROCESS;
Qua trnh nay cha phat bieu WAIT ON se lam cho qua trnh ngng thc hien cho en khi co
mot trong hai s kien reset hoac xung clock thay oi. Sau o phat bieu IF c thc hien va neu
tn hieu reset la tch cc th flip flop b reset bat ong bo, ngc lai xung clock c kiem tra e
phat hien canh len va neu ung th se chuyen trang thai ngo vao d cho ngo ra q.

Ky thuat PLD va ASIC 89


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Phat bieu WAIT cung co the c s dung e ieu khien cac tn hieu cua qua trnh hay
chng trnh con nhay vi bat ky iem nao trong khi thc hien chng trnh.
V du 2-23:
PROCESS
BEGIN
WAIT ON a;
WAIT ON b;
END PROCESS;

a. Phat bieu WAIT ON signal


V du ve phat bieu nay a c trnh bay tren, phat bieu WAIT ON ch nh mot danh sach
mot hoac nhieu tn hieu ma phat bieu WAIT se i ch s thay oi. Neu co tn hieu nao thay oi
th viec thc hien se c tiep tuc vi phat bieu nam sau phat bieu WAIT.
V du 2-24:
WAIT ON a, b;
Khi mot trong hai s kien xay ra cho a hoac b th qua trnh se tiep tuc vi phat bieu tiep theo
phat bieu WAIT.
b. Phat bieu WAIT UNTIL expression
Menh e WAIT UNTIL boolean_expression se ngng qua trnh thc hien cho en khi ket
qua tra ve cua bieu thc la true. Phat bieu nay thiet lap mot danh sach nhay cac tn hieu c
dung trong bieu thc. Khi bat ky tn hieu nao trong bieu thc thay oi th bieu thc c anh gia.
Bieu thc tra ve ket qua kieu Boolean: khi ket qua la true th qua trnh thc hien se tiep tuc vi
phat bieu theo sau lenh WAIT. Ngc lai th qua trnh se tiep tuc ngng.
V du 2-25:
WAIT UNTIL ((x*10) < 100);
Trong v du nay th khi x ln hn hay bang 10 th qua trnh tiep tuc ngng va ch thc hien
lenh tiep theo khi x nho hn 10.
c. Phat bieu WAIT FOR time_expression
Menh e WAIT FOR time_expression se ngng qua trnh thc hien trong mot khoang thi
gian c ch nh bi bieu thc thi gian. Sau khi thi gian c ch nh trong bieu thc a het
th qua trnh tiep tuc vi phat bieu nam sau lenh WAIT.
V du 2-26:
WAIT FOR 10 ns;
WAIT FOR (a * (b * c));
Phat bieu th nhat th bieu thc ch n gian la hang so.
Phat bieu th hai th bieu thc thi gian la mot bieu thc phai c tnh toan trc va tra ve
la gia tr thi gian. Sau khi gia tr nay a c tnh toan th phat bieu WAIT se dung gia tr thi
gian nay lam thi gian i.
d. Phat bieu WAIT vi nhieu s kien
Phat bieu WAIT vi nhieu ieu kien vi v du 2-27 nh sau:

90 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

V du 2-27:
WAIT ON nmi, interrupt UNTIL ((nmi = true) or (interrupt = true) ) FOR 5 usec;
Phat bieu nay i mot s kien tren cac tn hieu nmi va interrupt va ch tiep tuc neu interrupt
hoac nmi la true hoac cho en het thi gian 5s. Ch khi mot hoac nhieu ieu kien tren la true th
qua trnh thc hien mi tiep tuc. Hay xem v du 2-28:
V du 2-28:
WAIT UNTIL (interrupt = true ) OR (old_clk = 1);
Phai chac chan co t nhat mot gia tr trong bieu thc cha tn hieu ieu nay la can thiet e
am bao phat bieu WAIT khong phai ch i mai.
Neu ca hai interrupt va old_clk eu la bien th phai bieu WAIT khong phai anh gia lai khi
hai bien nay thay oi gia tr. Ch can 1 tn hieu thay oi se lam cho phat bieu WAIT hoac cac phat
bieu gan tn hieu ong thi anh gia lai.
VI. CAC KIEU OI TNG TRONG VHDL
Cac oi tng cua VHDL cha mot trong cac kieu sau:
Signal: tng trng cho cac day dan ket noi ben trong dung e ket noi cac port cua
cac thanh phan vi nhau.
Variable: c dung nh mot o nh cuc bo e lu d lieu tam thi ch nhn thay c
ben trong qua trnh.
Constant: la khai bao hang so.
1. KHAI BAO TN HIEU (SIGNAL):
Kieu tn hieu c s dung e ket noi cac thc the lai vi nhau e tao ra mot module. Signal
la phng thc truyen cac tn hieu ong gia cac thc the vi nhau.
Kieu signal c khai bao nh sau
SIGNAL signal_name: signal_type[:=initial_value];
Theo sau t khoa SIGNAL la mot hoac nhieu ten tn hieu. Vi moi ten tn hieu se tao ra mot
signal mi. Phan biet ten vi loai tn hieu bang dau :. Loai tn hieu ch nh loai d lieu cua
thong tin cha trong tn hieu. Cuoi cung th tn hieu co the cha mot gia tr bat au (gia tr khi
gan) e cho gia tr tn hieu co the c khi ong.
Cac tn hieu co the c khai bao trong phan khai bao cua thc the, trong kien truc va trong
khai bao goi. Cac tn hieu trong khai bao goi c xem nh cac tn hieu toan cuc.
V du 2-29: ve khai bao tn hieu nh sau:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY mux IS
PORT (i0, i1, i2, i3, a, b: IN STD_LOGIC;
q: OUT STD_LOGIC);
END mux;

PACKAGE sigdecl IS
TYPE bus_type IS ARRAY (0 to 7) OF std_logic;

Ky thuat PLD va ASIC 91


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

SIGNAL vcc: std_logic := 1;


SIGNAL ground: std_logic := 0;
FUNCTION magic_function (a: IN bus_type) RETURN bus_type;
END sigdecl;

2. KHAI BAO BIEN (VARIABLE):


Cac bien so dung trong VHDL khong tao ra bat ky phan cng nao, cac bien lu tr gia tr tam
thi cua cac tn hieu. Kieu bien c khai bao nh sau:
VARIABLE variable_name : variable_type[:=value];
Theo sau t khoa variable la mot hoac nhieu ten bien. Cac ten bien cach nhau bang dau ;.
Moi ten bien se tao ra mot bien mi. Variable_type se xac nh kieu d lieu cho bien.
V du 2-30:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY and5 IS
PORT (a, b, c, d, e: IN std_logic;
q: OUT std_logic);
END and5;

ARCHITECTURE and5 OF and5 IS


BEGIN
PROCESS (a, b, c, d, e)
VARIABLE state: STD_LOGIC;
VARIABLE delay : time;
BEGIN

state := a AND b AND c AND d AND e;


IF state = 1 THEN delay:= 4 ns;
ELSIF state = 0 THEN delay := 3 ns
ELSE delay := 4 ns
END IF;
delay <= state AFTER delay;
END PROCESS ;
END and5;
V du nay la kien truc cho cong AND co 5 ngo vao. Co 2 bien c khai bao la bien state va
bien delay, bien state c s dung e cat gi gia tr tam thi cac ngo vao cua cong AND, delay
c s dung e lu gia tr thi gian tre. Ca hai d lieu nay khong the la d lieu tnh bi v gia tr
cua chung phu thuoc vao gia tr cua cac ngo vao a, b, c, d, e. Cac tn hieu co the c dung e lu
tr d lieu nhng khong c dung bi v cac ly do sau:
Cac bien thng hieu qua hn cho phep gan tn hieu bi v no xay ra ngay lap tc,
trong khi tn hieu th phai ch sap xep.
Cac bien chiem t bo nh hn trong khi cac tn hieu can nhieu thong tin e cho phep
sap xep va cac thuoc tnh tn hieu.
Dung tn hieu phai yeu cau phat bieu WAIT e ong bo phep gan tn hieu cho moi lan
thc hien khi s dung.
92 Ky thuat PLD va ASIC
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Khi bat ky tn hieu a, b, c, d, hoac e thay oi th qua trnh thc hien. Bien state c gan cho
ham AND cua tat ca cac ngo vao. Bc tiep theo th da vao gia tr cua bien state ma bien delay
c gan gia tr thi gian tre. Da vao gia tr thi gian a c gan cho bien delay, tn hieu ngo ra
q se co gia tr cua bien state.
3. KHAI BAO HANG SO :
Hang so gi mot gia tr khong oi trong qua trnh thiet ke. Hang so c khai bao nh sau
CONSTANT constant_name :type_name[:=value];
Cac ten hang cach nhau bang dau ;. Cac gia tr cua hang la tuy y, kieu hang co quy nh
giong kieu tn hieu.
Hang co the s dung trong toan thc the neu hang c khai bao trong khoi khai bao cua
thc the, hoac co the c s dung trong toan package neu no c khai bao trong oan khai bao
cua package.
V du 2-31:
CONSTANT PI : REAL := 3.1414;

VII. CAC KIEU D LIEU TRONG VHDL


Tat ca cac oi tng a trnh bay la tn hieu, bien va hang so co the khai bao dung cac kieu
d lieu. Ngon ng VHDL cha rat nhieu kieu d lieu dung e xay dng cho cac oi tng t n
gian en phc tap.
e nh ngha mot loai d lieu mi th phai khai bao loai d lieu. Khai bao loai d lieu nh
ngha ten cua loai d lieu va tam vc hay gii han cua d lieu. Cac khai bao d lieu c phep
khai bao trong phan khai bao goi, phan khai bao thc the, phan khai bao kien truc, phan khai bao
chng trnh con va phan khai bao qua trnh.
Hnh 2-10 trnh bay cac kieu d lieu co s dung trong ngon ng VHDL. Bon loai d lieu ln
la loai scalar, loai a hp (composite), loai access va loai file.
Loai scalar cha cac loai d lieu n gian nh so thc va so nguyen.
Loai a hp bao gom mang va ban ghi.
Loai access tng ng vi con tro trong cac ngon ng lap trnh thong thng.
Loai file cho ngi thiet ke kha nang khai bao oi tng file vi cac loai file c
nh ngha bi ngi thiet ke.

Ky thuat PLD va ASIC 93


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Hnh 2-10. Gian o cac loai d lieu trong VHDL.


1. LOAI SCALAR
Loai d lieu scalar bao gom cac d lieu nh sau:
Kieu so nguyen.
Kieu so thc.
Kieu em, liet ke c.
Kieu d lieu vat ly.
a. Kieu so nguyen INTEGER
Kieu so nguyen giong nh kieu so nguyen cua toan hoc. Tat ca cac ham toan hoc a xac nh
nh ham cong, tr, nhan va chia eu co the ap dung cho kieu d lieu nay.
Trong ngon ng VHDL khong co ch nh gii han so nguyen cc ai nhng co ch nh gii
han cc tieu cua so nguyen t -2,147, 483,647 en 12,147,483,647. Gii han cc tieu c ch
nh bi goi chuan cha trong th vien chuan.
Cac v du ve cac gia tr so nguyen nh sau:
V du 2-32:
ARCHITECTURE test OF test IS
BEGIN
PROCESS (X)
VARIABLE a: INTEGER;
VARIABLE b: int type;
BEGIN
a := 1; -- ok 1
a := -1; -- ok 2
a := 1.0; -- error 3
END PROCESS

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Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

END test;
Hai phat bieu th 1 va 2 la cac phep gan so nguyen. Phat bieu th 3 la phep cho bien so
nguyen la mot so khong phai so nguyen, khi bien dch th phat bieu nay co the sinh ra loi. Bat ky
con so nao co dau cham c xem la so thc.
b. Kieu d lieu a nh ngha
VHDL cha nhieu loai d lieu a c nh ngha, ac biet la cac chuan IEEE 1076 va IEEE
1164. ac biet hn na chang han nh nh ngha cac loai d lieu co the c tm thay trong th
vien va trong goi.
Goi chuan standard (package standard) cua th vien std: xac nh cac kieu d lieu
BIT, BOOLEAN, INTEGER va REAL.
Goi std_logic_1164 cua th vien IEEE: nh ngha cac kieu d lieu STD_LOGIC va
STD_ULOGIC.
Goi std_logic_arith cua th vien IEEE: nh ngha cac kieu d lieu SIGNED va
STD_ULOGIC, cung vi nhieu ham chuyen oi d lieu nh conv_integer (p),
conv_unsigned(p,b), conv_signed(p,b) va conv_std_vector(p,b).
Goi std_logic_signed va std_logic_unsigned cua th vien IEEE: cha cac ham cho
phep hoat ong vi cac d lieu STD_LOGIC_VECTOR c thc hien khi d lieu
loai SIGNED hoac UNSIGNED.
Tat ca cac d lieu a nh ngha (nam trong cac goi hoac th vien tren) c mo ta nh
sau:
BIT (and BIT_VECTOR): co 2 mc logic la 0 va 1.
V du 2-33: khai bao cac tn hieu dang BIT va BIT_VECTOR
SIGNAL x: BIT; -- x c khai bao la mot tn hieu bit
SIGNAL y: BIT_VECTOR (3 DOWNTO 0); -- y la mot vector 4 bit vi bit ben trai la MSB.
SIGNAL w: BIT_VECTOR (0 TO 7); -- w la mot vector 8 bit vi bit ben phai la MSB.
Da vao cac tn hieu tren th cac phat bieu gan sau la hp le:
x <= 1; -- x c gan vi gia tr la 1.
Chu y k hieu dau nhay n ch c dung cho 1 bit n.
y <= 0111; -- y c gan tn hieu 4 bit co gia tr la 0111 vi bit MSB la bit 0.
Chu y k hieu dau nhay kep c dung cho vector.
w <= 01110001; -- w c gan tn hieu 8 bit co gia tr la 01110001 vi bit MSB la bit
1.
STD_LOGIC va STD_LOGIC_VECTOR: co 8 gia tr logic c gii thieu trong chuan
IEEE 1164 chuan:
X co ngha la cha xac nh
0 co ngha la mc thap
1 co ngha la mc cao
Z trang thai tong tr cao
W yeu cha xac nh
L yeu thap

Ky thuat PLD va ASIC 95


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

H yeu cao
- bat chap
V du 2-34: khai bao cac tn hieu dang STD_LOGIC va STD_LOGIC_VECTOR
SIGNAL x: STD_LOGIC -- x c khai bao la tn hieu bit kieu STD_LOGIC.
SIGNAL y: STD_LOGIC_VECTOR (3 DOWNTO 0):= 0001;
-- y c khai bao la mot vector 4 bit vi bit ben trai la MSB va gia tr khi tao la 0001.
Chu y k hieu toan t := c dung e thiet lap gia tr khi gan.
STD_ULOGIC va STD_ULOGIC_VECTOR: co 9 gia tr logic c gii thieu trong chuan
IEEE 1164 chuan la (U, X, 0, 1, Z, W, L, H, -). K hieu U tng trng cho
unresolve khong quyet oan.
Kieu BOOLEAN: co 2 gia tr la TRUE va FALSE.
Kieu so nguyen INTEGER: la so nguyen 32 bit t -2,147,483,657 en +2,147, 483,
647.
Kieu so nguyen dng NATURAL: t 0 en +2,147, 483, 647.
Kieu so thc REAL: t -1.0E38 en +1.0E38. Khong c tong hp.
Kieu cac con so vat ly: c dung cho cac ai lng vat ly nh thi gian, ien ap,
dung cho mo phong. Khong c tong hp.
Kieu SIGNED va UNSIGNED: kieu d lieu a nh ngha trong goi std_logic_arith
cua th vien IEEE.
V du 2-35: ve cac lenh gan bit, vector, cac kieu he thong so:
x0 <= 0; -- co the xem x la bit, std_logic hoac std_ulogic co gia tr la 0.
x1 <= 00011111; -- co the xem la bit_vector, std_logic_vector, std_ulogic, signed hoac
unsigned.
x2 <= 0001_1111; -- dau gach cho phep e de nhn.
x3 <= 101111; -- tng trng cho so nh phan co gia tr thap phan la 47.
x4 <= B101111; -- tng trng cho so nh phan co gia tr thap phan la 47.
x5 <= O57; -- tng trng cho bat phan co gia tr thap phan la 47.
x6 <= X2F; -- tng trng cho so thap luc phan co gia tr thap phan la 47.
n<= 1200; -- so nguyen.
m<= 1_200; -- so nguyen cho phep tach ra e de nhn.
IF ready THEN -- ready kieu boolean c thc hien neu ready bang true.
y <= 1.2E-5; -- so thc, nhng khong tong hp.
q <= d AFTER 10 ns; -- vat ly nhng khong tong hp.

V du 2-36: ve cac khai bao hp le va khong hp le vi cac loai d lieu khac nhau:
SIGNAL a: BIT;
SIGNAL b: BIT_VECTOR (7 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL e: INTEGER RANGE 0 TO 255;

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Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

a <= b(5); -- phep gan bit th 5 cua b cho a la hp le v cung d lieu BIT.
b(0) <= a; -- phep gan a cho bit th 0 cua b la hp le v cung d lieu BIT.
c <= d(5); -- phep gan bit th 5 cua d cho c la hp le v cung d lieu
STD_LOGIC.
d(0) <= c; -- phep gan nay la hp le v cung kieu d lieu STD_LOGIC.
a <= c; -- phep gan nay khong hp le v khac kieu d lieu BIT va
STD_LOGIC.
b <= d; -- khong hp le v khac kieu BIT_VECTOR va
STD_LOGIC_VECTOR.
e <= b; -- khong hp le v khac kieu INTEGER va BIT_VECTOR.
e <= d; -- khong hp le v khac kieu INTEGER va STD_LOGIC_VECTOR.

c. Kieu d lieu do ngi dung nh ngha


VHDL cho phep ngi dung nh ngha cac loai d lieu rieng. Hai loai d lieu do ngi dung
nh ngha c trnh bay la kieu so nguyen INTEGER va kieu liet ke.
Kieu d lieu so nguyen do ngi dung nh ngha:
TYPE integer IS RANGE - 2147483647 TO 2147483647;
TYPE natural IS RANGE 0 TO 2147483647;
TYPE my_integer IS RANGE - 32 TO 32;
TYPE student_grade IS RANGE 0 TO 100;
TYPE color IS (red, green, blue, white);
Kieu d lieu liet ke do ngi dung nh ngha:
TYPE bit IS (0, 1);
TYPE my_logic IS (0, 1, Z);
d. Kieu d lieu SUBTYPE
SUBTYPE la kieu d lieu ep kieu. Ly do chnh e dung kieu subtype tot hn la do cac phep
toan gia cac d lieu khac nhau khong c phep thc hien ma chung ch cho phep thc hien kieu
d subtype vi cac kieu d lieu c ban khac.
V du 2-37: cho cac kieu subtype cho cac kieu d lieu a nh ngha tren:
SUBTYPE natural IS INTEGER RANGE 0 TO INTEGERHIGH;
SUBTYPE my_logic IS STD_LOGIC RANGE 0 TO Z;
-- Goi lai STD_LOGIC = (X, 0, 1, Z, W, L, H, -) nhng my_logic = (0, 1,
Z).
SUBTYPE my_color IS color RANGE red TO blue;
-- Goi lai color = (red, green, blue, white) nhng my_color = (red, green,blue).
SUBTYPE small_integer IS INTEGER RANGE -32 TO 32;

V du 2-38: ve cac phep toan hp le va khong hp le vi cac kieu d lieu va subtype:


SUBTYPE my_logic IS STD_LOGIC RANGE 0 TO 1;
SIGNAL a: BIT;

Ky thuat PLD va ASIC 97


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

SIGNAL b: STD_ LOGIC;


SIGNAL c: my_logic ;

b <= a; -- Khong hp le v khac kieu d lieu BIT va STD_LOGIC.


b <= c; -- Hp le v cung d lieu c ban STD_LOGIC.

e. Kieu d lieu mang ARRAY


Array la tap hp cac oi tng cung mot kieu d lieu, co the la mang 1 chieu (1D), mang 2
chieu (2D) hoac mang 1 chieu 1 chieu (1D 1D). Cac mang co the co nhieu chieu hn na
nhng chung khong c tong hp. Hnh 2-11 minh hoa cau truc cua mang d lieu. Hnh (a) la gia
tr n (scalar), hnh (b) la mang 1 chieu (1D), hnh (c) la mang cac vector (1D 1D) va hnh (d) la
mang scalar (2D).

Hnh 2-11. Cac kieu mang d lieu.


Cac loai d lieu co the tong hp a nh ngha cho cac kieu mang tren la
D lieu Scalar: BIT, STD_LOGIC, STD_ULOGIC va BOOLAEN.
Cac Vector: BIT_VECTOR, STD_LOGIC_VECTOR, STD_ULOGIC_VECTOR,
INTEGER, SIGNED va UNSIGNED.
Cu phap ch nh cho mot kieu d lieu mang mi nh sau:
TYPE type_name IS ARRAY (specification) OF data_type;
e s dung kieu d lieu mang mi nay th khai bao tn hieu nh sau:
SIGNAL signal_name: type_name [:=initial_value];
Trong cu phap tren tn hieu SIGNAL c khai bao. Tuy nhien cung co the la CONSTANT
hoac VARIABLE. Chu y tuy chon gia tr khi gan ch c dung cho mo phong.
V du 2-39: ve mang 1D1D:
Chung ta muon xay dng mot mang cha 4 vector, moi vector cha 8 bit ay la mang
1D1D. Chung ta goi moi vector la mot hang va mot mang ay u la mot ma tran. Cach khai bao
nh sau:
TYPE row IS ARRAY (7 DONWTO 0) OF STD_LOGIC; -- 1D array
TYPE matrix IS ARRAY (0 TO 3) OF row; -- 1D1D array
SIGNAL x: matrix; -- 1D1D signal

V du ve khai bao mang kieu khac:


TYPE matrix IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
V du ve khi gan cho mang:
:= 0001; -- gan cho mang 1D

98 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

:= (0, 0, 0, 1); -- gan cho mang 1D


:= ((0, 1, 1, 1), (1, 1, 1, 0)); -- gan cho mang 1D1D hoac 2D

V du 2-40: ve cac phep gan hp le va khong hp le cua mang:


Cho cac mang c khai bao nh sau:
TYPE row IS ARRAY (7 DONWTO 0) OF STD_LOGIC; -- 1D array
TYPE array1 IS ARRAY (0 TO 3) OF row; -- 1D1D array
TYPE array2 IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR (7 DOWNTO 0); --
1D1D array
TYPE array3 IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC;-- 2D array
SIGNAL x: row;
SIGNAL y: array1;
SIGNAL v: array2;
SIGNAL w: array3;

Cac phep gan bit nh sau:


x(0) <= y(1) (2); -- gan bit th 2 cua vector y1 cho x(0).
x(1) <= v(2) (1); -- gan bit th 1 cua vector v2 cho x(1).
x(2) <= w(2,1); -- gan bit th 1 cua vector w2 cho x(2).
y(1) (1) <= x(6);
y(2) (0) <= v(0) (0);

Cac phep gan vector nh sau:


x <= y(0) ; -- hp le v cung kieu d lieu row.
x <= v(1) ; -- khong hp le v khong tng thch kieu d lieu row
STD_LOGIC_VECTOR.
x <= w(2) ; -- khong hp le v khong tng thch kieu d lieu row
STD_LOGIC_VECTOR.
x <= w(2, 2 downto 0); -- khong hp le v khong tng thch kieu d lieu.
v(0) <= w(2, 2 downto 0); -- khong hp le v khong tng thch kieu d lieu.
v(0) <= w(2) ; -- khong hp le v khong tng thch kieu d lieu.
y(1) <= v(3) ; -- khong hp le v khong tng thch kieu d lieu.

y(1) (7 downto 3) <= x(4 downto 0); -- hp le v cung kieu va kch thc d lieu.
v(1) (7 downto 3) <= v(2) ( 4 downto 0); -- hp le v cung kieu va kch thc d lieu.
w(1, 5 downto 1) <= v(2) ( 4 downto 0); -- khong hp le v khong cung kieu.

f. Kieu d lieu mang port


Khong co cac kieu d lieu a nh ngha nhieu hn 1 chieu. Tuy nhien trong ch nh khai
bao PORT ngo vao hoac ra cua mach ien nam trong entity, chung ta co the ch nh cac port
Ky thuat PLD va ASIC 99
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

giong nh cac mang vector. Do kieu khai bao TYPE khong c phep khai bao trong thc the
entity nen giai phap e khai bao cac kieu d lieu do ngi dung nh ngha trong PACKAGE, sau
o co the dung cho toan thiet ke.
V du 2-41:
-- khai bao goi package--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
PACKAGE my_data_type IS
TYPE vector_array IS ARRAY ( NATURAL RANGE <>) OF std_logic_vector (7
downto 0);
END my_data_type;
-- khai bao d lieu dung cho chng trnh --
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.my_data_type.ALL; -- goi do ngi dung nh ngha

ENTITY mux IS
PORT (inp: IN vector_array (0 to 3);
: );
END mux;

g. Kieu d lieu bang ghi record


Record giong nh mang nhng ch khac la chung cha nhieu oi tng d lieu khac nhau.
V du 2-42: trnh bay nh sau:
TYPE birthday IS RECORD
Day: INTEGER RANGE 1 to 31;
month: month_name;
END RECORD;

h. Kieu d lieu SIGNED va UNSIGNED


La cac d lieu a nh ngha trong goi std_logic_arith cua th vien IEEE. Cu phap khai bao
nh sau:
V du 2-43:
SIGNAL x: SIGNED (7 downto 0);
SIGNAL y: UNSIGNED (0 to 3);
Gia tr cua so khong dau th khong c nho hn 0. V du 0101 tng trng cho so thap
phan 5, 1101 tng trng cho so thap phan 13. Neu so co dau c s dung th co gia tr ca am
va dng dang bu 2. V du 0101 tng trng cho so thap phan 5, con 1101 tng trng cho
so thap phan -3.
e s dung cac kieu d lieu SIGNED va UNSIGNED th goi std_logic_arith cua th vien
IEEE phai c khai bao.
V du 2-44: cac phep toan hp le va khong hp le vi cac d lieu co dau va khong dau:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
100 Ky thuat PLD va ASIC
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

USE IEEE.std_logic_arith.ALL; -- goi d lieu khai bao them



SIGNAL a: IN SIGNED (7 downto 0);
SIGNAL b: IN SIGNED (7 downto 0);
SIGNAL x: OUT SIGNED (7 downto 0);

v <= a + b ; -- hp le v cung kieu d lieu toan hoc.
w <= a AND b ; -- khong hp le v khong tng thch phep vi phep toan logic.

V du 2-45: cac phep toan hp le va khong hp le vi d lieu STD_LOGIC_VECTOR:


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

SIGNAL a: IN STD_LOGIC_VECTOR (7 downto 0);
SIGNAL b: IN STD_LOGIC_VECTOR (7 downto 0);
SIGNAL x: OUT STD_LOGIC_VECTOR (7 downto 0);

v <= a + b ; -- khong hp le v kieu d lieu logic.
w <= a AND b ; -- hp le v phep toan logic s dung kieu logic.
Mac du b cam tren nhng co mot cach rat n gian cho phep d lieu kieu
STD_LOGIC_VECTOR tham gia trc tiep vao cac phep toan so hoc. Th vien IEEE cung cap 2
goi d lieu STD_LOGIC_SIGNED va STD_LOGIC_UNSIGNED cho phep cac phep toan tren cac
d lieu STD_LOGIC_VECTOR co the c thc hien giong nh cac d lieu loai SIGNED va
UNSIGNED theo th t.
V du 2-46: cac phep toan vi d lieu STD_LOGIC_VECTOR:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL; -- khai bao them .

SIGNAL a: IN STD_LOGIC_VECTOR (7 downto 0);
SIGNAL b: IN STD_LOGIC_VECTOR (7 downto 0);
SIGNAL x: OUT STD_LOGIC_VECTOR (7 downto 0);

v <= a + b ; -- hp le
w <= a AND b ; -- hp le

i. Kieu so thc REAL


Kieu so thc c dung e khai bao cac oi tng s dung so thc. Gii han cc tieu cua so
thc cung c ch nh bi goi chuan trong th vien chuan va nam trong khoang t -1.0E +38
en +1.0E + 38.
V du 2-47: ve cac gia tr so thc nh sau:
ARCHITECTURE test OF test IS
Ky thuat PLD va ASIC 101
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

SIGNAL a: REAL;
BEGIN
a <= 1.0; -- ok 1
a <= 1; -- error 2
a <= -1.0E10; -- ok 3
a <= 1.5E-20; -- ok 4
a <= 5.3 ns; -- error 5
END test;
Hang 1 trnh bay cach gan so thc cho tn hieu loai REAL. Tat ca cac con so thc eu co dau
cham e phan biet vi so nguyen.
Hang th 2 se phat sinh loi v gan so nguyen cho bien kieu so thc.
Hang th 3 gan mot so thc rat ln va hang th 4 gan mot so thc rat nho.
Hang th 5 se phat sinh loi v khong the gan thi gian cho tn hieu so thc.
j. Kieu liet ke
Kieu liet ke la mot cong cu ho tr ac lc cho qua trnh thiet ke bang ngon ng VHDL.
Ngi thiet ke co the dung cac loai d lieu liet ke ai dien chnh xac cho cac gia tr chnh
xac c yeu cau cho phep toan ch nh. Tat ca cac gia tr cua kieu d lieu liet ke do ngi dung
nh ngha. Cac gia tr nay co the la ten hoac cac hang so ac tnh n, v du cho ten la x, abc,
hang so ac tnh n la X, 1 va 0.
Loai d lieu liet ke cho he thong co 4 gia tr mo phong nh sau:
TYPE fourval IS (X, 0, 1, Z);
Mot ng dung co dung kieu liet ke la minh hoa cho tat ca cac lenh cua vi x ly. V du 2-48
kieu liet ke cho mot vi x ly n gian nh sau:
V du 2-48:
TYPE instruction IS (add, sub, lda, ldb, sta, stb, outa, xfr);
Va mo hnh cho he thong vi x ly:
PACKAGE instr IS
TYPE instruction IS (add, sub, lda, ldb, sta, stb, outa, xfr);
END instr;

USE work.instr.ALL;
ENTITY mp IS
PORT (instr: IN instruction;
addr: IN INTEGER;
data: INOUT INTEGER);
END mp;

ARCHITECTURE mp OF mp IS
BEGIN
PROCESS (instr)
TYPE regtype IS ARRAY (0 to 255 ) OF INTEGER;
VARIABLE a, b: INTEGER;
VARIABLE reg: regtype;
BEGIN
102 Ky thuat PLD va ASIC
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

CASE instr IS
WHEN lda => a:= data; -- load a accumulator
WHEN ldb => b:= data; -- load b accumulator
WHEN add => a:= a + b; -- add accumulator
WHEN sub => a:= a - b; -- subtract accumulator
WHEN sta => reg(addr) := b; -- put b accu in reg array
WHEN out => data<= a ; -- output a accumulator
WHEN xfr => a:= b ; -- transfer b to a
END CASE;
END PROCESS ;
END mp;
Mo hnh nhan mot chuoi lenh (instr), mot a ch (addr) va mot chuoi d lieu (data). Da
vao gia tr cua instr c liet ke ma lenh tng ng c thc hien. Phat bieu CASE c dung
e la chon lenh e thc hien. Phat bieu c thc hien va sau o qua trnh se i cho en lenh
ke.
2. KIEU VAT LY:
Kieu vat ly c s dung e mo ta cac ai lng vat ly nh: khoang cach, dong ien, thi
gian V du 2-49 ve kieu d lieu vat ly ve dong ien nh sau:
V du 2-49:
TYPE current IS RANGE 0 TO 1000000000;
UNITS
na; -- nano amps
ua = 1000 na; -- micro amps
ma = 1000 ua; -- mili amps
a = 1000 ma; -- amps
END UNITS;
Viec xac nh kieu d lieu c bat au vi cau lenh khai bao ten kieu va vung cua kieu (0
to 1000000000), cac khai bao c thc hien trong oan UNITS. Trong v du tren n v chnh cua
UNITS la na. Sau khi n v chnh cua UNITS c khai bao cac n the khac se c xac nh.
Kieu vat ly a c nh ngha: trong VHDL co kieu vat ly a c nh ngha la thi gian
nh sau:
TYPE TIME IS <implementation defined>;
UNITS
fs; -- femtosecond
ps = 1000 fs; -- picosecond
ns = 1000 ps; -- nanosecond
us = 1000 ns; -- microsecond
ms = 1000 ns; -- milisecond
sec = 1000 ms; -- second
min = 60 sec; -- minute
hr = 60 min; -- hour
END UNITS;
3. CAC THUOC TNH:

Ky thuat PLD va ASIC 103


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

VHDL ho tr 5 loai thuoc tnh. Cac thuoc tnh a nh ngha luon c ap dung tiep au ng
nh ten cua tn hieu, ten cua bien hoac kieu. Cac thuoc tnh c dung e tra ve nhieu loai thong
tin khac nhau nh tn hieu, bien hoac kieu. Cac thong tin cha dau phay () theo sau la ten cua
thuoc tnh.
a. Thuoc tnh tn hieu
Bang sau ay liet ke cac thuoc tnh cua tn hieu:
Thuoc tnh Chc nang
signal_nameevent Tra ve gia tr Boolean la True neu co s kien tren tn hieu
xay ra, ngc lai th tra ve gia tr false.
signal_nameactive Tra ve gia tr Boolean la True neu co tch cc (gan) tren tn
hieu xay ra, ngc lai th tra ve gia tr false.
signal_nametransaction Tra ve tn hieu kieu bit lat trang thai (0 sang 1 hoac 1 sang
0) moi lan co chuyen trang thai tren tn hieu.
signal_namelast_event Tra ve gia tr khoang thi gian t khi xay ra s kien sau cung
tren tn hieu.
signal_namelast_active Tra ve gia tr khoang thi gian t khi xay ra mc tch cc
tren tn hieu.
signal_namelast_value Cung cap gia tr cua tn hieu trc khi s kien sau cung xay
ra tren tn hieu.
signal_namedelayed(T) Cung cap tn hieu tre i T lan so vi tn hieu goc. T la tuy
chon, mac nhien T = 0.
signal_namestable(T) Tra ve gia tr Boolean, la true neu khong co s kien xay ra
tren tn hieu trong khoang thi gian T, ngc lai th tra ve
gia tr false. T la tuy chon, mac nhien T = 0.
signal_namequiet(T) Tra ve gia tr Boolean, la true neu khong co s thay oi xay
ra tren tn hieu trong khoang thi gian T, ngc lai la false. T
la tuy chon va mac nhien T = 0.
Bang 2-1. Thuoc tnh tn hieu.
V du 2-50: ve cac thuoc tnh:
if (CLOCKevent and CLOCK= 1) then
Bieu thc nay kiem tra s xuat hien cua xung clock canh len. e tm khoang thi gian t khi
co xung clock canh len sau cung th dung thuoc tnh sau:
CLOCKlast_event

b. Thuoc tnh d lieu scalar


Mot vai thuoc tnh kieu d lieu scalar c ho tr nh bang sau:

Thuoc tnh Gia tr


scalar_typeleft Tra ve gia tr au tien hoac gia tr tan cung ben trai cua
kieu d lieu scalar trong kieu a nh ngha.
scalar_typeright Tra ve gia tr sau cung hoac gia tr tan cung ben phai cua
kieu d lieu scalar trong kieu a nh ngha.

104 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

scalar_typelow Tra ve gia tr thap nhat cua kieu d lieu scalar trong kieu
a nh ngha.
scalar_typehigh Tra ve gia tr cao nhat cua kieu d lieu scalar trong kieu
a nh ngha
scalar_typeascending La true neu T la day tang ngc lai th false.
scalar_typevalue(s) Tra ve gia tr cua T c tng trng bi s (string value).
Bang 2-2. Thuoc tnh d lieu scalar.
V du 2-51: ve cac thuoc tnh:
Type conductance is range 1E-6 to 1E3
Units mho;
End units conductance;
Type my_index is range 3 to 15;
Type my_levels is (low, high, dontcare, highZ);

conductanceright tra ve 1E3


conductancehigh 1E3
conductancelow 1E-6
my_indexleft 3
my_indexvalue(5) 5
my_levelsleft low
my_levelslow low
my_levelshigh highZ
my_levelsvalue(dontcare) dontcare

c. Thuoc tnh mang


Bang cach dung cac thuoc tnh mang se tra ve gia tr ch so tng ng vi day cua mang.
Cac thuoc tnh c xay dng nh sau:
Thuoc tnh Tra ve
MATRIXleft(N) Ch so phan t tan cung ben trai
MATRIXright(N) Ch so phan t tan cung ben phai
MATRIXhigh(N) Gii han tren
MATRIXlow(N) Gii han di
MATRIXlength(N) So lng cac phan t
MATRIXrange(N) Day
MATRIXreverse_range(N) Day bao ve
MATRIXascending(N) Tra ve gia tr true neu ch so theo th t tang, ngc
lai th bang false.
Bang 2-3. Thuoc tnh mang.
Con so N nam trong dau ngoac c xem nh chieu cua mang. oi vi mang 1 chieu th co
the bo nhng oi vi mang 2 chieu th phai dung con so N e ch ro. Cac v du ve thuoc tnh mang
nh sau:
V du 2-52: ve cac thuoc tnh:
Type myarr8x4 is range (8 downto 1, 0 to 3) of boolean;
Ky thuat PLD va ASIC 105
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Type myarr1 is range (-2 to 4) of integer;

MYARR1left tra ve: -2


MYARR1right 4
MYARR1high 4
MYARR1reverse_range 4 downto -2

MYARR8x4left(1) 8
MYARR8x4left(2) 0
MYARR8x4right(2) 3
MYARR8x4high(1) 8
MYARR8x4low(1) 1
MYARR8x4ascending(1) False

VIII. CAC TOAN T C BAN TRONG VHDL


VHDL ho tr 7 loai toan t khac nhau e x ly cac tn hieu, bien va hang so. Cac loai toan t
c liet ke nh sau:

Th t Loai
1 Toan logic and or nand nor xor xnor
2 Toan t quan he = /= < <= > >=
3 Toan t dch sll srl sla sra rol ror
4 Toan t so hoc + = &
5 Toan t khong xac nh + -
6 Toan t nhan chia * / mod rem
7 Toan t hon hp ** abs not
Bang 2-4. Tat ca cac toan t.
Th t u tien cao nhat cho toan t th 7, tiep theo la th 6 va thap nhat la toan t th 1. Tr
trng hp dau ngoac c s dung th toan t co th t u tien cao nhat se c thc hien trc.
Neu cac toan t cung th t u tien th cac toan t se c thc hien t trai sang phai cua bieu
thc.
V du 2-53: Cho cac d lieu nh sau: X (=010), Y(=10), and Z (=10101) eu thuoc
kieu std_ulogic_vectors.
not X & Y xor Z rol 1
th se tng ng vi ((not X) & Y) xor (Z rol 1) = ((101) & 10) xor (01011) =(10110) xor
(01011) = 11101.
1. CAC TOAN T LOGIC:
Toan t logic (And, Or, Nand, Nor, Xor va Xnor) c dung cho cac loai d lieu bit,
boolean, std_logic, std_ulogic va cac vector. Cac toan t nay c dung e xac nh bieu
thc logic Boolean hoac thc hien cac phep toan bit vi bit tren mot mang bit. Ket qua cung kieu

106 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

d lieu nh cac tac to (Bit hoac Boolean). Cac toan t nay co the c ap dung cho cac tn hieu,
cac bien va cac hang so.
Chu y: cac toan t nand va nor khong the ket hp. Phai s dung dau ngoac e chia cac toan
t nand va nor e khong phat sinh loi khi bien dch:
X nand Y nand Z se phat sinh loi va phai viet nh sau (X nand Y) nand Z.
2. CAC TOAN T QUAN HE:
Toan t quan he kiem tra cac gia tr quan he cua 2 loai d lieu scalar va cho ket qua la kieu
Boolean true hoac false.

Toan t Mo ta Kieu toan t Kieu ket qua


= Bang Bat ky Boolean
/= Khong bang Bat ky Boolean
< Nho hn Kieu scalar hoac mang ri rac Boolean
<= Nho hn hoac bang Kieu scalar hoac mang ri rac Boolean
> Ln hn Kieu scalar hoac mang ri rac Boolean
>= Ln hn hoac bang Kieu scalar hoac mang ri rac Boolean
Bang 2-5. Cac toan t quan he.
Toan t quan he kiem tra cac gia tr quan he cua 2 loai d lieu scalar va cho ket qua la kieu
Boolean true hoac false.
Chu y: k hieu <= (nho hn hay bang) giong nh k hieu cua phep gan gia tr cho tn hieu.
V du 2-54: ve cac thuoc tnh:
Variable STS : boolean;
Constant A : integer:= 24;
Constant B_count: integer:= 32;
Constant C : integer:= 14;
STS <= (A < B_count); -- gan gia tr true cho STS
STS <= ((A >= B_count) or (A>C)); -- gan gia tr true cho STS
STS <= (std_logic(1,0,1)<std_logic(0,1,1)); -- gan gia tr false cho STS

Type new_std_logic is (0, 1, Z, -);


Variable A1 : new_std_logic := 1;
Variable A2 : new_std_logic := Z;
STS <= (A1 < A2); -- gan gia tr true cho STS v 1 nam ben trai cua Z
3. CAC TOAN SO HOC:
Toan t so hoc c dung e thc hien cac phep toan cong va tr tren cac tac to cua bat k
kieu d lieu nao. Toan t & c dung e noi hai vector tao thanh 1 vector dai hn. e dung cac
toan t so hoc th phai khai bao cac th vien std_logic_unsigned.all hoac std_logic_arith package
vao th vien std_logic_1164 package.

Toan t Mo ta Tac to ben trai Tac to ben phai Ket qua

Ky thuat PLD va ASIC 107


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

+ Phep cong Kieu so Giong tac to ben trai Cung kieu


- Phep tr Kieu so Giong tac to ben trai Cung kieu
& Noi dai Kieu mang hoac phan t Giong tac to ben trai Cung kieu mang
Bang 2-6. Cac toan t so hoc.

V du 2-55: cho cac tn hieu


signal MYBUS :std_logic_vector (15 downto 0);
signal STATUS :std_logic_vector (2 downto 0);
signal RW, CS1, CS2 :std_logic;
signal MDATA :std_logic_vector ( 0 to 9);
Thc hien: MYBUS <= STATUS & RW & CS1 & SC2 & MDATA;

MYARRAY (15 downto 0) <= 1111_1111 & MDATA (2 to 9);


NEWWORD <= VHDL & 93;

4. CAC TOAN T CO DAU:


Toan t + va - c dung e ch nh dau cua d lieu so

Toan t Mo ta Kieu d lieu tac to Kieu d lieu ket qua


+ So dng Bat ky d lieu so nao Cung kieu
- So am Bat ky d lieu so nao Cung kieu
Bang 2-7. Cac toan t co dau.

108 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

5. CAC TOAN T NHAN CHIA:


Toan t nhan c dung e thc hien cac ham toan hoc tren cac kieu d lieu so nguyen hoac
kieu dau cham ong.

Tac Mo ta Kieu d lieu tt trai Kieu d lieu tt phai Kieu KQ


to
kieu integer va DC Cung kieu Cung kieu
* Nhan kieu vat ly Kieu so nguyen hoac thc Cung kieu tt trai
kieu so nguyen hoac thc Kieu vat ly Cung kieu tt
phai
/ Chia So nguyen hoac dau cham So nguyen hoac dau cham Cung kieu
ong ong
Kieu vat ly So nguyen hoac so thc Cung kieu tt trai
Kieu vat ly Cung kieu So nguyen
mod Chia Kieu so nguyen Cung kieu
nguyen
rem Remainder Kieu so nguyen Cung kieu
Bang 2-8. Cac toan t nhan chia.

V du 2-56: cho cac tn hieu


11 rem 4 ket qua bang 3
(-11) rem 4 ket qua bang -3
9 mod 4 ket qua bang 1
7 mod (-4) ket qua bang 1 (7 4*2 = -1).

6. CAC TOAN T DCH:


Toan t thc hien dch chuyen tng bit hoac xoay tng bit tren d lieu mang 1 chieu cua cac
phan t kieu d lieu bit hoac std_logic hoac Boolean.

Toan t Mo ta Kieu d lieu tac to


sll Dch sang trai lap ay bang cac bit 0. (Shift Mang 1 chieu vi cac phan t mang kieu bit
left logical) hoac Boolean; Right: integer
srl Dch sang phai lap ay bang cac bit 0. Giong nh tren
(Shift right logical)
sla Dch sang trai lap ay bang bit tan cung ben Giong nh tren
phai. (Shift left arithmetic)
sra Dch sang phai lap ay bang bit tan cung ben Giong nh tren
trai. (Shift right arithmetic)
rol Xoay vong tron sang trai (Rotate left Giong nh tren
circular)
ror Xoay vong tron sang phai (Rotate right Giong nh tren
circular)
Bang 2-9. Cac toan t dch.

Ky thuat PLD va ASIC 109


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Toan t nam ben trai toan t va so lan dch nam ben phai toan t xem v du 2-57:
V du 2-57: Cho variable NUM1 :bit_vector := 10010110;
Thc hien NUM1 srl 2;
Ket qua NUM1 = 00100101.
Khi so lan dch la so am th hoat ong dch xay ra theo chieu ngc lai, dch trai se tr thanh
dch phai.

V du 2-58: Cho variable NUM1 :bit_vector := 10010110;


NUM1 srl 2 se tng ng vi NUM1 sll 2 va cho ket qua la 01011000.

V du 2-59: Cho variable A: bit_vector := 101001;


A sll 2 results in 100100
A srl 2 results in 001010
A sla 2 results in 100111
A sra 2 results in 111010
A rol 2 results in 100110
A ror 2 results in 011010
7. CAC TOAN HON HP:
Toan t hon hp gom toan t tr tuyet oi va toan t so mu co the ap dung cho cac kieu d
lieu so. Toan t not se cho cung gia tr nhng ngc dau.

Toan t Mo ta D lieu ben trai D lieu ben phai D lieu ket qua
** Ham mu So nguyen So nguyen Giong d lieu ben trai
Dau cham So nguyen Giong d lieu ben trai
abs Ham tr tuyet oi Kieu so Cung kieu
not Ham phu nh Kieu bit hoac Boolean Cung kieu
Bang 2-10. Cac toan t hon hp.

IX. CHNG TRNH CON VA GOI


1. CHNG TRNH CON:
Chng trnh con bao gom cac thu tuc va cac ham. Thu tuc co the tra ve nhieu hn 1 oi so,
con ham th ch tra ve 1 oi so. Trong mot ham th tat ca cac thong so eu la thong so ngo vao,
trong thu tuc co the la thong so ngo vao, thong so ngo ra va co the la so vao ra.
Co hai kieu cho ham va thu tuc: thu va ham ong thi, thu tuc va ham tuan t. Ham va thu
tuc ong thi ch ton tai nam ben ngoai phat bieu qua trnh hoac mot chng trnh con; ham va thu
tuc tuan t ch ton tai trong phat bieu qua trnh hoac trong 1 chng trnh con khac.
Tat ca cac phat bieu nam ben trong mot chng trnh con la tuan t. Cac phat bieu giong
nhau ton tai trong mot phat bieu qua trnh th co the c dung trong mot chng trnh con bao
gom ca phat bieu WAIT.

110 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

a. Ham - FUNCTION:
V du 2-60 la mot ham, ham nay nhan vao mot mang co kieu STD_LOGIC va tra ve mot gia
tr so nguyen. Gia tr so nguyen nay bieu dien gia tr so hoc cua tat ca cac bit c x ly di dang
so nh phan:
V du 2-60: cach viet ham

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

PACKAGE num_type IS
TYPE log8 IS ARRAY (0 TO 7) OF std_logic; -- line 1
END num_type;

USE work.num_type.ALL;
ENTITY convert IS
PORT (I1: IN log8; -- line 2
O1: OUT INTEGER); -- line 3
END convert;

ARCHITECTURE behave OF convert IS

FUNCTION vector_to_int(S:log8) -- line 4


RETURN INTEGER is -- line 5
VARIABLE result: INTEGER := 0 -- line 6
BEGIN
For i IN 0 TO 7 LOOP -- line 7
result := result * 2; -- line 8
IF S(i) = 1 THEN -- line 9
result := result + 1; -- line 10
END IF ;
END LOOP;
RETURN result ; -- line 11
END vector_to_int;

BEGIN
O1 <= vector_to_int (I1);

END behave;
Dong 1 khai bao kieu mang c s dung cho toan bo chng trnh.
Cac dong 2 va 3 khai bao cac port ngo vao, ngo ra cua thc the convert va cac kieu d lieu.
Cac dong t 4 en 11 mo ta mot ham c khai bao trong mien khai bao cua kien truc
behave. Bang cach khai bao ham trong mien khai bao cua kien truc, ham nay se c s dung bat
ky mien nao cua kien truc.
Cac dong 4 va 5 khai bao ten cua ham, cac oi so cua ham va kieu ma ham tra ve.
dong 6 mot bien cuc bo cua ham c khai bao. Cac ham co cac mien khai bao rat giong
vi cac phat bieu qua trnh. Cac bien, cac hang va cac kieu co the c khai bao nhng tn hieu th
khong.

Ky thuat PLD va ASIC 111


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Cac dong t 7 en 10 khai bao mot phat bieu vong lap cho moi gia tr trong mang. Giai thuat
c ban cua ham nay la dch va cong vi moi v tr bit trong mang. au tien ket qua c dch (tc
la nhan 2) va tiep theo la v tr bit la 1 th gia tr 1 c cong vao ket qua.
cuoi phat bieu vong lap, bien result se cha gia tr nguyen cua mang c chuyen vao. Gia
tr cua ham c chuyen ngc ve thong qua phat bieu RETURN. Trong v du tren th phat bieu
RETURN c trnh bay dong 11.
Cuoi cung, dong 12 trnh bay cach thc mot ham c goi. Ten cua ham c theo sau bi
cac oi so cua ham trong hai ngoac n. Ham se luon luon tra ve mot gia tr, do vay qua trnh
goi, phat bieu ong thi, phai co mot v tr e ham co the tra ve gia tr nay. Trong v du nay, ngo
ra cua ham c gan cho mot port ngo ra.
Cac thong so cua ham la d lieu nhap. Khong co phep gan nao c thc hien cho bat ky
thong so nao cua ham. Trong v du tren cac thong so thuoc loai hang so do khong co loai ro rang
c ch nh va mac nh la hang. Cac oi so c x ly nh the chung la cac hang c khai bao
trong mien khai bao cua ham.
Loai thong so cua ham co the la thong so tn hieu. Vi mot thong so tn hieu, cac thuoc tnh
cua tn hieu c chuyen vao trong ham va san sang c s dung. Ngoai le oi vi phat bieu
thuoc tnh STABLE, QUIET, TRANSACTION, va DELAYED se tao ra cac tn hieu ac biet.
Mot v du 2-61 cho thay mot ham cha cac thong so tn hieu nh sau:
V du 2-61:

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dff IS
PORT (d, clk: IN std_logic;
q: OUT std_logic);
FUNCTION resing_edge (SINGAL S : std_logic) -- line 1
RETURN BOOLEAN IS -- line 2
BEGIN
IF (SEVENT) AND (S=1) AND -- line 3
(SLAST_VALUE = 0) THEN -- line 4
RETURN TRUE; -- line 5
ELSE RETURN FALSE; -- line 6
END IF;
END resing_edge;
END dff;

ARCHITECTURE behave OF dff IS

BEGIN
PROCESS (CLK)
BEGIN
IF rising_edge(clk) THEN -- line 7
q <= d; -- line 8

112 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

END IF;
END PROCESS;
END behave;
V du nay cung cap phng phap phat hien canh len cho mo hnh flip flop D. Ham khai bao
trong phan khai bao thc the va do vay co the s dung cho bat ky kien truc nao cua thc the nay.
Cac dong 1 va 2 cho thay khai bao ham. Ch co mot thong so (S) cho ham va thong so nay
thuoc loai tn hieu.
Cac dong 3 va 4 la mot phat bieu IF, phat bieu nay xac nh co phai tn hieu va thay oi hay
khong, co phai gia tr hien tai la 1 hay khong va co phai gia tr trc o la 0 hay khong. Neu tat
ca cac ieu kien nay la ung, phat bieu IF se tra ve gia tr ung (true), co ngha la mot canh tang
a c phat hien tren tn hieu. Neu mot ieu kien nao o trong cac ieu kien nay khong ung,
gia tr c tra ve se la sai (false), nh c trnh bay dong 6.
Dong 7 goi ham s dung tn hieu c tao ra bi port clk cua thc the dff. Neu co mot canh
tang tren tn hieu clk, gia tr cua d c chuyen en ngo ra q.
Cong dung pho bien nhat cua ham la tra ve mot gia tr trong mot bieu thc, tuy nhien con co
hai cong dung na co san trong VHDL. Cong dung au tien la ham chuyen oi (conversion
function) va cong dung th hai la ham phan tch (resolution function). Cac ham chuyen oi c s
dung e chuyen oi t kieu nay sang kieu khac. Cac ham phan tch c s dung e phan tch viec
tranh chap bus tren mot tn hieu co nhieu nguon kch (multiply-driven signal).
b. Ham chuyen oi:
Cac ham chuyen oi c s dung e chuyen oi mot oi tng co kieu nay thanh oi tng
co kieu khac. Cac ham chuyen oi c s dung trong cac phat bieu the hien thanh phan e cho
phep viec anh xa cac tn hieu va port co cac kieu khac nhau. Loai tnh huong nay thng phat sinh
khi mot ngi thiet ke muon s dung mot thc the t mot thiet ke khac.
Gia nh rang ngi thiet ke A ang s dung kieu d lieu co 4 gia tr nh sau:
TYPE fourval IS (X, L, H, Z);

Ngi thiet ke B ang s dung kieu d lieu cung cha 4 gia tr nhng cac nh danh gia tr lai
khac, nh c trnh bay sau ay
TYPE fourvalue IS (X, 0, 1, Z);
Ca hai kieu nay eu co the c s dung e bieu dien cac trang thai cua mot he thong gia tr
4-trang thai cho mot mo hnh cua VHDL. Neu ngi thiet ke A muon s dung mot mo hnh t
ngi thiet ke B, nhng ngi thiet ke B a s dung cac gia tr t kieu fuorvalue lam cac port giao
dien cua mo hnh, ngi thiet ke A khong the s dung mo hnh nay ma khong chuyen oi kieu cua
cac port thanh cac gia tr c s dung bi ngi thiet ke B. Van e nay co the giai quyet c
thong qua viec s dung cac ham chuyen oi.
Trc tien ta hay viet ham chuyen oi gia tr gia hai he thong.
Cac gia tr t he thong th nhat bieu dien cac trang thai phan biet:
X gia tr cha biet.
L gia tr logic 0.
H gia tr logic 1.

Ky thuat PLD va ASIC 113


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Z gia tr tong tr cao.


Cac gia tr t he thong th hai bieu dien cac trang thai:
X gia tr cha biet.
0 gia tr logic 0.
1 gia tr logic 1.
Z gia tr tong tr cao.
T mo ta tren cua hai he thong gia tr ta co mot v du ve ham chuyen oi nh sau:
V du 2-62:

FUNCTION convert4val (S : fourval) RETURN fourvalue IS


BEGIN
CASE S IS
WHEN X => RETURN X;
WHEN L => RETURN 0;
WHEN H => RETURN 1;
WHEN Z => RETURN Z;
END CASE ;
END convert4val;
Ham nay se nhan mot gia tr co kieu fourval va tra ve mot gia tr co kieu fourvalue. V du sau
ay cho thay ni ma ham co the c s dung:
V du 2-63:

PACKAGE my_std IS
TYPE fourval IS (X, L, H, Z) ;
TYPE fourvalue IS (X, L, H, Z) ;
TYPE fvector4 IS ARRAY (0 TO 3) OF fourval;

END my_std;

USE WORK.my_std.ALL;
ENTITY reg IS
PORT (a IN fvector4;
clr: IN fourval;
clk: IN fourval;
q: OUT fvector4);

FUNCTION convert4val (S : fourval) RETURN fourvalue IS


BEGIN
CASE S IS
WHEN X => RETURN X;
WHEN L => RETURN 0;

114 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

WHEN H => RETURN 1;


WHEN Z => RETURN Z;
END CASE ;
END convert4val;

FUNCTION convert4value (S : fourvalue) RETURN fourval IS


BEGIN
CASE S IS
WHEN X => RETURN X;
WHEN 0 => RETURN 0;
WHEN 1 => RETURN 1;
WHEN Z => RETURN Z;
END CASE ;
END convert4value;
END reg;

ARCHITECTURE structure OF reg IS


COMPONENT dff
PORT ( d, clk, clr: IN fourvalue;
q: OUT fourvalue;);
END COMPONENT;

BEGIN
U1: dff PORT MAP ( convert4val(a(0)),
convert4val(clk),
convert4val(clr),
convert4value(q) => q(0));

U2: dff PORT MAP ( convert4val(a(1)),


convert4val(clk),
convert4val(clr),
convert4value(q) => q(1));

U3: dff PORT MAP ( convert4val(a(2)),


convert4val(clk),
convert4val(clr),
convert4value(q) => q(2));

U4: dff PORT MAP ( convert4val(a(3)),


convert4val(clk),
convert4val(clr),
convert4value(q) => q(3));

END structure;

Ky thuat PLD va ASIC 115


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

V du nay la mot thanh ghi 4 bit c xay dng bang cac flip flop. Kieu c s dung trong
khai bao thc the cho thanh ghi la mot vector kieu fourval. Tuy nhien cac flip flop c the hien co
cac port co kieu fourvalue. Mot loi khong tng thch kieu se c tao ra neu cac port cua thc the
thanh ghi c anh xa trc tiep en cac port thanh phan. Do vay mot ham chuyen oi c can
en e chuyen oi hai he thong gia tr.
Neu cac port eu che o IN th ch mot chuyen oi c can en e anh xa t kieu cua
thc the cha en kieu cua thc the c cha. Trong v du nay, neu cac port eu che o ngo
vao th ch co ham convert4value c yeu cau.
Neu thanh phan cung co cac port ngo ra, cac gia tr ngo ra cua thc the c cha can c
chuyen oi tra ve kieu cua thc the cha. Trong v du nay port q cua thanh phan dff la mot port
ngo ra. Kieu cua cac gia tr ngo ra. Kieu cua cac gia tr ngo ra se la fourvalue. Cac gia tr nay
khong the c anh xa en cac port kieu fourval. Ham convert4value se chuyen oi t kieu
fourvalue thanh kieu fourval. Ap dung ham nay tren cac port ngo ra se cho phep anh xa port xay
ra.
Co 4 the hien thanh phan s dung cac ham chuyen oi nay: cac thanh phan t U1 en U4.
Lu y rang cac port ngo vao s dung ham chuyen oi convert4val trong khi cac port ngo ra s dung
ham chuyen oi convert4value.
Dung dang ket hp at nay cua anh xa cho the hien thanh phan U1 nh sau:
U1: dff PORT MAP ( d => convert4val(a(0)),
clk => convert4val(clk),
clr => convert4val(clk),
convert4value(p) => p(0));
Cac ham chuyen oi giai phong ngi thiet ke khoi viec tao ra nhieu tn hieu hoac bien tam
thi e the hien viec chuyen oi. V du 2-64 trnh bay mot phng phap khac e thc hien cac
ham chuyen oi:
V du 2-64:
Temp1 <= convert4val(a(0));
Temp2 <= convert4val(clk));
Temp3 <= convert4val(clr);

U1: dff PORT MAP ( d => temp1,


clk => temp2,
clr => temp3,
q => temp4);,
q(0) <= convert4value(temp4);

Phng phap nay dai dong, yeu cau mot bien tam trung gian cho moi port cua thanh phan
c anh xa. Phng phap t c la chon.
Neu mot port che o INOUT, cac ham chuyen oi khong the thc hien c vi ky hieu v
tr. Cac port phai s dung ket hp at ten do hai ham chuyen oi phai c ket hp vi port

116 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

INOUT. Mot ham chuyen oi se c s dung cho phan ngo vao cua port INOUT va mot ham
khac se c s dung cho phan ngo ra cua port nhap/xuat.
Trong v du sau ay, linh kien truyen hai chieu c cha trong thc the co ten la trans2:
V du 2-64:

PACKAGE my_pack IS
TYPE nineval IS (Z0, Z1, ZX, R0, R1, RX, F0, F1, FX) ;
TYPE nvector2 IS ARRAY (0 TO 1) OF (nineval) ;
TYPE fourstate IS (X, L, H, Z);

FUNCTION convert4state (a : fourstate) RETURN nineval;


FUNCTION convert9val(a : nineval) RETURN fourstate;
END my_pack;

PACKAGE body my_pack IS


FUNCTION convert4state (a : fourstate) RETURN nineval IS;
BEGIN
CASE a IS
WHEN X => RETURN FX;
WHEN L => RETURN F0;
WHEN H => RETURN F1;
WHEN Z => RETURN ZX;
END CASE ;
END convert4state;

FUNCTION convert9val (a : nineval) RETURN fourstate IS;


BEGIN
CASE a IS
WHEN Z0 => RETURN Z;
WHEN Z1 => RETURN Z;
WHEN ZX => RETURN Z;
WHEN R0 => RETURN L;
WHEN R1 => RETURN H;
WHEN RX => RETURN X;
WHEN F0 => RETURN L;
WHEN F1 => RETURN H;
WHEN FX => RETURN X;
END CASE ;
END convert9val;
END my_pack;

USE WORK.my_pack.ALL;
ENTITY trans2 IS
PORT ( a, b: INOUT nvector2;
enable: IN nineval);
END trans2;

ARCHITECTURE struct OF trans2 IS


COMPONENT trans
PORT ( x1, x2: INOUT fourstate;
En: OUT fourstate);
END COMPONENT;
Ky thuat PLD va ASIC 117
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

BEGIN
U1: trans PORT MAP ( convert4state(x1) => convert9val(a(0)) ,
( convert4state(x2) => convert9val(b(0)) ,
en => convert9val(enable));

U2: trans PORT MAP ( convert4state(x1) => convert4state(a(1)) ,


( convert4state(x2) => convert4state(b(1)) ,
en => convert9val(enable));
END struct;
Moi thanh phan la mot linh kien truyen hai chieu co ten la trans. Linh kien trans cha 3 port:
cac port x1 va x2 la cac port vao-ra con port en la port ngo vao. Khi port en co gia tr H th x1 c
chuyen en x2 va khi port en co gia tr L, x2 c chuyen en x1.
Cac thanh phan trans s dung kieu fourstate lam kieu cua cac port trong khi thc the cha s
dung kieu nineval. Cac ham chuyen oi c yeu cau e cho phep the hien cua cac thanh phan
trans trong kien truc struct cua thc the trans2.
Phat bieu the hien thanh phan au tien cho thanh phan trans co nhan la U1 trnh bay cach
thc ma cac ham chuyen oi c s dung cho cac port vao-ra. Anh xa port au tien se anh xa
port x1 en a(0). Port a(0) co kieu nineval do o tn hieu c tao bi port nay co kieu nineval.
Khi tn hieu nay c anh xa en port x1 cua thanh phan trans, tn hieu nay phai c
chuyen oi thanh fourstate. Ham chuyen oi convert9val phai c goi e hoan tat viec chuyen
oi. Khi d lieu c chuyen ra en port x1 oi vi phan xuat cua port vao-ra, ham chuyen oi
convert4state phai c goi.
Khi x1 thay oi, ham convert4state c goi e chuyen oi gia tr fourstate thanh gia tr
nineval trc khi c chuyen en thc the cha trans2. Ngc lai khi port a(0) thay oi, ham
convert9val c goi e chuyen oi gia tr nineval thanh gia tr fourstate, gia tr nay co the c s
dung ben trong mo hnh strans.
Cac ham chuyen oi c s dung e chuyen oi mot gia tr cua mot kieu nay thanh mot gia
tr cua kieu khac. Cac ham nay co the c goi mot cach ro rang nh la mot phan cua viec thc thi
hoac khong ro rang t mot anh xa trong mot the hien thanh phan.
c. Ham phan tch:
Ham phan tch c s dung e tra ve gia tr cua mot tn hieu khi tn hieu c kch bi
nhieu driver. Se khong hp le trong VHDL khi co mot tn hieu vi nhieu driver ma khong co ham
phan tch gan cho tn hieu o. Mot ham phan tch c goi moi khi mot driver cua tn hieu co mot
s kien xay ra. Ham phan tch se c thc thi va se tra ve mot gia tr duy nhat trong tat ca cac gia
tr cua cac driver; gia tr nay se la gia tr mi cua tn hieu.
Trong cac trnh mo phong ien hnh, cac ham phan tch c cai at san hoac co nh. Vi
VHDL ngi thiet ke co kha nang nh ngha bat ky loai ham phan tch nao mong muon, wired-or,
wired-and, gia tr trung bnh tn hieu,
Mot ham phan tch co mot ngo vao oi so duy nhat va tra ve mot gia tr duy nhat. oi so ngo
vao duy nhat nay bao gom mot dai rang buoc cac gia tr cua driver cua tn hieu ma ham phan tch
c gan. Neu tn hieu co hai driver, dai khong rang buoc se co hai phan t; neu tn hieu co ba
driver, dai khong rang buoc se co ba phan t. Ham phan tch se xem xet cac gia tr cua tat ca cac
driver va tra ve mot gia tr duy nhat goi la gia tr phan tch (resolved value) cua tn hieu.

118 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Ta hay khao sat mot ham phan tch oi vi kieu fourval a c s dung trong cac v du ham
chuyen oi. Khai bao kieu cho fourval nh sau:
TYPE fourval IS (X, L, H, Z);

4 gia tr phan biet c khai bao bieu dien tat ca cac gia tr co the co ma tn hieu co the
cha. Gia tr L bieu dien logic 0, gia tr H logic 1, gia tr Z bieu dien ieu kien tong tr cao, gia tr
X bieu dien ieu kien cha biet, trong o gia tr co the bieu dien logic 0 hoac logic 1 (ngha la tuy
nh) nhng ta khong chac la gia tr nao. Cac ieu kien nay co the xay ra khi hai driver ang kch
mot tn hieu mot driver kch vi logic H va driver kia kch vi logic L.
Liet ke vao theo th t o manh, vi yeu nhat tren cung, cac gia tr nay nh sau.
Z yeu nhat H, L va X co the ghi e.
H, L trung bnh ch co X co the ghi e.
X manh nhat khong b ghi e.
Bang cach s dung thong tin nay, mot bang gia tr co hai ngo vao co the c phat trien nh
c trnh bay bang di.
Bang 2-11 cho gia tr ngo ra co 2 ngo vao

Z L H X
Z Z L H X
L L L X X
H H X H X
X X X X X
Bang 2-11.
Bang gia tr nay dung cho cac gia tr hai ngo vao, ta co the m rong nhieu ngo vao hn bang
cach ap dung lien tiep bang nay cho hai gia tr mot thi iem. ieu nay co the thc hien c do
bang nay co tnh giao hoan va ket hp.
Mot L va mot Z hoac mot Z va mot L se cung cho ket qua.
Mot (L, Z) vi H se cho ket qua giong nh mot (H, Z) vi mot L.
Cac nguyen tac nay rat quan trong do th t cac gia tr cua driver ben trong oi so ngo vao
cua ham phan tch la khong nh trc theo quan iem cua ngi thiet ke. Bat ky phu thuoc nao
tren th t eu co the gay ra ket qua khong nh trc t ham phan tch.
Bang cach s dung tat ca cac thong tin nay, mot ngi thiet ke co the viet mot ham phan tch
cho kieu nay. Ham phan tch se duy tr o manh cao nhat trong chng mc thay c va so sanh
gia tr nay vi gia tr mi, mot phan t duy nhat mot thi iem cho en khi tat ca cac gia tr eu
a c s dung het. Giai thuat nay se tra ve gia tr co o manh cao nhat. Di ay la mot v du
cho mot ham phan tch nh vay.
V du 2-65:

PACKAGE fourpack IS
TYPE fourval IS (X, L, H, Z) ;
TYPE fourval_vector IS ARRAY (nineval RANGE <>) OF fourval;
FUNCTION resolve (s : fourval_vector) RETURN fourval;

Ky thuat PLD va ASIC 119


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

END fourpack;

PACKAGE BODY fourpack IS


FUNCTION resolve (s : fourval_vector) RETURN fourval IS
VARIABLE result : fourval := Z;

BEGIN
FOR i IN sRANGE LOOP
CASE result IS
WHEN Z =>
CASE s(i) IS
WHEN H => result := H;
WHEN L => result := L;
WHEN X => result := X;
WHEN OTHERS => NULL;
END CASE ;

WHEN L =>
CASE s(i) IS
WHEN H => result := X;
WHEN X => result := X;
WHEN OTHERS => NULL;
END CASE ;

WHEN H =>
CASE s(i) IS
WHEN L => result := X;
WHEN X => result := X;
WHEN OTHERS => NULL;
END CASE ;

WHEN X => result := X;


END CASE ;
END LOOP ;
RETURN result ;

END resolve ;
END fourpack ;
oi so ngo vao la mot mang khong rang buoc co kieu nen cua driver la fourval. Ham phan
tch se khao sat tat ca cac gia tr cua cac driver c chuyen vao oi so s, mot gia tr mot thi
iem, roi tra ve gia tr duy nhat co kieu fourval e c nh thi nh la gia tr cua tn hieu.
Bien result c khi ong bang gia tr Z cho trng hp khong co driver nao oi vi tn
hieu. Trong trng hp nay vong lap se khong bao gi c thc thi va gia tr cua result c tra
ve se la gia tr khi ong. ay cung la mot y hay neu ta khi ong gia tr cua result bang gia tr
yeu nhat cua he thong gia tr e cho phep ghi e bi cac gia tr manh hn.
Neu co mot driver c tien hanh, vong lap se c thc thi mot lan cho moi gia tr cua
driver c chuyen vao oi so s. Moi gia tr cua driver c so sanh vi gia tr hien tai c lu
trong bien result. Neu gia tr mi manh hn theo qui luat a c neu tren, gia tr cua result se
c cap nhat bang gia tr mi.
d. Thu tuc :
120 Ky thuat PLD va ASIC
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Thu tuc co the co nhieu thong so ngo vao, ra va vao-ra. Goi thu tuc c xem nh mot phat
bieu rieng, ham thng ton tai nh mot phan cua bieu thc. Trong hau het cac trng hp s dung
thu tuc ch khi co nhieu hn 1 gia tr c tra ve.
Thu tuc co nhng quy nh ve cu phap giong nh ham. Phan khai bao thu tuc bat au vi t
khoa PROCEDURE, tiep theo la ten cua thu tuc va sau o la danh sach cac oi so. S khac nhau
gia ham va thu tuc la danh sach cac oi so cua thu tuc giong nh co hng ket hp vi moi thong
so, con danh sach cua ham th khong co. Trong thu tuc, co nhieu oi so co the kieu IN, OUT
hoac INOUT, trong ham th tat ca cac oi so kieu IN.
V du 2-66 ve cach s dung thu tuc:
V du 2-66:
USE LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
PROCEDURE vector_to_int (z : IN std_logic_vector;
x_flag: OUT BOOLEAN, q : INOUT INTEGER) IS
BEGIN
Q := 0;
X_flag := false;
FOR I IN zRANGE LOOP
Q := q * 2;
IF z(i) = 1 THEN q := q + 1;
ELSIF z(i) /= F0 THEN x_flag := true;
END IF;
END LOOP ;
END vector_to_int ;
Hanh vi cua thu tuc la chuyen oi oi so ngo vao z t mang kieu so nguyen. Tuy nhien neu
mang ngo vao co gia tr cha xac nh th gia tr so nguyen khong the c tao ra t mang. Khi
ieu kien nay xay ra th oi so x_flag c thiet lap gia tr true e xac nh gia tr so nguyen ngo
ra la khong xac nh. Thu tuc c yeu cau e ieu khien hanh vi nay bi v co nhieu ket qua tra
ve. Chung ta hay kiem tra ket qua t thu tuc vi mang gia tr ngo vao nh sau:
0 0 1 1
Bc th nhat thu tuc se khi ong cac gia tr ngo ra vi cac ieu kien a biet, trong trng
hp oi so ngo vao dai bang 0 c truyen vao. oi so ngo ra x_flag c khi tao trang thai
false va tiep tuc trang thai false cho en khi chng minh trang thai ngc lai.
Phat bieu vong lap xuyen qua vector ngo vao z va tiep tuc cong moi gia tr cua vector cho
en khi tat ca cac gia tr a c cong.
Neu gia tr la 1 th sau o no c cong vao ket qua. Neu gia tr la 0 th khong cong.
Neu bat ky gia tr nao c tm thay trong vector th ket qua x_flag c thiet lap la true xac
nh rang ieu kien cha biet a c tm thay mot trong cac ngo vao. (Chu y thong so q a
c nh ngha nh thong so vao-ra, ieu nay la can thiet bi v gia tr c oc trong thu tuc).
Thu tuc khong co thong so
V du 2-67 trnh bay mot thu tuc co 1 oi so vao-ra thuoc dang ban ghi. Ban ghi cha mot
mang 8 so nguyen cung vi trng so c dung e lu gia tr trung bnh cua tat ca cac so nguyen.
Thu tuc tnh toan gia tr trung bnh cua cac gia tr so nguyen, ghi gia tr trung bnh trong vung
trng trung bnh cua ban ghi va tr ve vi ban ghi a cap nhat:

Ky thuat PLD va ASIC 121


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

V du 2-67:
PACKAGE intpack IS
TYPE bus_stat_vec IS ARRAY (0 TO 7) OF INTEGER;
TYPE bus_stat_t IS
RECORD
bus_val: bus_stat_vec;
average_val: INTEGER;
END RECORD;

PROCEDURE bus_average (x : INOUT bus_stat_t);


END intpack;

PACKAGE BODY intpack IS


PROCEDURE bus_average (x : INOUT bus_stat_t) IS
VARIABLE total : INTEGER := 0;
BEGIN
FOR i IN 0 TO 7 LOOP total := total + x.bus_val(i);
END LOOP ;
x.average_val := total / 8 ;
END bus_average ;
END intpack ;

PROCESS (mem_update)
VARIABLE bus_statistics : bus_stat_t;
BEGIN
bus_statistics.bus_val := (50, 40, 30, 35, 45, 55, 65, 85);
bus_average(bus_statistics);
average <= bus_statistics.average_val;
END PROCESS ;
Phat bieu au tien la gan bien. Phat bieu th hai la goi thu tuc bus_average e thc hien tnh
toan gia tr trung bnh. e bat au, oi so cho thu tuc bus_average la mot gia tr ngo vao nhng sau
khi thu tuc thc hien xong th oi so tr thanh gia tr ngo ra co the c s dung ben trong cho
viec goi x ly. Gia tr ngo ra t thu tuc c gan cho tn hieu ngo ra nam hang cuoi cung cua qua
trnh.
2. GOI:
Muc ch quan c ban cua goi la goi gon cac phan t co the dung chung, bao gom hai hay
nhieu n v thiet ke. Goi la mien lu tr chung c s dung e lu tr d lieu dung chung gia
mot so thc the. Viec khai bao d lieu ben trong mot goi cho phep d lieu c tham chieu bi cac
thc the khac.
Mot goi gom co hai phan: phan khai bao goi va phan than cua goi. Khai bao goi nh ngha
giao dien cho goi vi cung phng phap ma mot thc the nh ngha giao dien cho mot mo hnh.
Than cua goi ch ra hanh vi thc s cua goi theo cung phng phap ma phat bieu kien truc thc
hien oi vi mot mo hnh.
a. Khai bao goi:
Phan khai bao goi co the cha cac khai bao sau:
Khai bao chng trnh con.
Khai bao kieu, kieu con.

122 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Khai bao hang, hang tr hoan (deferred constant).


Khai bao tn hieu, tao ra mot tn hieu toan cuc.
Khai bao tap tin.
Khai bao b danh (ten khac).
Khai bao thanh phan.
Khai bao thuoc tnh, thuoc tnh do ngi s dung nh ngha.
ac ta thuoc tnh.
ac ta khong ket noi.
Menh e USE.
Tat ca cac muc c khai bao trong phan khai bao goi c nhn thay bat ky n v thiet ke
nao s dung goi nay bang menh e USE. Giao dien cua mot goi cha bat ky chng trnh con nao
hoac cac hang tr hoan c khai bao trong phan khai bao goi. Cac khai bao chng trnh con va
hang tr hoan phai co mot than chng trnh con tng ng va gia tr hang tr hoan tng ng trong
than cua goi.
Hang tr hoan: Cac hang tr hoan la cac hang co ten va kieu c khai bao trong phan khai
bao goi nhng co gia tr thc s c ch nh trong phan than cua goi. V du 2-68 ve hang tr hoan
trong khai bao goi nh sau:
V du 2-68:
PACKAGE tpack IS
CONSTANT timing_mode: t_mode;
END tpack;
V du tren trnh bay mot hang tr hoan co ten la timing_mode c nh ngha co kieu
t_mode. Gia tr thc s cua hang nay se c ch ra khi than cua goi c dch.
b. Khai bao chng trnh con:
Mot muc khac tao thanh giao dien cho goi la khai bao chng trnh con. Khai bao chng
trnh con cho phep ngi thiet ke ch nh giao dien cua mot chng trnh con tach biet khoi than
chng trnh con. Chc nang nay cho phep bat ky ngi thiet ke nao s dung chng trnh con e
bat au hoac tiep tuc viec thiet ke, trong khi o ac ta giao dien cua cac chng trnh con c
trnh bay chi tiet. Chc nang nay cung cung cap cho nha thiet ke than cac chng trnh con s t do
thay oi cac hoat ong ben trong cua cac chng trnh con ma khong anh hng en bat ky thiet
ke nao s dung chng trnh con o. V du 2-69 khai bao chng trnh con nh sau:
V du 2-69:
PACKAGE cluspack IS
TYPE nineval IS (Z0, Z1, ZX, R0, R1, RX, F0, F1, FX);
TYPE t_cluster IS ARRAY (0 TO 15) OF nineval;
TYPE t_clus_vec IS ARRAY (natural range <>) OF t_cluster;

FUNCTION resolve_cluster (s : t_clus_vec) RETURN t_cluster;


SUSTYPE t_wclus IS resolve_cluster t_cluster;
CONSTANT undriven: t_wclus;
END cluspack;

Ky thuat PLD va ASIC 123


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Khai bao chng trnh con cho resolve_cluster ch nh ten cua chng trnh con, cac oi so
bat ky cua chng trnh con, cac kieu va cac loai cua cac oi so va tra ve kieu neu chng trnh
con la mot ham. Khai bao nay co the c s dung e bien dch bat ky mo hnh nao d nh s
dung chng trnh con ma cha co than chng trnh con thc s c ch nh. Than chng trnh
con phai hien hu trc khi trnh mo phong c xay dng.
Than cua goi: Muc ch chnh cua than cua goi la nh ngha cac gia tr cho cac hang tr hoan
va ch nh cac than chng trnh con cho bat ky khai bao chng trnh con nao t khai bao goi.
Tuy nhien than goi cung co the cha cac khai bao sau:
Khai bao chng trnh con.
Than chng trnh con.
Khai bao kieu, kieu con.
Khai bao hang, khai bao nay ien vao gia tr cua hang tr hoan.
Khai bao tap tin.
Khai bao b danh.
Menh e USE.
Tat ca cac khai bao trong than cua goi ngoai tr khai bao hang ma chung ch nh gia tr
cua hang tr hoan va khai bao than chng trnh con la cuc bo oi vi than cua goi. Chung ta hay
khao sat than cua goi cho khai bao goi a c e cap phan trc.
V du 2-70:
PACKAGE BODY cluspack IS
CONSTANT undriven: t_wclus:=
(ZX, ZX, ZX, ZX,
ZX, ZX, ZX, ZX,
ZX, ZX, ZX, ZX,
ZX, ZX, ZX, ZX,);

FUNCTION resolve_cluster (s : t_clus_vec) RETURN t_cluster IS


VARIABLE result : t_cluster;
VARIABLE driver_count : integer;
BEGIN
IF SLENGTH = 0 THEN RETURN undriven;
END IF;
FOR i IN SRANGE LOOP
IF S(i) /= undriven THEN driver_count := driver_count + 1;
IF driver_count = 1 THEN result := s(i);
ELSE result := undriven;
ASSERT FALSE
REPORT multiple drivers detected
SEVERITY ERROR;
END IF;
END IF;
END LOOP ;
RETURN result;
END resolve_cluster ;
END cluspack;

124 Ky thuat PLD va ASIC


Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

Phat bieu than cua goi tng t nh khai bao goi ngoai tr t khoa BODY theo sau
PACKAGE. Tuy nhien cac noi dung cua hai n v thiet ke nay rat khac nhau. Than goi cho v du
nay ch cha hai muc: gia tr hang tr hoan cua hang tr hoan undriven va than chng trnh con
cua chng trnh con resolve_cluster. Ta hay lu y en cach thc ma ac ta gia tr hang tr hoan
tng thch vi khai bao hang tr hoan trong khai bao goi va than chng trnh con tng thch vi
khai bao chng trnh con trong khai bao goi. Than chng trnh con phai tng thch chnh xac vi
khai bao chng trnh con ve so thong so, kieu cua cac thong so va kieu tra ve.
Than cua goi cung co the cha cac khai bao cuc bo ch c s dung ben trong than cua goi
e xay dng cac than chng trnh con khac hoac cac gia tr hang tr hoan. Cac khai bao nay
khong c nhn thay t ben ngoai than cua goi nhng co the rat co ch ben trong than goi. V du
2-71 ve mot goi hoan chnh s dung tnh chat nay nh sau:
V du 2-71:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
PACKAGE math IS
TYPE st16 IS ARRAY (0 TO 15) OF std_logic;
FUNCTION add(a, b : IN st16) RETURN st16;
FUNCTION sub(a, b : IN st16) RETURN st16;
END math;

PACKAGE BODY math IS


FUNCTION vect_to_int (s : st16) RETURN INTEGER IS
VARIABLE result : INTEGER:=0;
BEGIN
FOR i IN 0 TO 7 LOOP
result := result * 2;
IF S(i) = 1 THEN result := result +1;
END IF;
END LOOP ;

RETURN result;
END vect_to_int ;

FUNCTION in_to_st16 (s : INTEGER) RETURN st16 IS


VARIABLE result : st16;
VARIABLE digit: INTEGER := 2**15;
VARIABLE local : INTEGER;
BEGIN
Local:= s;
FOR i IN 15 DOWNTO 0 LOOP
IF local/digit >= 1 THEN result(i) := 1;
Local:= Local - digit;
ELSE result(i) := 0;
END IF;
digit := digit /2;
END LOOP ;
RETURN result;
END in_to_st16 ;

FUNCTION add (a,b : IN st16) RETURN st16 IS


VARIABLE result : INTEGER;
Ky thuat PLD va ASIC 125
Chng 2. Ngon ng lap trnh VHDL SPKT Nguyen nh Phu

BEGIN
Result := vect_to_int(a) + vect_to_int(b) ;
RETURN int_to_st16 (result);

END add;
FUNCTION sub (a,b : IN st16) RETURN st16 IS
VARIABLE result : INTEGER;
BEGIN
Result := vect_to_int(a) - vect_to_int(b) ;
RETURN int_to_st16 (result);

END sub;
END math;
Khai bao goi tren la mot khai bao kieu st16 va hai ham add va sub hoat ong theo kieu neu
tren. Than goi co cha than cac ham cho cac khai bao ham add va sub va cung cha hai ham ch
c s dung trong than cua goi o la cac ham nay la int_to_st16 va vec_to_int. Cac ham nay
khong c thay t ben ngoai than cua goi. e lam cho cac ham nay co the nhn thay c, mot
khai bao ham can phai them vao phan khai bao goi cho moi ham.
Cac ham vec_to_int va int_to_st16 phai c khai bao trc ham add e dch chng trnh
cho ung. Tat ca cac ham phai c khai bao trc khi chung c s dung.

X. CAU HOI ON TAP VA BAI TAP


Cau 2-1. Hay phan biet s khac nhau gia bien va tn hieu?
Cau 2-2. Hay phan biet s khac nhau gi khai bao BIT va STD_LOGIC ?
Cau 2-3. Hay phan biet s khac nhau gi khai bao BIT va BIT_VECTOR?
Cau 2-4. Hay phan biet s khac nhau gi khai bao BIT va STD_LOGIC ?

end

126 Ky thuat PLD va ASIC


Chng 3
THIET KE MACH LOGIC TO HP BANG
VHDL

GII THIEU
THIET KE MACH GIAI MA MACH MA HOA
THIET KE MACH GIAI MA
THIET KE MACH MA HOA
THIET KE MACH GIAI MA LED 7 OAN LOAI ANODE CHUNG
THIET KE MACH A HP MACH GIAI A HP
THIET KE MACH A HP
THIET KE MACH GIAI A HP
CAU HOI ON TAP VA BAI TAP
Chng 3. Thiet Ke mach logic to hp SPKT Nguyen nh Phu
CAC HNH VE
Hnh 3-1. S o khoi mach GM 2 - 4.
Hnh 3-2. S o khoi mach GM 3 - 8.
Hnh 3-3. S o khoi mach MH 4 - 2.
Hnh 3-4. S o khoi mach GM led 7 oan loai anode chung.
Hnh 3-5. S o khoi mach H 4 vao.
Hnh 3-6. S o khoi mach GH 4 ra.

CAC BANG
Bang 3-1. BTT mach GM 2 - 4.
Bang 3-2. BTT mach GM 3 - 8.
Bang 3-3. BTT mach MH 4 - 2.
Bang 3-4. BTT mach GM led 7 oan anode chung.
Bang 3-5. BTT mach a hp 4 ngo vao.
Bang 3-6. BTT mach GH 4 ra.

128 Ky thuat PLD va ASIC


Chng 3. Thiet Ke mach logic to hp SPKT Nguyen nh Phu

I. GII THIEU:
Trong phan nay se thiet ke cac mach logic to hp dung ngon ng VHDL va s dung thiet
b lap trnh.
Cac mach logic to hp bao gom mach giai ma n ng sang m ng, mach ma hoa m
ng sang n ng, mach don kenh va mach phan kenh, mach giai ma led 7 oan loai anode
chung va cathode chung.
Cac thiet b lap trnh co the dung CPLD XC9572, XC 95144, Coolrunner XC2C256.
II. THIET KE MACH GIAI MA MACH MA HOA
1. THIET KE MACH GIAI MA:
Bai 3-1: Thiet ke mach giai ma 2 ng sang 4 ng vi ngo ra tch cc mc cao:
Bc 1: Ve s o khoi cua mach:
DECODE

I0 Q0
Q1
Q2
I1
Q3
2 to 4

Hnh 3-1. S o khoi mach GM 2 - 4.


Bc 2: Lap bang trang thai:
Ngo vao Ngo ra
I1 I0 Q3 Q2 Q1 Q0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
Bang 3-1. BTT mach GM 2 - 4.
Bc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity giaima_24 is
Port ( I : in STD_LOGIC_VECTOR (1 downto 0);
Q : out STD_LOGIC_VECTOR (3 downto 0));
end giaima_24;

architecture Behavioral of giaima_24 is

Ky thuat PLD va ASIC 129


Chng 3. Thiet Ke mach logic to hp SPKT Nguyen nh Phu
begin
PROCESS (I)
BEGIN
CASE I IS
WHEN "00" => Q <= "0001";
WHEN "01" => Q <= "0010";
WHEN "10" => Q <= "0100";
WHEN "11" => Q <= "1000";
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
end Behavioral;

Bai 3-2: Thiet ke mach giai ma 3 ng sang 8 ng vi ngo ra tch cc mc thap va 1


ngo cho phep E:
Bc 1: Ve s o khoi cua mach:
DECODE

I0 Q0
Q1
Q2
I1
Q3
I2 Q4
Q5
E Q6
Q7

3 to 8

Hnh 3-2. S o khoi mach GM 3 - 8.


Bc 2: Lap bang trang thai:
Ngo vao Ngo ra
E I2 I1 I0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
0 1 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1 1 1 1 0
1 0 0 1 1 1 1 1 1 1 0 1
1 0 1 0 1 1 1 1 1 0 1 1
1 0 1 1 1 1 1 1 0 1 1 1
1 1 0 0 1 1 1 0 1 1 1 1
1 1 0 1 1 1 0 1 1 1 1 1
1 1 1 0 1 0 1 1 1 1 1 1
1 1 1 1 0 1 1 1 1 1 1 1
Bang 3-2. BTT mach GM 3 - 8.
Bc 3: Viet chng trnh:

130 Ky thuat PLD va ASIC


Chng 3. Thiet Ke mach logic to hp SPKT Nguyen nh Phu
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity giaima_38 is
Port ( I : in STD_LOGIC_VECTOR (2 downto 0);
Q : out STD_LOGIC_VECTOR (7 downto 0);
E : in STD_LOGIC);
end giaima_38;
architecture Behavioral of giaima_38 is
BEGIN
PROCESS (I,E)
BEGIN
IF E = '0' THEN Q <= "11111111";
ELSE
CASE I IS
WHEN "000" => Q <= "11111110";
WHEN "001" => Q <= "11111101";
WHEN "010" => Q <= "11111011";
WHEN "011" => Q <= "11110111";
WHEN "100" => Q <= "11101111";
WHEN "101" => Q <= "11011111";
WHEN "110" => Q <= "10111111";
WHEN "111" => Q <= "01111111";
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
end Behavioral;

2. THIET KE MACH MA HOA


Bai 3-3: Thiet ke mach ma hoa 4 ng sang 2 ng vi ngo vao tch cc mc cao.
Bc 1: Ve s o khoi cua mach:

Ky thuat PLD va ASIC 131


Chng 3. Thiet Ke mach logic to hp SPKT Nguyen nh Phu

Hnh 3-3. S o khoi mach MH 4 - 2.


Bc 2: Lap bang trang thai:
Ngo vao Ngo ra
I3 I2 I1 I0 Q1 Q0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
Bang 3-3. BTT mach MH 4 - 2.
Bc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mahoa42 is
Port ( I : in STD_LOGIC_VECTOR (3 downto 0);
Q : out STD_LOGIC_VECTOR (1 downto 0));
end mahoa42;
architecture Behavioral of mahoa42 is
begin
PROCESS(I)
BEGIN
CASE I IS
WHEN "0001" => Q <= "00";
WHEN "0010" => Q <= "01";
WHEN "0100" => Q <= "10";
WHEN "1000" => Q <= "11";
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
end Behavioral;
3. THIET KE MACH GIAI MA LED 7 OAN LOAI ANODE CHUNG

132 Ky thuat PLD va ASIC


Chng 3. Thiet Ke mach logic to hp SPKT Nguyen nh Phu
Bai 3-4: Thiet ke mach giai ma led 7 oan loai anode chung
Bc 1: Ve s o khoi cua mach:

Hnh 3-4. S o khoi mach GM led 7 oan loai anode chung.


Bc 2: Lap bang trang thai:
So Ngo vao Ngo ra So
tp I3 I2 I1 I0 g f e d c b a hex
0 0 0 0 0 1 0 0 0 0 0 0 40
1 0 0 0 1 1 1 1 1 0 0 1 79
2 0 0 1 0 0 1 0 0 1 0 0 24
3 0 0 1 1 0 1 1 0 0 0 0 30
4 0 1 0 0 0 0 1 1 0 0 1 19
5 0 1 0 1 0 0 1 0 0 1 0 22
6 0 1 1 0 0 0 0 0 0 1 0 02
7 0 1 1 1 1 1 1 1 0 0 0 78
8 1 0 0 1 0 0 0 0 0 0 0 00
9 1 0 0 1 0 0 1 0 0 0 0 10
tat 1 0 1 0 1 1 1 1 1 1 1 7F
tat 1 0 1 1 1 1 1 1 1 1 1 7F
tat 1 1 0 0 1 1 1 1 1 1 1 7F
tat 1 1 0 1 1 1 1 1 1 1 1 7F
tat 1 1 1 0 1 1 1 1 1 1 1 7F
tat 1 1 1 1 1 1 1 1 1 1 1 7F
Bang 3-4. BTT mach GM led 7 oan anode chung.
Bc 3: Viet chng trnh:
e n gian nen trong chng trnh th ngo ra c at ten theo dang vector va ten la Y.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity giaima7doan is
Port ( I : in STD_LOGIC_VECTOR (3 downto 0);
Y : out STD_LOGIC_VECTOR (6 downto 0));
end giaima7doan;

Ky thuat PLD va ASIC 133


Chng 3. Thiet Ke mach logic to hp SPKT Nguyen nh Phu
architecture Behavioral of giaima7doan is
begin
PROCESS (I)
BEGIN
CASE I IS
when "0000" => Y <= "1000000"; -- so 0
when "0001" => Y <= "1111001"; -- so 1
when "0010" => Y <= "0100100"; -- so 2
when "0011" => Y <= "0110000"; -- so 3

when "0100" => Y <= "0011001"; -- so 4


when "0101" => Y <= "0010010"; -- so 5
when "0110" => Y <= "0000010"; -- so 6
when "0111" => Y <= "1111000"; -- so 7

when "1000" => Y <= "0000000"; -- so 8


when "1001" => Y <= "0010000"; -- so 9
when others => Y <= "1111111"; -- tat
END CASE;
END PROCESS;
end Behavioral;

III. THIET KE MACH A HP MACH GIAI A HP


1. THIET KE MACH A HP:
Bai 3-5: Thiet ke mach a hp 4 ngo vao, 1 ngo ra, 2 ngo la chon.
Bc 1: Ve s o khoi cua mach:

Hnh 3-5. S o khoi mach H 4 vao.

134 Ky thuat PLD va ASIC


Chng 3. Thiet Ke mach logic to hp SPKT Nguyen nh Phu
Bc 2: Lap bang trang thai:
Ngo vao Ngo ra
S1 S0 I3 I2 I1 I0 Q
0 0 x x x I0 I0
0 1 x X I1 X I1
1 0 X I2 x X I2
1 1 I3 x x X I3
Bang 3-5. BTT mach a hp 4 ngo vao.
Bc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity GMA is
Port ( I : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Q : out STD_LOGIC);
end GMA;
architecture Behavioral of GMA is
begin
PROCESS(I,S)
BEGIN
CASE S IS
WHEN "00" => Q <= I(0);
WHEN "01" => Q <= I(1);
WHEN "10" => Q <= I(2);
WHEN "11" => Q <= I(3);
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
end Behavioral;
2. THIET KE MACH GIAI A HP
Bai 3-6: Thiet ke mach giai a hp 1 ngo vao, 4 ngo ra, 2 ngo la chon.
Bc 1: Ve s o khoi cua mach:

Ky thuat PLD va ASIC 135


Chng 3. Thiet Ke mach logic to hp SPKT Nguyen nh Phu

Hnh 3-6. S o khoi mach GH 4 ra.


Bc 2: Lap bang trang thai:
Ngo vao Ngo ra
I S1 S0 Y3 Y2 Y1 Y0
I 0 0 0 0 0 I
I 0 1 0 0 I 0
I 1 0 0 I 0 0
I 1 1 I 0 0 0
Bang 3-6. BTT mach GH 4 ra.
Bc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity GDH is
Port ( I : in STD_LOGIC;
S : in STD_LOGIC_VECTOR (1 downto 0);
Q : out STD_LOGIC_VECTOR (3 downto 0));
end GDH;
architecture Behavioral of GDH is
begin
PROCESS(I,S)
BEGIN
CASE S IS
WHEN "00" => Q(0) <= I;
WHEN "01" => Q(1) <= I;
WHEN "10" => Q(2) <= I;
WHEN "11" => Q(3) <= I;
WHEN OTHERS => NULL;
END CASE;

136 Ky thuat PLD va ASIC


Chng 3. Thiet Ke mach logic to hp SPKT Nguyen nh Phu
END PROCESS;
end Behavioral;

IV. CAU HOI ON TAP VA BAI TAP


Bai tap 3-1: Thiet ke mach giai ma 2 ng sang 4 ng vi ngo ra tch cc mc thap va
co mot tn hieu cho phep E tch cc mc cao.
Bai tap 3-2: Thiet ke mach giai ma 2 ng sang 4 ng vi ngo ra tch cc mc thap va
co mot tn hieu cho phep E1 tch cc mc cao, va mot tn hieu cho phep E2 tch cc mc thap.
Bai tap 3-3: Thiet ke mach giai ma ben trong co 4 mach giai ma 2 ng sang 4 ng
vi ngo ra tch cc mc thap.
Bai tap 3-4: Thiet ke mach giai ma 3 ng sang 8 ng vi ngo ra tch cc mc thap va
co mot tn hieu cho phep E1 tch cc mc cao, va mot tn hieu cho phep E2 tch cc mc thap.
Bai tap 3-5: Thiet ke mach ma hoa 8 ng sang 3 ng vi cac ngo vao tch cc mc
thap.
Bai tap 3-6: Thiet ke mach ma hoa 8 ng sang 3 ng vi cac ngo vao tch cc mc
cao.
Bai tap 3-7: Thiet ke mach giai ma led 7 oan loai cathode chung.
Bai tap 3-8: Thiet ke mach giai ma led 7 oan loai giong nh IC 74247.
Bai tap 3-9: Thiet ke mach giai ma led 7 oan loai giong nh IC 4511.
Bai tap 3-10: Thiet ke mach a hp 8 ngo vao, 1 ngo ra va 3 ngo la chon.
Bai tap 3-11: Thiet ke mach a hp 16 ngo vao, 1 ngo ra va 4 ngo la chon.
Bai tap 3-12: Thiet ke mach giai a hp 1 ngo vao, 8 ngo ra va 3 ngo la chon.
Bai tap 3-13: Thiet ke mach giai a hp 1 ngo vao, 16 ngo ra va 4 ngo la chon.
Bai tap 3-14: Thiet ke mach giai a hp giong nh IC 74151.
Bai tap 3-15: Thiet ke mach so sanh 2 so 8 bit A va B va co 3 led hien th LEDLH,
LEDBA, LEDNH. Neu A>B th LEDLH sang, neu A=B th LEDBA sang, neu A<B th LEDNH
sang.
Bai tap 3-16: Thiet ke mach chuyen oi so nh phan 8 bit thanh so BCD.
Bai tap 3-17: Thiet ke mach chuyen oi so 2 so BCD thanh so nh phan.
Bai tap 3-18: Thiet ke mach kiem tra chan le cua mot so nh phan 8 bit, neu la so chan th
en chan sang, neu la so le th en le sang.

end
Ky thuat PLD va ASIC 137
Chng 3. Thiet Ke mach logic to hp SPKT Nguyen nh Phu

138 Ky thuat PLD va ASIC


Chng 4
CAC FLIP FLOP, THANH GHI, BO EM
TRONG VHDL

GII THIEU
THIET KE CAC LOAI FLIP FLOP
THIET KE FLIP FLOP JK
THIET KE FLIP FLOP D CO ENABLE
THIET KE THANH GHI DCH
THIET KE THANH GHI DCH 4 BIT
THIET KE THANH GHI DCH 8 BIT
THIET KE MACH EM JOHNSON 8 BIT
THIET KE MACH EM VONG 8 BIT
THIET KE MACH IEU KHIEN 8 LED SANG DAN TAT DAN
THIET KE MACH EM
THIET KE MACH EM NH PHAN 4 BIT EM LEN
THIET KE MACH BCD EM LEN
THIET KE MACH EM BCD VA GIAI MA HIEN TH LED 7 OAN
THIET KE MACH EM BCD T 00 EN 59 HIEN TH TREN 2 LED 7 OAN
THIET KE MACH EM BCD T 000 EN 999 HIEN TH TREN 3 LED 7 OAN
CAU HOI ON TAP VA BAI TAP
Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
Hnh 4-1. S o khoi FLIP FLIP JK.
Hnh 4-2. S o khoi FLIP FLIP D co enable.
Hnh 4-3. S o khoi thanh ghi 4 bit.
Hnh 4-4. S o khoi thanh ghi 4 bit, nap song song.
Hnh 4-5. S o khoi thanh ghi 8 bit.
Hnh 4-6. S o khoi mach em vong Johnson 8 bit.
Hnh 4-7. S o khoi mach em vong 8 bit.
Hnh 4-8. S o khoi mach ieu khien 8 led sang tat dan.
Hnh 4-9. S o khoi mach em nh phan 4 bit.
Hnh 4-10. S o khoi mach em BCD.
Hnh 4-11. S o khoi mach em BCD co giai ma 7 oan anode chung.
Hnh 4-12. S o khoi mach em t 00 en 59 co hien th.
Hnh 4-13. S o khoi mach em t 000 en 999.

Bang 4-1. BTT FLIP FLIP JK.


Bang 4-2. BTT FLIP FLIP D co enable.
Bang 4-3. BTT mach thanh ghi dch 4 bit.
Bang 4-4. BTT mach thanh ghi dch 4 bit, nap song song.
Bang 4-5. BTT thanh ghi dch 8 bit.
Bang 4-6. BTT mach em JOHNSON 8 bit.
Bang 4-7. BTT mach mach em vong 8bit.
Bang 4-8. BTT mach ieu khien 8 led sang tat dan.
Bang 4-9. BTT mach em nh phan 4 bit.
Bang 4-10. BTT mach em BCD.
Bang 4-11. BTT mach em BCD co giai ma 7 oan.

142 Ky thuat PLD va ASIC


Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu

I. GII THIEU:
Trong phan nay se thiet ke cac mach flip flop, thanh ghi va mach em dung ngon ng VHDL
va s dung thiet b lap trnh.
Cac mach flip flop bao gom flip flop JK, flip flop T, flip flop D.
Thanh ghi dch bao gom thanh ghi dch noi tiep sang noi tiep, noi tiep sang song song, mach
em vong, mach em JohnSon.
Mach em nh phan, mach em len em xuong, mach em BCD, mach em at trc so
em, mach em co giai ma sang led 7 oan, mach em giay, em phut giay,
Cac thiet b lap trnh co the dung CPLD XC9572, XC 95144, Coolrunner XC2C256.
II. THIET KE CAC LOAI FLIP FLOP
1. THIET KE FLIP FLOP JK:
Bai 4-1: Thiet ke flip flop JK gom co cac ngo vao J, K, CLK, PRE, CLR va cac ngo ra gom Q
va Q :

Bc 1: Ve s o khoi cua mach:

Hnh 4-1. S o khoi FF JK.


Bc 2: Bang trang thai:

NGO VAO NGO RA


Pre CLR CLK J K Q QD
0 0 X X X 1 1
0 1 X X X 1 0
1 0 X X X 0 1
1 1 0 X X Q0 QD0
1 1 0 0 Q0 QD0
1 1 0 1 0 1
1 1 1 0 1 0
1 1 1 1 NOT Q0 NOT QD0
Bang 4-1. BTT FF JK.
Bc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
Ky thuat PLD va ASIC 143
Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ffjk is
Port ( J : in STD_LOGIC;
K : in STD_LOGIC;
CLK : in STD_LOGIC;
PRE : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out STD_LOGIC;
QD : out STD_LOGIC);
end ffjk;
architecture Behav_ffjk of ffjk is
SIGNAL QT,QDT: STD_LOGIC;
SIGNAL JK : STD_LOGIC_VECTOR(1 DOWNTO 0);
begin
PROCESS(J,K,CLK,PRE,CLR)
BEGIN
IF (PRE='0') AND (CLR='0') THEN QT <='1'; QDT <='1';
IF (PRE='0') AND (CLR='1') THEN QT <='1'; QDT <='0';
ELSIF (PRE='1') AND (CLR='0') THEN QT <='0'; QDT <='1';
ELSIF (PRE='1') AND (CLR='1') THEN
IF CLK='0' AND CLK'EVENT THEN
JK <=J & K;
CASE T IS
WHEN "11" => QT <=NOT QT; QDT <=NOT QDT;
WHEN "10" => QT <='1'; QDT <='0';
WHEN "01" => QT <='0'; QDT <='1';
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
END PROCESS;
Q <= QT;
QD <= QDT;
end Behav_ffjk;
2. THIET KE FLIP FLOP D CO ENABLE:

144 Ky thuat PLD va ASIC


Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
Bai 4-2: Thiet ke flip flop D gom co cac ngo vao D, CLK, Enable va ngo ra gom Q va Q :

Bc 1: Ve s o khoi cua mach:

Hnh 4-2. S o khoi FF D co enable.


Bc 2: Bang trang thai:
NGO VAO NGO RA
E clk D Q QD
0 x x Q0 QD0
1 0 0 Q0 QD0
1 0 0 1
1 1 1 0
Bang 4-2. BTT FF D co enable.
Bc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ff_de is
Port ( D : in STD_LOGIC;
E : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC;
QD : out STD_LOGIC);
end ff_de;
architecture Behavioral of ff_de is
SIGNAL QT: STD_LOGIC;
begin
PROCESS(D,E,CLK)
BEGIN
IF E='1' THEN
IF CLK='0' AND CLK'EVENT THEN QT <= D;
END IF;
END IF;
Ky thuat PLD va ASIC 145
Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
Q <= QT;
QD <= NOT QT;
END PROCESS;
end Behavioral;

III. THIET KE THANH GHI DCH


1. THIET KE THANH GHI DCH 4 BIT:
Bai 4-3: Thiet ke thanh ghi dch 4 bit vao noi tiep ra noi tiep.
Bc 1: Ve s o khoi cua mach:

Hnh 4-3. S o khoi thanh ghi 4 bit.


Bc 2: Lap bang trang thai:
NGO VAO NGO RA Ghi chu
clr clk D Q3 Q2 Q1 Q0
0 x x 0 0 0 0 Reset
1 0 x Q30 Q20 Q10 Q00 Khong co xung clk
1 d Q20 Q10 Q00 d Dch d lieu vao
Bang 4-3. BTT thanh ghi 4 bit.
Bc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg4b is
Port ( D : in STD_LOGIC;
CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end reg4b;
architecture Behavioral of reg4b is
begin
process(D,CLK,CLR)
variable QT: std_logic_vector(3 downto 0);
146 Ky thuat PLD va ASIC
Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
begin
if CLR ='0' then QT :="0000";
elsif CLK='1' and CLK'event then
QT(3 downto 0) := QT(2 downto 0) & D;
end if;
Q <= QT;
end process;
end Behavioral;
Bai 4-4: Thiet ke thanh ghi dch 4 bit vao noi tiep, song song, ra noi tiep song song.
Bc 1: Ve s o khoi cua mach:

Hnh 4-4. S o khoi thanh ghi 4 bit, nap song song, noi tiep.
Bc 2: Lap bang trang thai:
NGO VAO NGO RA Ghi chu
CLR CLK D PL P3 P2 P1 P0 Q3 Q2 Q1 Q0
0 x x x x x x x 0 0 0 0 Reset
1 x x 0 P3 P2 P1 P0 P3 P2 P1 P0 Load
1 0 x 1 x x x x Q30 Q20 Q10 Q00 Khong co xung clk
1 d 1 x x x X Q20 Q10 Q00 d Dch d lieu vao
Bang 4-4. BTT mach thanh ghi dch 4 bit, nap song song, noi tiep.
Bc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tghi4b_ntss is
Port ( D : in STD_LOGIC;
CLR : in STD_LOGIC;
CLK : in STD_LOGIC;

Ky thuat PLD va ASIC 147


Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
P : in STD_LOGIC_VECTOR (3 downto 0);
Q : out STD_LOGIC_VECTOR (3 downto 0);
PL : in STD_LOGIC);
end tghi4b_ntss;
architecture Behavioral of tghi4b_ntss is
begin
PROCESS(D,CLR,CLK,P,LOAD)
VARIABLE QT: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF CLR='0' THEN QT:= "0000";
ELSIF PL='0' THEN QT:= P;
ELSIF CLK='1' AND CLK'EVENT THEN QT:= QT(2 DOWNTO 0) & D;
END IF;
Q <= QT;
END PROCESS;
end Behavioral;
2. THIET KE THANH GHI DCH 8 BIT:
Bai 4-5: Thiet ke thanh ghi dch 8 bit vao noi tiep, ra noi tiep song song.
Bc 1: Ve s o khoi cua mach:

D Q0
Q1
CLK
Q2
CLR Q3
Q4
Q5
Q6
Q7

Hnh 4-5. S o khoi thanh ghi 8 bit.


Bc 2: Lap bang trang thai:
NGO VAO NGO RA Ghi chu
clr clk D Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
0 x x 0 0 0 0 0 0 0 0 Reset
1 0 x Q7O Q6O Q5O Q4O Q3O Q2O Q1O Q0O Khong co xung clk
1 d Q6O Q5O Q4O Q3O Q2O Q1O Q0O d Dch d lieu vao
Bang 4-5. BTT thanh ghi dch 8 bit.
Bc 3: Viet chng trnh:

148 Ky thuat PLD va ASIC


Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TGHI8BIT is
Port ( CLK : in STD_LOGIC;
CLR,D : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end TGHI8BIT;
architecture Behavioral of TGHI8BIT is
SIGNAL QT: STD_LOGIC_VECTOR (7 downto 0);
begin
PROCESS (CLK,CLR)
BEGIN
IF CLR = '0' THEN QT <= "00000000";
ELSIF CLK='1' AND CLK'EVENT THEN
QT <= QT(6 DOWNTO 0) & D;
END IF;
END PROCESS;
Q <= QT;
end Behavioral;
3. THIET KE MACH EM JOHNSON 8 BIT:
Bai 4-6: Thiet ke mach em vong JONHSON 8 bit.
Bc 1: Ve s o khoi cua mach:

Hnh 4-6. S o khoi mach em vong Johnson 8 bit.


Chu y: D a c ket noi vi ngo ra Q7 va nam ben trong mach ien.

Bc 2: Lap bang trang thai:


Ky thuat PLD va ASIC 149
Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
NGO VAO NGO RA
clr clk Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
0 X 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1 1
1 0 0 0 0 0 1 1 1
1 0 0 0 0 1 1 1 1
1 0 0 0 1 1 1 1 1
1 0 0 1 1 1 1 1 1
1 0 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 0 0
1 1 1 1 1 1 0 0 0
1 1 1 1 1 0 0 0 0
1 1 1 1 0 0 0 0 0
1 1 1 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0
Bang 4-6. BTT mach em JOHNSON 8 bit.
Bc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity johnson8bit is
Port ( CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end johnson8bit;
architecture Behavioral of johnson8bit is
SIGNAL QT: STD_LOGIC_VECTOR (7 downto 0);
SIGNAL D : STD_LOGIC;
begin
PROCESS (CLK,CLR)
BEGIN
IF CLR = '1' THEN QT <= "00000000";
ELSIF CLK='1' AND CLK'EVENT THEN
D <= NOT QT(7);

150 Ky thuat PLD va ASIC


Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
QT <= QT(6 DOWNTO 0) & D;
END IF;
END PROCESS;
Q <= QT;
end Behavioral;
4. THIET KE MACH EM VONG 8 BIT:
Bai 4-7: Thiet ke mach em vong 8 bit.
Bc 1: Ve s o khoi cua mach:

Q0
Q1
CLK Q2
CLR Q3
Q4
Q5
D Q6
Q7

8 BIT RING COUNTER

Hnh 4-7. S o khoi mach em vong 8 bit.


Bc 2: Lap bang trang thai:
NGO VAO NGO RA
clr clk Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
0 X 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1 0
1 0 0 0 0 0 1 0 0
1 0 0 0 0 1 0 0 0
1 0 0 0 1 0 0 0 0
1 0 0 1 0 0 0 0 0
1 0 1 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0
Bang 4-7. BTT mach em vong 8bit.
Bc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ringcounter8 is
Port ( CLK : in STD_LOGIC;

Ky thuat PLD va ASIC 151


Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
CLR : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(7 downto 0));
end ringcounter8;
architecture Behavioral of ringcounter8 is
SIGNAL QT: STD_LOGIC_VECTOR(7 downto 0):=00000001;
begin
PROCESS (CLK,CLR)
BEGIN
IF CLR = '0' THEN QT <="00000001";
ELSIF CLK='1' AND CLK'EVENT THEN
QT <= QT(6 DOWNTO 0) & QT(7);
END IF;
END PROCESS;
Q <= QT;
end Behavioral;

Chu y: Chng trnh sau s dung bien thay v tn hieu nh cac chng trnh tren:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ringcounter8 is
Port ( CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end ringcounter8;
architecture Behavioral of ringcounter8 is
begin
PROCESS (CLK,CLR)
VARIABLE QT: STD_LOGIC_VECTOR (7 downto 0);
BEGIN
IF CLR = '0' THEN QT:="00000001";
ELSIF CLK='0' AND CLK'EVENT THEN
QT := QT(6 DOWNTO 0) & QT(7);
END IF;
Q <= QT;

152 Ky thuat PLD va ASIC


Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
END PROCESS;
end Behavioral;
5. THIET KE MACH IEU KHIEN 8 LED SANG DAN TAT DAN:
Bai 4-8: Thiet ke mach ieu khien 8 led sang dan, tat dan t trai sang phai va t phai sang
trai theo xung clock.
Bc 1: Ve s o khoi cua mach:

Hnh 4-8. S o khoi mach ieu khien 8 led sang tat dan.
Bc 2: Lap bang trang thai:
NGO VAO NGO RA
clr clk Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 THAP PHAN
0 X 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 1 1
1 0 0 0 0 0 0 1 1 2
1 0 0 0 0 0 1 1 1 3
1 0 0 0 0 1 1 1 1 4
1 0 0 0 1 1 1 1 1 5
1 0 0 1 1 1 1 1 1 6
1 0 1 1 1 1 1 1 1 7
1 1 1 1 1 1 1 1 1 8
1 1 1 1 1 1 1 1 0 9
1 1 1 1 1 1 1 0 0 10
1 1 1 1 1 1 0 0 0 11
1 1 1 1 1 0 0 0 0 12
1 1 1 1 0 0 0 0 0 13
1 1 1 0 0 0 0 0 0 14
1 1 0 0 0 0 0 0 0 15
1 0 0 0 0 0 0 0 0 16
1 1 0 0 0 0 0 0 0 17
1 1 1 0 0 0 0 0 0 18
1 1 1 1 0 0 0 0 0 19
1 1 1 1 1 0 0 0 0 20
1 1 1 1 1 1 0 0 0 21
1 1 1 1 1 1 1 0 0 22
1 1 1 1 1 1 1 1 0 23
1 1 1 1 1 1 1 1 1 24
1 0 1 1 1 1 1 1 1 25
1 0 0 1 1 1 1 1 1 26

Ky thuat PLD va ASIC 153


Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
1 0 0 0 1 1 1 1 1 27
1 0 0 0 0 1 1 1 1 28
1 0 0 0 0 0 1 1 1 29
1 0 0 0 0 0 0 1 1 30
1 0 0 0 0 0 0 0 1 31
1 0 0 0 0 0 0 0 0 32
Bang 4-8. BTT mach ieu khien 8 led sang tat dan.
Cac trang thai sang dan tat dan t phai sang trai can 16 xung clock va trang thai ngc lai
cung can 16 xung clock.
Bc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sangtatdan_tppt is
Port ( CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end sangtatdan_tppt;
architecture Behavioral of sangtatdan_tppt is
SIGNAL QT: STD_LOGIC_VECTOR (7 downto 0);
begin
PROCESS(CLK,CLR)
VARIABLE DEM: INTEGER RANGE 0 TO 32;
BEGIN
IF CLR ='1' THEN QT <= "00000000";
ELSIF CLK='1' AND CLK'EVENT THEN
IF DEM <16 THEN
QT <= QT(6 DOWNTO 0) & NOT QT(7);
DEM:= DEM +1;
ELSE QT <= NOT QT(0) & QT(7 DOWNTO 1);
DEM:= DEM +1;
END IF;
IF DEM = 32 THEN DEM:=0;
END IF;
END IF;
END PROCESS;

154 Ky thuat PLD va ASIC


Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
Q <= QT;
end Behavioral;
Trong chng trnh bien DEM co chc nang lam bien em e thc hien lan lt cac trang
thai.
IV. THIET KE MACH EM
1. THIET KE MACH EM NH PHAN 4 BIT EM LEN
Bai 4-9: Thiet ke mach em nh phan 4 bit.
Bc 1: Ve s o khoi cua mach:

Hnh 4-9. S o khoi mach em nh phan 4 bit.


Bc 2: Lap bang trang thai:
NGO VAO NGO RA Ghi chu
clr clk Q3 Q2 Q1 Q0
0 x 0 0 0 0 Reset
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
. .. ..
1 1 1 1 1
1 0 0 0 0
Bang 4-9. BTT mach em nh phan 4 bit.
Bc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cout_4bit is
Port ( CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end cout_4bit;
architecture Behavioral of cout_4bit is
begin
Ky thuat PLD va ASIC 155
Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
PROCESS(CLK,CLR)
VARIABLE QT: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF CLR ='0' THEN QT:= "0000";
ELSIF CLK='1' AND CLK'EVENT THEN QT:= QT +1;
END IF;
Q <= QT;
END PROCESS;
end Behavioral;
2. THIET KE MACH EM BCD EM LEN:
Bai 4-10: Thiet ke mach em bcd.
Bc 1: Ve s o khoi cua mach:

Hnh 4-10. S o khoi mach em BCD.


Bc 2: Lap bang trang thai:
NGO VAO NGO RA Ghi chu
clr clk Q3 Q2 Q1 Q0
0 x 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 0 0 0 0
Bang 4-10. BTT mach em BCD.
Bc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

156 Ky thuat PLD va ASIC


Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcdcounter is
Port ( CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end bcdcounter;
architecture Behavioral of bcdcounter is
begin
PROCESS(CLK,CLR)
VARIABLE QT: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF CLR ='0' THEN QT:= "0000";
ELSIF CLK='1' AND CLK'EVENT THEN QT:= QT +1;
IF QT = "1010" THEN QT := 0000 ;
END IF;
END IF;
Q <= QT;
END PROCESS;
end Behavioral;
3. THIET KE MACH EM BCD VA GIAI MA HIEN TH LED 7 OAN
Bai 4-11: Thiet ke mach em bcd hien th tren led 7 oan.
Bc 1: Ve s o khoi cua mach:

Q0 I0 a
b
Q1 I1 c
CLK d
CLR Q2 I2 e
f
Q3 I3 g

BCD SEGMENT LED


COUNTER DECODE

Hnh 4-11. S o khoi mach em BCD co giai ma 7 oan anode chung.


Bc 2: Lap bang trang thai:
NGO VAO NGO RA
tp clr clk Q3 Q2 Q1 Q0 dp g f e d c b a hex
0 0 x 0 0 0 0 1 1 0 0 0 0 0 0 C0
1 1 0 0 0 1 1 1 1 1 1 0 0 1 F9

Ky thuat PLD va ASIC 157


Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
2 1 0 0 1 0 1 0 1 0 0 1 0 0 A4
3 1 0 0 1 1 1 0 1 1 0 0 0 0 B0
4 1 0 1 0 0 1 0 0 1 1 0 0 1 99
5 1 0 1 0 1 1 0 0 1 0 0 1 0 92
6 1 0 1 1 0 1 0 0 0 0 0 1 0 82
7 1 0 1 1 1 1 1 1 1 1 0 0 0 F8
8 1 1 0 0 0 1 0 0 0 0 0 0 0 80
9 1 1 0 0 1 1 0 0 1 0 0 0 0 90
Bang 4-11. BTT mach em BCD co giai ma 7 oan.
Bc 3: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity count_bcd_gma is
Port ( CLR : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0);
L7D : out STD_LOGIC_VECTOR (6 downto 0));
end count_bcd_gma;
architecture Behavioral of count_bcd_gma is
begin
PROCESS (CLR,CLK)
VARIABLE QTAM: STD_LOGIC_VECTOR (3 downto 0);
VARIABLE YTAM: STD_LOGIC_VECTOR (6 downto 0);
BEGIN
IF CLR='0' THEN QTAM :="0000";
ELSIF CLK='1' AND CLK'EVENT THEN QTAM:= QTAM +1;
IF QTAM = "1010" THEN QTAM:="0000";
END IF;
END IF;
CASE QTAM IS
when "0000" => YTAM := x"C0"; -- so 0
when "0001" => YTAM := x"F9"; -- so 1
when "0010" => YTAM := x"A4"; -- so 2
when "0011" => YTAM := x"B0"; -- so 3
when "0100" => YTAM := x"99"; -- so 4

158 Ky thuat PLD va ASIC


Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
when "0101" => YTAM := x"92"; -- so 5
when "0110" => YTAM := x"82"; -- so 6
when "0111" => YTAM := x"F8"; -- so 7
when "1000" => YTAM := x"80"; -- so 8
when "1001" => YTAM := x"90"; -- so 9
when others => YTAM := x"FF"; -- tat
END CASE;
Q <= QTAM;
L7D <= YTAM;
END PROCESS;
end Behavioral;
4. THIET KE MACH EM BCD T 00 EN 59 HIEN TH TREN 2 LED 7 OAN
Bai 4-12: Thiet ke mach em bcd t 00 en 59 hien th tren 2 led 7 oan ket noi theo phng
phap quet. S dung nguon xung clock co tan so 1,8432MHz tren bo th nghiem dung e quet va
lam xung tang gia tr em.
Bc 1: Ve s o khoi cua mach:
Vcc

OSC anod0
1,8432MHz CLK anod1

a
b
c
CLR d
e
f
g

Hnh 4-12. S o khoi mach em t 00 en 59 co hien th.


Bc 2: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DEM0099 is
Port ( CLR : in std_logic;
CLK : in std_logic;
anod : out std_logic_vector(3 downto 0);

Ky thuat PLD va ASIC 159


Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
QB : out std_logic_vector( 7 downto 0);
ma7d : out std_logic_vector( 7 downto 0));
end DEM0099;

architecture Behavioral of DEM0099 is


signal F: std_logic_vector(18 downto 0);
signal mabl: std_logic_vector(7 downto 0);
signal mabh: std_logic_vector(7 downto 0);

function giai_ma(x1: in std_logic_vector(3 downto 0)) return std_logic_vector is

variable z1: std_logic_vector(7 downto 0);


begin
case x1 is
when "0000" => z1 := "11000000"; -- so 0
when "0001" => z1 := "11111001"; -- so 1
when "0010" => z1 := "10100100"; -- so 2
when "0011" => z1 := "10110000"; -- so 3

when "0100" => z1 := "10011001"; -- so 4


when "0101" => z1 := "10010010"; -- so 5
when "0110" => z1 := "10000010"; -- so 6
when "0111" => z1 := "11111000"; -- so 7

when "1000" => z1 := "10000000"; -- so 8


when "1001" => z1 := "10010000"; -- so 9
when others =>z1 := "11111111"; -- so
end case;
return z1;
end giai_ma;
begin
process (CLR,CLK,F,mabl,mabh)
variable bcd1: std_logic_vector(3 downto 0);
variable bcd2: std_logic_vector(3 downto 0);
begin

160 Ky thuat PLD va ASIC


Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
if CLR = '1' then bcd1:="0000"; bcd2:="0000";
F <= "0000000000000000000";
elsif RISING_EDGE(CLK) then F <= F + 1;
if F = "1111111111111111111" then bcd1:=bcd1+1;
if bcd1 = "1010" then bcd1:="0000";
bcd2:= bcd2+1;
if bcd2 = "0110" then bcd2:="0000";
end if;
end if;
nd if;
end if;
QB <= bcd2 & bcd1 ; -- hien thi 8 led don
mabh <= giai_ma(bcd2);
mabl <= giai_ma(bcd1);
case F (10 downto 9)is
when "00" => ma7d <= mabh;
anod <="0010";
when "10" => ma7d <= mabl;
anod <="0001";
when others => null;
end case;
END PROCESS;
end Behavioral;
5. THIET KE MACH EM BCD T 000 EN 999 HIEN TH TREN 3 LED 7 OAN
Bai 4-13: Thiet ke mach em bcd t 000 en 999 hien th tren 3 led 7 oan ket noi theo
phng phap bnh thng. S dung nguon xung clock tuy y.
Bc 1: Ve s o khoi cua mach:
g

g
d

d
c

c
b

e
a

a
f

Hnh 4-13. S o khoi mach em t 000 en 999.

Ky thuat PLD va ASIC 161


Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
Bc 2: Viet chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DEM_999000 is
Port ( CLR : in STD_LOGIC;
CLK : in STD_LOGIC;
QDVI : out STD_LOGIC_VECTOR (6 downto 0);
QCHU : out STD_LOGIC_VECTOR (6 downto 0);
QTRA : out STD_LOGIC_VECTOR (6 downto 0));
end DEM_999000;

architecture Behavioral of DEM_999000 is


signal GMA_DVI: std_logic_vector(7 downto 0);
signal GMA_CHU: std_logic_vector(7 downto 0);
signal GMA_TRM: std_logic_vector(7 downto 0);

function giai_ma(x1: in std_logic_vector(3 downto 0)) return std_logic_vector is

variable z1: std_logic_vector(6 downto 0);


begin
case x1 is
when "0000" => z1 := "1000000"; -- so 0
when "0001" => z1 := "1111001"; -- so 1
when "0010" => z1 := "0100100"; -- so 2
when "0011" => z1 := "0110000"; -- so 3
when "0100" => z1 := "0011001"; -- so 4
when "0101" => z1 := "0010010"; -- so 5
when "0110" => z1 := "0000010"; -- so 6
when "0111" => z1 := "1111000"; -- so 7
when "1000" => z1 := "0000000"; -- so 8
when "1001" => z1 := "0010000"; -- so 9
when others =>z1 := "1111111"; -- TATLED
end case;

162 Ky thuat PLD va ASIC


Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
return z1;
end giai_ma;
begin
process (CLR,CLK)
variable BCD_DVI: std_logic_vector(3 downto 0);
variable BCD_CHU: std_logic_vector(3 downto 0);
variable BCD_TRA: std_logic_vector(3 downto 0);
begin
if CLR = '1' then BCD_DVI:="0000";
BCD_CHU:="0000";
BCD_TRA:="0000";

Elsif CLK= '1' and CLK'event then


BCD_DVI:=BCD_DVI+1;
if BCD_DVI= "1010" then
BCD_DVI:="0000";
BCD_CHU:= BCD_CHU+1;
if BCD_CHU= "1010" then
BCD_CHU:="0000";
BCD_TRA:= BCD_TRA+1;
if BCD_TRA= "1010" then
BCD_TRA:="0000";
end if;
end if;
end if;
end if;
QDVI <= giai_ma(BCD_DVI);
QCHU <= giai_ma(BCD_CHU);
QTRA <= giai_ma(BCD_TRA);
END PROCESS;
end Behavioral;

V. CAU HOI ON TAP VA BAI TAP


Bai tap 4-1: Thiet ke flip flop RS.
Bai tap 4-2: Thiet ke mach chot D.
Bai tap 4-3: Thiet ke flip flop D.

Ky thuat PLD va ASIC 163


Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
Bai tap 4-4: Thiet ke flip flop T.
Bai tap 4-5: Thiet ke 4 flip flop D gom 4 ngo vao D, 4 ngo ra Q va 4 ngo ra QD, dung chung
1 CLK.
Bai tap 4-6: Thiet ke 8 flip flop T gom 8 ngo vao T, 8 ngo ra Q va 8 ngo ra QD, dung chung
CLK.
Bai tap 4-7: Thiet ke thanh ghi dch giong nh IC 74164.
Bai tap 4-8: Thiet ke thanh ghi dch giong nh IC 47194.
Bai tap 4-9: Thiet ke mach ieu khien en giao thong vi xanh_1, vang_1, o_1, xanh_2,
vang_2, o_2. Cho xanh sang 15 giay, vang sang 5 giay va o sang 20 giay.
Bai tap 4-10: Thiet ke mach ieu khien en 8 led n vi yeu cau nh sau: iem sang chay
t phai sang trai va t trai sang phai theo xung clock va co 1 chan cho phep E tch cc mc 0.
Bai tap 4-11: Thiet ke mach co chc nang giong nh IC 4017.
Bai tap 4-12: Thiet ke mach co chc nang giong nh IC 4017 nhng gom co 20 ngo ra.
Bai tap 4-13: Thiet ke mach co chc nang giong nh IC 4017 nhng gom 2 con: mot con em
hang n v va mot con em hang chuc.
Bai tap 4-14: Thiet ke mach em nh phan 4 bit em xuong.
Bai tap 4-15: Thiet ke mach em nh phan 4 bit em len, em xuong c ieu khien bang
tn hieu UD (UD = 0 th em len, UD = 1 th em xuong), co mot tn hieu CLK, mot tn hieu CLR.
Bai tap 4-16: Thiet ke mach em nh phan 4 bit em len, em xuong c ieu khien bang
tn hieu UD (UD = 0 th em len, UD = 1 th em xuong), co mot tn hieu CLK, mot tn hieu CLR.
Co them chc nang at trc so em nh IC 74193.
Bai tap 4-17: Thiet ke mach em nh phan 4 bit em len, em xuong c ieu khien bang
tn hieu UD (UD = 0 th em len, UD = 1 th em xuong), co mot tn hieu CLK, mot tn hieu CLR,
co giai ma hien th ra 1 led 7 oan t 0 en F tng ng vi so thap luc phan.
Bai tap 4-18: Thiet ke mach em BCD em len, em xuong c ieu khien bang tn hieu
UD (UD = 0 th em len, UD = 1 th em xuong), co mot tn hieu CLK, mot tn hieu CLR, co giai
ma hien th ra 1 led 7 oan.
Bai tap 4-19: Thiet ke mach em BCD t 00 en 99 em len, em xuong c ieu khien
bang tn hieu UD (UD = 0 th em len, UD = 1 th em xuong), co mot tn hieu CLK, mot tn hieu
CLR, co giai ma hien th ra 2 led 7 oan khong dung quet.
Bai tap 4-20: Thiet ke mach em BCD t 000 en 999 em len, em xuong c ieu
khien bang tn hieu UD (UD = 0 th em len, UD = 1 th em xuong), co mot tn hieu CLK, mot tn
hieu CLR, co giai ma hien th ra 3 led 7 oan dung quet.
Bai tap 4-21: Thiet ke mach gom co 3 led 7 oan, ban phm gom 10 phm so t 0 en 9.
Ban au th 3 led hien th so 000, khi nhan phm nao th phm o c dch vao t ben phai.
(giong nh may tnh calculator).
Bai tap 4-22: Thiet ke mach nh thi: gom co 2 led 7 oan e hien th so giay t 00 en 99,
ban phm gom 10 phm so t 0 en 0 va phm chc nang nh clear, enter, test, mot ngo
ra ieu khien relay. Ban au th 2 led hien th so 00, khi nhan phm nao th phm o c dch

164 Ky thuat PLD va ASIC


Chng 4. Flip flop, thanh ghi, bo em trong VHDL SPKT Nguyen nh Phu
vao t ben phai. Sau khi nhan xong th nhan enter qua trnh em xuong se bat au cho en khi
gia tr em bang 00 th relay se tac ong. He thong ngng.

end

Ky thuat PLD va ASIC 165


TAI LIEU THAM KHAO

[1]. Digital Fundamental Experiments and Concepts with CPLDs , Thomson


Delmar Learning_Chartrand, 2004
[2]. Mivhael.Dciletti, Starter, Pearson Pretice Hall, 2004.
[3]. Wayne Wolf, FPGA based System design , Prentice Hall, 2004
[4]. William Kleitz, Digital Electronics with VHDL Quartus II version,
Pearson Pretice Hall, 2004.
[5]. Jong Ching Chuen, Chang Chip Hong, Digital System Design Principle
and Practices, Pearson Prentice Hall, 2007.