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Tu.D1.

3 148 ICTON 2008

Application of Semiconductor Optical Amplifier Logic Gates


in High-Speed All-Optical Pattern Recognition
Xuelin Yang, Roderick P. Webb, Robert J. Manning, David Cotter
Graeme D. Maxwell*, Alistair J. Poustie* and Sebastien Lardenois*
Photonic Systems Group, Tyndall National Institute & Department of Physics
University College Cork, Ireland. Email: xuelin.yang@tyndall.ie
*Centre for Integrated Photonics (CIP) Ltd, B55 Adastral Park, Martlesham Heath
Ipswich IP5 3RE, UK. Email: graeme.maxwell@ciphotonics.com
ABSTRACT
In this paper, we propose and demonstrate a novel all-optical pattern recognition system. The system is able to
detect and locate a specified target pattern within an input data sequence at high line-rate. The key elements of
the system are an all-optical XNOR logic gate and an all-optical AND gate, the latter forming part of a
recirculating loop. Both these gates are based on semiconductor optical amplifiers (SOAs). Arbitrary 8-bit target
patterns at 10.65 and 21.3 Gbit/s are successfully recognised and located using three SOA-based logic gates.
Keywords: Semiconductor optical amplifier, All-optical signal processing, Optical pattern recognition.

1. INTRODUCTION
Pattern recognition will find many applications, such as the optical header processing and address recognition,
especially in packet-switched networks. It is currently realised by opto-electronics and therefore, in the case of
high bit rate transmission, relies on very high-speed devices, which are generally complex and costly, since the
electronics has to demultiplex and use parallel processing. A simple all-optical approach previously
demonstrated is to perform a parallel comparison of the N bits of the target pattern with N bits of the data;
however that requires N parallel high-speed gates [1]. Thus the target length is limited by the numbers of optical
gates that can be practically integrated. The approach described in this paper employs a re-circulating loop to
permit logic operations between adjacent bits of the high-speed data [2]. This approach, first proposed in [3]
reduces dramatically the number of optical gates required, which becomes independent of target pattern length,
albeit at the expense of increased latency. In addition to applications such as IP address or port number
recognition for routing in packet-switched networks, there will be applications related to data security. For
instance, the photonic firewall being developed by the European FP6 project WISDOM [4] will use pattern
recognition in the optical layer for the initial screening of incoming packets.
In this paper, we will first review the initial experimental results of the key SOA-based logic elements used
in the pattern recognition system and then demonstrate the operation of the complete system. The principle of
the system is explained in Sec. 2. Sec. 3 describes the experimental realisation of both an exclusive NOR gate
(XNOR) and an AND gate in a loop at 42.6 Gbit/s using Mach-Zehnder interferometers (MZI) incorporating
SOAs. In Sec. 4, we present the experimental results of the complete all-optical pattern recognition system at
10.65 and 21.3 Gbit/s, where 8-bit random target patterns were successfully recognised and the locations of the
target pattern were correctly indicated.

2. OPERATING PRINCIPLE OF PATTERN RECOGNITION SYSTEM


The principle of the pattern recognition system was firstly described in Ref. [3]. The system consists of an
XNOR gate followed by an AND gate in a recirculating loop, as shown in Fig. 1. To find a target pattern N bits
long in an n-bit data segment {a1an}, the data segment is repeated N times by a storage loop, and the target
{b1bN} is
Repeated n-bit data segment
Storage loop

Target pattern (1101)


nT

Output
XNOR
data / data AND

Recirculating
Recirculated signal (1 bit relative delay) loop
(n+1)T

Output Regen

Frame: 1 2 3 4 Prob e Initialising pulse


(clock pulses)
Pulse in final frame shows position of target

Fig. 1. Schematic of pattern recognition system with example waveforms.

978-1-4244-2626-3/08/$25.00 2008 IEEE


ICTON 2008 149 Tu.D1.3

generated with a bit period of nT, where T is the bit period of the data. During the first frame, an XNOR gate
compares all the bits ai with the first bit of the target, b1, giving an output Y1 = (ai= b1) for i = 1n. An
initialising pulse opens the AND gate and allows the first frame of Y to enter a recirculating loop of length
(n+1)T. During the second frame, the XNOR gate compares all the ai with the second bit of the target and,
because the recirculating loop is one bit period longer than the storage loop, the results of this comparison are
aligned at the AND gate with the first frame of Y with a 1-bit relative delay. The output of the AND gate is thus
Y2 = (ai= b1) (ai+1= b2). After each circulation, the data in the recirculating loop is gated with the results of the
comparison of the ai with the next target bit, and after N circulations the output is given by YN = (ai= b1) (ai+1=
b2) (ai+N-1 = bN). A true bit in the final frame, therefore, indicates an occurrence of the complete target
pattern in the data. The system can search for targets of any length with the same number of gates, but at the
expense of an increase in the latency to a minimum of nNT.

3. EXPERIMENTAL DEMONSTRATION OF XNOR GATE AND RECIRCULATING LOOP


The two key parts of the system, the XNOR gate and the recirculating loop, were first demonstrated separately,
both at 42.6 Gbit/s.
3.1 XNOR Gate
In Fig. 2(a), the XNOR gate was based on a push-pull 42.6 Gbit/s XOR gate using an MZI incorporating two
SOAs [5]. It is a monolithic SOA array mounted on a passive silica-on-silicon planar lightwave circuit [6].
Because the target pattern is a relatively slow signal, it was not necessary to use the push-pull configuration for
this input. Moreover, it was possible to enter this target signal in the counter-propagating direction which allows
greater flexibility in choice of operating wavelengths. The outputs of the XNOR gate were monitored by
a 70 GHz oscilloscope. In Fig. 2(b), the output waveforms show the original data and its inverse by setting the
target high (1 level) and low (0 level) at 1 Hz. The 42.6 GHz clock consisted of 3ps pulses at 1552 nm, with an
average power of 0 dBm. The 1540 nm target peak power was 6dBm and the 256-bits, 42.6 Gbit/s repeated push
and pull data inputs were 3ps pulses at 1547 nm, with average powers of 2 dBm and -1 dBm, respectively. The
applied currents of the two SOAs were 300 mA. The contrast ratios of both the inverted and non-inverted
output signals were over 12 dB.
Original

0.06
Power (au)

0.04

Repeated data Delay line Attenuator


XNOR 0.02
256 bits@42.6Gb/s Push 1
gate
2=1547nm 0
100 200 300 400 500 600 700 800 900 1000
Clock, 42.6GHz SOAs Output
Inverted
1=1552nm
Pull
0.06
Power (au)

0.04
Target pattern
3=1540nm 0.02

0
100 200 300 400 500 600 700 800 900 1000
Time (ps)

(a) (b)
Fig. 2. Experimental (a) setup and (b) output of 42.6 Gbit/s XNOR gate for target =1 (upper frame, original)
and target = 0 (lower frame, inverted).

3.2 Recirculating Loop


The recirculating loop was constructed employing a twin MZI-SOA device, which consisted of two separate
planar silica MZIs and a monolithic array of four SOAs [6], as depicted schematically in Fig. 3(a). The
additional discrete devices brought the total loop length to 168 ns. Repeated 42.6 Gbit/s data patterns composed
of 1550 nm, 3 ps pulses (mean power of -6 dBm) were connected to the probe input of the AND gate.
An initialising pulse (-3 dBm peak power) allowed the data to enter the loop on one in every eight frames and an
appropriately timed reset (5 dBm peak power) interrupted the CW probe to the regenerator to block any signal
still circulating in the loop. The delay between the initialising pulse and the reset pulse was 168 ns. In order to
verify the loop performance, the frames at the output port was monitored by a 70 GHz oscilloscope. During
subsequent frames, the recirculating signal reached the push and pull inputs of the AND gate and switched the
data as described in Sec. 2. The target pattern, initial pulse and probe with reset were obtained by externally
modulating a CW laser. The modulators were driven by a programmable pattern generator.
The output results in Fig. 3(b) show the pulse sequence evolution with respect to the number of circulations.
Because the input repeated data to the loop were non-invented for all frames, it can be regarded as a special
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example of a target pattern 1111 1111. In Fig. 3(b), the circulation No. 7 indicates the occurrences of the
specified target pattern 1111 1111, as described in Sec. 2. The locations of each pulse in the circulation No. 7
show the position of the last bit of the target pattern in the original data.
42.6Gb/s random data
Repeated data Delay AND gate Loop length delay Circulation No. Target
(42.6Gb/s, 256bits Attenuator
SOA1 adjustment
2=1547nm) Push Original data 1
Output
1 1
1
2 1
Initial pulse Pull SOA2 Linear
( 3=1540nm) SOA 3 1
Regenerator
1
SOA3 Push 4 1
3 3
Probe with reset 5 1
Frame = 168ns Linear ( 3=1540nm)
6 1
SOA
SOA4 Pull
7 1
0 500 1000 1500 2000
t, ps
(a) (b)

Fig. 3. Recirculating loop (a) setup and (b) output at 42.6Gbit/s. The waveforms show the evolution of the input
data sequence (original data).

Repeated data
64 bits@10.65Gb/s Delay line Attenuator XNOR AND gate Loop length
(or 128 bits@21.3Gb/s) Push 1 Push adjustment
gate
2=1547nm Output
Clock
10.65/21.3GHz SOAs SOAs
1
1=1556nm
Pull Pull Linear SOA

3
Target pattern 1
Regenerator Push
3=1540nm 3
Initial pulse, 3
SOAs
Linear SOA Probe with reset, 3
Frame = 168ns
Pull

Fig. 4. Experimental setup of the complete pattern recognition system.

4. PATTERN RECOGNITION EXPERIMENTAL RESULTS


The complete experimental setup of the pattern recognition scheme is basically the combination of the XNOR
gate and the recirculating loop, as described in Sec. 2. The setup is constructed with three CIP hybrid-integrated
MZI gates [5], as shown in Fig. 4. The input repeated data were 64-bits at 10.65 or 128-bits at 21.3 Gbit/s.

Circulation No.
Original data
1
2
3
power

power

4
5
6
7
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
t, ps t, ps

(a) (b)

Fig. 5 Recognition of an 8-bit target (a) 1011 0100 at 10.65Gbit/s, (b) 1100 1100 at 21.3 Gbit/s. The target
patterns are marked by boxes in the original data. The waveforms show the evolution of the input data sequence.

The clock signal was 2 ps pulses at 10.65 GHz or 21.3 GHz. The output waveforms, monitored on a 70 GHz
oscilloscope, are plotted in Fig. 5(a) and 5(b) for an 8-bit target at 10.65 Gbit/s and 21.3 Gbit/s. Fig. 5 shows
that the occurrences of the target pattern were identified from the input data sequence (only part of the repeated
ICTON 2008 151 Tu.D1.3

original data is shown in Fig. 5). Moreover, the pulse locations in the last frame (Circulation No. 7)
demonstrated the last bit of the corresponding target pattern.
The applied currents of the SOAs were 300 mA for XNOR gate, 400 mA for linear SOAs, AND gate and
regenerator. Both linear SOAs have a linear gain of 23 dB. The average input powers to three logic gates are
listed in Table 1. The loop fibre length was about 33.6 m, corresponding to a round-trip time of 168 ns.
Table 1. Average input powers of the XNOR gate, AND gate and regenerator
at 10.65 Gbit/s and 21.3 Gbit/s.
10.65 Gbit/s, dBm 21.3 Gbit/s, dBm
XNOR Gate
Clock, 10.65/21.3GHz -13.3 (19 fJ/pulse) +2.0 (317 fJ/pulse)
Push/Pull -3.4 (91 fJ/pulse) / none +1.6/-2.3 (145/59 fJ/pulse)
Target CW -4.0 +0.8
AND Gate
Data -12.5 (90 fJ/pulse) -7.0 (158 fJ/pulse)
Push/Pull -15.0 (50 fJ/pulse) / none -11.4/-21.6 (58/6 fJ/pulse)
Initialising pulse -9.5 -9.5
Regenerator
Reset pulse +9.5 +9.5
Push/Pull +1.0 (1.6 pJ/pulse) / none -2.4/-15 (460/25 fJ/pulse)

5. DISCUSSION AND CONCLUSIONS


The above experiment results show that this scheme could test the address or other part of a received packet for
the presence of a significant target pattern and would therefore be useful in an optical-layer security screen. For
example, to search 16-bits within the IP packet header for a 16-bit target, the required processing time would be
a period of 32 bytes. If the total packet length is longer than 32 bytes (and the shortest IP datagram has a length
of 40 bytes), there would be sufficient time to finish the search before the arrival of the next packet. This scheme
could also find many other applications in high-speed optical codeword checking in telecommunication systems.
In addition, subsets of a data field could be searched in parallel by dividing a target pattern between multiple
integrated recognition systems in order to shorten the overall processing time.
In conclusion, we have demonstrated for the first time an all-optical pattern recognition system that can
search and locate an 8-bit target pattern in a data sequence at both 10.65 and 21.3 Gbit/s, with only three SOA-
based MZI logic gates. The two key elements of the system: XNOR gate and recirculation loop were
demonstrated at 42.6 Gbit/s. The approach allows checking for any length of the target pattern, and could find
various applications in high speed network security systems and optical header recognition. Further work on
higher bit-rate operation and recognition of longer target pattern lengths is under way.

ACKNOWLEDGEMENTS
This work was supported by Science Foundation Ireland under grant 06/IN/I969 and by the European Union
under project WISDOM.

REFERENCES
[1] F. Ramos. et al.: IST-LASAGNE: towards all-optical label swapping employing optical logic gates and
optical flip-flops, Journal of Lightwave Technology 23(2005), p. 2993.
[2] A.J. Poustie, et al.: All-optical parity checker, OFC 1999, p. 137.
[3] R.P. Webb, et al.: 42Gbit/s All-Optical Pattern Recognition System, OFC 2008, OTuL2.
[4] www.ist-wisdom.org .
[5] R.P.Webb, et al.: 40Gbit/s all-optical XOR gate based on hybrid-integrated Mach-Zehnder interferometer,
Elect. Lett., 41 (2005), p. 1396.
[6] A.J. Poustie. et al.: Semiconductor Devices for All-optical Signal Processing, ECOC 2005, p. 475.