You are on page 1of 40

NumberRepresentationandArithmeticCircuits:

p
NumberRepresentationandUnsignedAddition

Positionalrepresentation
Firstconsiderintegers
Beginwithpositiveonlydescriptionsandexpandtoincludenegativenumbers
Numbersthatarepositiveonlyareunsignedandnumbersthatcanalsoassume
negative values are signed
negativevaluesaresigned
Forthedecimalsystem:
Representingthevalue
Anumberconsistsofdigitshavingtenpossiblevalues(09)
Eachdigitrepresentsamultipleofapowerof10

(123)10=1x102+2x101+3x100
Ingeneral,anintegerisrepresentedbyndecimaldigits

D=dn1dn2...d1d0
Representingthevalue
V(D)=dnn11x10n1 +dnn22x10n2+...+d1x101 +d0x100
Positionalrepresentation
Becausethedigitshave10possiblevaluesandeachdigitisweightedasapower
of 10 we say that decimal numbers are base10 or radix10 numbers
of10,wesaythatdecimalnumbersarebase10orradix10numbers
Indigitalsystemswecommonlyusethebinary,orbase2,numbersystemin
whichdigitscanbe0or1 Eachdigitiscalledabit
Thepositionalrepresentationis
B=bn1bn2...b1b0
Representingaintegerwiththevalue
V(B)=bn1x2n1 +bn2x2n2 +...+b1x21 +b0x20
Thebinarynumber1101representsthevalue
Th bi b 1101 h l
V=1x23 +1x22+0x21+1x20
V=8+4+1=13
So
(1101)2=(13)10
Therangeofnumbersthatcanberepresentedbya
binarynumberdependsofthenumberofbitsused
In general using n bits allows a representation of positive integers in the range 0 to 2n1
Ingeneral,usingnbitsallowsarepresentationofpositiveintegersintherange0to2
Decimal/Binaryconversion
Abinarynumbercanbeconvertedtoadecimalnumberdirectlybyevaluatingtheexpression
V(B)=bn1x2n1 +bn2x2n2 +...+b1x21 +b0x20
usingdecimalarithmetic(byexpansion)
using decimal arithmetic (by expansion)
Convertingfromadecimaltoabinarynumbercanbepreformedbysuccessivelydividingthe
decimalnumberby2asfollows
Dividethedecimalnumber(D)by2producingaquotientD/2andaremainder.Theremainder
willbe0or1(sincewedivideby2)andwillrepresentasinglebit(theLSB)ofthebinary
ill b 0 1 ( i di id b 2) d ill i l bi ( h LSB) f h bi
equivalent
Repeatedlydividethegeneratedquotientby2untilthequotient=0.Foreachdivide,the
p y g ( ) y q
remainderrepresentsoneofthebinarydigits(bits)ofthebinaryequivalent
Octalandhexadecimalnumbers
Positionalnotationcanbeusedforanyradix(base).Iftheradixisr,thenthenumber
K=kn1kn2...k1k0 hasthevalue

Numberswithradix8arecalledoctalandnumberswithradix16arecalled
hexadecimal (or hex)
hexadecimal(orhex)
Foroctal,digitvaluesrangefrom0to7
Forhex,digitalvaluesrangefrom09andAF

Numbers in different systems


Numbersindifferentsystems
Binarytohexoroctalconversion
Groupbinarydigitsintogroupsoffourandassigneachgroupahexadecimaldigit.
011010110111
6B7
Binarytooctal:
011010110111
3
3267
2 6 7
Hexadecimaltobinary:A19101000011001
Octaltobinary:5031101000011001

Unsignednumberaddition
Additionaloftwo1bitnumbersgivesfourpossiblecombinations
Unsignednumberaddition
Largernumbershavemorebitsinvolved
Thereisstilltheneedtoaddeachpairofbits
But,foreachbitpositioni,theadditionoperationmayincludeacarryinfrombitpositioni1

Fulladdercircuit
Fulladdercircuit

F ll dd i i (d
Fulladdercircuit(decomposed)
d)
Ripplecarryadder
Inperformingaddition,westartfromtheleastsignificantdigitandaddpairsofdigits
progressingtothemostsignificantdigit
Ifacarryisproducedinpositioni,itisaddedtooperands(digits)inpositioni+1
Achainoffulladders,connectedinsequence,canperformthisoperation
Suchaconfigurationiscalledaripplecarryadderbecauseofthewaythecarrysignal
ripple
ripple throughfromstagetostage
through from stage to stage

Eachfulladderintroducesacertaindelaybeforeitssi andci+1 outputsarevalid


Thepropagationdelaythroughthefulladder
Th i d l h h h f ll dd
Letthisdelaybet
Thecarryoutofthefirststagec1 arrivesatthesecondstagetaftertheapplicationofthex0
andyy0 inputs
p
Thecarryoutofthesecondstagec2arrivesatthethirdstagewithadelayof2t,andsoon
Thesignalcn1 isvalidafter(n1)t,andthecompletesumisavailableafteradelayof(n)t
Thedelayobviouslydependsonthesizeofthenumbers(i.e.thenumberofbits)
.Circuitthatmultipliesaneightbitunsignednumberby3.

A : a7 a0

A : a7 a0

x7 x0 y7 y0
c7 0 0
s7 s0
x8 x1 x0 y8 y7 y0
c8
s8 s0
0

x8 x7 x0 y8 y7 y0
P = 3
3AA : P9 P8 P0
c8
s8 s0
(b) Efficient design

P = 3 A : P9 P8 P0

(a) Naive approach


Signednumbers
Forsignednumbers,inthebinarysystem,thesign
of the number is denoted by the leftmost bit
ofthenumberisdenotedbytheleftmostbit
0=positive
1=negative
Forannbitnumber,theremainingn1bitsrepresentthemagnitude

Negativenumbers
Forsignednumbers,therearethreecommonformatsforrepresentingnegativenumbers
Signmagnitude
1scomplement
2scomplement
Sign
Signmagnitude
magnitudeusesonebitforthesign(0
uses one bit for the sign (0=+,
+,1
1=))andtheremainingbitsrepresentthe
and the remaining bits represent the
magnitudeofthenumberasinthecaseofunsignednumbers
Forexample,using4bitnumbers
+5=01015=1101
+3=00113=1011
3 0011 3 1011
+7=01117=1111
Althoughthisiseasytounderstand,itisnotwellsuitedforuseincomputers
1scomplementrepresentation
Inthe1scomplementscheme,annbitnegativenumberK,isobtainedbysubtractingits
equivalentpositivenumber,P,from2n1
K (2n1)P
K=(2 1) P
Forexample,ifn=4,then
K=(241)P=(15)10P=(1111)2P
5=(15)105=(1111)2(0101)2=(1010)2
3=(15)103=(1111)2(0011)2=(1100)2
Fromtheseexamples,clearlythe1scomplementcanbeformedsimplybycomplementing
eachbitofthenumber,includingthesignbit
Numbers in the 1sscomplementformhavesomedrawbackswhenusedinarithmeticoperations
Numbersinthe1 complement form have some drawbacks when used in arithmetic operations

2scomplementrepresentation
Inthe2scomplementscheme,annbitnegativenumberK,isobtainedbysubtractingits
equivalent positive number P from 2n
equivalentpositivenumber,P,from2
K=2nP
Forexample,ifn=4,then
K=24P=(16)10P=(10000)2P
5=(16)105=(10000)2(0101)2=(1011)2
3=(16)103=(10000)2(0011)2=(1101)2
Asimplewayoffindingthe2scomplementofanumberistoadd1toits1scomplement
Ruleforfinding2scomplements
Givenasignednumber,B=bn1bn2b1b0,its2scomplement,K=kn1kn2k1k0,can
befoundby:
examiningallthebitsofBfromrighttoleftandcomplementingallthebitsafter
examining all the bits of B from right to left and complementing all the bits after
thefirst1isencountered
ForexampleifB=00110100
Thenthe2scomplementofBisK=11001100changedbitsunchangedbits

Additionandsubtraction
Forsignmagnitudenumbers,additionissimple,butifthenumbershavedifferent
signsthetaskbecomesmorecomplicated
Logiccircuitsthatcompareandsubtractnumbersarealsoneeded
Itispossibletoperformsubtractionwithoutthiscircuitry
Forthisreason,sign
For this reason, signmagnitude
magnitudeisnotusedincomputers
is not used in computers

For1scomplementnumbers,addingorsubtractingsomenumbersmayrequirea
correctiontoobtaintheactualbinaryresult
Forexample,(5)+(2)=(7),butwhenaddingthebinaryequivalentsof5and2,
F l ( 5) ( 2) ( 7) b t h ddi th bi i l t f 5 d 2
theresultis0111withandadditionalcarryoutof1whichmustbe
addedbackthetheresulttoproducethefinal
(
(correct)resultof1000
)
2scomplementoperations
Foraddition,theresultisalwayscorrect
Anycarryoutfromthesignbitpositionis
simply ignored
simplyignored

2scomplementsubtraction
Theeasiestwayofperformingsubtractionistonegatethesubtrahendandaddittothe
Th i t f f i bt ti i t t th bt h d d dd it t th
minuend
Findthe2scomplementofthesubtrahendandthenperformaddition
Adderandsubtractorunit
Thesubtractionoperationcanberealizedastheadditionoperation,usinga2scomplementof
thesubtrahend,regardlessofthesignsofthetwooperands
Itispossibletousethesameaddercircuittoperformbothadditionandsubtraction
It is possible to use the same adder circuit to perform both addition and subtraction
Recallthatthe2scomplementcanbeformedfromthe1scomplementsimplybyadding1
WecanusetheXORoperationtoperforma1scomplement
Recallx1=xandx0=x
Ifweareperformingasubtractoperation,1scomplementthesubtrahendbyXORingeachbit
with1

Adder and subtractor unit


Adderandsubtractorunit
Arithmeticoverflow
Theresultofadditionorsubtractionissupposedtofitwithinthesignificantbits
usedtorepresentthenumbers
Ifnbitsareusedtorepresentsignednumbers,thentheresultmustbeintherange
If bi d i d b h h l b i h
2n1 to+2n11
Iftheresultdoesnotfitinthisrange,wesaythatarithmeticoverflowhasoccurred
Toinsurecorrectoperationofanarithmeticcircuit,itisimportanttobeabletodetectthe
p , p
occurrenceofoverflow
Examplesfordeterminingarithmeticoverflow
Arithmeticoverflow
Inthepreviousexamples,overflowwasdetectedby
overflow=c3c4+c
+c3cc4 overflow=c3c4
Fornbitnumberswehaveoverflow=cn1cn
Theadder/subtractorcircuitintroducedcanbemodifiedtoincludeoverflowcheckingwith
theadditionofoneXORgate
DesignArithmeticCircuitusingVerilog
UsingVectoredSignals
Eachofthefourbitinputsandthefourbitoutputoftheadderisrepresented
using singlebit
usingsingle bitsignals.Amoreconvenientapproachistousemultibitsignals,called
signals. A more convenient approach is to use multibit signals, called
vectors,torepresentthenumbers.

Justasanumberisrepresentedinalogiccircuitas
signalsonmultiplewires,itcanberepresentedinVerilogcodeasamultibitvector.
i l lti l i it b t d i V il d ltibit t

Anexampleofaninputvectorisinput[3:0]W;
M
Mostsignificantbit(MSB)isreferredtoasW[3]andtheleastsignificantbit(LSB)isW[0].
i ifi bi (MSB) i f d W[3] d h l i ifi bi (LSB) i W[0]

AtwobitvectorthatconsistsofthetwomiddlebitsofWisdenotedasW[2:1].
In addition to the input vectors X and Y and output vector S
InadditiontotheinputvectorsXandY,andoutputvectorS,
Carryintostage0isstillcalledcarryin,whilethecarryfromstage3iscalledcarryout.

To define the carry signals between the fulladder


Todefinethecarrysignalsbetweenthefull adderstagesasathree
stages as a threebit
bitvectorC[3:1].
vector C[3:1].

Forspecifyingsignalsthatareneitherinputsnoroutputsofamodule,whichareused
onlyforinternalconnectionswithinthemodule,Verilogprovidesthewiretype.

wire[3:1]C;
Thevectorspecificationgivesthebitwidthinsquarebrackets,asinW[3:0].Thebit
widthisspecifiedusingtheindexoftheMSBfirstandtheLSBlast.Hence,W[3]isMSB
andW[0]isLSB.Areverseorderingcanalsobeused.Forexample,Z[0:3]definesa
four bit vector in which Z[0] is its MSB and Z[3] is its LSB
fourbitvectorinwhichZ[0]isitsMSBandZ[3]isitsLSB.
UsingaGenericSpecification
Verilogallowstheuseofgeneralparametersthatcanbegivenaspecificvalueasdesired.For
example,annbitvectorrepresen nganumbermaybegivenasW[n1:0].
IfnisdefinedintheVerilogstatement

parametern=4;

thenthebitrangeofWis[3:0].

fork=0,1,...,n1.

TheinputsXandY,andtheoutputsumS,aredeclaredtobenbitvectors.
Tosimplifytheuseofcarrysignalsintheaddercircuit,wedefinedavectorCthathasn+1
p fy f y g ,
bits.BitC[0]isthecarryintotheLSBposition,whileC[n]isthecarryfromtheMSBposition.
HenceC[0]=carryin andcarryout=C[n]intermsofthenbitadder.

Tospecifytherepetitivestructureoftheripple
To specify the repetitive structure of the ripplecarry
carryadder,thefollowingprogram
adder, the following program
introducestheVerilogforstatement.Liketheifelsestatementintroduced,thefor
statementisaproceduralstatementthatmustbeplacedinsideanalwaysblock,as

Suchsignalsaredeclaredtobeofregtype;theyarecarryout,S,andCsignalsin
Such signals are declared to be of reg type; they are carryout S and C signals in
thefollowingprogram.ThesensitivityvariablesareX,Y,andcarryin.
NetsandVariablesinVerilog

Connections between logic elements are defined using nets


Connectionsbetweenlogicelementsaredefinedusingnets.

Signalsproducedbyproceduralstatementsarereferredtoasvariables

Netscanbeofdifferenttypes.Forsynthesispurposestheonlyimportantnetsareofwiretype

Itcanbeascalarthatrepresentsasingleconnectionoravectorthatrepresentsmultiple
connections.
connections

wirec3,c2,c1;

Verilog provides variables to allow a circuit to be described in terms of its


behavior.

two types of variables:


reg andd integer.
i t

Scalar carryout and the vectors S and C in are examples of the reg type.
The loop variable k in the same illustrates the integer type.
type
Arithmetic Assignment Statements

Verilog
V il iimplements
l t AArithmetic
ith ti operations
ti using
i arithmetic
ith ti assignment
i t
statements and vectors.

then, the arithmetic assignment statement


then
S = X +Y;
represents an n-bit adder.

Home Assignment-
Show that the carry-out
y from the MSB p position,, n 1,, can be derived from
the values of xn1, yn1, and sn1 by using the expression
Representation of Numbers in Verilog Code

Numbers can be given as constants in Verilog code: binary (b), octal


(o) hexadecimal (h)
(o), (h), or decimal (d) numbers
numbers. Their size can be either fixed or
unspecified

For example, the decimal number 2217 can be represented using 12 bits as
follows

Unsized numbers are given without specifying the size. Decimal number
278 may be given as
Negative numbers are represented by placing the minus sign in front.
Thus if 5
Thus, 5 is specified as 4b101
4 b101,
it will be interpreted as a four-bit 2s-complement of 5, which is 1011.

The specified size may exceed the number of bits that are actually needed to
represent a given number.
In this case, the final representation is padded to the left to yield the required
size.
Signals in a digital circuit have values 0 and 1.
sometimes used x to denote a signal that could be either 0 or 1.

Possible values: 0, 1, z, and x

A constant used in a Verilog design may be given as 8hz3


8 hz3, which is
the same as 8bzzzz0011.

Concatenation
{1 b0,x}
Other number representations

Other number representations are also


commonly used :
Fixed-point: allows for fractional representation
Floating-point: allows for high precision, very large and/or very small numbers
Binary
Binary-coded
coded decimal (BCD): another form for integer representation

Floating-point numbers
Fixed-point numbers have a range that is limited by the significant digits
usedd tto representt the
th numberb
For some applications, it is often necessary to deal with numbers that are
very large (or very small)
For these cases
cases, it is better to use a floating-point
floating point representation in
which numbers are represented by a mantissa comprising the significant
digits and an exponent of the radix R

The format is Mantissa x R Exponent

The numbers are usually normalized such that the radix point is placed to
the right off the first
f non-zero digit (for
(f example, 5.234x1043 or 3.75x10-35
35)
IEEE single precision format
The IEEE standard calls for a normalized mantissa, which means that the
most significant bit is always set to 1.
It is not necessary to include this bit explicitly in the mantissa field
If M is the value in the 23-bit mantissa field, the true (24-bit) mantissa is
actually 1.M
The
Th valuel off the
th floating
fl ti pointi t number
b is i then
th

Range
g of E is 0 to 255. The extreme values of E = 0 and E = 255
are taken to denote the exact zero and infinity, respectively. Therefore, the
normal range of the exponent is 126 to 127, which is represented by the
values of E from 1 to 254.

The exponent field range of 2126 to 2127 corresponds to


about 10-38 to 1038, .
For 64 bits *double precision , The range of E is 0 to 2047, but again the
values E = 0 and E = 2047 are used to indicate the exact 0 and infinity,
respectively Thus the normal range of the exponent is 1022
respectively. 1022 to 1023
1023,
which is represented by the values of E from 1 to 2046.
The mantissa field has 52 bits. Since the mantissa is assumed to be
normalized, its actual value is again 1.M. Therefore, the value of a
floating-point number is

Binary-coded-decimal numbers
It is possible to represent decimal numbers simply by encoding each decimal
digit in binary form
Called binary-coded-decimal (BCD)
Because there are 10 digits to represent
represent, it isnecessary to use four bits per
digit
The addition of two BCD digits is complicated by the fact that the sum may
exceed
9 iin which
9, hi h case a correction
ti will
ill h
have tto b
be made.
d
Let X = x3x2x1x0 and Y = y3y2y1y0 the two BCD digits
S = s3s2s1s0 be the desired sum digit, S = X + Y .
Obviously if X +Y 9
Obviously, 9, then the addition is the same as the addition of 2 four
four-bit
bit
unsigned binary numbers.
But, if X + Y > 9, then the result requires two BCD digits.

There are two cases


when the sum is greater than 9 but no carry-out is generated using four bits,
when the sum is g
greater than 15 so that a carry-out
y is g
generated using
g four bits.

In the first case, the four-bit addition yields 7 + 5 = 12 = Z.


To obtain a correct BCD result, we must generate S = 2 and a carry-out of 1.
The necessary correction is apparent from the fact that the four-bit addition is a
modulo-16 scheme, whereas decimal addition is a modulo-10 scheme.

Therefore, a correct decimal digit can be generated b


Therefore by adding 6 to the res
result
lt of
four-bit addition whenever this result exceeds 9.
Z > 9 produces an output signal, Adjust, which
controls the multiplexer that provides the correction when needed. A
second four-bit
fo r bit adder generates the corrected sum
s m bits.
bits If Adj
Adjust
st = 0
0, then
S = Z + 0; if Adjust = 1, then S = Z + 6 and carry-out = 1
To define the Adjust function, we can observe that the intermediate
sum will exceed 9 if the carry-out from the four-bit adder is equal to 1,
or if z3 = 1 and either z2 or z1 (or both) are equal to 1. Hence the logic
expression for this function is

s0, is not affected at all; hence s0 = z0.


A two
two-bit
bit adder may be used to
develop bits s2 and s1. Bit s3 is the
same as z3 if the carry-out from the
two-bit adder is 0,, and it is equal
q to z3
if this carry-out is equal to 1.