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# EXPERIMENT - 1

NMOS IV CHARACTERISTICS

Aim:
To analyse the IV characteristics of NMOS, including the following:-
1. Drain current (Id) vs Gate-source voltage (Vgs) input characteristics
Task-1: Effect of substrate source voltage (Vsb) on Id
Analyse the input characteristics of NMOS with V sb ranges from 0 to Vdd in
parametric analysis Body Effect

2. Drain current (Id) vs Drain-source voltage with various Vgs in parametric analysis --
output characteristics
Task-2: Channel length modulation
Enumerate the channel length modulation coefficient () for a fixed Vgs

## A. Drain current vs gate voltage (Id vs Vgs):-

Circuit Diagram:-
Draw the schematic of NMOS or paste your screenshot from virtuoso editor

Graph:-
Paste your results as screenshot from waveform window
Note: Highlight the threshold voltage in the graph with a tracer.

## Task-1: (Body Effect) - Effect of substrate source voltage (Vsb) on Id

Circuit Diagram:-
Draw the schematic of NMOS with Vsb or paste your screenshot from virtuoso editor

Graph:-
Paste your results as screenshot from waveform window
Note: Highlight the values of Id for various Vsb in the graph with a tracer.
Calculation:-
V Tn=V Tn 0+ ( (|2 f|+V sb )|2 f|)

## B. Drain current vs drain voltage with parametric analysis (Id vs Vgs):-

Circuit Diagram:-
Draw the schematic of NMOS or paste your screenshot from virtuoso editor

Graph:-
Paste your results as screenshot from waveform window
Note: Highlight the various Vgs values in the graph with a label/tracer.

## Task-2: Channel length modulation

Graph:-
Paste your results as screenshot from waveform window
Note: Plot the graph with a single Vgs and mark two different positions on the graph with a tracer.

Calculation:-
Note down the values of Id and Vds at these points.

## The ratio of two currents is given by

I d 1 (1+ V ds1 )
=
I d 2 1+ V ds2

## Thus, the channel length modulation coefficient is found to be ..

Result:-
Hence, the IV characteristics for NMOS transistor have been analysed.
EXPERIMENT - 2
PMOS IV CHARACTERISTICS

Aim:
To analyse the IV characteristics of PMOS, including the following:-
1. Drain current (Id) vs Gate-source voltage (Vgs) input characteristics
Task-1: Effect of substrate source voltage (Vsb) on Id
Analyse the input characteristics of PMOS with V sb ranges from 0 to Vdd in
parametric analysis body effect

2. Drain current (Id) vs Drain-source voltage with various Vgs in parametric analysis --
output characteristics
Task-2: Channel length modulation
Enumerate the channel length modulation coefficient () for a fixed Vgs

## A. Drain current vs gate voltage (Id vs Vgs)

Circuit Diagram:
Draw the schematic of PMOS or paste your screenshot from virtuoso editor

Graph:
Paste your results as screenshot from waveform window
Note: Highlight the threshold voltage in the graph with a tracer.

## Task-1: (Body Effect) - Effect of substrate source voltage (Vsb) on Id

Circuit Diagram:
Draw the schematic of PMOS with Vsb or paste your screenshot from virtuoso editor

Graph:
Paste your results as screenshot from waveform window
Note: Highlight the values of Id for various Vsb in the graph with a tracer.
Calculation:
V Tp =V Tp0 + ( (|2 f|+V sb) |2 f|)

I d=K 'p ( W /L ) ( V gs V Tp )2

## B. Drain current vs drain voltage with parametric analysis (Id vs Vgs)

Circuit Diagram:
Draw the schematic of PMOS or paste your screenshot from virtuoso editor

Graph:
Paste your results as screenshot from waveform window
Note: Highlight the various Vgs values in the graph with a label/tracer.

## Task-2: Channel length modulation

Graph:
Paste your results as screenshot from waveform window
Note: Plot the graph with single Vgs and mark two different points on the graph with a
tracer.

Calculation:
Note down the values of Id and Vds at those points.

## The ratio of two currents is given by

I d 1 (1+ V ds1 )
=
I d 2 (1+ V ds2 )

## Thus, the channel length modulation coefficient is found to be ..

Result:
Hence, the IV characteristics for PMOS transistor have been analysed.
EXPERIMENT - 3
CMOS IV CHARACTERISTICS
Aim:
To analyse the characteristics of CMOS inverter, including the following:-

## 1. Input voltage (Vin) vs Output Voltage (Vout) DC characteristics

Task-1: Find (W/L) p to achieve Vout = Vdd/2
For a fixed (W/L) n, vary the (W/L) p in parametric analysis
Task-2: Find the noise margin of the inverter
Determine NML and NMH
2. Analyse the transient analysis of the CMOS inverter
Task-3: Estimate the propagation delay of the inverter
Calculate the difference in time between 50% of input and output at both
raising and falling edge.
Task-4: Estimate the power consumption of the inverter

## A. DC characteristics with parametric analysis:

Circuit Diagram:
Draw the schematic of CMOS inverter or paste your screenshot from virtuoso editor

## Task-1: Find (W/L) p to achieve Vout = Vdd/2

Graph (Vin vs Vout without PMOS sizing):
Paste your results as screenshot from waveform window
Note: Highlight the value of Vout at Vin = Vdd/2 in the graph with a tracer.

## Graph (Vin vs Vout (with width of PMOS as variable)):

Paste your results as screenshot from waveform window
Thus, the width for PMOS will be to achieve Vout at Vin = Vdd/2

## Task-2: Find the noise margin of the inverter

Graph (Vin vs Vout with (W/L)p = .. ):
Paste your results as screenshot from waveform window
Graph (Vin vs Vout with derivative of Vout ):
Paste your results as screenshot from waveform window
Note: Highlight the value of Vin and Vout at the slope of -1.

## To find noise margin,

NM L=V IL V OL

NM H =V OH V IH

Where,
VIH = minimum HIGH input voltage
VIL = maximum LOW input voltage
VOH= minimum HIGH output voltage
VOL = maximum LOW output voltage
Therefore the noise margin the sized inverter is

## Graph (Vin and Vout ):

Paste your results as screenshot from waveform window

## Task-3: Estimate the propagation delay of the inverter

Graph (low-to-high & high-to-low of at 50% of Vin and Vout):
Paste your results as screenshot from waveform window
Note: Highlight the tpdr and tpdf of your inverter.

In general, the total propagation delay is the average of the output rising and falling delay.
t pdr +t pdf
t pd =
2

Where,
t pdr = the delays for the output rising to 50%

## Task-4: Estimate the power consumption of the inverter

Graph:
Paste your results as screenshot from waveform window
Note: Highlight the power values with a tracer on the graph.

## The power consumption is observed to be .

Result:
Hence, the DC and transient characteristics for CMOS inverter has been analysed.