You are on page 1of 3

Chapter 3

Research Design and Methodology

This chapter will discuss the design and the methods for the implementation of the study.

This chapter includes the procedures and methods to come up with a solution to answer the

objectives of this study. The review of related literature has been a great help for coming up with

a solution.

3.1 Flow Chart

zv Architectural

Is the flash memory IP



ASIC Design

Can the architectures power consumption be reduced further?


Publish the Paper

Figure 3.1. System Design flow chart

The flow of the verification of the RTL code of flash memory IP is shown on the Figure 3.1. The

constraints in choosing the flash memory IP to be synthesize in RTL is given by the scope and

limitations of this paper.

3.2 ASIC Design Flow

Figure 3.2. ASIC design flow.

A typical design workflow for standard

cell based ASIC is described in the Figure 3.2. The

workflow for full custom ASIC contains these

stages as well as some other stages connected with new cells design. The ASIC design process
begins from writing a functional description containing detailed requirements for the chip. The

design is based on the functional description of the proposed design.