Lecture9 Multiple CTS

90-nm Physical Implementation Flow
Multiple clock tree synthesis
Synopsys University Courseware

Copyright 2011 Synopsys, Inc. All rights reserved.
Developed by: Vazgen Melikyan
1
Overview
Clock Tree General Concepts

Impact of clock skew
Clock Skew Types
CTS in design flow + basic steps
CTS in real P&G flow
CTS : goals & prerequisites
CTS : clock root & sinks
CTS : buffering
Multiple Clocks
CTS effects
Clock Tree Optimization
Multi-voltage-aware CTS and Optimization

2
CLK CLK
Unbuffered clock tree Buffered/balanced clock tree
Skew Area
Power Slew rates

3
Skew impact: Available Timing Margin for
Datapath

4
Skew impact: Hold Time

5
Overview

Clock Skew Types
CTS : buffering
Multiple Clocks
CTS effects

6
Clock Skew Types
Global
Recommended - fastest
Local
Longer runtime
Useful
Used to fix small timing violations

7
Clock Skew Types: Global
A_OUT A_OUT
DIN
A
DIN
D
FF3
Q
T3 A D
FF3
Q
CLK (0.38ns) CLK
D Q
CLOCK
D
FF1
Q
B CLOCK FF1
CLK
CLK
T1
(0.37ns)
B_OUT
B
B_OUT
D Q
D Q FF2
FF2 CLK
CLK
T2
(0.38ns)

8
Clock Skew Types: Local
DIN A_OUT DIN A_OUT

A D
FF3
Q
T3 A D
FF3
Q
CLK
(0.4ns) CLK
D Q
CLOCK
D
FF1
Q
B CLOCK FF1
CLK
CLK
T1
(0.2ns)
B_OUT
B_OUT B D
FF2
Q
D Q
FF2 T2 CLK
CLK (0.2ns)

9
Clock Skew Types: Useful
DIN A_OUT
DIN
A D Q
A_OUT
A D
FF3
Q
FF3
CLK
CLK
T3
(0.22ns)
D Q
B CLOCK
D
FF1
Q
B
CLOCK FF1
CLK B_OUT
CLK D Q
T1
FF2
(0.11ns)
CLK
B_OUT
D Q
FF2
CLK
T2
(0.35ns)

10
Extra Clock Skew: Variability
Unwanted Skew Variations
Process variations T W
S
Power supply noise
H
Temperature variations
Ground plane
. L effective
. Gate length
. Gate width tox

11
Overview

Clock Skew Types
CTS : buffering
Multiple Clocks
CTS effects

12
CTS in a Design Flow + Steps
VLSI Design Steps CTS Design Flow
RTL
Logical Sequential
Clock Tree (x,y), sizes
Logic
Synthesis
Clock
Physical Buffering
Synthesis (Placement)
Routing
Clock Nets
CTS
Sizing
Clock Buffers
Routing

13
CTS in a Real P&R Flow
Eg.
100.000 FF
1.5 h cpu time

14
Overview

Clock Skew Types
CTS : buffering
Multiple Clocks
CTS effects

15
CTS : Goals
Meeting the clock tree design rule

constraints
Maximum transition delay
Constraints are upper
Maximum load capacitance
bound goals. If constraints
Maximum fanout are not met, violations will
[Maximum buffer levels] be reported.
Meeting the clock tree targets

Maximum skew
Min/Max insertion delay (latency)

16
CTS: Prerequisites
The design is placed and optimized
Placement completed, Power and ground nets prerouted

Estimated congestion acceptable
Estimated timing acceptable (small negative slack)
Estimated max cap/transition no violations

High fanout nets
Reset, Scan Enable synthesized with buffers
Clocks are still not buffered
Clock sinks not in narrow channels
No large blockages between clock root and its sinks.

17
Overview

Clock Skew Types
CTS : buffering
Multiple Clocks
CTS effects

18
Clock Root
Case 1: primary port of a block
Define driving cell
Otherwise default driving cell used (same as for other inputs)

affects clock tree QoR during CTS
Ideal clock during synthesis

No effect on design QoR
Case 2: primary port at the chip-level through an IO Pad

Define appropriate input transition
Driving Cell Specifying input

transition
External driving cell CLK
specified for clock CLK
port IOPAD
Clock root
Clock root defined on
defined on
primary clock port
primary clock port

19
Clock Sinks: Stop, Float and Exclude Pins
Implicit STOP Skew and insertion
or FLOAT delay are optimized
pins D
Q
FF
STOP Pins GATED
CLK
D
optimized for DRC and skew, + Q
insertion delay FF
CLOCK
CLK
IP_CLK
EXCLUDE Pins
IP
ignored
Skew and
insertion delay
FLOAT Pins are ignored D
Q
Implicit FF
Like Stop pins, but with delays on CLK
clock pin
EXCLUDE
pins CLK_OUT

20
Clock Sinks: Exclude Pins
D
CLOCK Q
FF3
CLK
If the clock pin inside a macro

cell is correctly defined, CTS skew and insertion
will treat that pin as an implicit delay are ignored
stop pin.
?
IP_CLK D
Q
FF
Implicit CLKn
exclude pin no clock pin

definition
The macros clock pin is marked
as an implicit exclude pin no
skew optimization. IP
21
Clock Sinks: Explicit Stop Pin
D
CLOCK Q
0.42 FF
CLK
Defining an explicit stop pin

allows CTS to optimize for skew skew and insertion delay
0.43 are optimized
and insertion delay targets.
CTS has no knowledge of the IP_CLK D

Q
IP-internal clock delay it can 0.17
FF
CLKn
only see up to the stop pin.
Explicit stop
pin defined
IP

22
Clock Sinks: Explicit Float Pin
D
CLOCK Q
0.42 FF
CLK
Defining an explicit float pin 0.27 skew and insertion delay

are now optimized
allows CTS to adjust the
insertion delays based on
IP_CLK D
specification. 0.15
Q
FF
CLKn
D
Q
FF
Explicit float
pin defined IP CLKn

23
Overview

Clock Skew Types
CTS : buffering
Multiple Clocks
CTS effects

24
CTS: Buffering
Clock tree buffer list

Starting point
Build the buffer tree
Logical hierarchy

25
Clock Tree Buffer List
Different lists
Clock tree synthesis
Sizing
Delay insertion
Sometimes only inverters
Better for power
Reduced list
Too much cpu time to make selection
Largest buffers : not in list (e.g. max load 16)
Too much power
Smallest buffers : not in list (e.g. min load 4)
Too sensitive for output load
Symmetrical rise and fall times
To keep the duty cycle at 50 - 50 %

26
CTS Buffering: Starting Point
FF FF FF FF FF FF
FF FF FF FF FF FF
Clock
FF FF FF FF FF FF
FF FF FF FF FF FF

27
CTS Buffering: Build
FF FF FF FF FF FF
FF FF FF FF FF FF
FF FF FF FF FF FF
Clock
FF FF FF FF FF FF
A buffer tree is built to balance the loads and minimize the skew
28
CTS Buffering: Insertion Delay
FF FF FF FF FF FF
FF FF FF FF FF FF
FF FF FF FF FF FF
Clock
FF FF FF FF FF FF
A delay line is added to meet the minimum insertion delay

29
CTS buffering: Logical Hierarchy
Extra ports
CTS always on flat design
Need for uniquify

30
Overview

Clock Skew Types
CTS : buffering
Multiple Clocks
CTS effects

31
Multiple Clocks: Balance or Not?
Define the buffers used for delay balancing
Define the clocks that need interclock delay balancing
Define the interclock delay requirements

32
Multiple Synchronous Clocks: Balance
D Q

0.75 FF1
CLK
CLOCK1 D Q
FF2
CLK

D Q
0.32 FF3
CLK
CLOCK2 D Q
FF4
CLK
The path from FF1 to FF3 will have an additional setup

penalty of 0.75-0.32=0.43
33
Generated and Gated Clocks: Balance
D
Q
GATED
0.64 FF1
CLK
All insertion delays D

Q
are matched 0.65 FF2

CLK
D
Q
FF3
CLK
CLOCK
D 0.63
master Q
FFD
D
Q
FF4
CLK
QN CLK
D
Q
generated clock FF5

CLK
Skew will be balanced globally, within each clock domain, across all
clock-pins of both master and generated clock.
34
Independent Clocks: No Skew Balancing
D
Q
0.42 FF
CLK

CLOCK
D
Q
FF
CLK
CLOCK
D
D Q
Q
FFD 0.67 FF
CLK
CLK QN

Divided CLOCK
D
Q
Defining an explicit FF
CLK
exclude pin

35
Preserving Pre-existing Clock Trees
Pre-existing D
clock tree Q
FF1
A Y CLK

Does not change D
Q
during CTS Custom logic FFn

hand-built CLK
CLOCK
D
Q
Delays are balanced FFa
across pre-existing and CLK
new clock trees CTS will only build D

Q
this part of the tree FFb

CLK

36
Overview

Clock Skew Types
CTS : buffering
Multiple Clocks
CTS effects

37
Effects of Clock Tree Synthesis
Clock buffers added
Congestion may increase
Non clock cells may have been

moved to less ideal locations
Inserting clock trees can

introduce new timing and max
tran/cap violations

38
CTS in a Real P&R Flow
[CTO]

39
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
Buffer relocation 3X 2X 4X
3X 3X 4X
Buffer sizing
4X
After
4X
After Gate relocation
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
3X 2X 4X
3X 2X 5X
4X
Gate sizing
4X
4X Delay insertion Before
After
40
MV-Aware CTS and Optimization
Voltage area (VA) based CTS and

optimization
VA specific constraints
Sink pins are separated and

clustered by VA so that clock
subtrees are built for each VA
A guide buffer is inserted for the

set of sink pins for each VA to
ensure that any subsequent
levels of clustering do not mix
pins from different VAs

41
Summary
Clock tree synthesis is one of the most important steps

of IC design and can have a significant impact on timing,
power, area, etc.
Clock tree synthesis and optimization are an iterative
processes and can require replacement and rerouting
various times in order to optimize clock tree parameters.
CTS importance increases for 90nm and below
technologies and especially when applying low power
design techniques as they significantly change the ratio
of gate interconnects as well as manners of building
clock trees depending on their multi-level structures.

42

Lecture9 Multiple CTS

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90-nm Physical Implementation Flow

Multiple clock tree synthesis

Synopsys University Courseware

Clock Tree General Concepts

Synopsys University Courseware

Unbuffered clock tree Buffered/balanced clock tree

Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

Clock Tree General Concepts

Synopsys University Courseware

Used to fix small timing violations

Synopsys University Courseware

CLK (0.38ns) CLK

Synopsys University Courseware

DIN A_OUT DIN A_OUT

Synopsys University Courseware

Synopsys University Courseware

Unwanted Skew Variations

Synopsys University Courseware

Clock Tree General Concepts

Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

Clock Tree General Concepts

Synopsys University Courseware

Meeting the clock tree design rule

Meeting the clock tree targets

Synopsys University Courseware

The design is placed and optimized

Placement completed, Power and ground nets prerouted

Estimated max cap/transition no violations

Clocks are still not buffered

Clock sinks not in narrow channels

No large blockages between clock root and its sinks.

Synopsys University Courseware

Clock Tree General Concepts

Synopsys University Courseware

Otherwise default driving cell used (same as for other inputs)

Ideal clock during synthesis

Case 2: primary port at the chip-level through an IO Pad

Driving Cell Specifying input

Synopsys University Courseware

Synopsys University Courseware

If the clock pin inside a macro

exclude pin no clock pin

Defining an explicit stop pin

CTS has no knowledge of the IP_CLK D

only see up to the stop pin.

Synopsys University Courseware

Defining an explicit float pin 0.27 skew and insertion delay

Synopsys University Courseware

Clock Tree General Concepts

Synopsys University Courseware

Clock tree buffer list

Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

A delay line is added to meet the minimum insertion delay

Synopsys University Courseware

Clock Tree General Concepts

Synopsys University Courseware

Define the buffers used for delay balancing

Define the clocks that need interclock delay balancing