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Using Variable Latency Design

Shibina Salim , Riyas A . N

Abstract - High speed and low power consumption is one of the if the input bit coefficient is zero, corresponding row or

most important design objectives in integrated circuits. Digital column of adders need not be activated. Negative bias

multipliers are most critical functional units. The overall temperature instability (NBTI) occurs when a PMOS

performance of these system depends on the throughput of transistor is under negative bias, results in aging effect. Aging

multiplier design. Aging problem of transistors has a significant

effect degrades transistor speed by increase in threshold

effect on performance of these systems and in long term, the

system may fail due to timing violations. Aging effect can be

voltage, which results in real time delay problems. The

reduced by using over-design approaches, but these leads to corresponding effect on an nMOS transistor is positive bias

area, power inefficiency. Hence to reduce the maximum power temperature instability (PBTI), which occurs when an nMOS

consumption and delay, variable latency multiplier with transistor is under positive bias. Traditional methods to

adaptive hold logic is used. The multiplier is able to provide reduce this aging effect were area and power inefficient.

higher throughput through the variable latency and can adjust

the AHL circuit to mitigate performance degradation that is due In variable- latency design, shortest paths are assigned to

to the aging effect. The proposed architecture can be applied to be executed within one cycle and longest paths within two or

image multiplication. Based on the idea of razor flip flop and more cycle. When shorter paths are activated frequently, the

adaptive hold logic the timing violations are reduced. In the average latency of variable-latency designs is better than that

fixed latency usage of clock cycles is increased. The reexecution of fixed latency designs. The main objective of the work is to

of clock cycles is reduced by using variable latency. multiply two images using low power variable latency

multiplier with AH logic. The coding can be synthesized by

the Xilinx ISE Design Suite, simulated using Model-Sim

Index Terms - Adaptive hold logic; Negative bias simulator. The major application of these digital multiplier

temperature instability; Variable latency ; Fixed latency are in the field of digital filtering and signal processing.

Multiplication is an essential arithmetic operation for DEGRADATION OF DIGITAL CIRCUITS

common DSP applications, such as filtering and fast Fourier

transform (FFT). To achieve high execution speed, parallel NBTI is a major side effect on the lifetime reliability of

array multipliers are widely used. These multipliers tend to integrated circuits. With the continuous scaling of transistor

consume most of the power in DSP computations, and thus dimensions, the reliability degradation of circuits has become

power-efficient multipliers are very important for the design an important issue. Due to an increasing electric eld across

of low-power DSP systems. If the multipliers are too slow, the the thin oxide, the generation of interface traps under negative

performance of entire circuits will be reduced. bias temperature instability (NBTI) in pMOS transistors has

Traditional circuits use critical path delay as the overall become one of the most critical reliability issues that

circuit clock cycle in order to perform correctly. Hence, the determine the lifetime of CMOS devices. Due to NBTI, the

variable-latency design was proposed to reduce the timing threshold voltage of the transistor increases with time

waste of traditional circuits. The variable-latency design resulting in the reduction in drive current, which in turn

divides the circuit into two parts they are shorter paths and results in temporal performance degradation of circuits.

longer paths. Shorter paths can execute correctly in one cycle,

whereas longer paths need two cycles to execute. When Vth Degradation Model: NBTI is the result of trap

shorter paths are activated frequently, the average latency of generation at Si/SiO interface in negatively based PMOS

variable-latency designs is better than that of traditional transistors at elevated temperatures. The interaction of

designs. It is well known that multipliers consume most of the inversion layer holes with hydrogen passivated Si atoms can

power in DSP computations. In this paper, we presents low break the SiH bonds, creating an interface trap and one H

power Column bypass multiplier and row bypass multiplier atom that can diffuse away from the interface or can anneal an

design methodology that inserts more number of zeros in the existing trap.

multiplicand and multiplier thereby reducing the number of

delay as well as power consumption. The delay and power are Gate Delay Degradation Model: Delay of gate depends on

threshold voltage value. Therefore, by monitoring the

SHIBINA SALIM, Department of ECE, Kerala University, Younus threshold voltage degradation, the change in gate delay can be

College of Engineering and Technology, Kollam, Kerala, India. easily estimated with a high degree of accuracy.

RIYAS A N, Department of ECE, Kerala University, Younus College of

Engineering and Technology, Kollam, Kerala, India.

380 www.erpublication.org

Efficient Adaptive Hold Logic Reliable Multiplier Design Using Variable Latency Design

From the above analysis, it is clear that circuit delay B) COLUMN BYPASSING MULTIPILER

depends on threshold voltage variation and hence A column-bypassing multiplier is an improvement of the

performance degradation will occur. Various techniques used array multiplier and is shown in Fig.2. A low-power

to mitigate this effect is Vdd tuning, PMOS sizing, Tuning of column-bypassing multiplier design is proposed in which the

gate length and Tuning of switching frequency. By this full adder operations are disabled if the corresponding bit in

techniques we can reduce NBTI to a greater extend but area, the multiplicand is zero. Supposing the inputs are 1010 *

power inefficiency is a major problem. 1111, it can be seen that for the full adders in the first and third

diagonals, two of the three input bits are 0 and the carry bit

III. BYPASSING TECHNIQUE from its upper right full adder and the partial product aibi .

bypassing method when the multiplier has more zeros in input

data. To perform isolation, transmission gates can be used, as

ideal switches with small power consumption, propagation

delay similar to the inverter and small area. To study the

proposed design we have consider column bypassing

multiplier in which columns of adders are bypassed. In this

multiplier, the operations in a column can be disabled if the

corresponding bit in the multiplicand is 0. The advantage of

this multiplier is it eliminates the extra correcting circuit.

multipliers. Dynamic power consumption can be reduced by

bypassing method when the multiplier has more zeros in input

data. The path delay for an operation is strongly tied to the

number of zeros in the multiplicands in the column- bypassing Fig.2. Column bypassing multiplier

multiplier. The column bypassing multiplier (CBM) only

needs two tristate gates and one multiplexer in a adder cell. The multiplicand bit ai can be used as the selector of the

Traditional filter design using bypassing multiplier does not multiplexer to decide the output of the full adder, and ai can

consider variable latency technique. However, no digital FIR also be used as the selector of the tristate gate to turn off the

Filter using variable latency based multiplier that considers input path of the full adder. If ai is 0, the inputs of full adder

the aging effect and can adjust dynamically has yet been are disabled, and the sum bit of the current full adder is equal

developed. to the sum bit from its upper full adder, thus reducing the

power consumption of the multiplier. If ai is 1, the normal

IV. METHODOLOGY sum result is selected.

A) ARRAY MULTIPLIER C) Variable Latency Design

The array multiplier is a fast parallel multiplier and is The variable-latency design was proposed to reduce the

shown in Fig.1 and it consists of (n-1) rows of carry save timing waste occurring in traditional circuits that use the

adder, in which each row contains (n-1) full adders. Each full critical path cycle as an execution cycle period. The basic

adder in the carry save adder array has two outputs they are concept is to execute a shorter path using a shorter cycle and

the sum bit goes down and the carry bit goes to the lower left longer path using two cycles. Since most paths execute in a

full adder. The last row is a ripple adder for carry propagation cycle period that is much smaller than the critical path delay,

the variable-latency design has smaller average latency.

violations occur before the next input pattern arrives. A 1-bit

Razor flip-flop contains a main flip-flop, shadow latch, XOR

gate, and multiplexer. The main flip-flop catches the

execution result for the combination circuit using a normal

clock signal, and the shadow latch catches the execution result

using a delayed clock signal, which is slower than the normal

clock signal. If the latched bit of the shadow latch is different

from that of the main flip-flop, this means the path delay of the

current operation exceeds the cycle period, and the main

Fig.1. Normal array multiplier flip-flop catches an incorrect result. If errors occur, the Razor

flip-flop will set the error signal to 1 to notify the system to

reexecute the operation and notify the AHL circuit that an

error has occurred.

381 www.erpublication.org

International Journal of Engineering and Technical Research (IJETR)

ISSN: 2321-0869 (O) 2454-4698 (P), Volume-3, Issue-7, July 2015

E) Adaptive hold logic to complete, the AHL will output 0 to disable the clock signal

of the input flip-flops. Otherwise, the AHL will output 1 for

The Adaptive Hold Logic circuit is the key component of normal operations.

variable-latency multiplier. The AHL circuit contains

decision block, MUX and a D flip-flop. If the cycle period is

too short, the column-bypassing multiplier is not able to

complete these operations successfully, causing timing

violations. These timing violations will be caught by the

Razor flip-flops, which generate error signals. If errors

happen frequently, it means the circuit has suffered significant

timing degradation due to the aging effect.

operation, the result will be passed to the Razor flip-flops.

The Razor flip-flops check for any path delay timing

violations. If timing violations occur, it means that the cycle

period is not long enough for the current operation to

complete and that the execution result of the multiplier is

Fig.3. Adaptive hold logic incorrect. Thus, the Razor flip-flops will output an error to

inform the system that the current operation needs to be

When an input pattern arrives, decision block will decide re-executed using two cycles to ensure the operation is

whether the pattern requires one cycle or two cycles to correct.

complete and pass both results to the multiplexer. The

multiplexer selects one of either result based on the output of

the razor flip-flop. Then an OR operation is performed

between the result of the multiplexer, and the Q bar signal is VI. APPLICATION : IMAGE PROCESSING

used to determine the input of the D flip-flop. When the In this section the application of the proposed multipliers to

pattern requires one cycle, the output of the multiplexer is 1. image processing is illustrated. A multiplier is used to

The (gating) signal will become 1, and the input flip-flops will multiply two images on a pixel by pixel basis, thus blending

latch new data in the next cycle. On the other hand, when the the two images into a single output image.

output of the multiplexer is 0, which means the input pattern

requires two cycles to complete, the OR gate will output 0 to

the D flip-flop. Therefore, the (gating) signal will be 0 to VII. RESULT AND DISCUSSION

disable the clock signal of the input flip-flops in the next

cycle.

AHL

Aging aware multiplier design includes two m-bit inputs

(m is a positive number), one 2m-bit output, one

column-bypassing multiplier, 2m 1-bit Razor flip- flops, and

an AHL circuit. Clock is provided by the AND gate at the

input.

multiplier and the AHL circuit execute simultaneously.

Depending on the number of zeros in the multiplicand, the

AHL circuit decides number of clock cycles required for the

current input pattern. If the input pattern requires two cycles Fig.5. Simulation result of 16*16 fixed latency

382 www.erpublication.org

Efficient Adaptive Hold Logic Reliable Multiplier Design Using Variable Latency Design

ACKNOWLEDGMENT

The authors would like to thank anonymous reviewers for

their constructive comments and valuable suggestions that

helped in the improvement of this paper.

REFERENCE

[1] Ing-Chao Lin, Member, IEEE, Yu-Hung Cho, and Yi- Ming Yang,

Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

IEEE Transactions On Very Large Scale Integration (VLSI) Systems,

Vol.75,Feb 2014.

[2] Prabhu E, Mangalam H, Saranya K, Design of Low Power Digital

FIR Filter based on Bypassing Multiplier, International Journal of

Computer Applications (0975 8887) Volume 70 No.9, May 2013

[3] J.Sudha Rani, D.Ramadevi, B.Santhosh Kmar,Jeevan Reddy K,

Design of Low Power Col-umn bypass Multiplier using FPGA, IOSR

Journal of VLSI and Signal Processing (IOSR-JVSP),Vol.1, Issue 3

(Nov. - Dec. 2012).

[4] Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Member, IEEE, and

Malgorzata Marek-Sadowska, Performance Optimization Using

Variable-Latency Design Style, IEEE Trans-actions On Very Large

Scale Integration (VLSI) Systems, Vol. 19, No. 10, October 2011.

Fig.6. Simulation result of 16*16 variable latency [5] N.Ravi, Dr.T.S.Rao, Dr.T.J.Prasad, Performance Evaluation of

Bypassing Array Multiplier with Optimized Design, International

Journal of Computer Applications, Vol. 28, No.5, 2011.

TABLE I

SIMULATION RESULT SHIBINA SALIM received B. Tech bachelor degree

in ECE from Younus College of Engineering and

Technology under Kerala University in 2007.

Currently she is pursuing M. Tech in Applied

PARAMETERS Electronics and Instrumentation from Younus

Delay (ns) Power (mW) Area (Gate count) College of Engineering and Technology under Kerala

Multiplier University, Kollam, Kerala. Her areas of interest in

research are VLSI and Signal processing

Fixed 6.199 129 12,826

latency

RIYAS A N received B.Tech bachelor degree in ECE

from TKM Institute under CUSAT University and

Variable 3.076 49 8,199

received his masters degree M.Tech in VLSI and

latency

Embedded system from TKM Institute of Technology

under CUSAT. He is working as Asst. Professor in

Dept. of ECE , Younus College of Engineering and

Technology, Kollam, Kerala. His areas of interest are

In the fixed latency the more number of clock cycle are VLSI and embedded systems, signal processing

required and due to which the area, power and delay are

increased. In the variable latency lesser number of clock cycle

are used, the error is reduced so that the area, power and delay

are reduced.

VIII. CONCLUSION

Variable-latency design minimizes the timing waste of the

noncritical paths. This multiplier is able to adjust the adaptive

hold logic to mitigate performance degradation due to delay

problems. Variable-latency design can adjust clock cycle

required by input patterns. And hence variable latency

multipliers have less performance degradation when

compared with traditional fixed latency multipliers, which

needs to consider the degradation by both the NBTI effect and

use the worst case delay as the cycle period. This can be used

as an application of image multiplication. We can multiply

two images using low power variable latency multiplier with

AH logic, can be enhanced by reduced delay, area and power.

383 www.erpublication.org

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