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Microprocessing

and
Microprogramming
EISEVIER Microprocessing and Microprogramming 41 (1996) 68 I-689

Modelling and performance assessment of large ATM switching


networks on loosely-coupled parallel processors
W. Liu a, E. Dirkx a, G. Petit b, J. Tiberghien a**
a Vrije Universiteit Brussel, Dept. INFO, Pleinhan 2, B-1050 Brussel, Belgium
b Trajic Technology Dept., Research Centre, Bell Telephone Co., F. Wellesplein I, B-2018 Antwerpen, Belgium

Received 22 February 1995; revised 6 April 1995; accepted IO October 1995

Abstract

A parallel simulation tool has been developed with the aim of evaluating the performance of a class of ATM switching
systems. In this paper, the class of ATM switching networks of interest and the corresponding modelling are addressed. An
appropriate decomposition scheme is revealed with respect to the model being built. The performance of the parallel tool is
examined, based on a scalable ATM switching network, by means of a loosely-coupled parallel computer system. A
combination of general purpose and problem specific algorithms results in a high computational efficiency, portability and
scalability.

Keywords: Parallel simulation; Performance evaluation; Asynchronous transfer mode

1. Introduction Telecommunications Union (ITU). The performance


of such a switching network should be evaluated in
Many architectures of the Asynchronous Transfer order to make sure that the design and implementa-
Mode (ATM) switching system have been proposed tion will satisfy the future communication require-
in literature since ATM is chosen as the transfer ments. Two general approaches are available to eval-
mode for implementing Broadband Integrated Ser- uate the performance of digital switching systems:
vices Digital Networks (BISDN) by the International analytic and simulation techniques. The former anal-
yses the model of a system design mathematically or
with computer-aided numerical methods. The latter
simulates the system behaviour by means of com-
l Communicating author. Email: jgtiberg@info.vub.ac.be puter(s), and global performance parameters are

0165~6074/96/$15.00 0 1996 Elsevier Science B.V. All rights reserved


SD/ 0165-6074(96)00029- 1
682 W. Liu et al./Microprocessing and Microprogramming 41 (1996) 681-689

measured during simulated operation of the system 2. System modelling


under study.
Analytic techniques are able to reflect the rela- An ATM switch will be capable of handling a
tionships of system-characteristic parameters intu- minimum of several hundreds of thousands of cells
itively over a wide variety of operating conditions. per second at every input line [8,9]. Such a switch is
Its functional range is however restricted to a high designed to be able to route all cells from their input
degree of abstraction due to unrealistic assumptions, lines to their requested output lines with low enough
and many approximations are necessary to keep a possibility for cell loss and unbearable cell delay,
model tractable. It proves to be very difficult to while preserving the correct cell order for individual
analyse complex systems such as large-scale multi- virtual connections. The switches, having been pro-
stage ATM switching networks at a very low level posed in the literature, take various architectures,
(i.e. highly detailed) with the current analytic ap- with the size ranging from a few ports to thousands
proach. Simulation techniques on the contrary are of ports. Each switch port will typically work with
more flexible and can be applied to a wide area of the transmission rate of 155 Mbit/s or higher. The
applications in arbitrary degree of detail. A disadvan- technology used in implementing the switch places
tage is that a simulation consumes a large amount of certain limitations on the size of the switch and line
CPU time, even for a modest problem. Hence, with- speed; thus to build large switches, many modules
out strong enough computing power, simulation are interconnected in a multistage configuration [lo].
techniques are also not applicable to a complicated The time-division switches [9] allow several in-
system. The only cost-effective solution to this put-output connections to share the same physical
dilemma is to partition the system under study into a resource, say a conducting medium or memory, based
number of components and execute them in parallel on discrete time slot. A memory module is a typical
on a multicomputer system. example for implementing connections based on time
To implement a parallel simulation, it is necessary division. Such a memory module is the repository in
to decompose the system under study to a set of which cells are supplied by input ports and removed
executable components that can be simulated concur- by output ports. The switching principle is similar to
rently. The decomposition of an application can be the Time Slot Interchange (TSI) mechanism [l 11 for
done according to parallel heuristics such as pipelin- synchronous Time Division Multiplexing (TDM). A
ing [1,2], farming [3] and/or data level techniques controller is required to sequentially process all in-
for Parallel Discrete Event Simulation (PDES) such coming cells and select all outgoing cells in each
as the Chandy-Misra algorithm [4,5] and the Time- time cycle. This class of switches, with buffer mem-
Warp algorithm 161. ory in basic switching blocks to solve cell output
In the following, the modelling of a class of ATM conflict, is intended to construct large switching
switching networks of interest is first addressed in systems. Many proposed architectures fall into this
Section 2. Section 3 then approaches the appropriate class in order to construct a scalable ATM switch
algorithms for the model under study. The imple- (e.g. [13-161).
mentation of the strategy on a MIMD parallel com-
puter resulted in a general purpose, yet highly effi- 2.1. Fabrics with shared memory
cient software tool. The performance of the parallel
tool implemented is examined, in Section 4, based It is our intention to develop a simulation tool to
on a scalable ATM switching network. At last, some evaluate the performance of a class of ATM switch
remarks are given in Section 5 to conclude the paper. architectures with shared memory. The previous work
W. Liu et al./ Microprocessing and Microprogramming 41 (1996) 681-689 683

has proven that output buffer can achieve better reaches the requested outlet. Thus, the cell traffic
switch performance, e.g. higher throughput, than in- forms a unidirectional data flow.
put buffer, and shared output buffer will utilise When arriving at an SE, an internal cell will be
buffer memory more efficient than separate output buffered in the shared memory. The cell may be sent
buffers for all traffic patterns [ 13,171. Shared buffer out immediately if the requested output link is free at
type switches are very attractive and many imple- the time cycle; otherwise, it has to stay in the
mented prototypes use them as the building blocks corresponding logical queue and wait for its turn to
for large switch fabrics. The building blocks, or go. Each logical queue is applied with First-In First-
Switching Elements @Es), are organised in ‘stages’, Out (FIFO) discipline, even though the buffer is
with interconnection restricted to adjacent stages. In shared by several of such queues. An SE at different
a k-stage network, the inputs are connected to SEs in stages may have a different routing mode, which
stage 0, while the outputs are connected to SEs in results in a different number of output links in a
stage k-l. routing group. An incoming cell would be lost if the
Besides adopting shared memory within SEs, the buffer had been fully occupied in an SE.
class of ATM switch systems have the following At the output side of the switch interface, internal
characteristics: cells may stay in a resequencing buffer with an
(1) The switch fabrics are scalable with Clos topol- engineerable constant delay in order to compensate
ogy Dl; for distinct cell transfer delay due to multiple paths.
(2) multipaths are available for cells; When a cell has waited long enough, it will be
(3) cells are synchronised with the certain interval of delivered to the output buffer, where the internal
each time cycle; cells are depacketized into ATM cells.
(4) cells are routed with respect to the self-routing
tag in the fabrics. 2.3. Performance indices
The simulation model for the class of ATM switch
architectures involves a series of modules: the source, The performance indices of ATM switching net-
the interface, the SEs, the queueing and routing works involve throughput, connection blocking prob-
management, and the analysis. ability, cell loss probability, cell insertion probabil-
ity, bit error rate, switching delay, and jitter on the
delay [ 121. We concentrate mainly on two perfor-
2.2. Data flow mance indices in the model of the ATM switching
systems: the cell loss probability and the switching
ATM cells are generated at the source and flow delay, though other parameters are also measured
towards the switch fabric via external links. How- (throughput, average link load, packet resequence
ever, the internal packet format is required in order mechanism, etc.>.
to support the self-routing protocol within a switch Cells may be lost due to the resource shortage
fabric. At the switch interface, a self-routing tag is inside an ATM switch fabric. Cells entering from
added to each ATM cell according to its VP1 and different input ports can compete the same output
VCI. This tag points out the appropriate outlet to- port at the same cycle in an SE, i.e., a cell outputs
wards the cell’s destination. Together with the tag conflict. For the ATM switch fabric to be modelled,
and other control information, an ATM cell is con- buffers are used to relieve the cell contention at
verted to an internal packet. Such a packet will routing spots. However, severe congestion may cause
traverse the switch fabric one stage at a time until it buffer memory overflow, and thus result in the loss
684 W. Liu et al. / Microprocessing and Microprogramming 41 (1996) 681-689

of the incoming cells at the moment. The cell loss ing as the potential parallelism and resulting speedup
probability is an important performance metric for an with the network model are significantly less than
ATM switch because it must be restricted to a anticipated [20].
certain quantity for a class of communication ser- To achieve results with a reasonable computing
vices. In fact, it is the key parameter for determining period, the model should be partitioned, with suitable
the buffer memory size of the individual SEs. If the decomposition and process-processor mapping meth-
size is too large, precious network resources would ods, into concurrent processes that can be distributed
be wasted and the implementation becomes more over a network of processors of a MIMD machine.
complicated; if it is too small, cell loss ratio would
3.1. Process partition
increase so that the network could not guarantee the
Quality Of Service (QOS> requirements for user As there are inherent dependent relationships
applications. A satisfactory size of the buffer mem- among data and switching blocks, the farming
ory can only be determined by means of very de- heuristic will not be applicable properly to the model.
tailed evaluation of the internal operation of the No matter which way is used to partition the model,
switching network. the processes could not work independently as the
Switching delay and delay jitter are other impor- algorithm required. In other words, communications
tant performance indices for ATM switching net- are necessary between the processes. Therefore, the
works. The ATM techniques multiply a diverse mix corresponding simulation would not be efficient.
of sources on a single transmitting medium. Real-time The PDES techniques look attractive for the simu-
messages such as voice are very sensitive to the lation of communication networks. Indeed, these ap-
delay and delay variation. Cell switching delay can proaches are based on the principle of using a net-
be affected by many factors: link load, cell arrival work of logical processes to simulate the correspond-
patterns, cell congestion, and so on. Again a mea- ing physical processes in the system to be modelled.
surement can be made based on very detailed evalua- Nevertheless, the topology of interactions among
tion of the internal operation of the switching net- components of the system is the key to determine
work. whether an approach is reasonable [7].
Significant differences exist between the ATM
switch fabric and a conventional communication net-
3. Distributed simulation architecture
work. The conventional communication network car-
In order to obtain details about the performance of ries variable (large generally) packets with relatively
the ATM switch under study, a very small time unit low transmission rate. The network topology is more
should be used to describe the simulation progress. flexible with relatively less interaction among the
With large quantities of high-speed cells being han- nodes of the system. The packets may be sent from
dled inside, huge computing power and large mem- any node with the destination of any other node.
ory space are required when simulating a large scale Therefore, the routing algorithm and communication
switching network. The conventional event-driven protocols need to be designed with more efforts.
mechanism is not suitable for this kind of simulation On the other hand, the ATM switch fabric has
because of the global event-list. Although techniques regular arrangements of the building blocks, and will
for performing event-list manipulation and event be used to switch short fixed-size cells in high speed.
simulation in parallel have been suggested [ 181, large The cell movements are unidirectional and synchro-
scale performance increases seem unlikely [ 191. The nised with the certain time interval within the fabric.
strategy of the distributed event-list is also unpromis- As ATM switches handle very high speed and high
W. Liu et al./ Microprocessing and Microprogramming 41 (1996) 681-689 685

density traffic, the arrival and departure events occur According to the characteristics of the system, a
almost in every simulation cycle, even for a moder- time-driven mechanism is adopted by the simulation
ate-size switching system. The components of the tool. We think that the asynchronous simulation with
ATM switch fabric are tightly-coupled with high local clocks is more applicable to the system of
frequent interactions among them. The simulation interest. When clocks are local and simulation is
time becomes a more crucial factor when evaluating asynchronous a process can begin simulating the
the performance of ATM switches. With highly regu- next tick as soon as its predecessors have finished
lar configurations of switching blocks and fixed- the last tick. Synchronisation for local clocks is
length packets, the implementation of routing and implicitly provided by sending a message from a
protocol algorithms becomes simple in contrast to processor to its successors [7]. The restricted com-
the simulation of classical communication networks. munication overhead is the main benefit derived
Based on the above comparisons, it can be seen from this choice. The synchronisation has been hid-
that it is unlikely to achieve high performance of the den in the necessary data flow of the model. To save
model of the ATM switching system with the PDES the transmission and setup time, the communicating
approaches. Even though the conservative approach data between processors are organised as a single
is suitable for the networks with static interconnec- message at a given simulation clock time.
tion, the overhead, such as the Chandy-Misra dead- A drawback of time-driven simulation is that the
lock avoidance algorithm, is too high for implement- statistical results would be erroneous if the variance
ing the simulation of the ATM switches. A large of event arrival is large. However, the simulation of
ATM switch fabric may involve several hundreds (or ATM switches will not suffer it due to the operating
thousands) of SEs, while each SE may have several behaviour. An ATM cell may occupy a number of
dozens of inputs/outputs. If one process emulates time slots on a TDM transmission medium. Before
one SE, it must exchange messages with all its entering a switch fabric, cells will be aligned with
predecessors and successors. Even with a light load the time slot for delineation. This implies that cells
in the network, the sending of one useful cell means are synchronised with time slot boundary within the
that corresponding null messages will be sent to all switch fabric. The slot interval can therefore be used
other outputs. In addition, the data priorities result in as basic unit of simulation time, which reflects the
poor lookahead for cell streams. The conservative very detail of cell movement.
algorithms appear to be poorly suited for the applica-
3.2. Process assignment
tions with poor lookahead properties, even if there is
a healthy amount of parallelism available [21]. For A large ATM switch fabric may involve a dozen
the optimistic approach such as the Time Warp stages with respect to the switching blocks, and each
algorithm, consider individual switching block(s) of stage may have several tens or hundreds of such
a fabric as a process running on a processor with its blocks. With the regular arrangement of these
local simulation time. The clock of the process is switching blocks, it is possible to partition such a
seldom faster than that of its predecessors, due to the switch fabric in horizontal direction, vertical direc-
unidirectional traffic. Thus, there is no chance for a tion or a mix of both. To the model under study, the
node to have some spare periods to schedule specula- vertical partitioning has several advantages in con-
tive events. In case the chance exists with the ap- trast with the other two. First, the vertical partition-
proach, the cost of roll-back would be excessive for ing coincides naturally with the traffic flowing. In
a model of the ATM switch due to the large quanti- the model, packets enter the switch from the external
ties of cells being processed. links, traverse the switch fabric stage by stage, and
686 W. Liu et al. / Microprocessing and Microprogramming 41 (1996) 681-689

finally leave the switch via the respective output each. The processors can be constructed as a recon-
ports. Thus, the switch fabric is just like a pipeline; figurable processing network by software through a
the SEs in a column form a stage of the pipe, and network configuration unit.
arrival packets are flowing data to be handled. With To execute concurrent processes on MIMD paral-
this partitioning, the communication relationships are lel machines, much attention should be paid on two
clear among those concurrent components. important aspects. One is to avoid load unbalance on
Second, it is easier to achieve the granularity different processors, and the other is to try to de-
balance among the concurrent components divided. crease the communication overhead among different
The activating time of each component depends on processors.
the amount of data to be processed. For a multi-path Due to the unidirectional packet flow, the model
self-routing ATM switch, in general, the quantity of has been partitioned according to the individual
arrival packets on individual links (thus stages) is stages, which reflects the packet flow naturally and
statistically equivalent. The balanced load in differ- simplifies the communication relationships among
ent stages hence means the balanced execution time processes. With a small size switch fabric of interest,
among processes on behalf of different stages. How- one stage can be mapped to one process on a pro-
ever, this load balance is ensured with the promise of cess. When the switch fabric grows, each stage can
identical processors. be mapped to more processes, thus more processors,
Third, it is natural for collecting statistics. The to speedup the simulation. Each process will spawn
SEs of the same stage within a switching network some child processes at execution time dynamically.
play identical functions for the traffic. The SEs of a All processes will be executed on a single processor.
stage will either distribute incoming packets, or route The child processes are responsible for receiving/
incoming packets under a specific routing mode. sending packets from/to the processes on other pro-
Thus, this partitioning makes the relationship of cessors respectively.
concurrent processes very logical. The time-driven mode is adopted, and the simula-
Forth, furthermore decomposition still can simply tion is asynchronous with local clocks of individual
go on to result in balanced partitioning. With more processes. Process’ local times are synchronised
available processors, each partitioned component, i.e. through message passing among processors. The
a stage, can be further partitioned in horizontal direc- large quantities of dependent data in the system are
tion so as to invite more processors to deal with the the main reason to choose time-driven mode in the
simulation. The balanced load can still be kept if the simulation.
same number of identical processors is used for each However, the time-driven mechanism also has a
individual stage. However, speedup may not be negative effect on the simulation. Empty cells have
achieved by introducing more processors to join the to be inserted into cell streams in order to maintain
simulation if the communicatidn time dominates the the time continuation. T’his means spending extra
computation time in the simulation. CPU time in checking the links on which no packets
are carried at the time unit.
3.3. Parallel simulation tool

The simulation tool is developed under a UNIX- 4. Simulation experiment and performance
like environment, programmed in C language, on a
transputer based multicomputer. The processors used A series of simulations has been carried out for a
are INMOS T800 with one or two Mbytes memory scalar ATM switching network, proposed in [22], by
W. Liu et al./ Microprocessing and Microprogramming 41 (1996) 681-689 687

means of the simulation tool on a transputer based sages. The simulation of the large size switch is not
multicomputer. The traffic sources generate ATM so efficient as that of other two because the commu-
cell streams on external links of the switching sys- nication relationships become more complex be-
tem. In the interface module, a self-routing tag and tween stages. We achieved the statistical results about
control information are added to each ATM cell, thus cell loss ratio and cell queueing delay in the quantity
introducing an overhead. The simulation tick corre- less than 10m6 from all three simulation runs.
sponds one eighth of transmission time of an internal Eventhough these simulations spend a large
packet on the link operating at 155,52 Mbit/s. This amount of time, the speedups are significant. It was
implies that an internal packet needs eight simulation also found that during execution of the simulation,
ticks to be processed, while a tick is about 0,437 the computation time dominates the communication
microseconds. The fine time cycle may produce time. This implies that the efforts to reduce the
precise results for performance metrics, but with the communication cost to a minimum by overlapping
cost of long simulation time. the communications on different physical links on
In order to achieve reliable results, all the follow- each processor with computation have been very
ing simulation runs extend five million ticks. Inde- successful.
pendent uniform traffic pattern [lo] is assumed with
80 percent load on each external links. Unfortu-
nately, it is not possible to run the following versions 5. Conclusions
on a single transputer due to the memory require-
ment. Thus, the speedup obtained is deduced based The integration of simulation and parallel process-
on the idea that simulation time taken on one trans- ing techniques can provide strong enough computing
puter is approximately equal to the sum of the useful power for the simulation of large scale ATM switch
time spent by all transputers involved. networks. A parallel simulation tool to evaluate the
Table 1 gives the simulation performance about performance of a class of ATM switching networks
three specific ATM switches with six, ten, and twelve has been developed and implemented. First, the sim-
stages respectively. The mapping strategy of a single ulation model is built based on a class of ATM
processor for each stage is applied to the first two switching systems. In order to implement an efficient
simulations, whereas that of two processors for a simulation tool, various parallel processing tech-
single stage is used for the third simulation. The niques are then approached together with the system
simulation run for the middle size switch is more model under study. Through this approach, the model
efficient than the small in that the packet communi- has been decomposed into a set of processes for a
cation cost is decreased due to the large size mes- loosely-coupled parallel computer. With a very high
level of detail in the simulation, the benefits from
parallelism are significant (and necessary). From the
experiments, we can conclude that MIMD multicom-
Table 1 puters are quite suitable to the problems of evaluat-
Simulation Performance ing performance for large high-speed ATM switch-
Int. Stages Running SpeedUP Efficiency ing systems.
links time Even though we emphasise that the simulation
256 6 44 hours 4.5 75% tool is used to assess performance for a class of
512 10 79 hours 8.7 87% ATM switching systems, the tool can be generalised
4096 12 301 hours 18.76 72%
to the packet switch architectures for variable length
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Weixin Liu received the B.S. degree in G.H. Petit is traffic technology manager
computer science from Changsha Insti- at the Alcatel Corporate Research Cen-
tute of Technology, Changshu, China, in ter in Antwerp (Alcatel-Bell). He is an
1982. IEEE member and since 1992 part-time
He is currently working towards the Ph.J. lecturer at the University of Antwerp.
degree at the Free Universitv of BNS- He is active in the area of B-ISDN
sel’; (Vtije Universiteit B&el), BNS- traffic and flow control, resource man-
sels, Belgium. His current research in- agement strategies and performance
terests include parallel computation, evaluation of large ATM switching sys-
ATM switching networks, and perfor- tems and networks.
mance evaluation techniques.

E. Dirkx has an M.Sc. Electronic Engi-


neering 1984, M.Sc. Computer Science
1986, Ph.D. Computer Science 1990,
I and an M.Sc. Management 1990. Dr.
Dirkx has been a research scientist at
I.B.M. T.J. Watson Research Centre
(Yorktown Heights, 1992) and Elec-
trotechnical Laboratorv (Tsukuba. 1993).
Since 1995, he is lecturer at the VriJe
Universiteit Brussel. His research inter-
ests are parallel computer architecture,
distributed computing, (discrete) simula-
tion and telecommunication networks.