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5 4 3 2 1

01. Block Diagram


02. System Setting
03. CPU_DMI,PEG,FDI,CLK,MISC
N73Sv Block Diagram
04. CPU_DDR3
05. CPU_CFG,RSVD,GND
06. CPU_PWR
07. CPU_XDP
14. DIM_DDR3 SO-DIMM 0 (for CFD)
D
16. DIM_DDR3 SO-DIMM 1 D
17. DIM_DDR3 SO-DIMM 3
18. DIM_CA/DQ Voltage
19. CPU_VID Controller PCIE x16
CPU
NVIDIA N12P-GS
20. SB_Cougar SATA,HDA,RTC,LPC Sandy Bridge DDR3 1066/1333MHz
21. SB_Cougar PCIE,CLK,SMB,PEG DDR3 SO-DIMM X3
4 Core or 2Core
22. SB_Cougar FDI,DMI,SYS PWR Page 35 , 70~79 Page 14~18
23. SB_Cougar DP,LVDS,CRT
24. SB_Cougar PCI,NVRAM,USB Page 3~6

25. SB_Cougar CPU,GPIO,MISC


26. SB_Cougar PWR,GND
27. SB_Cougar PWR,GND

FDI x8

DMI x4
28. SB_SPI ROM,SMBus HDMI CRT LCD Panel
29. CLK_ICS9LRS3161 Page 48 Page 46 Page 45
30. KBC_IT8572E
31. KBC_KB & TP SPI ROM
32. RST_Reset Circuit Page 30
33. LAN_AR8131
34. LAN_RJ45 Conn.
C 35. Hybrid switch Debug Conn. GigaLAN
C

36. AUD_CODEC ALC269 Page 44 RJ45


37. AUO_SPKR,Woofer,Mic Touchpad Atheros AR8131 Page 34
38. MIC&LINE IN Page 31 EC PCH PCIE x1
Page 33

42. CB_AU6433 LPC


44. BUG_NewCard & LPC
ITE IT8572E
Cougar Point-M MiniCard
Keyboard
Power
45. CRT_LVDS & CMOS Page 30 WiFi / WiMax
46. CRT_D-Sub Page 31 Page 53

48. CRT_HDMI
49. TV TUNE Page 20~27 MiniCard VCORE
50. FAN_Thermal Sensor & Fan TV Tuner Page 80
SATA Page 64
51. XDD_HDD & ODD CON.
System
52. USB_USB Port
53. PCI_WiFi/WiMax HDD (1) Page 81

56. LED_LED & Switch Page 51 +VTT_CPU & +VTT_PCH


57. DSG_Discharge
58. PRO_Protect HDD (2) Card Reader
Page 82

60. DC_DC & BAT IN Page 51


Alcor AU6433
+1.5V & +0.75V
61. BT_Bluetooth
B 64. TUN_TV Tuner ODD USB3.0 Page 42
Page 83 B

65. ME_W2B conm. & NUT Fresco FL1000G


Page 51 +1.8V & +1.1VSG
66. USB_USB Port USB Page 68
68. USB3.0_FRESCO CMOS Camera Page 84

69. USB3.0 Port USB Port 1 Page 45


70. VGA_N11P-GS Main (1) Page 33
INT. MIC
71. VGA_N11P-GS Main (2)
72. VGA_N11P-GS VRAM CH_A Page 37 Bluetooth
73. VGA_N11P-GS VRAM CH_C USB Port 0
Azalia Codec Azalia Page 33
Page 61
74. VGA_N11P-GS Main (5) Audio Amp
75. VGA_N11P-GS Main (6) Realtek ALC269
Page 37 Charger
76. VGA_N11P-GS Main (7) Page 36 USB Port 3
77. VGA_N11P-GS Main (7)
Jack Page 66 Clock Generator Page 88

78. VGA_SG Display Switch


Page 38 IDT ICS9LRS3161 Load Switch
79. VGA_SG PWR Switch
Page 29 Page 91
80. PWR_VCORE(NCP3218)
81. PWR_SYSTEM(RT8206A)
82. PWR_I/O_VCCP_PCH(RT8202A)
A 83. PWR_I/O_DDR(RT8202A+uP7711) CPU XDP Thermal Sensor Skew Holes DC & Battery A

84. PWR_+1.8V_+1.1V(RT8015+LDO) Page 7 Page 50 Page 65 Page 60

1bios.ru
85. PWR_VGA_CORE(RT8202A)
86. PWR_RENDER_CORE(RT8152D) PCH XDP PWM Fan Discharge Circuit
88. PWR_CHARGER(MB39A132) Page 67 Page 50 Page 57
91. PWR_LOAD SWITCH
93. PWR_SIGNAL Reset Circuit Power Protect Switch & LEDs Title : Block Diagram
ASUSTeK COMPUTER INC. NB3 Engineer: Wish
94. PWR_Flowchart Page 32 Page 58 Page 56
Size Project Name Rev
95. Revision History C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 1 of 95
5 4 3 2 1
5 4 3 2 1

EC GPIO Use As Signal Name


PCH PCH_IBEX
Use As Signal Name Int.& Ext
Power
EC IT8572 GPA0 OD PWR_LED#
Design IP Source:N73JF
GPIO Pull up / down
GPIO GPIO 00 GPO NC_TP - +3VS GPIO GPA1 OD CHG_LED#
-
GPA2 O CHG_FULL_LED#
GPIO 01 GPO NC_TP +3VS
EXT PU
GPA3 O MUTE_LED# SM_BUS ADDRESS :
GPIO [2:5] GPI PCI_INT[E:H]# +5VS
GPA4 ALT LCD_BL_PWM PCH Master
GPIO 06 GPI NC_TP EXT PU +3VS
GPA5 ALT FAN_PWM SM-Bus Device SM-Bus Address
GPIO 07 GPI USB3_SMI# EXT PU +3VS
GPA6 ALT VOLUME_LED# Clock Generator(ICS9LRS3197) 1101001x ( D2 )
GPIO 08 GPI EXT_SMI# EXT PU & INT PU +3VSUS
GPA7 O MEDIA_KEY_LED# SO-DIMM 0 1010000x ( A0 )
D GPIO 09 Native NC_PU EXT PU +3VSUS D
GPB0 O BATSEL_0 SO-DIMM 1 1010001x ( A2 )
GPIO 10 Native NC_PU EXT PU +3VSUS
GPB1 O BATSEL_1 VID Controller(ASM8272) 0011011x ( 36 )
GPIO 11 GPI EXT_SCI# EXT PU +3VSUS
GPB2 O ME_AC_PRESENT EC Master (SMB1)
GPIO 12 Native NC_TP - +3VSUS
GPB3 ALT SMB0_CLK SM-Bus Device SM-Bus Address
GPIO 13 GPO NC_TP INT PD +3VSUS
GPB4 ALT SMB0_DAT CPU Thermal Sensor(G781) 1001100x ( 9A )
GPIO 14 Native NC_PU EXT PU +3VSUS
GPB5 OD A20GATE VGA Thermal IC(G781-1) 1001101x ( 9E )
GPIO 15 GPO BT_LED INT PD +3VSUS
EXT PU
GPB6 OD RC_IN#
GPIO 16 GPO DGPU_HOLD_RST# +3VS
EXT PD & INT TBD
GPB7 O PM_RSMRST# PCI Express USB Port
GPIO 17 GPI DGPU_PWROK +3VS
GPC0 CLK_UC PCIE 1 Minicard TV Tuner USB 0 USB Port 0
GPIO 18 GPI CLKREQ1_TV# EXT PD +3VS
GPC1 ALT SMB1_CLK PCIE 2 Minicard WLAN USB 1 USB Port 1
GPIO 19 GPI SATA1GP EXT PU +3VS
GPC2 ALT SMB1_DAT PCIE 3 Newcard USB 2 USB Port 2
GPIO 20 Native CLKREQ2_WLAN# EXT PD +3VS
GPC3 O PM_PWRBTN# PCIE 4 USB 3.0 USB 3 USB Port 3
GPIO 21 GPI SATA0GP EXT PU +3VS
GPC4 ALT AC_IN_OC# PCIE 5 Card Reader USB 4 Minicard TV Tuner
GPIO 22 GPO WLAN_LED - +3VS
GPC5 O OP_SD# PCIE 6 GLAN USB 5 NewCard
GPIO 23 Native NC_TP INT PU +3VS
GPC6 ALT BAT1_IN_OC# PCIE 7 USB 6
GPIO 24 GPO NC_TP - +3VSUS
GPC7 I RFON_SW# PCIE 8 USB 7
GPIO 25 GPI CLKREQ3_NEWCARD# EXT PD +3VSUS
GPD0 I PWRLIMIT# USB 8 WLAN
GPIO 26 GPI CLKREQ4_USB3# EXT PD +3VSUS
GPD1 I PM_SUSC# SATA Port USB 9 CMOS Camera
GPIO 27 GPO NC_TP INT PU +3VSUS
GPD2 ALT BUF_PLT_RST# SATA 0 SATA HDD (1) USB 10
C
GPIO 28 GPO WLAN_ON# - +3VSUS C
GPD3 OD EXT_SCI# SATA1 SATA ODD USB 11
GPIO 29 Native - +3VSUS
GPD4 OD EXT_SMI# SATA4 SATA HDD (2) USB 12 Bluetooth
GPIO 30 GPO ME_SusPwrDnAck EXT PU +3VSUS
GPD5 O LCD_BACKOFF# SATA5 ESATA USB 13
GPIO 31 Native ME_AC_PRESENT_PCH EXT PU +3VSUS
EXT PU
GPD6 ALT FAN0_TACH
GPIO 32 GPIO PM_CLKRUN# +3VS
-
GPD7 OD EXP_GATE_LED# Device Identification
GPIO 33 GPI HDA_DOCK_EN# +3VS
GPE0 O - CPU Thermal Senser
GPIO 34 Native NC_TP - +3VS
GPE1 I /PU - 1st 06G023048011 G781F
GPIO 35 GPI SATA_CLK_REQ#_R EXT PD +3VS
GPE2 I /PU - 2nd
GPIO 36 GPO DGPU_PWR_EN# EXT PD +3VS
GPE3 -
GPIO 37 GPI DGPU_PRSNT# EXT PD +3VS VGA Thermal Senser
GPE4 ALT PWR_SW#
GPIO 38 GPI PCB_ID0 EXT PU / PD +3VS 1st 06G023048010 G781-1
GPE5 ALT CLK_OC#
GPIO 39 GPI PCB_ID1 EXT PU / PD +3VS 2nd
EXT PU
GPE6 I LID_SW#
GPIO 40 Native NC_PU +3VSUS
GPE7 I EXP_GATE# Clock Gen
GPIO 41 Native NC_PU EXT PU +3VSUS
GPF0 ALT OS_LED# 1st 06G011614010 ICS9LVS3161
GPIO 42 Native NC_PU EXT PU +3VSUS
GPF1 O VSUS_ON 2nd
GPIO 43 Native NC_PU EXT PU +3VSUS
EXT PU
GPF2 I VCCP_DV0
GPIO 44 Native CLK_REQ5# +3VSUS
-
GPF3 I VCCP_DV1
GPIO 45 Native NC_TP +3VSUS
-
GPF4 ALT TP_CLK
GPIO 46 Native NC_TP +3VSUS
B
EXT PD
GPF5 ALT TP_DAT B
GPIO 47 GPI CLKREQ_PEG# +3VSUS
-
GPF6 O THRO_CPU
GPIO 48 GPO NC_TP +3VS
EXT PU
GPF7 O PCH_SPI_OV
GPIO 49 GPO PCH_TEMP_ALERT# +3VS
EXT PU
GPG0 I ME_SusPwrDnAck
GPIO 50 Native PCI_REQ1# +5VS
INT PU
GPG1 I PM_SUSB#
GPIO 51 Native PCI_GNT1# +3VS
EXT PU
GPG2 CLK_STRAP0
GPIO 52 GPO DGPU_SELECT#_R +5VS
INT PU
GPG6 CLK_STRAP1
GPIO 53 GPO DGPU_PWM_SELECT#_R +3VS
EXT PD
GPH0 ALT PM_CLKRUN#
GPIO 54 Native PCI_REQ3# +5VS
INT PU
GPH1 GFX_VR_ON
GPIO 55 Native PCI_GNT3# +3VS
EXT PD
GPH2 O CHG_EN
GPIO 56 GPI CLKREQ_GLAN# +3VSUS
EXT PU (Diode)
GPH3 O SUSC_EC#
GPIO 57 GPO BT_ON +3VSUS
EXT PU
GPH4 O SUSB_EC#
GPIO 58 GPIO SML1_CLK +3VSUS
EXT PU
GPH5 OD NUM_LED#
GPIO 59 Native NC_PU +3VSUS
EXT PU
GPH6 OD CAP_LED#
GPIO 60 Native SML0ALERT# +3VSUS
-
GPI0 HDMI_HPD
GPIO 61 Native NC_TP +3VSUS
-
GPI1 I SUS_PWRGD
GPIO 62 Native NC_TP +3VSUS
-
GPI2 I ALL_SYSTEM_PWRGD
GPIO 63 Native NC_TP +3VSUS
INT TBD
GPI3 I VRM_PWRGD
GPIO 64 Native NC_TP +3VS
INT TBD
GPI4 I PCH_TEMP_ALERT#
GPIO 65 Native NC_TP +3VS
A
INT TBD
GPI5 - A
GPIO 66 GPO EDID_SELECT# +3VS
GPI6 IDLE_HPD_INT#

1bios.ru
GPIO 67 Native CLK_CR48 INT TBD +3VS
INT PU
GPI7 -
GPIO 72 GPO PM_BATLOW# +3VSUS
EXT PU
GPJ0 O CPU_VRON
GPIO 73 Native CLK_REQ0# +3VSUS
EXT PU
GPJ1 O PM_PWROK
GPIO 74 Native SML1ALERT +3VSUS
GPJ2 ALT VSET_EC
GPIO 75 GPIO SML1_DATA EXT PU +3VSUS Title : System Setting
GPJ3 ALT ISET_EC
ASUSTeK COMPUTER INC. NB3 Engineer: Wish
GPJ4 CPU_DV0 Size Project Name Rev
GPJ5 O CPU_DV1 C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 2 of 95
5 4 3 2 1
5 4 3 2 1

Main Board
FDI disable: (For discrete graphic) CPU socket P/N change to 12G011909893 +VTT_CPU
U0301A
1. NC: PEG_ICOMPI J22 PEG_IRCOMP_R R0301 1 2 24.9Ohm 1%
PEG_ICOMPO J21
FDI_TX#[0:7],FDI_TX[0:7],VCC_AXGSENSE,VSS_AXGSENSE <22> DMI_TXN0 B27 DMI_RX#[0] PEG_RCOMPO H22
<22> DMI_TXN1 B25 DMI_RX#[1]
<22> DMI_TXN2 A25 DMI_RX#[2] PCIENB_RXN[15:0] <70>
2. Pull-down to GND via 1K 5% resistor: <22> DMI_TXN3 B24 DMI_RX#[3] PEG_RX#[0] K33 PCIENB_RXN0
PCIENB_RXN1
PEG_RX#[1] M35
FDI_FSYNC[0:1],FDI_LSYNC[0:1],FDI_INT,GFX_IMON <22> DMI_TXP0 B28 L34 PCIENB_RXN2
DMI_RX[0] PEG_RX#[2] PCIENB_RXN3
<22> DMI_TXP1 B26 J35
~15mW power saving DMI_RX[1] PEG_RX#[3]

DMI
<22> DMI_TXP2 A24 J32 PCIENB_RXN4
DMI_RX[2] PEG_RX#[4]
3. Connected to GND: <22> DMI_TXP3 B23 DMI_RX[3] PEG_RX#[5] H34 PCIENB_RXN5
PCIENB_RXN6
PEG_RX#[6] H31
VCCAXG <22> DMI_RXN0 G21 G33 PCIENB_RXN7
DMI_TX#[0] PEG_RX#[7] PCIENB_RXN8
D <22> DMI_RXN1 E22 DMI_TX#[1] PEG_RX#[8] G30 D
4. Can be connected to GND directly: <22> DMI_RXN2 F21 DMI_TX#[2] PEG_RX#[9] F35 PCIENB_RXN9
PCIENB_RXN10
<22> DMI_RXN3 D21 DMI_TX#[3] PEG_RX#[10] E34
DPLL_REF_CLK,DPLL_REF_CLK# E32 PCIENB_RXN11
PEG_RX#[11] PCIENB_RXN12
<22> DMI_RXP0 G22 DMI_TX[0] PEG_RX#[12] D33
5. Connect to +V1.05S rail: <22> DMI_RXP1 D22 DMI_TX[1] PEG_RX#[13] D31 PCIENB_RXN13

PCI EXPRESS* - GRAPHICS


<22> DMI_RXP2 F20 B33 PCIENB_RXN14
DMI_TX[2] PEG_RX#[14] PCIENB_RXN15
VCCFDIPLL <22> DMI_RXP3 C21 DMI_TX[3] PEG_RX#[15] C32 Huron River PCIE support
J33 PCIENB_RXP0
PCIENB_RXP[15:0] <70> 2.5 GT/s, 5 GT/s and 8 GT/s
PEG_RX[0] PCIENB_RXP1
eDP disable/Enable <22> FDI_TXN[7:0]
PEG_RX[1] L35
K34 PCIENB_RXP2
PEG_RX[2]
CFG[4]: FDI_TXN0
FDI_TXN1
A21 FDI0_TX#[0] PEG_RX[3] H35 PCIENB_RXP3
PCIENB_RXP4
H19 FDI0_TX#[1] PEG_RX[4] H32
Enable: Mount R0503, R0303=1K FDI_TXN2
FDI_TXN3
E19 FDI0_TX#[2] PEG_RX[5] G34 PCIENB_RXP5
PCIENB_RXP6

Intel(R) FDI
F18 FDI0_TX#[3] PEG_RX[6] G31
Disable: un-mount R0503, R0303=10Kohm FDI_TXN4
FDI_TXN5
B21 FDI1_TX#[0] PEG_RX[7] F33 PCIENB_RXP7
PCIENB_RXP8
C20 FDI1_TX#[1] PEG_RX[8] F30
FDI_TXN6 D18 E35 PCIENB_RXP9
FDI1_TX#[2] PEG_RX[9]
CPU Reset,meet Rise +VDDQ
FDI_TXN7 E17 FDI1_TX#[3] PEG_RX[10] E33 PCIENB_RXP10
F32 PCIENB_RXP11
and fall time spec PEG_RX[11]
D34 PCIENB_RXP12
<22> FDI_TXP[7:0] PEG_RX[12]
FDI_TXP0 A22 E31 PCIENB_RXP13
+3V +3V FDI_TXP1 FDI0_TX[0] PEG_RX[13] PCIENB_RXP14
G19 FDI0_TX[1] PEG_RX[14] C33
FDI_TXP2 E20 B32 PCIENB_RXP15
FDI0_TX[2] PEG_RX[15]

2
FDI_TXP3 G18 FDI0_TX[3] PCIEG_RXN[15:0] <70>
2

R0335 FDI_TXP4 B20 M29 PCIENB_TXN0 CX0301 1 2 0.1UF/16V PCIEG_RXN0 PCIE AC Coupling Capacitors:
R0334 200Ohm FDI_TXP5 FDI1_TX[0] PEG_TX#[0] PCIENB_TXN1 CX0302 0.1UF/16V PCIEG_RXN1
C19 FDI1_TX[1] PEG_TX#[1] M32 1 2
200Ohm FDI_TXP6 D19 M31 PCIENB_TXN2 CX0303 1 2 0.1UF/16V PCIEG_RXN2 1. 436735 PDG Page 39, 75nF~200nF
FDI_TXP7 FDI1_TX[2] PEG_TX#[2] PCIENB_TXN3 CX0304 0.1UF/16V PCIEG_RXN3
F17 L32 1 2
1
FDI1_TX[3] PEG_TX#[3] PCIENB_TXN4 CX0305 0.1UF/16V PCIEG_RXN4
L29 1 2 2. 431433 EMERALD LAKE Schematic 220nF
1

PEG_TX#[4] PCIENB_TXN5 CX0306 0.1UF/16V PCIEG_RXN5


<22> FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 1 2
U0303 <22> FDI_FSYNC1 J17 K28 PCIENB_TXN6 CX0307 1 2 0.1UF/16V PCIEG_RXN6 3. 436735 PDG Page 41, 180nF~265nF
FDI1_FSYNC PEG_TX#[6] PCIENB_TXN7 CX0308 0.1UF/16V PCIEG_RXN7
PEG_TX#[7] J30 1 2
1 NC VCC 5 <22> FDI_INT H20 J28 PCIENB_TXN8 CX0309 1 2 0.1UF/16V PCIEG_RXN8
FDI_INT PEG_TX#[8]
2

2 A H29 PCIENB_TXN9 CX0310 1 2 0.1UF/16V PCIEG_RXN9


<22> H_DRAM_PWRGD Y PEG_TX#[9]
3 GND 4 DRAMPWROK R0336 <22> FDI_LSYNC0 J19 G27 PCIENB_TXN10 CX0311 1 2 0.1UF/16V PCIEG_RXN10
FDI0_LSYNC PEG_TX#[10] PCIENB_TXN11 CX0312 0.1UF/16V PCIEG_RXN11
22Ohm <22> FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#[11] E29 1 2
C N/A F27 PCIENB_TXN12 CX0313 1 2 0.1UF/16V PCIEG_RXN12 C
74LVC1G07GW PEG_TX#[12] PCIENB_TXN13 CX0314 0.1UF/16V PCIEG_RXN13
D28 1 2
1

+VTT_CPU PEG_TX#[13] PCIENB_TXN14 CX0315 0.1UF/16V PCIEG_RXN14


PEG_TX#[14] F26 1 2
R0338 2 1 0Ohm E25 PCIENB_TXN15 CX0316 1 2 0.1UF/16V PCIEG_RXN15
PEG_TX#[15]
6

1 2 A18 eDP_COMPIO PCIEG_RXP[15:0] <70>


3

@ Q0302A R0302 24.9Ohm A17 M28 PCIENB_TXP0 CX0317 1 2 0.1UF/16V PCIEG_RXP0


Q0302B UM6K31N +VTT_CPU 1% eDP_ICOMPO PEG_TX[0] PCIENB_TXP1 CX0318 0.1UF/16V PCIEG_RXP1
<57> SUSB_EC 2 B16 eDP_HPD PEG_TX[1] M33 1 2
5 UM6K31N N/A M30 PCIENB_TXP2 CX0319 1 2 0.1UF/16V PCIEG_RXP2
1

N/A eDP_HPD# PEG_TX[2] PCIENB_TXP3 CX0320 0.1UF/16V PCIEG_RXP3


1 2 L31 1 2
4

R0303 10KOhm PEG_TX[3] PCIENB_TXP4 CX0321 0.1UF/16V PCIEG_RXP4


C15 eDP_AUX PEG_TX[4] L28 1 2
/X D15 K30 PCIENB_TXP5 CX0322 1 2 0.1UF/16V PCIEG_RXP5
eDP_AUX# PEG_TX[5]

eDP
K27 PCIENB_TXP6 CX0323 1 2 0.1UF/16V PCIEG_RXP6
+3VS PEG_TX[6] PCIENB_TXP7 CX0324 0.1UF/16V PCIEG_RXP7
PEG_TX[7] J29 1 2
C17 J27 PCIENB_TXP8 CX0325 1 2 0.1UF/16V PCIEG_RXP8
can float on processor by DG eDP_TX[0] PEG_TX[8] PCIENB_TXP9 CX0326 0.1UF/16V PCIEG_RXP9
F16 eDP_TX[1] PEG_TX[9] H28 1 2
2

C16 G28 PCIENB_TXP10 CX0327 1 2 0.1UF/16V PCIEG_RXP10


R0337 eDP_TX[2] PEG_TX[10] PCIENB_TXP11 CX0328 0.1UF/16V PCIEG_RXP11
G15 eDP_TX[3] PEG_TX[11] E28 1 2
200Ohm F28 PCIENB_TXP12 CX0329 1 2 0.1UF/16V PCIEG_RXP12
D0302 @ PEG_TX[12] PCIENB_TXP13 CX0330 0.1UF/16V PCIEG_RXP13
C18 eDP_TX#[0] PEG_TX[13] D27 1 2
RB751V-40 E16 E26 PCIENB_TXP14 CX0331 1 2 0.1UF/16V PCIEG_RXP14
1

H_DRAM_PWRGD eDP_TX#[1] PEG_TX[14] PCIENB_TXP15 CX0332 0.1UF/16V PCIEG_RXP15 T0313 CLK_CPU_BCLK


<58> SYSTEM_PWRGD 2 1 D16 eDP_TX#[2] PEG_TX[15] D25 1 2 1
F15 T0314 1 CLK_CPU_BCLK#
@ eDP_TX#[3]
SKTOCC# (Socket
Occupied): pulled
to ground on the SOCKET989
processor package

U0301B CLK_CPU_BCLK_L 3 @ RNX0303B


0OHM 4 ICS_BCLK <29>
CLK_CPU_BCLK#_L 1 RNX0303A RNX0301 close to CPU, C0301 and
0OHM 2 ICS_BCLK# <29>
@
PROCHOT#: 0.15nS<Tr<0.44nS, C0337 1 2 0.01UF/16V C0301 1 2 1.8PF/50V @
C0302 Close to RNX0301
0.1ns<Tf<0.45ns (measured CATEER#: This signal @ A28 CLK_CPU_BCLK_L 3 4 RNX0301B
0OHM CLK_CPU_BCLK <21>

MISC

CLOCKS
BCLK CLK_CPU_BCLK#_L
between 0.7*VCCP and indicates that the <24> H_SNB_INV# C26 PROC_SELECT# BCLK# A27 1 0OHM 2 RNX0301A CLK_CPU_BCLK# <21> 100 MHz, Come form PCH
0.3*VCCP system has experienced a
catastrophic error and 1 2 1.8PF/50V @
<80> SNB_SKTOCC# AN34 C0302
can't continue to SKTOCC#
B DPLL_REF_SSCLK A16 CLK_DREF <21> For eDP 120MHz B
operate A15
DPLL_REF_SSCLK# CLK_DREF# <21>

T0303 1 H_CATERR# AL33 CLK_DREF# 1KOhm 2 1 R0340 +VTT_CPU


CATERR#

<30> PECI_EC CLK_DREF 1KOhm 1 2 R0341


THERMAL

H_PECI_ISO AN33 R8
PECI SM_DRAMRST# M_DRAMRST# <4>
<80> H_PROCHOT_S#
DDR3
MISC
+VTT_CPU

D0301 R0307 1 2 200Ohm H_PROCHOT_S#_R AL32 AK1 SM_RCOMP0 R0323 1 2 140Ohm 1%


RB751V-40 PROCHOT# SM_RCOMP[0] SM_RCOMP1 R0324
SM_RCOMP[1] A5 1 2 25.5OHM 1% Follow 436715_4_sodimm_Rev0.9
<30,75,88> PWRLIMIT# 2 1 H_PROCHOT_S#_R1 R0308 1 2 56OHM A4 SM_RCOMP2 R0325 1 2 200Ohm 1%
SM_RCOMP[2]
@ <25> H_THRMTRIP# SL0301 2 1 H_THRMTRIP#_R AN32
R0345 0402 THERMTRIP#
2 1 0Ohm
1

connected
PC0334
+3VA_EC +3VS 43PF/50V
43pF close T0315 1 XDP_TCLK
2

@ to the IMVP PRDY# AP29 XDP_PRDY# <7> T0316 1 XDP_TRST#


1

AP27 XDP_PREQ# T0317 1 XDP_TMS


PREQ#
1

R0347 T0318 1 XDP_TDI


3

R0346 100KOhm C0336 1 2 0.01UF/16V AR26 T0319 1 XDP_TDO


TCK XDP_TCLK <7>
PWR MANAGEMENT

100KOhm @ Q0301B @ T0320 XDP_DBRESET#


JTAG & BPM

TMS AR27 XDP_TMS <7> 1


@ 5 UM6K31N <22> PM_SYNC# SL0302 1 2 PM_SYNC#_R AM34 AP30 XDP_TRST# <7>
6 2

@ 0402 PM_SYNC TRST#


2

C0335 1 2 0.01UF/16V AR28 XDP_TDI_R R0326 1 2 0Ohm XDP_TDI <7>


Q0301A @ TDI XDP_TDO_R R0327
TDO AP26 1 2 0Ohm XDP_TDO <7>
<30> THRO_CPU# 2 UM6K31N <7,25> H_CPUPWRGD SL0303 1 2 H_CPUPWRGD_R AP33
@ 0402 UNCOREPWRGOOD
1

R0309 2 1 10KOhm
AL35 H_DBR#_R R0328 1 2 0Ohm XDP_DBRESET# <7,22,67>
DRAMPWROK DBR# +VTT_CPU
R0322 1 2 130Ohm VDDPWRGOOD_R V8 SM_DRAMPWROK
PM_DRAMPWROK: 0.15nS<Tr<0.42nS, 0.09ns<Tf<0.36ns 1% AT28 XDP_OBS0 1 T0304
T0302 BPM#[0] XDP_OBS1 T0305 XDP_TMS R0329 51Ohm
(measured between 0.7*VCCP and 0.3*VCCP 1 BPM#[1] AR29 1 2 1
A AR30 XDP_OBS2 1 T0306 XDP_TDI_R R0330 2 1 51Ohm A
CPU_RST# BPM#[2] XDP_OBS3 T0307 XDP_PREQ# R0331 51Ohm @
AR33 RESET# BPM#[3] AT30 1 2 1
+VTT_CPU AP32 XDP_OBS4 1 T0308 XDP_TCLK R0332 1 2 51Ohm
BPM#[4]

1bios.ru
AR31 XDP_OBS5 1 T0309 XDP_TRST# R0333 1 2 51Ohm
BPM#[5] XDP_OBS6 T0310
BPM#[6] AT31 1
1

U0302 +3VS AR32 XDP_OBS7 1 T0311


<24,30,33,42,45,53,54,68,70> BUF_PLT_RST# BPM#[7]
R0313
1 NC VCC 5 75Ohm
2 A
3 GND Y 4
2

PLT_RST#_R R0310 2 1 43Ohm SOCKET989


CPU CPU_RST#: Title : CPU_DMI,PEG,FDI,CLK,MISC
1

C0333 74LVC1G07GW 0.25nS<Tr<0.42nS,


Reset,meet
Rise and fall time spec
0.01UF/16V
@
R0311
750Ohm
0.09ns<Tf<0.36ns (measured ASUSTeK COMPUTER INC. NB3 Engineer: Wish
2

1% between 0.7*VCCP and Size Project Name Rev


0.3*VCCP
R0312 2 1 0Ohm @
C N73Sv 1.0
2

@
Date: Wednesday, October 13, 2010 Sheet 3 of 95
5 4 3 2 1
5 4 3 2 1

Main Board

D D

U0301C U0301D

SA_CLK[0] AB6 M_CLK_DDR0 <16> SB_CLK[0] AE2 M_CLK_DDR2 <17>


<14,16> M_A_DQ[63:0] SA_CLK#[0] AA6 M_CLK_DDR#0 <16> <17> M_B_DQ[63:0] SB_CLK#[0] AD2 M_CLK_DDR#2 <17>
M_A_DQ0 C5 V9 M_CKE0 <16> M_B_DQ0 C9 R9
SA_DQ[0] SA_CKE[0] SB_DQ[0] SB_CKE[0] M_CKE2 <17>
M_A_DQ1 D5 M_B_DQ1 A7
M_A_DQ2 SA_DQ[1] M_B_DQ2 SB_DQ[1]
D3 SA_DQ[2] D10 SB_DQ[2]
M_A_DQ3 D2 M_B_DQ3 C8
M_A_DQ4 SA_DQ[3] M_B_DQ4 SB_DQ[3]
D6 SA_DQ[4] SA_CLK[1] AA5 M_CLK_DDR1 <16> A9 SB_DQ[4] SB_CLK[1] AE1 M_CLK_DDR3 <17>
M_A_DQ5 C6 AB5 M_CLK_DDR#1 <16> M_B_DQ5 A8 AD1
SA_DQ[5] SA_CLK#[1] SB_DQ[5] SB_CLK#[1] M_CLK_DDR#3 <17>
M_A_DQ6 C2 V10 M_CKE1 <16> M_B_DQ6 D9 R10
SA_DQ[6] SA_CKE[1] SB_DQ[6] SB_CKE[1] M_CKE3 <17>
M_A_DQ7 C3 M_B_DQ7 D8
M_A_DQ8 SA_DQ[7] M_B_DQ8 SB_DQ[7]
F10 SA_DQ[8] G4 SB_DQ[8]
M_A_DQ9 F8 M_B_DQ9 F4
M_A_DQ10 SA_DQ[9] M_B_DQ10 SB_DQ[9]
G10 SA_DQ[10] SA_CLK[2] AB4 M_CLK_DDR4 <14> F1 SB_DQ[10] SB_CLK[2] AB2
M_A_DQ11 G9 AA4 M_CLK_DDR#4 <14> M_B_DQ11 G1 AA2
M_A_DQ12 SA_DQ[11] SA_CLK#[2] M_B_DQ12 SB_DQ[11] SB_CLK#[2]
F9 SA_DQ[12] SA_CKE[2] W9 M_CKE4 <14> G5 SB_DQ[12] SB_CKE[2] T9
M_A_DQ13 F7 M_B_DQ13 F5
M_A_DQ14 SA_DQ[13] M_B_DQ14 SB_DQ[13]
M_A_DQ15
G8
G7
SA_DQ[14] For Second DIMM M_B_DQ15
F2
G2
SB_DQ[14]
M_A_DQ16 SA_DQ[15] M_B_DQ16 SB_DQ[15]
K4 SA_DQ[16] SA_CLK[3] AB3 M_CLK_DDR5 <14> J7 SB_DQ[16] SB_CLK[3] AA1
M_A_DQ17 K5 AA3 M_CLK_DDR#5 <14> M_B_DQ17 J8 AB1
M_A_DQ18 SA_DQ[17] SA_CLK#[3] M_B_DQ18 SB_DQ[17] SB_CLK#[3]
K1 SA_DQ[18] SA_CKE[3] W10 M_CKE5 <14> K10 SB_DQ[18] SB_CKE[3] T10
M_A_DQ19 J1 M_B_DQ19 K9
M_A_DQ20 SA_DQ[19] M_B_DQ20 SB_DQ[19]
J5 SA_DQ[20] J9 SB_DQ[20]
M_A_DQ21 J4 M_B_DQ21 J10
M_A_DQ22 SA_DQ[21] M_B_DQ22 SB_DQ[21]
J2 SA_DQ[22] SA_CS#[0] AK3 M_CS#0 <16> K8 SB_DQ[22] SB_CS#[0] AD3 M_CS#2 <17>
M_A_DQ23 K2 AL3 M_CS#1 <16> M_B_DQ23 K7 AE3 M_CS#3 <17>
M_A_DQ24 SA_DQ[23] SA_CS#[1] M_B_DQ24 SB_DQ[23] SB_CS#[1]
M_A_DQ25
M8
N10
SA_DQ[24] SA_CS#[2] AG1
AH1
M_CS#4 <14> For Second DIMM M_B_DQ25
M5
N4
SB_DQ[24] SB_CS#[2] AD6
AE6
SA_DQ[25] SA_CS#[3] M_CS#5 <14> SB_DQ[25] SB_CS#[3]
C M_A_DQ26 N8 M_B_DQ26 N2 C
M_A_DQ27 SA_DQ[26] M_B_DQ27 SB_DQ[26]
N7 SA_DQ[27] N1 SB_DQ[27]
M_A_DQ28 M10 M_B_DQ28 M4
M_A_DQ29 SA_DQ[28] M_B_DQ29 SB_DQ[28]
M9 SA_DQ[29] SA_ODT[0] AH3 M_ODT0 <16> N5 SB_DQ[29] SB_ODT[0] AE4 M_ODT2 <17>

DDR SYSTEM MEMORY B


M_A_DQ30 N9 DDR SYSTEM MEMORY A AG3 M_ODT1 <16> M_B_DQ30 M2 AD4 M_ODT3 <17>
M_A_DQ31 SA_DQ[30] SA_ODT[1] M_B_DQ31 SB_DQ[30] SB_ODT[1]
M_A_DQ32
M7
AG6
SA_DQ[31] SA_ODT[2] AG2
AH2
M_ODT4 <14> For Second DIMM M_B_DQ32
M1
AM5
SB_DQ[31] SB_ODT[2] AD5
AE5
SA_DQ[32] SA_ODT[3] M_ODT5 <14> SB_DQ[32] SB_ODT[3]
M_A_DQ33 AG5 M_B_DQ33 AM6
M_A_DQ34 SA_DQ[33] M_B_DQ34 SB_DQ[33]
AK6 SA_DQ[34] AR3 SB_DQ[34]
M_A_DQ35 AK5 M_B_DQ35 AP3
M_A_DQ36 SA_DQ[35] M_B_DQ36 SB_DQ[35]
AH5 SA_DQ[36] M_A_DQS#[7:0] <14,16> AN3 SB_DQ[36] M_B_DQS#[7:0] <17>
M_A_DQ37 AH6 C4 M_A_DQS#0 M_B_DQ37 AN2 D7 M_B_DQS#0
M_A_DQ38 SA_DQ[37] SA_DQS#[0] M_A_DQS#1 M_B_DQ38 SB_DQ[37] SB_DQS#[0] M_B_DQS#1
AJ5 SA_DQ[38] SA_DQS#[1] G6 AN1 SB_DQ[38] SB_DQS#[1] F3
M_A_DQ39 AJ6 J3 M_A_DQS#2 M_B_DQ39 AP2 K6 M_B_DQS#2
M_A_DQ40 SA_DQ[39] SA_DQS#[2] M_A_DQS#3 M_B_DQ40 SB_DQ[39] SB_DQS#[2] M_B_DQS#3
AJ8 SA_DQ[40] SA_DQS#[3] M6 AP5 SB_DQ[40] SB_DQS#[3] N3
M_A_DQ41 AK8 AL6 M_A_DQS#4 M_B_DQ41 AN9 AN5 M_B_DQS#4
M_A_DQ42 SA_DQ[41] SA_DQS#[4] M_A_DQS#5 M_B_DQ42 SB_DQ[41] SB_DQS#[4] M_B_DQS#5
AJ9 SA_DQ[42] SA_DQS#[5] AM8 AT5 SB_DQ[42] SB_DQS#[5] AP9
M_A_DQ43 AK9 AR12 M_A_DQS#6 M_B_DQ43 AT6 AK12 M_B_DQS#6
M_A_DQ44 SA_DQ[43] SA_DQS#[6] M_A_DQS#7 M_B_DQ44 SB_DQ[43] SB_DQS#[6] M_B_DQS#7
AH8 SA_DQ[44] SA_DQS#[7] AM15 AP6 SB_DQ[44] SB_DQS#[7] AP15
M_A_DQ45 AH9 M_B_DQ45 AN8
M_A_DQ46 SA_DQ[45] M_B_DQ46 SB_DQ[45]
AL9 SA_DQ[46] AR6 SB_DQ[46]
M_A_DQ47 AL8 M_B_DQ47 AR5
M_A_DQ48 SA_DQ[47] M_B_DQ48 SB_DQ[47]
AP11 SA_DQ[48] M_A_DQS[7:0] <14,16> AR9 SB_DQ[48] M_B_DQS[7:0] <17>
M_A_DQ49 AN11 D4 M_A_DQS0 M_B_DQ49 AJ11 C7 M_B_DQS0
M_A_DQ50 SA_DQ[49] SA_DQS[0] M_A_DQS1 M_B_DQ50 SB_DQ[49] SB_DQS[0] M_B_DQS1
AL12 SA_DQ[50] SA_DQS[1] F6 AT8 SB_DQ[50] SB_DQS[1] G3
M_A_DQ51 AM12 K3 M_A_DQS2 M_B_DQ51 AT9 J6 M_B_DQS2
M_A_DQ52 SA_DQ[51] SA_DQS[2] M_A_DQS3 M_B_DQ52 SB_DQ[51] SB_DQS[2] M_B_DQS3
AM11 SA_DQ[52] SA_DQS[3] N6 AH11 SB_DQ[52] SB_DQS[3] M3
M_A_DQ53 AL11 AL5 M_A_DQS4 M_B_DQ53 AR8 AN6 M_B_DQS4
M_A_DQ54 SA_DQ[53] SA_DQS[4] M_A_DQS5 M_B_DQ54 SB_DQ[53] SB_DQS[4] M_B_DQS5
AP12 SA_DQ[54] SA_DQS[5] AM9 AJ12 SB_DQ[54] SB_DQS[5] AP8
M_A_DQ55 AN12 AR11 M_A_DQS6 M_B_DQ55 AH12 AK11 M_B_DQS6
M_A_DQ56 SA_DQ[55] SA_DQS[6] M_A_DQS7 M_B_DQ56 SB_DQ[55] SB_DQS[6] M_B_DQS7
AJ14 SA_DQ[56] SA_DQS[7] AM14 AT11 SB_DQ[56] SB_DQS[7] AP14
M_A_DQ57 AH14 M_B_DQ57 AN14
M_A_DQ58 SA_DQ[57] M_B_DQ58 SB_DQ[57]
AL15 SA_DQ[58] AR14 SB_DQ[58]
M_A_DQ59 AK15 M_B_DQ59 AT14
M_A_DQ60 SA_DQ[59] M_B_DQ60 SB_DQ[59]
AL14 SA_DQ[60] M_A_A[15:0] <14,16> AT12 SB_DQ[60] M_B_A[15:0] <17>
M_A_DQ61 AK14 AD10 M_A_A0 M_B_DQ61 AN15 AA8 M_B_A0
M_A_DQ62 SA_DQ[61] SA_MA[0] M_A_A1 M_B_DQ62 SB_DQ[61] SB_MA[0] M_B_A1
AJ15 SA_DQ[62] SA_MA[1] W1 AR15 SB_DQ[62] SB_MA[1] T7
M_A_DQ63 AH15 W2 M_A_A2 M_B_DQ63 AT15 R7 M_B_A2
B SA_DQ[63] SA_MA[2] M_A_A3 SB_DQ[63] SB_MA[2] M_B_A3 B
SA_MA[3] W7 SB_MA[3] T6
V3 M_A_A4 T2 M_B_A4
SA_MA[4] M_A_A5 SB_MA[4] M_B_A5
SA_MA[5] V2 SB_MA[5] T4
W3 M_A_A6 T3 M_B_A6
SA_MA[6] M_A_A7 SB_MA[6] M_B_A7
<14,16> M_A_BS0 AE10 SA_BS[0] SA_MA[7] W6 <17> M_B_BS0 AA9 SB_BS[0] SB_MA[7] R2
<14,16> M_A_BS1 AF10 V1 M_A_A8 <17> M_B_BS1 AA7 T5 M_B_A8
SA_BS[1] SA_MA[8] M_A_A9 SB_BS[1] SB_MA[8] M_B_A9
<14,16> M_A_BS2 V6 SA_BS[2] SA_MA[9] W5 <17> M_B_BS2 R6 SB_BS[2] SB_MA[9] R3
AD8 M_A_A10 AB7 M_B_A10
SA_MA[10] M_A_A11 SB_MA[10] M_B_A11
SA_MA[11] V4 SB_MA[11] R1
W4 M_A_A12 T1 M_B_A12
SA_MA[12] M_A_A13 SB_MA[12] M_B_A13
<14,16> M_A_CAS# AE8 SA_CAS# SA_MA[13] AF8 <17> M_B_CAS# AA10 SB_CAS# SB_MA[13] AB10
<14,16> M_A_RAS# AD9 V5 M_A_A14 <17> M_B_RAS# AB8 R5 M_B_A14
SA_RAS# SA_MA[14] M_A_A15 SB_RAS# SB_MA[14] M_B_A15
<14,16> M_A_WE# AF9 SA_WE# SA_MA[15] V7 <17> M_B_WE# AB9 SB_WE# SB_MA[15] R4

SOCKET989 SOCKET989

R0403 1 2 0Ohm DRAM RESET


@

+1.5V
1

R0401
Q0401 1KOhm

A A
2
S 2

<3> M_DRAMRST# 2 3 DRAMRST# <14>


3

1bios.ru
2N7002ET1G
G
1

R0402 1 2 4.99KOhm
1

Rdson=3Ohm/Vgs(th)=2.5V
1%
<21> DRAMRST_PCH

Title :
1

Come from PCH, must


pull high to +3VSUS C0401 CPU_DDR3
0.047UF/16V Engineer: Wish
2

ASUSTeK COMPUTER INC. NB3


Size Project Name Rev
C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 4 of 95
5 4 3 2 1
5 4 3 2 1

Main Board

1,Via 2net
CFG1,CFG3,CFG8~CFG17,layout

D D
U0301H U0301I

U0301E AT35 AJ22


VSS1 VSS81
AT32 VSS2 VSS82 AJ19
AT29 VSS3 VSS83 AJ16 T35 VSS161 VSS234 F22
RSVD28 L7 AT27 VSS4 VSS84 AJ13 T34 VSS162 VSS235 F19
RSVD29 AG7 AT25 VSS5 VSS85 AJ10 T33 VSS163 VSS236 E30
<7> CFG0 CFG0 AK28 AE7 AT22 AJ7 T32 E27
CFG[0] RSVD30 VSS6 VSS86 VSS164 VSS237
AK29 CFG[1] RSVD31 AK2 AT19 VSS7 VSS87 AJ4 T31 VSS165 VSS238 E24
CFG2 AL26 W8 AT16 AJ3 T30 E21
CFG[2] RSVD32 VSS8 VSS88 VSS166 VSS239
AL27 CFG[3] AT13 VSS9 VSS89 AJ2 T29 VSS167 VSS240 E18
CFG4 AK26 AT10 AJ1 T28 E15
CFG5 CFG[4] VSS10 VSS90 VSS168 VSS241
AL29 CFG[5] RSVD33 AT26 AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13
CFG6 AL30 AM33 AT4 AH34 T26 E10
CFG7 CFG[6] RSVD34 VSS12 VSS92 VSS170 VSS243
AM31 CFG[7] RSVD35 AJ27 AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9
AM32 CFG[8] AR25 VSS14 VSS94 AH30 P8 VSS172 VSS245 E8
AM30 CFG[9] AR22 VSS15 VSS95 AH29 P6 VSS173 VSS246 E7
AM28 CFG[10] AR19 VSS16 VSS96 AH28 P5 VSS174 VSS247 E6
AM26 CFG[11] AR16 VSS17 VSS97 AH26 P3 VSS175 VSS248 E5
AN28 CFG[12] AR13 VSS18 VSS98 AH25 P2 VSS176 VSS249 E4
AN31 CFG[13] RSVD37 T8 AR10 VSS19 VSS99 AH22 N35 VSS177 VSS250 E3
AN26 CFG[14] RSVD38 J16 AR7 VSS20 VSS100 AH19 N34 VSS178 VSS251 E2
AM27 CFG[15] RSVD39 H16 AR4 VSS21 VSS101 AH16 N33 VSS179 VSS252 E1
AK31 CFG[16] RSVD40 G16 AR2 VSS22 VSS102 AH7 N32 VSS180 VSS253 D35
AN29 CFG[17] AP34 VSS23 VSS103 AH4 N31 VSS181 VSS254 D32
AP31 VSS24 VSS104 AG9 N30 VSS182 VSS255 D29
AP28 VSS25 VSS105 AG8 N29 VSS183 VSS256 D26
AP25 VSS26 VSS106 AG4 N28 VSS184 VSS257 D20
RSVD_NCTF_5 AR35 AP22 VSS27 VSS107 AF6 N27 VSS185 VSS258 D17
+VGFX @ R0512 2 1 49.9Ohm 1% H_CPU_RSVD1 AJ31 AT34 AP19 AF5 N26 C34
@ R0511 49.9Ohm 1% H_CPU_RSVD2 VAXG_VAL_SENSE RSVD_NCTF_1 VSS28 VSS108 VSS186 VSS259
2 1 AH31 VSSAXG_VAL_SENSE RSVD_NCTF_2 AT33 AP16 VSS29 VSS109 AF3 M34 VSS187 VSS260 C31
+VCORE @ R0509 2 1 49.9Ohm 1% H_CPU_RSVD3 AJ33 AP35 AP13 AF2 L33 C28
@ R0510 49.9Ohm 1% H_CPU_RSVD4 VCC_VAL_SENSE RSVD_NCTF_8 VSS30 VSS110 VSS188 VSS261
2 1 AH33 VSS_VAL_SENSE RSVD_NCTF_6 AR34 AP10 VSS31 VSS111 AE35 L30 VSS189 VSS262 C27
AP7 VSS32 VSS112 AE34 L27 VSS190 VSS263 C25
AP4 VSS33 VSS113 AE33 L9 VSS191 VSS264 C23
AJ26 RSVD5 AP1 VSS34 VSS114 AE32 L8 VSS192 VSS265 C10

RESERVED
C DIMM_DQ_VREF AN30 AE31 L6 C1 C
DIMM_CA_VREF VSS35 VSS115 VSS193 VSS266
AN27 VSS36 VSS116 AE30 L5 VSS194 VSS267 B22
B34 AN25 AE29 L4 B19
B4
D1
RSVD6
RSVD7
RSVD_NCTF_11
RSVD_NCTF_13
RSVD_NCTF_12
A33
A34
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
AE28
AE27
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
RSVD_NCTF_10 B35 AN16 VSS40 VSS120 AE26 L1 VSS198 VSS271 B13
RSVD_NCTF_9 C35 AN13 VSS41 VSS121 AE9 K35 VSS199 VSS272 B11
2

AN10 VSS42 VSS122 AD7 K32 VSS200 VSS273 B9


R0508 R0507 F25 AN7 AC9 K29 B8
RSVD8 VSS43 VSS123 VSS201 VSS274
1KOhm 1KOhm F24 RSVD9 AN4 VSS44 VSS124 AC8 K26 VSS202 VSS275 B7
@ @ F23 RSVD10 AM29 VSS45 VSS125 AC6 J34 VSS203 VSS276 B5
D24 AJ32 AM25 AC5 J31 B3
1

1% 1% RSVD11 RSVD51 VSS46 VSS126 VSS204 VSS277


G25 RSVD12 RSVD52 AK32 AM22 VSS47 VSS127 AC3 H33 VSS205 VSS278 B2
G24 RSVD13 AM19 VSS48 VSS128 AC2 H30 VSS206 VSS279 A35
E23 RSVD14 AM16 VSS49 VSS129 AB35 H27 VSS207 VSS280 A32
D23 RSVD15 AM13 VSS50 VSS130 AB34 H24 VSS208 VSS281 A29
C30 AH27 VCC_DIESENSE 1 T0519 AM10 AB33 H21 A26
+3VSUS RSVD16 VCC_DIE_SENSE VSS51 VSS131 VSS209 VSS282
A31 RSVD17 AM7 VSS52 VSS132 AB32 H18 VSS210 VSS283 A23
B30 RSVD18 AM4 VSS53 VSS133 AB31 H15 VSS211 VSS284 A20
B29 RSVD19 AM3 VSS54 VSS134 AB30 H13 VSS212 VSS285 A3
D30 RSVD20 BCLK_ITP AN35 CLK_ITP_BCLK <7> AM2 VSS55 VSS135 AB29 H10 VSS213
1

B31 RSVD21 BCLK_ITP# AM35 CLK_ITP_BCLK# <7> AM1 VSS56 VSS136 AB28 H9 VSS214
R0513 A30 AL34 AB27 H8
10KOhm RSVD22 VSS57 VSS137 VSS215
C29 RSVD23 AL31 VSS58 VSS138 AB26 H7 VSS216
AL28 VSS59 VSS139 Y9 H6 VSS217
AL25 Y8 H5
2

VSS60 VSS140 VSS218


J20 RSVD24 AL22 VSS61 VSS141 Y6 H4 VSS219
B18 RSVD25 RSVD_NCTF_3 AT2 AL19 VSS62 VSS142 Y5 H3 VSS220
<82> H_SNB#_PWRCTRL R0501 1 2 0Ohm H_VCCP_SEL A19 RSVD26 RSVD_NCTF_4 AT1 AL16 VSS63 VSS143 Y3 H2 VSS221
RSVD_NCTF_7 AR1 AL13 VSS64 VSS144 Y2 H1 VSS222
H_SNB_IVB#_PWRCTRL= LOW, VCCP=1.0V AL10 VSS65 VSS145 W35 G35 VSS223
J15 RSVD27 AL7 VSS66 VSS146 W34 G32 VSS224
H_SNB_IVB#_PWRCTRL= High/NC, VCCP=1.05V NTCF B1 AL4 VSS67 VSS147 W33 G29 VSS225
AL2 VSS68 VSS148 W32 G26 VSS226
AK33 VSS69 VSS149 W31 G23 VSS227
AK30 VSS70 VSS150 W30 G20 VSS228
AK27 VSS71 VSS151 W29 G17 VSS229
B
AK25 VSS72 VSS152 W28 G11 VSS230 B
AK22 VSS73 VSS153 W27 F34 VSS231
AK19 VSS74 VSS154 W26 F31 VSS232
AK16 VSS75 VSS155 U9 F29 VSS233
SOCKET989 AK13 U8
VSS76 VSS156
AK10 VSS77 VSS157 U6
AK7 VSS78 VSS158 U5
AK4 VSS79 VSS159 U3
AJ25 VSS80 VSS160 U2

SOCKET989 SOCKET989

CFG strapping information:


CFG[2]: PEG Static Lane Reversal (For the 16X)
- 1: (Default) Normal Operation; Lane # definition matches socket pin map definition
- 0: Lane Reversed CFG2 R0502 1 2 1KOhm @ 1%
CFG[4]: Display Port Presence Strap
- 1 : (Default) Disable; No Physical Display Port attached to Embedded Display Port CFG4 R0503 1 2 1KOhm @ 1%
- 0 : Enable; An external Display Port device is connected to the Embeded Display port
CFG[6:5]: PCIE Port Bifurcation Straps CFG5 R0504 1 2 1KOhm @ 1%

- 11 : (Default) X16 - Device 1 functions 1 and 2 disable


CFG6 R0505 1 2 1KOhm @ 1%
- 10 : X8, X8 - Device 1 function 1 enabled; Function 2 disable
A - 01 : Reserved - (Device 1 Function 1 disable ; Function 2 enable A
CFG7 R0506 1 2 1KOhm @ 1%
- 00 : X8, X4 X4 - Device 1 function 1 and 2 enabled

1bios.ru
CFG[7]: Defer Training
-1: (Default) PEG Train immediately following xxRESETB de assertion
-0: PEG Wait for BIOS for training
Title : CPU_CFG,RSVD,GND
ASUSTeK COMPUTER INC. NB3 Engineer: Wish
Size Project Name Rev
C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 5 of 95
5 4 3 2 1
5 4 3 2 1

Main Board
+VCORE
+VCORE_CPU

+VGFX_CORE +VGFX

+1.05VS +VTT_CPU

2C (35W) : 52A
4C (45W) : 78A U0301F POWER
D
+VGFX U0301G
POWER It must be min 100ns after to +1.5Vs reaches 80%
D

+VCORE_CPU
+VTT_CPU
33A
10A

SENSE
LINES
AG35 VCC1 AT24 VAXG1 VAXG_SENSE AK35 VCC_AXG_SENSE <80>
AG34 VCC2 VCCIO1 AH13 AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE <80>

1
AG33 AH10 C0628 C0629 C0630 AT21
VCC3 VCCIO2 VAXG3

1
AG32 AG10 C0604 C0605 22UF/6.3V 22UF/6.3V 22UF/6.3V AT20
VCC4 VCCIO3 VAXG4
AG31 AC10 22UF/6.3V 22UF/6.3V AT18 0930: R0617, R0618 Change to 1K +VDDQ

2
VCC5 VCCIO4 VAXG5
AG30 Y10 AT17

2
VCC6 VCCIO5 VAXG6
AG29 VCC7 VCCIO6 U10 AR24 VAXG7

2
AG28 VCC8 VCCIO7 P10 AR23 VAXG8
AG27 L10 AR21 R0617
VCC9 VCCIO8 VAXG9

1
AG26 J14 C0631 C0632 C0633 AR20 1KOhm

VREF
VCC10 VCCIO9 VAXG10

1
AF35 J13 C0607 C0608 C0609 C0610 22UF/6.3V 22UF/6.3V 22UF/6.3V AR18 1%
VCC11 VCCIO10 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V VAXG11
AF34 J12 AR17

1
VCC12 VCCIO11 VAXG12 +V_SM_VREF_CNT
AF33 J11 AP24 AL1

2
VCC13 VCCIO12 VAXG13 SM_VREF
AF32 VCC14 VCCIO13 H14 AP23 VAXG14

2
AF31 VCC15 VCCIO14 H12 AP21 VAXG15 +V_SM_VREF Should have 10
AF30 H11 AP20 R0618
VCC16 VCCIO15 VAXG16 mils trace width

1
AF29 G14 C0634 +
AP18 1KOhm
VCC17 VCCIO16 VAXG17

CE0604
C0614 C0615 22UF/6.3V 1%

330UF/2V
AF28 VCC18 VCCIO17 G13 AP17 VAXG18
PEG AND DDR

AF27 G12 22UF/6.3V 22UF/6.3V AN24 +1.5VS

1
VCC19 VCCIO18 VAXG19
AF26 F14 AN23

2
VCC20 VCCIO19 VAXG20
AD35 VCC21 VCCIO20 F13 AN21 VAXG21 +VDDQ
AD34 VCC22 VCCIO21 F12 AN20 VAXG22

DDR3 -1.5V RAILS


AD33 F11 @ AN18
VCC23 VCCIO22 VAXG23
AD32 VCC24 VCCIO23 E14 Power stuff AN17 VAXG24 5A

GRAPHICS
AD31 E12 C0617 C0618 C0619 C0620 AM24 AF7
VCC25 VCCIO24 220uF*2,so EE only VAXG25 VDDQ1

1
AD30 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V C0635 C0636 C0637 AM23 AF4
VCC26 VAXG26 VDDQ2

1
AD29 E11 reserve *1 22UF/6.3V 22UF/6.3V 22UF/6.3V AM21 AF1 C0647 C0648 C0649

2
VCC27 VCCIO25 VAXG27 VDDQ3 10UF/6.3V 10UF/6.3V 10UF/6.3V
AD28 D14 AM20 AC7

2
VCC28 VCCIO26 VAXG28 VDDQ4
AD27 D13 AM18 AC4

2
VCC29 VCCIO27 VAXG29 VDDQ5
AD26 VCC30 VCCIO28 D12 AM17 VAXG30 VDDQ6 AC1 1009 change +1.5V to
AC35 VCC31 VCCIO29 D11 AL24 VAXG31 VDDQ7 Y7 +1.5VS for energy star

1
+ +
AC34 VCC32 VCCIO30 C14 AL23 VAXG32 VDDQ8 Y4

1
CE0601

CE0802
C0638 C0639 C0640

330UF/2V

330UF/2V
AC33 VCC33 VCCIO31 C13 AL21 VAXG33 VDDQ9 Y1

1
C AC32 C12 22UF/6.3V 22UF/6.3V 22UF/6.3V AL20 U7 C0650 C0651 C0652 C
VCC34 VCCIO32 VAXG34 VDDQ10 10UF/6.3V 10UF/6.3V 10UF/6.3V
AC31 C11 AL18 U4

2
VCC35 VCCIO33 VAXG35 VDDQ11
AC30 B14 AL17 U1

2
VCC36 VCCIO34 VAXG36 VDDQ12
AC29 VCC37 VCCIO35 B12 AK24 VAXG37 VDDQ13 P7
AC28 A14 @ AK23 P4
VCC38 VCCIO36 VAXG38 VDDQ14
AC27 VCC39 VCCIO37 A13 AK21 VAXG39 VDDQ15 P1

1
AC26 VCC40 VCCIO38 A12 C0643 AK20 VAXG40
+
+0.8VS

CE0607
22UF/6.3V

330UF/2V
AA35 VCC41 VCCIO39 A11 AK18 VAXG41
AA34 AK17

2
VCC42 +VTT_CPU VAXG42 @
AA33 J23 AJ24

2
VCC43 VCCIO40 VAXG43
AA32 VCC44 AJ23 VAXG44
AA31 VCC45 AJ21 VAXG45
AA30 VCC46 AJ20 VAXG46
AA29 VCC47 AJ18 VAXG47
AA28 VCC48 AJ17 VAXG48
AA27 AH24

SA RAIL
VCC49 VAXG49
1

1
AA26 VCC50 AH23 VAXG50 6A
CORE SUPPLY

Y35 C0677 C0678 C0679 AH21 M27 VCCSA


VCC51 VAXG51 VCCSA1

1
Y34 0.1UF/16V 0.1UF/16V 0.1UF/16V AH20 M26 C0653 C0654 C0655 C0656 +
2

2
VCC52 VAXG52 VCCSA2

CE0608
10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V

330UF/2V
Y33 VCC53 AH18 VAXG53 VCCSA3 L26
Y32 AH17 J26

2
VCC54 @ @ @ +1.8VS VAXG54 VCCSA4
Y31 J25

2
VCC55 VCCSA5
Y30 VCC56 VCCSA6 J24
Y29 VCC57 VCCSA7 H26
Y28 VCC58 VCCSA8 H25

2
Y27 +VTT_CPU R0605 1 2 75Ohm
VCC59

1.8V RAIL
Y26 SL0607

0805
VCC60 R0610 2
V35 1 100Ohm +0.8VS
SVID

VCC61 H_CPU_SVIDALRT# R0602


V34 VCC62 VIDALERT# AJ29 1 2 43Ohm VR_SVID_ALERT# <80>
V33 AJ30 H_CPU_SVIDCLK
VR_SVID_CLK <80> 1A 1%

1
VCC63 VIDSCLK H_CPU_SVIDDAT VCCPLL VCCSA_SENSE T0602
V32 AJ28 VR_SVID_DATA <80> B6 H23 1

MISC
VCC64 VIDSOUT VCCPLL1 VCCSA_SENSE
V31 VCC65 A6 VCCPLL2

1
V30 C0644 C0645 C0646 +
A2
VCC66 VCCPLL3 VCCSA_SEL0 <87>

CE0606
R0604 2 130Ohm 10UF/6.3V 1UF/6.3V 1UF/6.3V

330UF/2V
V29 VCC67 +VTT_CPU 1
V28 C22 R0608 1 2 1KOhm

2
VCC68 1% FC_C22
V27 C24 VCCSA_SEL1 <87>

2
VCC69 VCCSA_VID1
V26 VCC70
B
U35 VCC71 B
U34 @ R0609 1 2 1KOhm
VCC72 SOCKET989
U33 VCC73
U32 VCC74
U31 VCC75
U30 VCC76 VCCSA_SEL0 VCCSA_SEL1 VCCSA_SEL
U29 VCC77
U28 VCC78
U27 VCC79
U26 VCC80 L L
R35
R34
VCC81 0.9V
VCC82
R33
R32
VCC83 100ohm R0606 & R0607 delete,Power stuff
VCC84
R31 VCC85 L H
R30
R29
VCC86 0.8V
VCC87
SENSE LINES

R28 VCC88
R27 AJ35 SL0604 1 2
VCC89 VCC_SENSE 0402 VCCSENSE <80>
R26 AJ34 SL0605 1 2
VCC90 VSS_SENSE 0402 VSSSENSE <80>
P35
P34
VCC91
1
H L 0.75V
VCC92 T0601
P33 VCC93
P32 VCC94 VCCIO_SENSE B10 VCCP_SENSE <82>
P31 VCC95 VSSIO_SENSE A10 VSSP_SENSE <82>
P30 VCC96
P29 VCC97 H H 0.65V
P28 VCC98 PC8071,PC8072 change to 10uF,so its can be in CPU socket
P27 VCC99
P26 VCC100

+VCORE In CPU socket


1

1
PC8070 PC8071 PC8072 PC8073 PC8074 PC8075 PC8076 PC8077 PC8078 PC8079
22UF/6.3V 10UF/6.3V 10UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V
A SOCKET989 c0805 c0603 c0603 c0805 c0805 c0805 c0805 c0805 c0805 c0805 A
2

1bios.ru +VCORE close CPU socket

Title :
1

PC8080
22UF/6.3V
PC8081
22UF/6.3V
PC8082
22UF/6.3V
PC8083
22UF/6.3V
PC8084
22UF/6.3V
PC8085
22UF/6.3V
PC8086
22UF/6.3V
PC8087
22UF/6.3V
PC8088
22UF/6.3V
PC8089
22UF/6.3V CPU_PWR
c0805 c0805 c0805 c0805 c0805 c0805 c0805 c0805 c0805 c0805 Engineer: Wish
2

ASUSTeK COMPUTER INC. NB3


Size Project Name Rev
C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 6 of 95
5 4 3 2 1
5 4 3 2 1

Main Board

D D

+1.05VSO +3VS

C C

1
R0706 R0707
51Ohm 1KOhm

2
XDP_DBRESET# <3,22,67>

XDP_TDO <3>

R0708 1 2 0Ohm @
PCH_JTAG_TDO <20,67>

XDP_TDI <3>
XDP_TMS <3>

R0709 1 2 0Ohm @
PCH_JTAG_TDI <20,67>

FPC_CON_26P R0710 1 2 0Ohm @


PCH_JTAG_TMS <20,67>
1 XDP_PREQ#_D 1
T0706 1 +3VA
<3> XDP_PRDY# 2 2 SIDE1 27
3 3
1 OBS_DATA0 4
T0701 OBS_DATA1 4
B
1 5 5 1 B
T0702 6
OBS_DATA2 6 R0711
1 7 7
T0703 1 OBS_DATA3 8 1KOhm
T0704 8
9 9 @
R0701 2 1KOhm 1 CPUPWRGD_XDP 10
<3,25> H_CPUPWRGD
2

R0702 0Ohm PM_PWRBTN#_XDP 10


<22,67> PM_PWRBTN#_R 2 1 11 11
R0703 1 1KOhm
/X 2 XDP_HOOK2 12
<5> CFG0 12
R0704 1 0Ohm
/X 2 SYS_PWROK_XDP 13 SYS_PWROK_XDP
<22> PM_SYSPWROK_PCH 13
/X CLK_XDP_P 14
CLK_XDP_N 14
/X 15 15
+1.05VSO 16 16
R0705 1 1KOhm 2 XDP_RST#_R 17
<3,25> H_CPUPWRGD 17
<3,22,67> XDP_DBRESET# 18 18
/X 19 19
<3> XDP_TDO 20 20
<3> XDP_TRST# 21 21
<3> XDP_TDI 22 22
<3> XDP_TMS 23 23
1 TCK1 24
T0705 24
25 25 SIDE2 28
<3> XDP_TCLK 26 26 CLK_XDP_P 3 @ RNX0703B
0OHM 4 CLK_ITP_BCLK <5>
CLK_XDP_N 1 RNX0703A
J0701 0OHM 2 CLK_ITP_BCLK# <5>
@
CLK_XDP_N 3 RNX0702B
0OHM 4 CLK_ITP_BCLK_PCH# <21>
CLK_XDP_P 1 RNX0702A
/X 0OHM 2 CLK_ITP_BCLK_PCH <21>
/X
/X

A A

1bios.ru Title : CPU_XDP


ASUSTeK COMPUTER INC. NB3 Engineer: Wish
Size Project Name Rev
C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 7 of 95
5 4 3 2 1
5 4 3 2 1

Main Board

D D

C C

B B

A A

1bios.ru Title : NB_****


ASUSTeK COMPUTER INC. NB3 Engineer: Wish
Size Project Name Rev
C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 8 of 95
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A
Title : NB_****
1bios.ru ASUSTeK COMPUTER INC. NB3
Size Project Name
Engineer: Wish
Rev
A N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 9 of 95
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A
Title : NB_****
1bios.ru ASUSTeK COMPUTER INC. NB3
Size Project Name
Engineer: Wish
Rev
A N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 10 of 95
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A
Title : NB_****
1bios.ru ASUSTeK COMPUTER INC. NB3
Size Project Name
Engineer: Wish
Rev
A N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 11 of 95
5 4 3 2 1
5 4 3 2 1

Main Board

D D

C C

B B

A A

1bios.ru Title : NB_****


ASUSTeK COMPUTER INC. NB3 Engineer: Wish
Size Project Name Rev
C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 12 of 95
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

1bios.ru Title : NB_****


ASUSTeK COMPUTER INC. NB3 Engineer: Wish
Size Project Name Rev
C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 13 of 95
5 4 3 2 1
5 4 3 2 1

D
CH-A-4mm-TOP M_A_DQ[63:0] <4,16>
D

J1401A J1401B
<4,16> M_A_A[15:0]
5 M_A_DQ8
DQ0 M_A_DQ10
DQ1 7
M_A_A0 98 15 M_A_DQ9 <16,17,30> PM_EXTTS#0 198 2
M_A_A1 A0 DQ2 M_A_DQ13 EVENT# VSS1
97 A1 DQ3 17 VSS2 3
M_A_A2 96 4 M_A_DQ11 8
M_A_A3 A2 DQ4 M_A_DQ12 VSS3
95 A3 DQ5 6 207 GND1 VSS4 9
M_A_A4 M_A_DQ14
M_A_A5
92
91
A4 DQ6 16
18 M_A_DQ15
0 208 GND2 VSS5 13
14
M_A_A6 A5 DQ7 M_A_DQ5 VSS6
90 A6 DQ8 21 VSS7 19
M_A_A7 86 23 M_A_DQ4 SMBus Slave Address: A2H 77 20
M_A_A8 A7 DQ9 M_A_DQ7 NC1 VSS8
89 A8 DQ10 33 122 NC2 VSS9 25
M_A_A9 85 35 M_A_DQ2 26
M_A_A10 A9 DQ11 M_A_DQ0 VSS10
107 A10/AP DQ12 22 205 NP_NC1 VSS11 31
M_A_A11 84 24 M_A_DQ1 +3VS 206 32
M_A_A12 A11 DQ13 M_A_DQ3 NP_NC2 VSS12
83 A12/BC# DQ14 34 1 VSS13 37
M_A_A13 119 36 M_A_DQ6 116 38
A13 DQ15 <4> M_ODT4 ODT0 VSS14
M_A_A14 80 39 M_A_DQ17 120 43
A14 DQ16 <4> M_ODT5 ODT1 VSS15
M_A_A15 78 41 M_A_DQ20 44
A15 DQ17 VSS16

1
51 M_A_DQ23 48
DQ18 M_A_DQ19 R1401 VSS17
DQ19 53 <4,16> M_A_RAS# 110 RAS# VSS18 49
109 40 M_A_DQ21 10KOhm <4> DRAMRST# 2 1 30 54
<4,16> M_A_BS0 BA0 DQ20 RESET# VSS19
108 42 M_A_DQ16 R1403 1% 1KOhm 55
<4,16> M_A_BS1 BA1 DQ21 <16,17> DRAMRST#_R VSS20
79 50 M_A_DQ18 114 60
<4,16> M_A_BS2 2 <4> M_CS#4

2
BA2 DQ22 M_A_DQ22 S#0 VSS21
DQ23 52 <4> M_CS#5 121 S#1 VSS22 61
57 M_A_DQ28 65
DQ24 M_A_DQ30 VSS23
DQ25 59 197 SA0 VSS24 66
115 67 M_A_DQ27 201 71
<4,16> M_A_CAS# CAS# DQ26 SA1 VSS25
103 69 M_A_DQ31 72
<4> M_CLK_DDR#4 CK#0 DQ27 VSS26
104 56 M_A_DQ24 127
C <4> M_CLK_DDR#5 CK#1 DQ28 VSS27 C
101 58 M_A_DQ26 202 128
<4> M_CLK_DDR4 CK0 DQ29 <16,17,28,29,53> SMB_CLK_S SCL VSS28
102 68 M_A_DQ25 200 133
<4> M_CLK_DDR5
73
CK1 DQ30
70 M_A_DQ29
3 <16,17,28,29,53> SMB_DAT_S SDA VSS29
134
<4> M_CKE4 CKE0 DQ31 VSS30
74 129 M_A_DQ32 138
<4> M_CKE5 CKE1 DQ32 VSS31
131 M_A_DQ38 125 139
DQ33 M_A_DQ33 TEST VSS32
DQ34 141 VSS33 144
11 143 M_A_DQ36 145
DM0 DQ35 M_A_DQ35 VSS34
28 DM1 DQ36 130 75 VDD1 VSS35 150
46 132 M_A_DQ37 76 151
DM2 DQ37 M_A_DQ34 VDD2 VSS36
63
136
DM3 DQ38 140
142 M_A_DQ39
4 +1.5V
81
82
VDD3 VSS37 155
156
DM4 DQ39 M_A_DQ47 VDD4 VSS38
153 DM5 DQ40 147
M_A_DQ41
Layout Note: Place these caps near SO DIMM 0 87 VDD5 VSS39 161
170 DM6 DQ41 149 88 VDD6 VSS40 162
187 157 M_A_DQ40 93 167
DM7 DQ42 VDD7 VSS41

1
159 M_A_DQ46 94 168
DQ43 M_A_DQ44 C1405 C1406 C1407 C1408 VDD8 VSS42
<4,16> M_A_DQS[7:0] DQ44 146 99 VDD9 VSS43 172
M_A_DQS1 12 148 M_A_DQ42 1UF/10V 1UF/10V 1UF/10V 1UF/10V 100 173

2
M_A_DQS0 DQS0 DQ45 M_A_DQ43 VDD10 VSS44
M_A_DQS2
29
47
DQS1 DQ46 158
160 M_A_DQ45
5 105
106
VDD11 VSS45 178
179
M_A_DQS3 DQS2 DQ47 M_A_DQ49 VDD12 VSS46
64 DQS3 DQ48 163 111 VDD13 VSS47 184
M_A_DQS4 137 165 M_A_DQ53 112 185
DQS4 DQ49 VDD14 VSS48

1
M_A_DQS5 154 175 M_A_DQ50 + 117 189
DQS5 DQ50 VDD15 VSS49

1
M_A_DQS6 171 177 M_A_DQ52 @ @ 118 190 +0.75VS
M_A_DQS7 DQS6 DQ51 M_A_DQ51 CE1403 C1410 C1411 C1412 C1413 C1420 VDD16 VSS50
188 DQS7 DQ52 164 123 VDD17 VSS51 195
166 M_A_DQ48 220UF/4V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 1UF/10V 124 196

2
DQ53 M_A_DQ54 VDD18 VSS52
<4,16> M_A_DQS#[7:0] DQ54 174 6
M_A_DQS#1 10 176 M_A_DQ55
M_A_DQS#0 DQS#0 DQ55 M_A_DQ61 ESR=40mOhm/Ir=1.9A
27 DQS#1 DQ56 181 199 VDDSPD VTT1 203
M_A_DQS#2 45 183 M_A_DQ57 204
M_A_DQS#3 DQS#2 DQ57 M_A_DQ58 VTT2
62 DQS#3 DQ58 191
M_A_DQS#4 135 193 M_A_DQ60 126
M_A_DQS#5 DQS#4 DQ59 M_A_DQ62 +3VS VREFCA
152 DQS#5 DQ60 180 1 VREFDQ
B M_A_DQS#6 169 182 M_A_DQ56 113 M_A_WE# <4,16> B
M_A_DQS#7 DQS#6 DQ61 M_A_DQ63 WE#
186 DQS#7 DQ62 192 7
194 M_A_DQ59
DQ63
1

1
C1414 C1415 DDR3_DIMM_204P
2.2UF/10V 0.1UF/16V
2

2
DDR3_DIMM_204P
M_VREFCA_DIMM0
+0.75VS

12G02554204A

1
C1424 C1423

1
2.2UF/10V 0.1UF/16V

2
C1416 C1417 C1418 C1419
1UF/10V 1UF/10V 1UF/10V 1UF/10V

2
M_VREFDQ_DIMM0

1
C1422 C1425
2.2UF/10V 0.1UF/16V
2

A A

1bios.ru Title :DDR3 SO-DIMM_0


Engineer: Wish
ASUSTeK COMPUTER INC. NB6
Size Project Name Rev
Custom N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 14 of 95
5 4 3 2 1
5 4 3 2 1

Main Board

D D

C C

B B

A A

1bios.ru Title : DDR3_****


ASUSTeK COMPUTER INC. NB3 Engineer: Wish
Size Project Name Rev
C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 15 of 95
5 4 3 2 1
5 4 3 2 1

CH-A-5.2mm-BOT M_A_DQ[63:0] <4,14>


J1601A J1601B
<4,14> M_A_A[15:0]
5 M_A_DQ11
DQ0 M_A_DQ12
DQ1 7
M_A_A0 98 15 M_A_DQ15 <14,17,30> PM_EXTTS#0 198 2
M_A_A1 A0 DQ2 M_A_DQ14 EVENT# VSS1
97 A1 DQ3 17 VSS2 3
M_A_A2 96 4 M_A_DQ8 8
M_A_A3 A2 DQ4 M_A_DQ10 VSS3
95 A3 DQ5 6 207 GND1 VSS4 9
M_A_A4 M_A_DQ9
M_A_A5
92
91
A4 DQ6 16
18 M_A_DQ13
0 208 GND2 VSS5 13
14
M_A_A6 A5 DQ7 M_A_DQ1 VSS6
90 A6 DQ8 21 VSS7 19
M_A_A7 86 23 M_A_DQ0 77 20
M_A_A8 A7 DQ9 M_A_DQ3 NC1 VSS8
D
89 A8 DQ10 33 122 NC2 VSS9 25 D
M_A_A9 85 35 M_A_DQ6 26
M_A_A10 A9 DQ11 M_A_DQ5 VSS10
107 A10/AP DQ12 22 205 NP_NC1 VSS11 31
M_A_A11 84 24 M_A_DQ4 206 32
M_A_A12 A11 DQ13 M_A_DQ7 NP_NC2 VSS12
83 A12/BC# DQ14 34 1 VSS13 37
M_A_A13 119 36 M_A_DQ2 116 38
A13 DQ15 <4> M_ODT0 ODT0 VSS14
M_A_A14 80 39 M_A_DQ21 120 43
A14 DQ16 <4> M_ODT1 ODT1 VSS15
M_A_A15 78 41 M_A_DQ16 44
A15 DQ17 M_A_DQ22 VSS16
DQ18 51 VSS17 48
53 M_A_DQ18 110 49
DQ19 <4,14> M_A_RAS# RAS# VSS18
109 40 M_A_DQ20 30 54
<4,14> M_A_BS0 BA0 DQ20 <14,17> DRAMRST#_R RESET# VSS19
108 42 M_A_DQ17 SMBus Slave Address: A0H 55
<4,14> M_A_BS1 BA1 DQ21 VSS20
M_A_DQ23
<4,14> M_A_BS2 79 BA2 DQ22 50
52 M_A_DQ19
2 <4> M_CS#0 114
121
S#0 VSS21 60
61
DQ23 <4> M_CS#1 S#1 VSS22
57 M_A_DQ26 65
DQ24 M_A_DQ24 VSS23
DQ25 59 2 1 SL1605 197 SA0 VSS24 66
M_A_DQ25 0402
<4,14> M_A_CAS# 115 CAS# DQ26 67 201 SA1 VSS25 71
103 69 M_A_DQ29 72
<4> M_CLK_DDR#0 CK#0 DQ27 VSS26
104 56 M_A_DQ28 127
<4> M_CLK_DDR#1 CK#1 DQ28 VSS27
101 58 M_A_DQ30 202 128
<4> M_CLK_DDR0 CK0 DQ29 <14,17,28,29,53> SMB_CLK_S SCL VSS28
M_A_DQ31
<4> M_CLK_DDR1 102
73
CK1 DQ30 68
70 M_A_DQ27
3 <14,17,28,29,53> SMB_DAT_S 200 SDA VSS29 133
134
<4> M_CKE0 CKE0 DQ31 VSS30
74 129 M_A_DQ35 138
<4> M_CKE1 CKE1 DQ32 VSS31
131 M_A_DQ37 125 139
DQ33 M_A_DQ34 TEST VSS32
DQ34 141 VSS33 144
11 143 M_A_DQ39 145
DM0 DQ35 M_A_DQ32 VSS34
28 DM1 DQ36 130 75 VDD1 VSS35 150
46 132 M_A_DQ38 76 151
DM2 DQ37 M_A_DQ33 +1.5V VDD2 VSS36
63
136
DM3 DQ38 140
142 M_A_DQ36
4 81
82
VDD3 VSS37 155
156
DM4 DQ39 M_A_DQ44 VDD4 VSS38
153 DM5 DQ40 147 Layout Note: Place these caps near SO DIMM 0 87 VDD5 VSS39 161
170 149 M_A_DQ42 88 162
DM6 DQ41 M_A_DQ43 VDD6 VSS40
187 DM7 DQ42 157 93 VDD7 VSS41 167

1
159 M_A_DQ45 94 168
DQ43 M_A_DQ47 C1605 C1606 C1607 C1608 VDD8 VSS42
<4,14> M_A_DQS[7:0] DQ44 146 99 VDD9 VSS43 172
M_A_DQS1 12 148 M_A_DQ41 1UF/10V 1UF/10V 1UF/10V 1UF/10V 100 173

2
M_A_DQS0 DQS0 DQ45 M_A_DQ40 VDD10 VSS44
M_A_DQS2
29
47
DQS1 DQ46 158
160 M_A_DQ46
5 105
106
VDD11 VSS45 178
179
M_A_DQS3 DQS2 DQ47 M_A_DQ49 VDD12 VSS46
C 64 DQS3 DQ48 163 111 VDD13 VSS47 184 C
M_A_DQS4 137 165 M_A_DQ48 112 185
DQS4 DQ49 VDD14 VSS48

1
M_A_DQS5 154 175 M_A_DQ54 + 117 189
DQS5 DQ50 VDD15 VSS49

1
M_A_DQS6 171 177 M_A_DQ55 @ @ 118 190 +0.75VS
M_A_DQS7 DQS6 DQ51 M_A_DQ51 ESR=40mOhm/Ir=1.9A CE1603 C1610 C1611 C1612 C1613 C1620 VDD16 VSS50
188 DQS7 DQ52 164 123 VDD17 VSS51 195
166 M_A_DQ53 220UF/4V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 1UF/10V 124 196

2
DQ53 M_A_DQ50 VDD18 VSS52
<4,14> M_A_DQS#[7:0] DQ54 174 6
M_A_DQS#1 10 176 M_A_DQ52
M_A_DQS#0 DQS#0 DQ55 M_A_DQ62
27 DQS#1 DQ56 181 199 VDDSPD VTT1 203
M_A_DQS#2 45 183 M_A_DQ56 204
M_A_DQS#3 DQS#2 DQ57 M_A_DQ63 VTT2
62 DQS#3 DQ58 191
M_A_DQS#4 135 193 M_A_DQ59 126
M_A_DQS#5 DQS#4 DQ59 M_A_DQ61 VREFCA
152 DQS#5 DQ60 180 1 VREFDQ
M_A_DQS#6 169 182 M_A_DQ57 113 M_A_WE# <4,14>
M_A_DQS#7 DQS#6 DQ61 M_A_DQ58 +3VS WE#
186 DQS#7 DQ62 192
194 M_A_DQ60
7
DQ63

DDR3_DIMM_204P DDR3_DIMM_204P

1
C1614 C1615
12G025542044 2.2UF/10V 0.1UF/16V M_VREFCA_DIMM0

2
+0.75VS

1
C1624 C1623

1
2.2UF/10V 0.1UF/16V

2
C1616 C1617 C1618 C1619
1UF/10V 1UF/10V 1UF/10V 1UF/10V

2
M_VREFDQ_DIMM0

1
B B
C1622 C1625
2.2UF/10V 0.1UF/16V

A A

1bios.ru Title :DDR3 SO-DIMM_0


ASUSTeK COMPUTER INC. NB6 Engineer: Wish
Size Project Name Rev
C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 16 of 95
5 4 3 2 1
5 4 3 2 1

CH-B-9.2mm-BOT SWAP
M_B_DQ[63:0] <4>
<14,16,30> PM_EXTTS#0 198
J1701B

2
EVENT# VSS1
VSS2 3
VSS3 8
<4> M_B_A[15:0] J1701A 207 9
M_B_DQ2 GND1 VSS4
DQ0 5 208 GND2 VSS5 13
7 M_B_DQ5 14
M_B_A0 DQ1 M_B_DQ1 VSS6
98 A0 DQ2 15 VSS7 19
M_B_A1 97 17 M_B_DQ3 77 20
M_B_A2 A1 DQ3 M_B_DQ4 NC1 VSS8
96 A2 DQ4 4 SMBus Slave Address: A4H 122 NC2 VSS9 25
M_B_A3 95 6 M_B_DQ0 26
M_B_A4 A3 DQ5 M_B_DQ6 VSS10
92 A4 DQ6 16 205 NP_NC1 VSS11 31
M_B_A5 91 18 M_B_DQ7 206 32
D
M_B_A6 A5 DQ7 M_B_DQ13 +3VS NP_NC2 VSS12 D
90 A6 DQ8 21 VSS13 37
M_B_A7 86 23 M_B_DQ10 116 38
A7 DQ9 <4> M_ODT2 ODT0 VSS14
M_B_A8 89 33 M_B_DQ12 0930: add pull up R1701 120 43
A8 DQ10 <4> M_ODT3 ODT1 VSS15
M_B_A9 85 35 M_B_DQ15 44
M_B_A10 A9 DQ11 M_B_DQ9 VSS16
107 A10/AP DQ12 22 VSS17 48

1
M_B_A11 84 24 M_B_DQ14 110 49
A11 DQ13 <4> M_B_RAS# RAS# VSS18
M_B_A12 83 34 M_B_DQ8 R1701 30 54
A12/BC# DQ14 <14,16> DRAMRST#_R RESET# VSS19
M_B_A13 119 36 M_B_DQ11 10KOhm 55
M_B_A14 A13 DQ15 M_B_DQ16 VSS20
80 A14 DQ16 39 <4> M_CS#2 114 S#0 VSS21 60
M_B_A15 78 41 M_B_DQ20 121 61
<4> M_CS#3

2
A15 DQ17 M_B_DQ18 S#1 VSS22
DQ18 51 VSS23 65
53 M_B_DQ21 197 66
DQ19 M_B_DQ22 SA0 VSS24
<4> M_B_BS0 109 BA0 DQ20 40 201 SA1 VSS25 71
108 42 M_B_DQ17 72
<4> M_B_BS1 BA1 DQ21 VSS26
79 50 M_B_DQ23 127
<4> M_B_BS2 BA2 DQ22 VSS27
52 M_B_DQ19 202 128
DQ23 <14,16,28,29,53> SMB_CLK_S SCL VSS28
57 M_B_DQ26 200 133
DQ24 <14,16,28,29,53> SMB_DAT_S SDA VSS29
59 M_B_DQ27 134
DQ25 M_B_DQ29 VSS30
<4> M_B_CAS# 115 CAS# DQ26 67 VSS31 138
103 69 M_B_DQ25 125 139
<4> M_CLK_DDR#2 CK#0 DQ27 TEST VSS32
104 56 M_B_DQ30 144
<4> M_CLK_DDR#3 CK#1 DQ28 VSS33
101 58 M_B_DQ31 145
<4> M_CLK_DDR2 CK0 DQ29 VSS34
102 68 M_B_DQ28 75 150
<4> M_CLK_DDR3 CK1 DQ30 VDD1 VSS35
73 70 M_B_DQ24 76 151
<4> M_CKE2 CKE0 DQ31 +1.5V VDD2 VSS36
74 129 M_B_DQ32 81 155
<4> M_CKE3 CKE1 DQ32 VDD3 VSS37
131 M_B_DQ33 82 156
DQ33 M_B_DQ38 VDD4 VSS38
DQ34 141 Layout Note: Place these caps near SO DIMM 1 87 VDD5 VSS39 161
11 143 M_B_DQ37 88 162
DM0 DQ35 M_B_DQ34 VDD6 VSS40
28 DM1 DQ36 130 93 VDD7 VSS41 167
46 132 M_B_DQ36 94 168
DM2 DQ37 VDD8 VSS42

1
63 140 M_B_DQ39 99 172
DM3 DQ38 M_B_DQ35 C1705 C1706 C1707 C1708 VDD9 VSS43
136 DM4 DQ39 142 100 VDD10 VSS44 173
153 147 M_B_DQ44 1UF/10V 1UF/10V 1UF/10V 1UF/10V 105 178

2
DM5 DQ40 M_B_DQ42 VDD11 VSS45
170 DM6 DQ41 149 106 VDD12 VSS46 179
187 157 M_B_DQ45 111 184
DM7 DQ42 M_B_DQ41 VDD13 VSS47
DQ43 159 112 VDD14 VSS48 185
146 M_B_DQ47 117 189
<4> M_B_DQS[7:0] DQ44 VDD15 VSS49

1
C M_B_DQS0 12 148 M_B_DQ40 + 118 190 +0.75VS C
DQS0 DQ45 VDD16 VSS50

1
M_B_DQS1 29 158 M_B_DQ46 @ @ 123 195
M_B_DQS2 DQS1 DQ46 M_B_DQ43 CE1703 C1710 C1711 C1712 C1713 C1720 VDD17 VSS51
47 DQS2 DQ47 160 124 VDD18 VSS52 196
M_B_DQS3 64 163 M_B_DQ52 220UF/4V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 1UF/10V

2
M_B_DQS4 DQS3 DQ48 M_B_DQ49
137 DQS4 DQ49 165
M_B_DQS5 154 175 M_B_DQ54 199 203
M_B_DQS6 DQS5 DQ50 M_B_DQ55 ESR=40mOhm/Ir=1.9A VDDSPD VTT1
171 DQS6 DQ51 177 VTT2 204
M_B_DQS7 188 164 M_B_DQ51
DQS7 DQ52 M_B_DQ53
DQ53 166 126 VREFCA
174 M_B_DQ48 +3VS 1
<4> M_B_DQS#[7:0] DQ54 VREFDQ M_B_WE# <4>
M_B_DQS#0 10 176 M_B_DQ50 113
M_B_DQS#1 DQS#0 DQ55 M_B_DQ58 WE#
27 DQS#1 DQ56 181
M_B_DQS#2 45 183 M_B_DQ59
M_B_DQS#3 DQS#2 DQ57 M_B_DQ61
62 DQS#3 DQ58 191

1
M_B_DQS#4 135 193 M_B_DQ62 DDR3_DIMM_204P
M_B_DQS#5 DQS#4 DQ59 M_B_DQ60 C1714 C1715
152 DQS#5 DQ60 180
M_B_DQS#6 169 182 M_B_DQ56 2.2UF/10V 0.1UF/16V

2
M_B_DQS#7 DQS#6 DQ61 M_B_DQ63
186 DQS#7 DQ62 192
194 M_B_DQ57 M_VREFCA_DIMM1
DQ63

+0.75VS
DDR3_DIMM_204P

1
C1724 C1723
12G02555204B 2.2UF/10V 0.1UF/16V

1
C1716 C1717 C1718 C1719
M_VREFDQ_DIMM1 1UF/10V 1UF/10V 1UF/10V 1UF/10V

2
1

1
C1722 C1725
2.2UF/10V 0.1UF/16V

2
B B

A A

1bios.ru Title :DDR3 SO-DIMM_1


ASUSTeK COMPUTER INC. NB6 Engineer: Wish
Size Project Name Rev
C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 17 of 95
5 4 3 2 1
5 4 3 2 1

+1.5V For DDR3_VREF command & address.

2
R1801
1KOhm
1% M_VREFDQ_DIMM0

1
2

1
R1802 C1805
D D
1KOhm 0.1UF/16V
1%

2
1
+1.5V

2
R1803
1KOhm M_VREFCA_DIMM0
1%
1
2

1
R1804 C1804
1KOhm 0.1UF/16V
1% 2
1

M1
M1: Fixed SO-DIMM VREF_DQ
(Default Stuffing)

C C

+1.5V
2

R1818
1KOhm
1% M_VREFCA_DIMM1
1
2

R1820 C1806
1KOhm 0.1UF/16V
1%
2
1

+1.5V
2

B B
R1821
1KOhm
1% M_VREFDQ_DIMM1
1
2

R1819 C1807
1KOhm 0.1UF/16V
1%
2
1

A A

1bios.ru Title : DIM_CA/DQ Voltage


ASUSTeK COMPUTER INC. NB3 Engineer: Wish
Size Project Name Rev
C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 18 of 95
5 4 3 2 1
5 4 3 2 1

Main Board

D D

C C

B B

A A

1bios.ru Title : CPU_VID Controller_*


ASUSTeK COMPUTER INC. NB3 Engineer: Wish
Size Project Name Rev
C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 19 of 95
5 4 3 2 1
5 4 3 2 1

RTC battery
BATT HOLDER @ IO BOARD 2

+3VA
PCH P/N : 02G010027100
+RTCBAT +VCC_RTC
D2001
1
+VCC_RTC 3
2 1 +RTC_BAT 2

1
R2001 1KOhm 5% C2001
2 1 BAT54CW 1UF/10V

1
@

2
R2002 2 1 3 BAT1
20KOhm 4 BATT_HOLDER_2P

1
D D
1% GND C2005 GND

1
JRST2001 18PF/50V X2001

1
CMOS Settings JRST2001

2
1
C2002 SGL_JUMP 2 32.768Khz R2006

2
1UF/6.3V @ 10MOhm
Clear CMOS Shunt 5% GND U2001A
3

2
Open

2
Keep CMOS (Default)
C2006 X1_RTC A20 RTCX1 FWH0 / LAD0 C38 LPC_AD0 <30,44>
18PF/50V SL2001 A38

LPC
LPC_AD1 <30,44>

4
X2RTC X2_RTC FWH1 / LAD1
2 1 2 1 C20 RTCX2 FWH2 / LAD2 B37 LPC_AD2 <30,44>
GND GND 0402
TPM Settings JRST2002 FWH3 / LAD3 C37 LPC_AD3 <30,44>
GND RTCRST# D20
@ RTCRST#
Clear ME RTC Shunt FWH4 / LFRAME# D36 LPC_FRAME# <30,44>
2 1 SRTCRST# G22
Registers R2009 0Ohm SRTCRST# PCH_DRQ#0 T2005
E36 1

RTC
SM_INTRUDER# LDRQ0#
Keep ME RTC Open 1 2 K22 INTRUDER# LDRQ1# / GPIO23 K36
R2004 1MOhm 5%
Registers (Default) 2 1 1 2 INTVRMEN C17 V5
+VCC_RTC INTVRMEN SERIRQ INT_SERIRQ <30>
R2007 330KOhm 5%

1
R2003
20KOhm R2018 AM3 SATA_RXN0 <51>
SATA0RXN

1
1% 330KOhm ACZ_BCLK N34 AM1 SATA_RXP0 <51>
HDA_BCLK SATA0RXP

SATA 6G
JRST2002 Stuff For Moff 5% @ AP7

1
SATA0TXN SATA_TXN0 <51>
1

C2003 SGL_JUMP ACZ_SYNC L34 AP5 SATA_TXP0 <51>

2
HDA_SYNC SATA0TXP
2
1UF/6.3V @
PCH_SPKR T10 AM10 SATA_RXN1 <51>
2

GND SPKR SATA1RXN


SATA1RXP AM8 SATA_RXP1 <51>
ACZ_RST# K34 AP11
HDA_RST# SATA1TXN SATA_TXN1 <51>
SATA1TXP AP10 SATA_TXP1 <51>
GND GND <36> ACZ_SDIN0_AUD E34 AD7 SATA_RXN2 <51>
HDA_SDIN0 SATA2RXN
SATA2RXP AD5 SATA_RXP2 <51>
T2007 1ACZ_SDIN1_MDC G34 HDA_SDIN1 SATA2TXN AH5 SATA_TXN2 <51>
SATA2TXP AH4 SATA_TXP2 <51> SATA 0 Main HD
T2004 1ACZ_SDIN2 C34

IHDA
HDA_SDIN2
HDA_SYNC(On-Die PLL VR voltage select): reserve for power noise SATA3RXN AB8 SATA 1 2nd HD
Rising edge of RSMRST# pin A34 HDA_SDIN3 SATA3RXP AB10
SATA3TXN AF3 SATA 2 ODD
C High:1.5V, Low:1.8V (default) ACZ_SDIN0_AUD AF1 C
ACZ_SDOUT SATA3TXP
A36 SATA 3

SATA
HDA_SDO
SATA4RXN Y7
SATA4RXP Y5 SATA 4

1
+3VSUS_HDA C2007 T2018 1 HDA_DOCK_EN# C36 AD3
15PF/50V HDA_DOCK_EN# / GPIO33 SATA4TXN
SATA4TXP AD1 SATA 5
1 2 ACZ_SYNC @ T2017 1 HDA_DOCK_RST# N32

2
R2027 1KOhm HDA_DOCK_RST# / GPIO13
SATA5RXN Y3
SATA5RXP Y1
SATA5TXN AB3
stuff R2027 for 1.5V +VCCAFDI <67> PCH_JTAG_TCK PCH_JTAG_TCK J3 AB1
ACZ_BCLK_AUD JTAG_TCK SATA5TXP
PCH_JTAG_TMS H7 Y11

JTAG
<7,67> PCH_JTAG_TMS JTAG_TMS SATAICOMPO

<7,67> PCH_JTAG_TDI PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2 +VTT_SATA


JTAG_TDI SATAICOMPI
1

R2021 37.4Ohm 1%
C2008 <7,67> PCH_JTAG_TDO PCH_JTAG_TDO H1
0.1UF/16V /EMI JTAG_TDO
AB12
2

SATA3RCOMPO
AB13 SATA3_COMP 1 2 +VTT_SATA3
+3VS GND SATA3COMPI R2022 49.9Ohm 1%

<28> SPI_CLK T3 AH1 RBIAS_SATA3 1 2


SPI_CLK SATA3RBIAS R2023 750Ohm 1%
<28> SPI_CS#0 2 1 SB_SPICS0# Y14
R2010 15Ohm 5% SPI_CS0# GND
1 SB_SPICS1# T1

SPI
SPI_CS1#
T2003 SATALED# P3 SATA_LED# <56>
SATALED#: O.D. 6mA
2

R2028 U2002 <28> SPI_SI V4 V14 SATA0GP


200Ohm SPI_MOSI SATA0GP / GPIO21
5 VCC NC 1 <28> SPI_SO U3 SPI_MISO SATA1GP / GPIO19 P1 SATA1GP <24>
@ A 2 ACZ_SYNC
1

ACZ_SYNC_AUD 4 Y GND 3
COUGARPOINT-H
Boot BIOS Strap:GNT1#(BBS0), SATA1GP(BBS1)
74LVC1G07GW
@
B +3VS_VCC3_3 B
GND

HDA_SYNC signal also serves as a strap for selecting VRM voltage to the PCH. The

2
strap is sampled on the rising edge of RSMRST# signal. Due to potential leakage
R2011
on the codec (path to GND), the strap may not be able to achive the Vihmin at PCH 10KOhm Intel Anti-Theft
input.Therefore, platform may need to isolate this signal from the codec during @ Technology:
the strap phase. Enable=High
1

SPI_SI

ACZ_SDOUT:(1) PCH: Internal PD 20k


ohm, VIL=0.35V, VIH=0.65~3.3V (2) Boundary Scan TP (PCH)
ALC269:VIL<0.35*3.3V, VIH>0.65*3.3V
0930: Maunt for ME firmware update PCH_JTAG_TCK 1 T2008

HD Audio +3VSUS_ORG
JTAG For PU/PD PCH_JTAG_TMS

PCH_JTAG_TDI
1 T2009

T2010
1
2

+3VS_VCC3_3 PCH_JTAG_TDO 1 T2011


<36> ACZ_BCLK_AUD R2019 1 2 33Ohm ACZ_BCLK R2008
<36> ACZ_SYNC_AUD R2024 1 2 33Ohm ACZ_SYNC 1KOhm
R2025 1 2 33Ohm ACZ_RST# +3VSUS_ORG +3VSUS_ORG +3VSUS_ORG SATA0GP 3 RN2002B
<36,37> ACZ_RST#_AUD 10KOHM4
<36> ACZ_SDOUT_AUD R2026 1 2 33Ohm ACZ_SDOUT N/A RTCRST# 1 T2013
1

ACZ_SDOUT INT_SERIRQ 5 RN2002C


10KOHM6
2

R2012 R2014 R2016 INTVRMEN 1 T2015


1

1 RN2002A
200Ohm 200Ohm 200Ohm 10KOHM2
R2043 1% 1% 1% SRTCRST# 1 T2016
33Ohm
1

SATA_LED# 7 RN2002D
A
10KOHM8 A
PCH_JTAG_TMS PCH_JTAG_TCK
2

PCH_JTAG_TDI

1bios.ru
PCH_JTAG_TDO
3

3 PCH_SPKR 1 2 @
D
Q2001 R2044 1KOhm
2

<30> PCH_SPI_OV 11 2N7002ET1G R2013 R2015 R2017 R2020 SPKR:No Reboot strap
G 100Ohm 100Ohm 100Ohm 51Ohm
2 S 1% 1% 1%
2

TitlePCH_IBEX(1)SATA,IHDA,RTC,LPC
:
1

GPIO33 is a signal used for Flash


Descriptor security Override/ME debug mode GND GND GND GND GND ASUSTeK COMPUTER INC. Engineer: Wish
HIGH : Disable, LOW : Enable DPDG(P.28):51Ohm, CRB:4.7KOhm Size Project Name Rev

stuff ??
C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 20 of 95
5 4 3 2 1
5 4 3 2 1

If support PCIE 3.0, pls change all 0.1uF to 0.22uF


U2001B
+3VSUS_ORG
PCIE1: TV <54> PCIE_RXN1_TV BG34 PERN1
BJ34 E12 Please refer to DG V0.7 P245
<54> PCIE_RXP1_TV PERP1 SMBALERT# / GPIO11 EXT_SCI# <30>
<54> PCIE_TXN1_C 0.1UF/16V 2 1 CX2101 PCIE_TXN1 AV32
0.1UF/16V 2 PCIE_TXP1 PETN1
<54> PCIE_TXP1_C 1 CX2102 AU32 PETP1 SMBCLK H14 SCL_3A <28>
PCHHOT# 1 RN2101A
10KOHM2
PCIE2: WLAN <53> PCIE_RXN2_WLAN BE34 PERN2 SMBDATA C9 SDA_3A <28>
BF34 EXT_SCI# 3 RN2101B
<53> PCIE_RXP2_WLAN PERP2 10KOHM4
<53> PCIE_TXN2_C 0.1UF/16V 2 1 CX2103 PCIE_TXN2 BB32
0.1UF/16V 2 PCIE_TXP2 PETN2
1 CX2104 AY32 5 10KOHM6
RN2101C

SMBUS
<53> PCIE_TXP2_C PETP2
A12 DRAMRST_PCH DRAMRST_PCH <4>
SML0ALERT# / GPIO60 CLK_PEGB_REQ# RN2101D
BG36 PERN3 7 10KOHM8
BJ36 C8 SML0_CLK 1 T2106
D PERP3 SML0CLK SDA_3A RN2102A D
AV34 PETN3 1 2.2KOhm2
AU34 G12 SML0_DAT 1 T2107
PETP3 SML0DATA RN2102B
3 2.2KOhm4
PCIE4: USB3.0 <68> PCIE_RXN4_USB3 BF36 PERN4
BE36 SCL_3A 5 RN2102C
<68> PCIE_RXP4_USB3 PERP4 2.2KOhm6
<68> PCIE_TXN4_C 0.1UF/16V 2 1 CX2107 PCIE_TXN4 AY34 C13 PCHHOT# 1 T2111
0.1UF/16V 2 PCIE_TXP4 PETN4 SML1ALERT# / PCHHOT# / GPIO74 DRAMRST_PCH
<68> PCIE_TXP4_C 1 CX2108 BB34 PETP4 7 2.2KOhm8
RN2102D
E14 SML1_CLK RC Delay Time

PCI-E*
SML1CLK / GPIO58 SML1_CLK <28>
BG37 PERN5
To EC
BH37 M16 SML1_DAT SML1_CLK 5 RN2103C
PERP5 SML1DATA / GPIO75 SML1_DAT <28> 2.2KOhm6
AY36 PETN5
BB36 SML1_DAT 7 RN2103D
PETP5 2.2KOhm8

PCIE6: LAN <33> PCIE_RXN6_GLAN BJ38 PERN6


BG38 SML0_DAT 1 RN2103A
<33> PCIE_RXP6_GLAN 2.2KOhm2

Controller
0.1UF/16V 2 PCIE_TXN6 PERP6 CL_CLK
<33> PCIE_TXN6_C 1 CX2111 AU36 PETN6 CL_CLK1 M7 1 T2108
0.1UF/16V 2 1 CX2112 PCIE_TXP6 AV36 SML0_CLK 3 RN2103B
<33> PCIE_TXP6_C PETP6 2.2KOhm4
PCH CLKREQ Setting:

Link
BG40 T11 CL_DAT 1 T2109
PERN7 CL_DATA1 +3VSUS_ORG +3VS_VCC3_3
BJ40 PERP7
AY40 PETN7
BB40 P10 CL_RST# 1 T2110
PETP7 CL_RST1# RN2105A
1 10KOHM2
BE38 CLK_REQ7# 3 RN2105B
PERN8 10KOHM4
BC38 CLK_REQ6# 5 RN2105C
PERP8 10KOHM6
AW38 CLK_REQ2# 7 RN2105D
PETN8 10KOHM8
AY38 PETP8
M10 CLK_PEGA_REQ# +3VSUS_ORG
CLK_PCH_SRC0_N PEG_A_CLKRQ# / GPIO47 +3VSUS_ORG
<54> CLK_PCIE_TV#_PCH 2 1 SL2101 Y40 CLKOUT_PCIE0N
0402 CLK_PCH_SRC0_P CLK_REQ4#
<54> CLK_PCIE_TV_PCH 2 1 SL2102 Y39 CLKOUT_PCIE0P 1 10KOHM2
RN2104A
0402 CLK_PCIE_PEG#_PCH_R CLK_REQ5#
AB37 2 1 SL2126 CLK_PCIE_PEG#_PCH <70> 3 10KOHM4
RN2104B

CLOCKS
CLK_REQ0# CLKOUT_PEG_A_N CLK_PCIE_PEG_PCH_R 0402
<54> CLKREQ0_TV# 2 1 SL2103 J2 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AB38 2 1 SL2125 CLK_PCIE_PEG_PCH <70>
0402 0402

<53> CLK_PCIE_WLAN#_PCH 2 1 SL2104 CLK_PCH_SRC1_N AB49 AV22 CLK_CPU_BCLK#_PCH 2 1 SL2127


0402 CLKOUT_PCIE1N CLKOUT_DMI_N 0402 CLK_CPU_BCLK# <3> +3VSUS_ORG +3VS_VCC3_3
<53> CLK_PCIE_WLAN_PCH 2 1 SL2105 CLK_PCH_SRC1_P AB47 AU22 CLK_CPU_BCLK_PCH 2 1 SL2128
0402 CLKOUT_PCIE1P CLKOUT_DMI_P 0402 CLK_CPU_BCLK <3>
C C
<53> CLKREQ1_WLAN# 2 1 SL2106 CLK_REQ1# M1 CLK_REQ1# 610KOHM 5 RN2104C
0402 PCIECLKRQ1# / GPIO18 CLK_DREF#_PCH R2118 1 @ CLK_REQ0#
CLKOUT_DP_N AM12 2 0Ohm CLK_DREF# <3> 810KOHM 7 RN2104D
AM13 CLK_DREF_PCH R2119 1 @ 2 0Ohm
CLKOUT_DP_P CLK_DREF <3>
AA48 CLKOUT_PCIE2N
AA47 CLKOUT_PCIE2P
BF18 CLK_DMI#_PCH R2116 1 @ 2 0Ohm CLK_DMI# <29>
T2123 CLK_REQ2# CLKIN_DMI_N CLK_DMI_PCH R2117 1 @ CLK_REQ0#
1 V10 PCIECLKRQ2# / GPIO20 CLKIN_DMI_P BE18 2 0Ohm CLK_DMI <29> @ 1 10KOHM2
RN2106A
CLK_REQ4# @ 3 RN2106B
10KOHM4
CLK_REQ1# @ 5 RN2106C
10KOHM6
2 1 SL2107 CLK_PCH_SRC3_N Y37 BJ30 CLK_GND# CLK_REQ5# @ 7 RN2106D
<68> CLK_PCIE_USB3#_PCH 0402 CLKOUT_PCIE3N CLKIN_GND1_N 10KOHM8
<68> CLK_PCIE_USB3_PCH 2 1 SL2108 CLK_PCH_SRC3_P Y36 BG30 CLK_GND
0402 CLKOUT_PCIE3P CLKIN_GND1_P
T2125 1 CLK_REQ3#_USB3 A8 PCIECLKRQ3# / GPIO25 CLK_DOT96#_PCH R2111 1 @ CLK_PEGA_REQ#
CLKIN_DOT_96N G24 2 0Ohm CLK_DOT96# <29> R2132 1 2 10KOhm @
E24 CLK_DOT96_PCH R2112 1 @ 2 0Ohm CLK_DOT96 <29>
CLKIN_DOT_96P
Y43 CLKOUT_PCIE4N C2108C210910pF
Y45 GND
CLKOUT_PCIE4P CLK_SATA#_PCH R2113 1 @
CLKIN_SATA_N AK7 2 0Ohm CLK_SATA# <29>
T2124 1 CLK_REQ4# L12 AK5 CLK_SATA_PCH R2115 1 @ 2 0Ohm CLK_SATA <29>
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P +3VSUS_ORG

<33> CLK_PCIE_GLAN#_N_PCH 2 1 SL2110 CLK_PCH_SRC5_N V45 K45 CLK_ICH14_PCH R2114 1 @ 2 0Ohm CLK_ICH14 <29> CLK_REQ3#_USB3 R2124 1 2 10KOhm
0402 CLK_PCH_SRC5_P CLKOUT_PCIE5N REFCLK14IN X1_25IN_XTAL
<33> CLK_PCIE_GLAN_P_PCH 2 1 SL2111 V46 CLKOUT_PCIE5P 1 2
0402 T2118 C2108 10PF/50V
1

3
<33> CLKREQ_GLAN# 2 1 SL2112 CLK_REQ5# L14 H45 CLK_PCI_FB CLK_PCI_FB <24> R2135 1 2 10KOhm
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK

2
0402
R2107 X2101 4 @
AB42 V47 X1_25IN 1MOhm 25Mhz
CLKOUT_PEG_B_N XTAL25_IN X2_25OUT 5% GND
AB40 CLKOUT_PEG_B_P XTAL25_OUT V49 2

1
T2115 1 CLK_PEGB_REQ# E6 PEG_B_CLKRQ# / GPIO56

1
XCLK_RCOMP Y47 XCLK_COMP 1 2 +VCCDIFFCLKN 2 1 X225OUT 1 2
R2101 90.9Ohm SL2123 0402 C2109 10PF/50V
V40 CLKOUT_PCIE6N
V42 1%
CLKOUT_PCIE6P GND
R2108: For Xtal measurement
T2126 1 CLK_REQ6# T13
B PCIECLKRQ6# / GPIO45 B

V38 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 K43 CLK_OUT0 1 T2119


V37 CLKOUT_PCIE7P
F47 CLK_OUT1 1 T2121
FLEX CLOCKS

T2117 CLK_REQ7# CLKOUTFLEX1 / GPIO65


1 K12 PCIECLKRQ7# / GPIO46
H47 CLK_OUT2 1 T2120
CLKOUTFLEX2 / GPIO66
<7> CLK_ITP_BCLK_PCH# AK14 CLKOUT_ITPXDP_N
<7> CLK_ITP_BCLK_PCH AK13 CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 K49 CLK_OUT3 1 2 CLK_USB48 <42>
R2103 33Ohm

1
COUGARPOINT-H C2107
10PF/50V
@
Check BIOS 2
Programmable output clock
GND

CLK_GND# 1 2
CLK_GND R2130 1 10KOhm
2
R2131 10KOhm

CLK_DMI#_PCH 1 2
CLK_DMI_PCH R2123 1 10KOhm
2
+3VSUS_ORG R2125 10KOhm

CLK_DOT96#_PCH 1 2
CLK_DOT96_PCH R2126 1 10KOhm
2

2
+3VSG R2127 10KOhm
R2134
10KOhm CLK_SATA#_PCH 1 2
CLK_SATA_PCH R2128 1 10KOhm
2
1

R2129 10KOhm
1

1
G

R2133
CLKREQ_PEG#_R CLK_PEGA_REQ#
2 S

<70> CLKREQ_PEG# 2 3 2 1
D

CLK_ICH14_PCH 1 2
0Ohm @ R2122 10KOhm
2N7002 @
3

A Q2104 3 A
D
stuff:Integrated clock mode
Q2101

1bios.ru
11
2N7002 DGPU_PWROK <25,70>
G
S 2
GND
2

GND

Title : PCH_IBEX(2)_PCIE,CLK,SMB,PEG

ASUSTeK COMPUTER INC. Engineer: Wish


Size Project Name Rev
C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 21 of 95
5 4 3 2 1
5 4 3 2 1

FDI_TXN[7:0] <3>
U2001C
D D

<3> DMI_RXN0 BC24 BJ14 FDI_TXN0


DMI0RXN FDI_RXN0 FDI_TXN1
<3> DMI_RXN1 BE20 DMI1RXN FDI_RXN1 AY14
<3> DMI_RXN2 BG18 BE14 FDI_TXN2 DSWVRMEN:
DMI2RXN FDI_RXN2 FDI_TXN3
<3> DMI_RXN3 BG20 DMI3RXN FDI_RXN3 BH13 High -> DSW On-Die VR Enable
BC12 FDI_TXN4 Low -> DSW On-Die VR disable
FDI_RXN4 FDI_TXN5
<3> DMI_RXP0 BE24 DMI0RXP FDI_RXN5 BJ12
<3> DMI_RXP1 BC20 BG10 FDI_TXN6 R2203
DMI1RXP FDI_RXN6 FDI_TXN7 330KOhm
<3> DMI_RXP2 BJ18 DMI2RXP FDI_RXN7 BG9 FDI_TXP[7:0] <3>
<3> DMI_RXP3 BJ20 5%
DMI3RXP FDI_TXP0 DSWVRMEN
FDI_RXP0 BG14 2 1 +VCC_RTC
+VTT_PCH_VCCIO AW24 BB14 FDI_TXP1 DPWROK:
<3> DMI_TXN0 DMI0TXN FDI_RXP1
<3> DMI_TXN1 AW20 BF14 FDI_TXP2 This input is tied
DMI1TXN FDI_RXP2

1
<3> DMI_TXN2 BB18 BG13 FDI_TXP3 together with RSMRST#
DMI2TXN FDI_RXP3 FDI_TXP4 R2204
AV18 BE12

DMI
FDI
<3> DMI_TXN3 DMI3TXN FDI_RXP4 in platforms that do not
BG12 FDI_TXP5 330KOhm
FDI_RXP5

2
SUSACK#: AY24 BJ10 FDI_TXP6 5% @ support DeepSx
<3> DMI_TXP0 DMI0TXP FDI_RXP6
SUSACK# and SUSWARN# can be tied together R2202 <3> DMI_TXP1 AY20 BH9 FDI_TXP7

2
DMI1TXP FDI_RXP7
if EC does not want to involve in handshake 49.9Ohm <3> DMI_TXP2 AY18 DMI2TXP
mechanism for the Deep Sleep state entry and exit. <3> DMI_TXP3 AU18 DMI3TXP
VCCDSW stable to DPWROK
1% AW16 GND assertion is 10ms (min)
FDI_INT <3>

1
FDI_INT
BJ24 DMI_ZCOMP FDI_FSYNC0 AV12 FDI_FSYNC0 <3>
DMI_COMP BG25 BC10
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <3>
1 2 BH21 DMI2RBIAS FDI_LSYNC0 AV14 FDI_LSYNC0 <3>
R2201 750Ohm
1% BB10
FDI_LSYNC1 FDI_LSYNC1 <3>
GND

A18 DSWVRMEN
ME_SusPwrDnAck_R DSWVRMEN
2 1

System Power Management


R2208 0Ohm
PM_SUSACK# C12 E22 DPWROK_R 2 1PM_RSMRST#_PCH
SUSACK# DPWROK R2221 0Ohm
C @ C
<3,7,67> XDP_DBRESET# 2 1 SYS_RESET# K3 B9 WAKE# 1 2 SL2206 PCIE_WAKE# <33,53,68>
R2212 0Ohm SYS_RESET# WAKE# 0402

<7> PM_SYSPWROK_PCH PM_SYSPWROK_PCH P12 N3 PM_CLKRUN# Delete R2222, R2228, U2201, R2230,
SYS_PWROK CLKRUN# / GPIO32 PM_CLKRUN# <30>
@ R2233, C2201 and D2203, Deeper
<29,30,58,80> ALL_SYSTEM_PWRGD 2 1 PM_PWROK_PCH L22 G8 PM_SUS_STAT# 1 T2214 sleeper
R2223 0Ohm PWROK SUS_STAT# / GPIO61
ASW Power well stable for at least 1ms 2 1
before platform logic asserts APWROK R2213 0Ohm APWROK_R L10 N14 SUS_CLK# 1 T2213
APWROK SUSCLK / GPIO62
T2203 1
Have Pull up Res. in CPU side <3> H_DRAM_PWRGD B13 D10 SLP_S5# 1 T2205
DRAMPWROK SLP_S5# / GPIO63
APWROK:
For platform not supporting iAMT PM_RSMRST#_PCH C21 H4 SLP_S4#_R 1 2 SL2204
RSMRST# SLP_S4# 0402 PM_SUSC# <30>
it can be connected to PWROK.
<30> ME_SUSPWRDNACK 2 1 ME_SusPwrDnAck_RK16 F4 SLP_S3#_R 1 2 SL2205
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SUSB# <30>
SL2212 0402 0402
SUSPWRDNACK (PCH to EC): <7,67> PM_PWRBTN#_R
This pin requires a pull-up to +3VSUS. <30> PM_PWRBTN# 2 1 E20 G10 SLP_A# 1 T2206
SL2203 0402 PWRBTN# SLP_A#
Platforms are not expected to use this
T2204 1
signal when the PCH's Deep S4/S5 feature is used. ME_AC_PRESENT_PCH H20 SLP_SUS#_R R2224
ACPRESENT / GPIO31 SLP_SUS# G16 2 1 0Ohm PM_SLP_SUS# <30>

T2201 1 PM_BATLOW# E10 AP14


BATLOW# / GPIO72 PMSYNCH PM_SYNC# <3>
SUSWARN# (PCH to EC): PMSYNCH is Low in C6/C7 states only
This pin aserts low when PCH is planning
to enter the DeepSx power state and remove T2202 1 PM_RI# A10 K14 SLP_LAN# 1 T2207
RI# SLP_LAN# / GPIO29
Suspend power(using SLP_SUS#)
COUGARPOINT-H

Entry Into Deep S4/S5 reserve for powr noise


A combination of condition is required for entry into Deep S4/S5
B
All of the following must be met: CHECK PULL-UP OR DOWN B

-Intel ME in Moff. WAKE#


-AND either "a" or "b"(EDS R0.7v1 p.186).

1
C2201
0.01UF/16V
+3VSUS_ORG +VCCPDSW @

2
Power failure solution (S0-->G3,S5-->G3):
2 R2231

2 R2216

2 R2215

2 R2214

09'MoW04:
PM_PWROK,PM_RSMRST#: previous platform solution.
Optional if ME FW is
ME_PWROK,ME_AC_PRESENT: reserved for test. Ignition FW
10KOhm1

10KOhm1

10KOhm1

10KOhm1

For PU/PD CRB:8.2K Ohm


Boundary Scan TP (PCH)
10KOhm 2 1 R2234 @ @ @ PM_SYSPWROK_PCH +3VS_VCC3_3
<30> PM_SYSPWROK

<30> PM_PWROK 10KOhm 2 1 R2217 PM_PWROK_PCH


+3VSUS_ORG PM_CLKRUN# 1 2 PM_RSMRST#_PCH 1 T2217
R2205 10KOhm
<30,67> PM_RSMRST# 10KOhm 2 1 R2218 PM_RSMRST#_PCH PM_PWROK_PCH 1 T2211
PM_RI# 1 2
@ R2209 10KOhm APWROK_R 1 T2215
10KOhm 2 1 R2219 ME_AC_PRESENT_PCH Internal PU 15K to 40K Strap high is GPIO mode
<30> ME_AC_PRESENT
1SS355PT 1 2 D2207 PCIE_WAKE# 1 2 SYS_RESET# 2 1 PM_SYSPWROK_PCH 1 T2216
D2207: Prevent EC drive hign, R2226 10KOhm 10KOhm R2210
SUS_PWRGD sink low in S5-->G3. XDP_DBRESET# 2 1
1

<29,30,58,80> ALL_SYSTEM_PWRGD 1 ME_SusPwrDnAck 1 2 10KOhm R2211


A 3 R2227 10KOhm A
R2229 R2220 <30,58,81> SUS_PWRGD 2
10KOhm 10KOhm PM_BATLOW# 1 2

1bios.ru
BAT54AW R2225 10KOhm
2

D2201 DG:Pull-up 10K Ohm to 3.3V(Core)


SLP_LAN# 1 2
D2204 R2206 10KOhm CRB:NO Pull-up or down resistor
1
DPWROK_R 3
GND GND 2
BAT54CW

D2202
Title : PCH_IBEX(3)_FDI,DMI,SYS PWR
1 ASUSTeK COMPUTER INC. Engineer: Wish
<30,58,81> SUS_PWRGD 3
2 Size Project Name Rev
BAT54CW C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 22 of 95
5 4 3 2 1
5 4 3 2 1

PORT STRAP ENABLE PORT DISABLE PORT


LVDS L_DDC_DATA
PORT B SDVO_CTRLDATA
Pull up to 3.3(V) NC
PORT C DDPC_CTRLDATA with 2.2k Ohm
PORT D DDPD_CTRLDATA
DG P.105,168
D D

+3VS_VCC3_3

L_CTRL_CLK 1 RN2303A U2001D


2.2KOHM2
<45> LCD_BACKEN J47 L_BKLTEN SDVO_TVCLKINN AP43
<45> LCD_VDD_EN M45 L_VDD_EN SDVO_TVCLKINP AP45
L_CTRL_DATA 3 RN2303B
2.2KOHM4
<45> L_BKLTCTL_PCH P45 L_BKLTCTL SDVO_STALLN AM42
SDVO_STALLP AM40
<45> EDID_CLK_PCH T40 L_DDC_CLK
<45> EDID_DAT_PCH K47 L_DDC_DATA SDVO_INTN AP39
SDVO_INTP AP40
T2301 1 L_CTRL_CLK T45
T2302 L_CTRL_DATA L_CTRL_CLK
1 P39 L_CTRL_DATA
R2301 2 1% 1 2.37KOHM AF37 P38
R2302 LVD_IBG SDVO_CTRLCLK
2 1 0Ohm AF36 LVD_VBG SDVO_CTRLDATA M39
@
AE48 LVD_VREFH
AE47 LVD_VREFL DDPB_AUXN AT49
DDPB_AUXP AT47
GND AT40
DDPB_HPD
AK39

LVDS
<45> LVDS_LCLKN_PCH LVDSA_CLK#
<45> LVDS_LCLKP_PCH AK40 LVDSA_CLK DDPB_0N AV42 PULL UP 2.2KOhm @ CONNECTOR SIDE
DDPB_0P AV40
CRT_BLUE_R <45> LVDS_L0N_PCH AN48 AV45
LVDSA_DATA#0 DDPB_1N

Digital Display Interface


<45> LVDS_L1N_PCH AM47 LVDSA_DATA#1 DDPB_1P AV46
<45> LVDS_L2N_PCH AK47 LVDSA_DATA#2 DDPB_2N AU48
CRT_GREEN_R AJ48 AU47
LVDSA_DATA#3 DDPB_2P
DDPB_3N AV47
CRT_RED_R <45> LVDS_L0P_PCH AN47 AV49
LVDSA_DATA0 DDPB_3P
C <45> LVDS_L1P_PCH AM49 LVDSA_DATA1
C
<45> LVDS_L2P_PCH AK49 LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46 HDMI_CLK <48>
DDPC_CTRLDATA P42 HDMI_DAT <48>
1

C2301 C2302 C2303


<45> LVDS_UCLKN_PCH AF40 LVDSB_CLK#
5PF/50V 5PF/50V 5PF/50V <45> LVDS_UCLKP_PCH AF39 AP47 1 T2305
2

@ @ @ LVDSB_CLK DDPC_AUXN T2306


DDPC_AUXP AP49 1
<45> LVDS_U0N_PCH AH45 LVDSB_DATA#0 DDPC_HPD AT38 HDMI_HPD <25,48>
<45> LVDS_U1N_PCH AH47 LVDSB_DATA#1
<45> LVDS_U2N_PCH AF49 AY47 TMDS_TXN2_PCH
LVDSB_DATA#2 DDPC_0N HDMI_TX2N <48>
AF45 AY49 TMDS_TXP2_PCH
LVDSB_DATA#3 DDPC_0P HDMI_TX2P <48>
GND GND GND AY43 TMDS_TXN1_PCH
DDPC_1N HDMI_TX1N <48>
<45> LVDS_U0P_PCH AH43 AY45 TMDS_TXP1_PCH DG P.106
LVDSB_DATA0 DDPC_1P HDMI_TX1P <48>
<45> LVDS_U1P_PCH AH49 BA47 TMDS_TXN0_PCH
LVDSB_DATA1 DDPC_2N HDMI_TX0N <48>
<45> LVDS_U2P_PCH AF47 BA48 TMDS_TXP0_PCH
LVDSB_DATA2 DDPC_2P HDMI_TX0P <48>
AF43 BB47 TMDS_CLKN_PCH
LVDSB_DATA3 DDPC_3N HDMI_CLKN <48>
BB49 TMDS_CLKP_PCH
DDPC_3P HDMI_CLKP <48>

<46> CRT_BLUE JP2301 1 2 SHORT_PIN @


CRT_BLUE_R N48 M43
JP2302 1 CRT_GREEN_R CRT_BLUE DDPD_CTRLCLK
<46> CRT_GREEN 2 SHORT_PIN @ P49 CRT_GREEN DDPD_CTRLDATA M36
CRT_RED_R T49
JP2303 1 CRT_RED
<46> CRT_RED 2 SHORT_PIN @ PULL UP 2.2KOhm@CONNECTOR SIDE
R2307

R2308

R2309

AT45

CRT
DDPD_AUXN
<46> DDC_CLK_PCH T39 CRT_DDC_CLK DDPD_AUXP AT43
<46> DDC_DATA_PCH M40 CRT_DDC_DATA DDPD_HPD BH41
1

DDPD_0N BB43
<46> CRT_HSYNC 2 1 SL2303 M47 CRT_HSYNC DDPD_0P BB45
0402
<46> CRT_VSYNC 2 1 SL2304 M49 CRT_VSYNC DDPD_1N BF44
0402
DDPD_1P BE44
BF42
2

DDPD_2N
2 1 T43 DAC_IREF DDPD_2P BE42
150Ohm

150Ohm

150Ohm

1KOhm R2310 T42 BJ42


0.5% CRT_IRTN DDPD_3N
DDPD_3P BG42

GND COUGARPOINT-H
B B
1% 1% 1% GND

GND

A A

1bios.ru Title : PCH_IBEX(4)_DP,LVDS,CRT


ASUSTeK COMPUTER INC. Engineer: Wish
Size Project Name Rev
C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 23 of 95
5 4 3 2 1
5 4 3 2 1

Tacoma Pass(NVRAM) Disabling and termination guidelines(DG R0.7 p.322)


If the tacoma Pass interface is not used,
the interface signals, inculding NV_RCOMP,
can be left as No connects with few exceptions.
U2001E
AY7
VccpNAND, NV_ALE, NV_CLE
NV_CE#0
NV_CE#1 AV7
BG26 TP1 NV_CE#2 AU3
BJ26 TP2 NV_CE#3 BG4
BH25 TP3
BJ16 TP4 NV_DQS0 AT10
BG16 TP5 NV_DQS1 BC8 DMI & FDI Termination Voltage
AH38 TP6
+3VS_VCC3_3 +3VS_VCC3_3 AH37 AU2
TP7 NV_DQ0 / NV_IO0
AK43 TP8 NV_DQ1 / NV_IO1 AT4 LOW : Set to Vss
D
PCB ID AK45
C18
TP9
TP10
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
AT3
AT1
NV_CLE
D
N30 TP11 NV_DQ4 / NV_IO4 AY3 HIGH : Set to Vcc +V_NVRAM_VCCPNAND
H3 TP12 NV_DQ5 / NV_IO5 AT5
1

AH12 AV3 CRB

NVRAM
R2501 R2502 TP13 NV_DQ6 / NV_IO6
AM4 TP14 NV_DQ7 / NV_IO7 AV1
10KOhm 10KOhm AM5 BB1
@ @ TP15 NV_DQ8 / NV_IO8
Y13 TP16 NV_DQ9 / NV_IO9 BA3

2
K24 BB5
2

TP17 NV_DQ10 / NV_IO10 R2418


L24 TP18 NV_DQ11 / NV_IO11 BB3
AB46 TP19 NV_DQ12 / NV_IO12 BB7 2.2kOHM
AB45 BE8

RSVD
PCB_ID0 TP20 NV_DQ13 / NV_IO13
BD4

1
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15 BF6

PCB_ID1 B21 AV5 1 T2401


TP21 NV_ALE NV_CLE R2420
M20 TP22 NV_CLE AY1 2 1 1KOhm H_SNB_INV# <3>
AY16 TP23
BG46 AV10 1 T2402
TP24 NV_RCOMP
1

1 T2403
R2503 R2504 AT8
10KOhm NV_RB#
10KOhm
BE28 TP25 NV_RE#_WRB0 AY5
BC30 BA2
2

TP26 NV_RE#_WRB1
BE32 TP27
BJ32 TP28 NV_WE#_CK0 AT12
BC28 TP29 NV_WE#_CK1 BF3
BE30 TP30
BF32 TP31
GND GND BG32 C24 USB 0 USB Port (LAN BD)
TP32 USBP0N USB_PN0 <33>
AV26 TP33 USBP0P A24 USB_PP0 <33>
BB26 TP34 USBP1N C25 USB_PN1 <33> USB 1 USB Port (LAN BD)
AU28 TP35 USBP1P B25 USB_PP1 <33>
AY30 TP36 USBP2N C26 USB_PN2 <66> USB 2 USB Port
AU26 TP37 USBP2P A26 USB_PP2 <66>
AY26 TP38 USBP3N K28 USB_PN3 <69> USB 3 USB 3.0 Port
AV28 TP39 USBP3P H28 USB_PP3 <69>
AW30 TP40 USBP4N E28 USB_PN4 <54> USB 4 TV Tuner
USBP4P D28 USB_PP4 <54>
C
USBP5N C28 USB 5 C

USBP5P A28
USBP6N C29 USB 6
USBP6P B29
PCI_INTA# K40 N28 USB 7
PCI_INTB# PIRQA# USBP7N
K38 M28

PCI
PCI_INTC# PIRQB# USBP7P
H38 PIRQC# USBP8N L30 USB_PN8 <53> USB 8 WiFi / WiMax
PCI_INTD# G38 K30
PIRQD# USBP8P USB_PP8 <53>
5V USBP9N G30 USB_PN9 <45> USB 9 Camera
GPU_RST# C46 E30

USB
<70> GPU_RST# REQ1# / GPIO50 USBP9P USB_PP9 <45>
<29> STP_27M STP_27M C44 C30 USB 10
REQ2# / GPIO52 USBP10N
<70> DGPU_PWR_EN# E40 REQ3# / GPIO54 USBP10P A30
5V USBP11N L32 USB_PN11 <42> USB 11 Card Reader
PCI_GNT1# D47 K32 +3VSUS_ORG
GNT1# / GPIO51 USBP11P USB_PP11 <42>
T2408 1 DGPU_PWM_SELECT# E42 G32 USB 12 Bluetooth
GNT2# / GPIO53 USBP12N USB_PN12 <61>
STP_A16OVR F46 E32
GNT3# / GPIO55 USBP12P USB_PP12 <61>
C32 USB 13 OC#0 RP2403A 1
USBP13N 10KOhm5
USBP13P A32 10
PCI_INTE# G42 OC#7 RP2403B 2
PIRQE# / GPIO2 10KOhm5
<51> SATA_ODD_DA# SATA_ODD_DA# G40 10
PCB_ID0 PIRQF# / GPIO3 OC#3 RP2403C
C42 PIRQG# / GPIO4 USBRBIAS# C33 3 10KOhm5
PCB_ID1 D44 10
PIRQH# / GPIO5 OC#5 RP2403D 4 10KOhm5
B33 USBRBIAS_PN 1 2 10
T2407 PCI_PME# USBRBIAS R2406 22.6Ohm OC#1 RP2403E
1 K10 PME# 6 10KOhm5
1% 10
PLT_RST# C6 A14 OC#0 GND OC#2 RP2403F 7
PLTRST# OC0# / GPIO59 10KOhm5
K20 OC#1 10
OC1# / GPIO40 OC#2 OC#6 RP2403G
OC2# / GPIO41 B17 8 10KOhm5
T2413 1 CLKOUT_PCI0 H49 CLKOUT_PCI0 OC3# / GPIO42 C16 OC#3 10
R2428 1 2 22Ohm CLK_PCI_FB_R H43 L16 OC#4 OC#4 RP2403H 9
<21> CLK_PCI_FB CLKOUT_PCI1 OC4# / GPIO43 10KOhm5
<30> CLK_KBCPCI_PCH R2429 1 2 39Ohm CLK_KBCPCI_PCH_R J48 A16 OC#5 10
R2430 CLK_DEBUG_R CLKOUT_PCI2 OC5# / GPIO9 OC#6
<44> CLK_DEBUG 1 2 22Ohm K42 CLKOUT_PCI3 OC6# / GPIO10 D14
H40 C14 OC#7
CLKOUT_PCI4 OC7# / GPIO14

COUGARPOINT-H
B B

+3VS_VCC3_3

PCI_INTA# RP2401A 1
Boot BIOS Strap : GNT1#, SATA1GP GNT3#: A16 swap override Strap/
10KOhm5
10 Top-Block swap override jumper +3V
PCI_INTB# RP2401B 2 10KOhm5 Boot BIOS Strap
10
PCI_INTC# RP2401C 3 10KOhm5
10 GNT1#(BBS1) SATA1GP(BBS0) Boot BIOS Location Low=Enabled A16 swap override/
RP2401D 4 10KOhm5 Top-Block swap override
10 0 1 Reserved U2401
SATA_ODD_DA# RP2401E 6 10KOhm5 1 INB VCC 5
10 1 0 PCI <32> PLT_RST# 2 INA
PCI_INTD# RP2401F 7 10KOhm5 High=Default 3 GND OUTY 4 BUF_PLT_RST# <3,30,33,42,45,53,54,68,70>
10 1 1 SPI (PCH)
PCI_INTE# RP2401G 8 74LVC1G08GW
10KOhm5
10 0 0 LPC
RP2401H 9 GND
10KOhm5
10 Sampled on rising edge of PWROK.
1 2
+3VS_VCC3_3 R2414 0Ohm @

STP_A16OVR 1 2
R2413 1KOhm @
2

A STP_27M R2427 2 1 10KOhm GND A


Default PU R2409
10KOhm R2410
20K OHM

1bios.ru
10KOhm
1

SATA_ODD_DA# 2 R2421 1 10KOhm @ <20> SATA1GP 1 2


R2411 1KOhm @
DGPU_PWR_EN# 2 R2422 1 10KOhm @ PCI_GNT1# 1 2
R2412 1KOhm @
GPU_RST# 2 R2423 1 10KOhm

STP_27M 2 R2424 1 10KOhm @


GND Title : PCH_IBEX(5)_PCI,NVRAM,USB
ASUSTeK COMPUTER INC. Engineer: Wish
Size Project Name Rev
GND C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 24 of 95
5 4 3 2 1
5 4 3 2 1

+3VSUS_ORG

BT_LED R2526 1 2 1KOhm


+3VS_VCC3_3

USB20_SEL R2527 2 1 10KOhm

1
R2506 @
1KOhm
5% ICC_EN# R2532 2 1 10KOhm

2
For XDP Debug, need to no stuff R2507
+3VS_VCC3_3
D D

S_GPIO
+3VS_VCC3_3 U2001F

R2507 1 2 100Ohm XDP_FN17_R T7 C40


BMBUSY# / GPIO0 TACH4 / GPIO68 SATA_ODD_PWRGT <51>
TMDS_HDMI_HPD R2528 2 1 10KOhm
<30> EXT_SMI# A42 B41 R2531 1 2 1KOhm GND
R2513 SATA_DET#4 TACH1 / GPIO1 TACH5 / GPIO69 STP_PCI#
2 1 10KOhm R2515 2 1 10KOhm
<23,48> HDMI_HPD 2 1 TMDS_HDMI_HPD H36 C41 R2529 1 2 1KOhm
R2505 0Ohm @ TACH2 / GPIO6 TACH6 / GPIO70 WLAN_LED R2540 2 1 10KOhm
<68> USB3_SMI# E38 A40 R2530 1 2 1KOhm +3VS_VCC3_3
TACH3 / GPIO7 TACH7 / GPIO71 PCH_TEMP_ALERT# R2541 2 1 10KOhm
T2508 1 ICC_EN# C10 GPIO8
R2510 2 1 10KOhm DGPU_PWROK EXT_SMI# R2537 2 1 10KOhm
T2506 1 PM_LANPHY_EN C4 LAN_PHY_PWR_CTRL / GPIO12 USB3_SMI# R2538 2 1 10KOhm
<56> BT_LED G2 GPIO15 A20GATE P4 A20GATE <30>
GND TEST_SET_UP R2523 2 1 10KOhm
AU16 1 T2503

CPU/MISC
R2536 2 SATA_DET#4 PECI USB30_RST#_PCH
1 10KOhm +3VSUS_ORG U2 SATA4GP / GPIO16
R2518 2 1 10KOhm
RCIN# P5 RCIN# <30>
1 T2505 @

GPIO
PLL_ODVR_EN 1 2 <21,70> DGPU_PWROK D40 AY11
TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD <3,7>
R2534 1KOhm
@ <56> WLAN_LED T5 AY10 PM_THRMTRIP# R2512 1 2 390Ohm H_THRMTRIP# <3>
SCLOCK / GPIO22 THRMTRIP# T2509
1
GND <69> USB20_SEL E8 T14 INT3_3V# 1 T2502
GPIO24 / MEM_LED INIT3_3V#
GPIO28(On-Die PLL VR):
DSW_WAKE# E16
High:Enable (default), Low:Disable <30> DSW_WAKE# GPIO27
<53> WLAN_ON# 2 1 SL2502 PLL_ODVR_EN P8
0402 GPIO28 N_TS_VSS1 R2516
NC_1 AH8 2 1 0Ohm
GPIO35_PCH R2535 2 1 10KOhm STP_PCI# K1 PDG V0.9, 3.9.3 These signals shouldn't float
STP_PCI# / GPIO34 N_TS_VSS2 R2517
NC_2 AK11 2 1 0Ohm on the motherboard. they should be tied to
@ T2507 1 GPIO35_PCH K4
GND GPIO35
AH10 N_TS_VSS3 R2522 2 1 0Ohm
GND directly.
DMI_OVRVLTG NC_3
V8 SATA2GP / GPIO36
AK10 N_TS_VSS4 R2524 2 1 0Ohm
FDI_OVRVLTG NC_4
C M5 SATA3GP / GPIO37
C

NC_5 P37
T2504 1 USB30_RST#_PCH N2 SLOAD / GPIO38
DMI Termination Voltage Override GFX_CRB_DET M3 GND
SDATAOUT0 / GPIO39
+3VS_VCC3_3 TEST_SET_UP V13 BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15
T2501 1 PCH_TEMP_ALERT# V3 BG48
SATA5GP / GPIO49 VSS_NCTF_16
DMI_OVRVLTG 200KOhm 2 1 R2509 <61> BT_ON D6 BH3
GPIO57 VSS_NCTF_17
2 1 BT_ON BH47
VSS_NCTF_18
FDI Termination Voltage Override
R2525 100KOhm A4 BJ4
VSS_NCTF_1 VSS_NCTF_19
A44 VSS_NCTF_2 VSS_NCTF_20 BJ44
2 1 FDI_OVRVLTG GND
A45 VSS_NCTF_3 VSS_NCTF_21 BJ45
R2520 100KOhm

NCTF
A46 VSS_NCTF_4 VSS_NCTF_22 BJ46

GND A5 BJ5
VSS_NCTF_5 VSS_NCTF_23
A6 VSS_NCTF_6 VSS_NCTF_24 BJ6

B3 VSS_NCTF_7 VSS_NCTF_25 C2

B47 VSS_NCTF_8 VSS_NCTF_26 C48

BD1 VSS_NCTF_9 VSS_NCTF_27 D1

BD49 VSS_NCTF_10 VSS_NCTF_28 D49

BE1 VSS_NCTF_11 VSS_NCTF_29 E1

BE49 VSS_NCTF_12 VSS_NCTF_30 E49


B B
BF1 VSS_NCTF_13 VSS_NCTF_31 F1
+3VS_VCC3_3 BF49 F49
VSS_NCTF_14 VSS_NCTF_32
2 1GFX_CRB_DET R2519 2 1 10KOhm
COUGARPOINT-H
R2521 100KOhm
@

GND

GPIO27(checklist r0.7):
Default = Do not connect (floating)
High (1) = Enables the internal VccVRM to have a
clean supply for analog rails. No need to use on-board
+VCCPDSW filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board
filter circuits for analog rails.
1

R2511
10KOhm
@
2

DSW_WAKE#
1

R2514
10KOhm
@
A A
2

1bios.ru
GND

Title : PCH_IBEX(6)CPU,GPIO,MISC
ASUSTeK COMPUTER INC. Engineer: Wish
Size Project Name Rev
C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 25 of 95
5 4 3 2 1
5 4 3 2 1

+VCCA_DAC_1_2 +3VS_VCC3_3

(VccADAC: 68mA@3.3V)
1KOhm/100Mhz 1 2 L2603

1
C2614 C2613 C2612
0.01UF/16V 0.1UF/16V 10UF/6.3V

2
GND GND GND
D D

+VTT_PCH_VCC U2001G POWER +3VS_VCCA_LVDS +3VS_VCC3_3


U2001H
H5 VSS[0]
(VccCore: 1.3A@1.05V)
AA23 VCCCORE[1] VCCADAC U48 (VccALVDS: 1mA@3.3V) AA17 VSS[1] VSS[80] AK38
AC23 VCCCORE[2] AA2 VSS[2] VSS[81] AK4

CRT
AD21 VCCCORE[3] 2 1 SL2604 AA3 VSS[3] VSS[82] AK42

1
C2601 C2602 C2603 C2604 0603
AD23 VCCCORE[4] VSSADAC U47 AA33 VSS[4] VSS[83] AK46
+1.8VS_VCCT_LVD +1.8VS

VCC CORE
10UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V AF21 AA34 AK8
VCCCORE[5] VSS[5] VSS[84]
AF23 AB11 AL16
2

2
VCCCORE[6] VSS[6] VSS[85]

1
AG21 GND (VccTXLVDS: 60mA@1.8V) AB14 AL17
VCCCORE[7] C2624 1KOhm/100Mhz 1 VSS[7] VSS[86]
AG23 VCCCORE[8] 2 L2604 AB39 VSS[8] VSS[87] AL19
AG24 AK36 0.1UF/16V AB4 AL2

2
GND GND GND GND VCCCORE[9] VCCALVDS @ VSS[9] VSS[88]
AG26 VCCCORE[10] AB43 VSS[10] VSS[89] AL21
AG27 VCCCORE[11] VSSALVDS AK37 AB5 VSS[11] VSS[90] AL23

1
AG29 C2615 C2616 C2617 AB7 AL26
VCCCORE[12] GND 0.01UF/16V 0.01UF/16V 22UF/6.3V VSS[12] VSS[91]
AJ23 AC19 AL27

LVDS
VCCCORE[13] GND VSS[13] VSS[92]
AJ26 AM37 AC2 AL31

2
VCCCORE[14] VCCTX_LVDS[1] VSS[14] VSS[93]
AJ27 VCCCORE[15] AC21 VSS[15] VSS[94] AL33
AJ29 VCCCORE[16] VCCTX_LVDS[2] AM38 AC24 VSS[16] VSS[95] AL34
AJ31 VCCCORE[17] AC33 VSS[17] VSS[96] AL48
+VTT_PCH_VCCIO +VTT_PCH_VCCDPLL_EXP AP36 GND GND GND AC34 AM11
VCCTX_LVDS[3] VSS[18] VSS[97]
AC48 VSS[19] VSS[98] AM14
VCCTX_LVDS[4] AP37 AD10 VSS[20] VSS[99] AM36
+VTT_PCH_VCC 2 1 SL2601 AN19 +3VS_VCC_GIO +3VS_VCC3_3 AD11 AM39
0603 VCCIO[28] VSS[21] VSS[100]
AD12 VSS[22] VSS[101] AM43
(VccAPLLEXP: 50mA@1.05V,CRB) 1 2 SL2605 AD13 VSS[23] VSS[102] AM45
0603 VCC_DMI is 1.1V for Mobile
2 1 BJ22 VCCAPLLEXP AD19 VSS[24] VSS[103] AM46

1
L2601 1KOhm/100Mhz Analog Power Supply for DMI PLL AD24 AM7
C2618 +VTT_CPU_VCC_DMI +VTT_PCH_VCC VSS[25] VSS[104]
V33 AD26 AN2

HVCMOS
VCC3_3[6] VSS[26] VSS[105]
1

@ C2605 AN16 0.1UF/16V AD27 AN29

2
10UF/6.3V VCCIO[15] VSS[27] VSS[106]
AD33 VSS[28] VSS[107] AN3
@ AN17 1 2 SL2607 AD34 AN31
2

VCCIO[16] VSS[29] VSS[108]

1
0603
VCC3_3[7] V34 AD36 VSS[30] VSS[109] AP12
GND C2625 AD37 AP19
VSS[31] VSS[110]

1
C AN21 C2619 0.1UF/16V AD38 AP28 C

2
GND VCCIO[17] +VCCAFDI_VRM 1UF/6.3V VSS[32] VSS[111]
AD39 VSS[33] VSS[112] AP30
AN26 +VccCLKDMI_PCH +VTT_PCH_VCC AD4 AP32

2
+VTT_PCH_VCCIO VCCIO[18] VSS[34] VSS[113]
AD40 VSS[35] VSS[114] AP38
(VccIO: 2.925A@1.05V) +VTT_PCH_VCC_EXP AN27 AT16 GND AD42 AP4
VCCIO[19] VCCVRM[3] VSS[36] VSS[115]
1 2 SL2610 AD43 VSS[37] VSS[116] AP42
GND 0603
AP21 VCCIO[20] AD45 VSS[38] VSS[117] AP46
(VccDMI: 42mA@1.05V) AD46 VSS[39] VSS[118] AP8
1

1
C2609 C2606 C2608 C2607 C2610 AP23 AT20 C2620 C2621 AD8 AR2
10UF/6.3V 1UF/6.3V 1UF/6.3V 0.1UF/16V 1UF/6.3V VCCIO[21] VCCDMI[1] 1UF/6.3V 10UF/6.3V VSS[40] VSS[119]
AE2 AR48

DMI
@ VSS[41] VSS[120]
AP24 AE3 AT11

VCCIO
2

2
VCCIO[22] VSS[42] VSS[121]
(VccCLKDMI: 20mA@1.05V) AF10 VSS[43] VSS[122] AT13
AP26 VCCIO[23] VCCCLKDMI AB36 AF12 VSS[44] VSS[123] AT18
AD14 VSS[45] VSS[124] AT22
GND GND GND GND GND AT24 GND GND AD16 AT26
VCCIO[24] VSS[46] VSS[125]
check with CRB (LC filter) AF16 VSS[47] VSS[126] AT28
AF19 VSS[48] VSS[127] AT30
AN33 VCCIO[25] AF24 VSS[49] VSS[128] AT32
AF26 VSS[50] VSS[129] AT34
+3VS_VCC3_3 +3VS_VCCA3GBG AN34 AG16 AF27 AT39
VCCIO[26] VCCPNAND[1] +V_NVRAM_VCCPNAND +1.8VS VSS[51] VSS[130]
AF29 VSS[52] VSS[131] AT42
(Vcc3_3: 266mA@3.3V) AF31 AT46

NAND / SPI
SL2602 VSS[53] VSS[132]
2
0603
1 BH29 VCC3_3[3] VCCPNAND[2] AG17 (VccpNAND: 190mA@1.8V) AF38 VSS[54] VSS[133] AT7
1 2 SL2608 AF4 AU24
VSS[55] VSS[134]
1

0603
AF42 VSS[56] VSS[135] AU30

1
C2611 +VCCAFDI_VRM AJ16 AF46 AV16
VCCPNAND[3] C2623 VSS[57] VSS[136]
0.1UF/16V AF5 AV20
2

+VTT_PCH_VCC +VccAFDIPLL_PCH VSS[58] VSS[137]


(VccVRM: 160mA@1.5V) AP16 0.1UF/16V AF7 AV24

2
VCCVRM[2] VSS[59] VSS[138]
VCCPNAND[4] AJ17 AF8 VSS[60] VSS[139] AV30
GND AG19 AV38
VSS[61] VSS[140]
2 1 (VccAFDIPLL: ???mA@1.05V)BG6 VccAFDIPLL AG2 VSS[62] VSS[141] AV4
L2602 1KOhm/100Mhz Analog Power Supply for FDI PLL GND +V3.3_VCCSPI +3VSUS_ORG AG31 AV43
@ VSS[63] VSS[142]
AG48 VSS[64] VSS[143] AV8
AP17 VCCIO[27] (VccSPI: 20mA@1.8V) AH11 VSS[65] VSS[144] AW14
+VTT_PCH_VCCIO +VTT_PCH_VCCDPLL_FDI
FDI

V1 1 2 SL2609 AH3 AW18


VCCSPI 0603 VSS[66] VSS[145]
AH36 VSS[67] VSS[146] AW2
2 1 SL2603 +VTT_CPU_VCC_DMI AU20 AH39 AW22
VCCDMI[2] VSS[68] VSS[147]

1
0603 C2622
B
AH40 VSS[69] VSS[148] AW26 B
1UF/6.3V AH42 AW28
COUGARPOINT-H VSS[70] VSS[149]
AH46 AW32

2
VSS[71] VSS[150]
AH7 VSS[72] VSS[151] AW34
AJ19 VSS[73] VSS[152] AW36
AJ21 VSS[74] VSS[153] AW40
GND AJ24 AW48
VSS[75] VSS[154]
AJ33 VSS[76] VSS[155] AV11
AJ34 VSS[77] VSS[156] AY12
AK12 VSS[78] VSS[157] AY22
AK3 AY28
All Beads : 0603 !! VSS[79]
COUGARPOINT-H
VSS[158]

GND GND

VccRAM : 1.5V/1.8V supply for internal PLL and VRMs PCH ICC Description

+VTT 4.68A
(+VTT_PCH: 4.68A@1.05V)
+1.5VS 0.16A
+VCCAFDI_VRM
+1.8VS 0.19A
(+VTT_PCH_VCC: 1.412A@1.05V)
+1.8VS +1.5VS +3VS 0.355A
+1.05VS +VTT_PCH_VCC

JP2601
+3VSUS 0.1A
N/A
1 1 2 2
R2605 2 1 0Ohm
A 2MM_OPEN_5MIL A
+VTT_PCH_VCCIO
R2607 2 1 0Ohm
JP2602

1bios.ru
N/A
@ 1 2
1 2
2MM_OPEN_5MIL
1

+
(+VTT_PCH_VCCIO: 2.925A@1.05V)
CE2601
330UF/2V
@
Title : PCH_IBEX(7)_POWER,GND
2

ASUSTeK COMPUTER INC. Engineer: Wish


Size Project Name Rev
C N73Sv 1.0
Date: Wednesday, October 13, 2010 Sheet 26 of 95
5 4 3 2 1
5 4 3 2 1

+VTT_PCH_VCC +VTT_PCH_VCCA_CLK +VCCIO_USB


+VTT_PCH_VCCIO
+3VSUS_ORG +VCCPDSW @ (VccACLK: ???A@1.05V)
2 1 1 2 SL2723
L2701 1KOhm/100Mhz 0603
POWER

1
1 2 U2001J C2730 U2001I
R2705 0Ohm (VccDSW3_3: 2mA@3.3V) 1UF/6.3V (VccSUS3_3: 97mA@3.3V)

1
+3VA C2708 AD49 N26 AY4 H46

2
0.1UF/16V VCCACLK VCCIO[29] VSS[159] VSS[259]
support DSx AY42 VSS[160] VSS[260] K18

1
C2707 P26 +3VSUS_ORG AY46 K26

2
0.1UF/16V VCCIO[30] GND VSS[161] VSS[261]
1 2 04/20 No-stuff T16 VCCDSW3_3 AY8 VSS[162] VSS[262] K39
R2706 0Ohm @ P28 B11 K46
for +1.05VS

2
@ VCCIO[31] +3VSUS_VCCPUSB VSS[163] VSS[263]
1 2 B15 VSS[164] VSS[264] K7
+3VS_VCC3_3 GND leakage V12 T27 C2731 0603 SL2701
B19 L18
DCPSUSBYP VCCIO[32] VSS[165] VSS[265]

1
GND 0.1UF/16V B23 L2
L2707 +3VSUS_VCCAUBG VSS[166] VSS[266]
D VCCIO[33] T29 2 1 B27 VSS[167] VSS[267] L20 D
+3VS_VCC_CLKF33 C2732 0402 SL2713
1 2 T38 B31 L26

2
VCC3_3[5] VSS[168] VSS[268]

1
0.1UF/16V B35 L28
VSS[169] VSS[269]
1

1
1KOhm/100Mhz C2744 C2745 T23 B39 L36
1UF/6.3V 10UF/6.3V VCCSUS3_3[7] GND VSS[170] VSS[270]
(VccAPLLDMI2: ???mA@1.8V) BH23 B7 L48

2
VCCAPLLDMI2 VSS[171] VSS[271]
T24 F45 M12
2

2
VCCSUS3_3[8] VSS[172] VSS[272]
AL29 VCCIO[14] BB12 VSS[173] VSS[273] P16
+VTT_PCH_VCC V23 GND D2702 BB16 M18

USB
GND GND VCCSUS3_3[9] +VTT_PCH_VCCIO VSS[174] VSS[274]
1 BB20 VSS[175] VSS[275] M22
@ AL24 V24 3 BB22 M24
+VCCAPLL_CPY_PCH DCPSUS[3] VCCSUS3_3[10] VSS[176] VSS[276]
2 1 2 +3VSUS_ORG BB24 VSS[177] VSS[277] M30
L2706 P24 BB28 M32
VCCSUS3_3[6] VSS[178] VSS[278]
1

1
1KOhm/100Mhz C2711 C2712 BAT54CW BB30 M34
10UF/6.3V +VTT_PCH_VCCIO 1UF/6.3V VSS[179] VSS[279]
AA19 VCCASW[1] BB38 VSS[180] VSS[280] M38
@ @ T26 +VTT_VCCAUPLL 2 1 +5VSUS BB4 M4
2

2
VCCIO[34] 0402 SL2714 VSS[181] VSS[281]
AA21 VCCASW[2] BB46 VSS[182] VSS[282] M42
2 1 +VCCDPLL_CPY R2701 BC14 VSS[183] VSS[283] M46
0603 SL2708 GND D2703
AA24 VCCASW[3] V5REF_SUS M26 (V5REF_SUS: 1mA@5V) 1 2 BC18 VSS[184] VSS[284] M8
GND C2733 1 BC2 N18
VSS[185] VSS[285]

1
+VTT_PCH_VCC

Clock and Miscellaneous


AA26 0.1UF/16V 10Ohm 3 BC22 P30
VCCASW[4] VSS[186] VSS[286]
DCPSUS[4] AN23 2 +3VS_VCC3_3 BC26 VSS[187] VSS[287] N47
(VccASW: 1.01A@1.05V) AA27 BC32 P11

2
VCCASW[5] VSS[188] VSS[288]

1
1 2 +V1.05M_VCCASW AN24 +VTT_VCCPSUS C2735 BAT54CW BC34 P18
SL2709 0603 VCCSUS3_3[1] 1UF/6.3V VSS[189] VSS[289]
AA29 VCCASW[6] BC36 VSS[190] VSS[290] T33
1

C2713 C2714 @ GND +5VS BC40 P40

2
22UF/6.3V 22UF/6.3V VSS[191] VSS[291]
AA31 VCCASW[7] BC42 VSS[192] VSS[292] P43
R2702 BC48 P47
2

GND VSS[193] VSS[293]


AC26 VCCASW[8] V5REF P34 (V5REF: 1mA@5V) 1 2 BD46 VSS[194] VSS[294] P7
BD5 VSS[195] VSS[295] R2

1
GND GND AC27 +3VSUS_ORG C2734 10Ohm BE22 R48
VCCASW[9] 1UF/6.3V VSS[196] VSS[296]
N20 BE26 T12

PCI/GPIO/LPC
VCCSUS3_3[2] +VTT_VCCPSUS VSS[197] VSS[297]
AC29 1 2 BE40 T31

2
VCCASW[10] 0603 SL2715 +3VS_VCC3_3 VSS[198] VSS[298]
VCCSUS3_3[3] N22 BF10 VSS[199] VSS[299] T37

1
AC31 C2736 BF12 T4
VCCASW[11] VSS[200] VSS[300]
1

C2717 C2715 C2716 P20 1UF/6.3V 1 2 GND BF16 W34


1UF/6.3V 1UF/6.3V 1UF/6.3V VCCSUS3_3[4] C2737 0603 SL2716 VSS[201] VSS[301]
AD29 BF20 T46

2
VCCASW[12] VSS[202] VSS[302]

1
P22 0.1UF/16V 2 1 BF22 T47
2

VCCSUS3_3[5] 0603 SL2717 VSS[203] VSS[303]


AD31 VCCASW[13] BF24 VSS[204] VSS[304] T8
C GND C2738 BF26 V11 C

2
VSS[205] VSS[305]

1
GND GND GND W21 AA16 0.1UF/16V BF28 V17
VCCASW[14] VCC3_3[1] VSS[206] VSS[306]
BD3 VSS[207] VSS[307] V26
W23 W16 GND BF30 V27

2
VCCASW[15] VCC3_3[8] VSS[208] VSS[308]
BF38 VSS[209] VSS[309] V29
W24 T34 +3VS_VCCPPCI BF40 V31
VCCASW[16] VCC3_3[4] GND VSS[210] VSS[310]
BF8 VSS[211] VSS[311] V36
W26 +3VS_VCC3_3 BG17 V39
VCCASW[17] VSS[212] VSS[312]
BG21 VSS[213] VSS[313] V43
W29 VCCASW[18] BG33 VSS[214] VSS[314] V7
1

+VTT_PCH_VCCA_B_DPL C2718 BG44 W17


0.1UF/16V C2739 +VTT_SATA3 +VTT_PCH_VCCIO VSS[215] VSS[315]
W31 VCCASW[19] VCC3_3[2] AJ2 (VccAPLLSATA: ???mA@1.05V) BG8 VSS[216] VSS[316] W19

1
+VTT_PCH_VCCA_A_DPL 0.1UF/16V BH11 W2
2

VSS[217] VSS[317]
W33 VCCASW[20] BH15 VSS[218] VSS[318] W27
AF13 2 1 BH17 W48

2
+VCCAFDI_VRM GND VCCIO[5] 0603 SL2718 +VTT_PCH_VCC VSS[219] VSS[319]
BH19 VSS[220] VSS[320] Y12

1
N16 C2740 H10 Y38
DCPRTC GND 1UF/6.3V +VTT_VCCAPLL_SATA3 L2702 VSS[221] VSS[321]
VCCIO[12] AH13 1 2 1KOhm/100Mhz BH27 VSS[222] VSS[322] Y4
@ BH31 Y42

2
+VTT_PCH_VCCIO VSS[223] VSS[323]
(VccADPLLA: 15mA@1.05V) Y49 VCCVRM[4] VCCIO[13] AH14 BH33 VSS[224] VSS[324] Y46

1
(VccADPLLB: 15mA@1.05V) C2741 BH35 Y8
GND 10UF/6.3V VSS[225] VSS[325]
BH39 VSS[226] VSS[328] BG29
1 2 +VCCDIFFCLK AF14 @ BH43 N24

2
0603 SL2710 VCCIO[6] VSS[227] VSS[329]
BD47 BH7 AJ3
SATA

+VCCDIFFCLKN VCCADPLLA VSS[228] VSS[330]


VCCAPLLSATA AK1 D3 VSS[229] VSS[331] AD47
1

C2719 BF47 GND D12 B43


+VCCDIFFCLKN 1UF/6.3V VCCADPLLB VSS[230] VSS[333]
1 2 D16 VSS[231] VSS[334] BE10
0603 SL2711 +VCCAFDI_VRM +VTT_SATA +VTT_PCH_VCCIO
AF11 D18 BG41
2

VCCVRM[1] VSS[232] VSS[335]


1

1 2 +VTT_SSCVCC C2720 AF17 D22 G14


0603 SL2712 1UF/6.3V VCCIO[7] VSS[233] VSS[337]
AF33 VCCDIFFCLKN[1] D24 VSS[234] VSS[338] H16
GND AF34 AC16 2 1 D26 T36
2

VCCDIFFCLKN[2] VCCIO[2] VSS[235] VSS[340]


1

C2721 0603 SL2719


AG34 VCCDIFFCLKN[3] D30 VSS[236] VSS[342] BG22

1
1UF/6.3V (VccDIFFCLKN: 55mA@1.05V) AC17 C2742 D32 BG24
GND VCCIO[3] 1UF/6.3V VSS[237] VSS[343]
D34 C22
2

VSS[238] VSS[344]
AG33 AD17 D38 AP13

2
VCCSSC VCCIO[4] VSS[239] VSS[345]
1

C2722 (VccSSC: 95mA@1.05V) D42 M14


0.1UF/16V GND VSS[240] VSS[346]
D8 VSS[241] VSS[347] AP3
V16 GND E18 AP1
2

B DCPSST +VTT_PCH_VCC VSS[242] VSS[348] B


E26 VSS[243] VSS[349] BE16
G18 VSS[244] VSS[350] BC16
1

GND C2723 T17 T21 2 1 G20 BG28


1UF/6.3V DCPSUS[1] VCCASW[22] 0402 SL2720 VSS[245] VSS[351]
V19 G26 BJ28
MISC

+VTT_PCH_VCC +VTT_CPU_VCCPCPU @ DCPSUS[2] VSS[246] VSS[352]


G28
2

VSS[247]
VCCASW[23] V21 2 1 G36 VSS[248]
0402 SL2721
(V_PROC_IO: 1mA@1.05V) G48
CPU

GND VSS[249]
2 1 BJ8 V_PROC_IO H12 VSS[250]
0603 SL2702
VCCASW[21] T19 2 1 H18 VSS[251]
0402 SL2722
H22 VSS[252]
1

C2724 C2725 C2726 +3VSUS_HDA +3VSUS_ORG H24


4.7UF/6.3V 0.1UF/16V 0.1UF/16V VSS[253]
(VccRTC: N/A@3.3V) (VccSUSHDA: 10mA@3.3V) H26 VSS[254]
RTC

A22 P32 1 2 H30


HDA
2

VCCRTC VCCSUSHDA 0603 SL2703 VSS[255]


H32 VSS[256]
+VCC_RTC C2743 H34 VSS[257]
1

GND GND GND COUGARPOINT-H 0.1UF/16V F3 VSS[258]


2
1

C2727 C2728 C2729 COUGARPOINT-H


1UF/6.3V 0.1UF/16V 0.1UF/16V GND
2

GND GND GND GND GND


All Beads : 0603 !!
VCCACLK, VCCAPLLEXP, VCCAPLLDMI2, VCCAFDIPLL,
VCCAPLLSATA can be left no connect in On-Die VR +VTT_PCH_VCCA_A_DPL +VTT_PCH_VCC
enable mode
L2703
+VTT_PCH_VCCA_A_DPL 1 2

1
357mA + 10UH
A S0 max 1 C2703 CE2701 A
1

+3VSUS +3VSUS_ORG 1UF/6.3V 220UF/4V


+3VS +3VS_VCC3_3 JP2702 0Ohm ESR=40mOhm/Ir=1.9A
2

2
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JP2701 2 1 R2703
2 1 @