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A B C D E

1 1

2
Compal confidential 2

Schematics Document
Mobile Dothan uFCPGA with Intel
Alviso_GM+ICH6-M core logic
3

2006-09-15 3

REV:1.0

4 4

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Cover Sheet
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 1 of 43
A B C D E
A B C D E

Compal confidential
File Name : LA-3361P

1 1

Fan Control Mobile Dothan/Yonah Thermal Sensor Clock Generator


page 13
uFCPGA-478 CPU ADM1032ARM ICS 954226
page 4,5,6
page 13 page 16

FSB
H_A#(3..31) 400/533MHz H_D#(0..63)

LVDS CONN
page 14 One Channel
DDR2 -400/533 DDR2-SO-DIMM0
Intel Alviso GMCH page 12

PCBGA 1257 One Channel


CRT conn
page 15 page 7,8,9,10,11

2 2

USB conn x2
page 28

PCI-E(DMI)
USB conn x2
Option(15.4 Sub board connector)
page 19

LAN I/F MODEM AMOM


Intel ICH6-M AC-LINK Audio Conexant CX20493-58
page 26
PCI BUS mBGA-609 CX20468-31
page 25
INTEL LAN
page 17,18,19,20 AMP & Audio Jack
82562V 10 /100 TPA6211 page 27
3 page 22 Mini PCI CardBus Controller 3

socket
CB-1410
page 24
page 23
RJ45/11 CONN LPC BUS IDEBUS IDE HDD IDE ODD
page 22 Connector
page 21
Connector
page 21

Slot 0
page 23
EC KB910L Intel CPU debug conn Page 4
EC debug conn Page 29
RTC CKT. page 29 SW debug conn Page 29
page 18
Switch Button list:
Power Botton Page 30
Int.KBD Lid Switch Page 30
Power On/Off CKT. Touch Pad CONN.
page 31
page 29 LED Function List
page 29 Flash ROM Power LED Page 28
4
Caps Lock LED Page 28
4

DC/DC Interface CKT. SST39VF080-70 Wireless LED


page 30
Page 28
page 32 Charger LED Page 28

Compal Electronics, Inc.


Power Circuit DC/DC Title

33,34,35,36,37,38,39 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Block Diagram Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 2 of 43
A B C D E
5 4 3 2 1

I2C / SMBUS ADDRESSING


Alviso 915GM SA00000K040
External PCI Devices
Alviso 910GML SA00000K100
DEVICE IDSEL # REQ/GNT # PIRQ
D BOM D

CARD BUS AD22 2 C

Wireless LAN(MINI PCI) AD20 0 EF


@ : not install
45@ : 45 level
14@ : 14"(IAT00) install
WLAN@ : with WLAN (mini PCI) install
Power Managment table
AMOM@ : with AMOM install
+CPU_CORE BATT@ : 45 level
Signal +VCCP(1.05V)
+5VS
+3VS
+2.5VS SPI@ : SPI ROM install
+3VALW +1.5VS
C
+1.8VS C
State +0.9VS
+5VALW +1.8V conn@ : ME part
IAT00 14"
S0 ON ON ON

S1 ON ON ON 46144232L01 915GM
46144232L02 910GML W/O WLAN
S3 ON ON OFF
46144232L03 910GML
S5 S4/AC ON OFF OFF

IAT10 15.4"
S5 S4/AC don't exist OFF OFF OFF

46144232L11 910GML
46144232L12 915GM
B 46144232L13 910GML W/O WLAN B

SMBUS Control Table

THERMAL
SOURCE INVERTER BATT SERIAL SENSOR SODIMM CLK CHIP MINI PCI LCD
EEPROM (CPU)
ADM1032

SMB_EC_CK1 KB910L
SMB_EC_DA1

SMB_EC_CK2 KB910L
SMB_EC_DA2

ICH_SMBCLK
ICH6-M
ICH_SMBDATA
LCD_DDCCLK Alviso
LCD_DDCDATA GM-GP
I2CC_SCL NV44M
A
I2CC_SDA A

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Design Note Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 3 of 43
5 4 3 2 1
5 4 3 2 1

ZZZ1

<7> H_A#[3..31] H_D#[0..63] <7>


U15A

H_A#3 P4 A19 H_D#0


H_A#4 U4
A3# Dothan D0#
A25 H_D#1 layout note: Change R2004 to 649 ohm if using XTP to ITP adapter
H_A#5
H_A#6
V3
R3
A4#
A5#
D1#
D2# A22
B21
H_D#2
H_D#3
XDP Connector +3VS

H_A#7 A6# D3# H_D#4 R1998


V2 A7# D4# A24
LA3361P-Rev0.1 H_A#8 W1 B26 H_D#5 XDP_DBRESET#_R 1 2 @ 1K_0402_5%
H_A#9 A8# D5# H_D#6
T4 A9# D6# A21
D H_A#10 W2 B20 H_D#7 04/10 no stuff +VCCP D
H_A#11 A10# D7# H_D#8
Y4 A11# D8# C20
H_A#12 Y1 B24 H_D#9
H_A#13 A12# D9# H_D#10 JP48 XDP_TDI R1999 1 54.9_0402_1%
U1 A13# D10# D24 2
H_A#14 AA3 E24 H_D#11 1 2
H_A#15 A14# D11# H_D#12 XDP_BPM#5 GND0 GND1 XDP_TMS R2000 1 54.9_0402_1%
Y3 A15# D12# C26 3 OBSFN_A0 OBSFN_C0 4 2
H_A#16 AA2 B23 H_D#13 XDP_BPM#4 5 6
H_A#17 A16# D13# H_D#14 OBSFN_A1 OBSFN_C1 XDP_TDO R2001 1 54.9_0402_1%
AF4 A17# D14# E23 7 GND2 GND3 8 2
H_A#18 AC4 C25 H_D#15 XDP_BPM#3 9 10
H_A#19 A18# D15# H_D#16 XDP_BPM#2 OBSDATA_A0 OBSDATA_C0 XDP_BPM#5 R2002 1 54.9_0402_1%
AC7 A19# D16# H23 11 OBSDATA_A1 OBSDATA_C1 12 2
H_A#20 AC3 G25 H_D#17 13 14
H_A#21 A20# D17# H_D#18 XDP_BPM#1 GND4 GND5 XDP_HOOK1 R2003 1
AD3 A21# D18# L23 15 OBSDATA_A2 OBSDATA_C2 16 2 @ 54.9_0402_1%
H_A#22 AE4 M26 H_D#19 XDP_BPM#0 17 18
H_A#23 A22# D19# H_D#20 OBSDATA_A3 OBSDATA_C3
AD2 A23# D20# H24 19 GND6 GND7 20
H_A#24 AB4 F25 H_D#21 21 22 XDP_TRST# R2004 1 2 51_0402_1%
H_A#25 A24# D21# H_D#22 OBSFN_B0 OBSFN_D0
AC6 A25# ADDR GROUP DATA GROUP D22# G24 23 OBSFN_B1 OBSFN_D1 24
H_A#26 AD5 J23 H_D#23 25 26 XDP_TCK R2005 1 2 54.9_0402_1%
H_A#27 A26# D23# H_D#24 GND8 GND9
AE2 A27# D24# M23 27 OBSDATA_B0 OBSDATA_D0 28
H_A#28 AD6 J25 H_D#25 29 30
H_A#29 A28# D25# H_D#26 OBSDATA_B1 OBSDATA_D1
AF3 A29# D26# L26 31 GND10 GND11 32
H_A#30 AE1 N24 H_D#27 33 34
H_A#31 A30# D27# H_D#28 OBSDATA_B2 OBSDATA_D2
<7> H_REQ#[0..4] AF1 A31# D28# M25 35 OBSDATA_B3 OBSDATA_D3 36
H26 H_D#29 37 38
H_REQ#0 D29# H_D#30 H_PWRGOOD_R GND12 GND13 CLK_ITP
R2 REQ0# D30# N25 39 PWRGOOD/HOOK0 ITPCLK/HOOK4 40
H_REQ#1 P3 K25 H_D#31 XDP_HOOK1 41 42 CLK_ITP#
H_REQ#2 REQ1# D31# H_D#32 HOOK1 ITPCLK#/HOOK5 1K_0402_1%
T2 REQ2# D32# Y26 +VCCP 43 VCC_OBS_AB VCC_OBS_CD 44 +VCCP
H_REQ#3 P1 AA24 H_D#33 45 46 H_RESET#_R 1 R2006 2 H_RESET#
H_REQ#4 REQ3# D33# H_D#34 HOOK2 RESET#/HOOK6 XDP_DBRESET#_R 2
T1 REQ4# D34# T25 1 47 HOOK3 DBR#/HOOK7 48 1 XDP_DBRESET#
U23 H_D#35 49 50 200_0402_1%
H_ADSTB#0 D35# H_D#36 C1531 GND14 GND15 XDP_TDO R2007
<7> H_ADSTB#0 U3 ADSTB0# D36# V23 51 SDA TD0 52
H_ADSTB#1 AE5 R24 H_D#37 53 54 XDP_TRST#
<7> H_ADSTB#1 ADSTB1# D37# 2 SCL TRST#
R26 H_D#38 55 56 XDP_TDI
C D38# H_D#39 XDP_TCK TCK1 TDI XDP_TMS C
D39# R23 57 TCK0 TMS 58
CLK_ITP A16 AA23 H_D#40 59 60 XDP_PRE 1 R2008 2 0_0402_5%
<16> CLK_ITP ITP_CLK0 D40# GND16 GND17
CLK_ITP# A15 U26 H_D#41 0.1U_0402_16V4Z
<16> CLK_ITP# ITP_CLK1 D41#
V24 H_D#42 CONN@ SAMTE_BSH-030-01-L-D-A
CLK_CPU_BCLK D42# H_D#43
<16> CLK_CPU_BCLK B15 BCLK0 D43# U25 Place R2006 within 200ps (~1") to CPU
CLK_CPU_BCLK# B14 HOST CLK V26 H_D#44
<16> CLK_CPU_BCLK# BCLK1 D44#
Y23 H_D#45
D45# H_D#46
D46# AA26
Y25 H_D#47
H_ADS# D47# H_D#48
<7> H_ADS# N2 ADS# D48# AB25
H_BNR# L1 AC23 H_D#49
<7> H_BNR# BNR# D49#
H_BPRI# J3 AB24 H_D#50
<7> H_BPRI# BPRI# D50#
H_BR0# N4 AC20 H_D#51
<7> H_BR0# BR0# D51# +3VS
H_DEFER# L4 AC22 H_D#52
<7> H_DEFER# DEFER# D52#
H_DRDY# H2 AC25 H_D#53
<7> H_DRDY# DRDY# D53# +VCCP
H_HIT# K3 AD23 H_D#54
<7> H_HIT# HIT# D54#

1
R37 H_HITM# K4 CONTROL GROUP AE22 H_D#55
<7> H_HITM# HITM# D55#
1 2 H_IERR# A4 AF23 H_D#56 R258
+VCCP 56_0402_5% H_LOCK# IERR# D56# H_D#57
<7> H_LOCK# J2 LOCK# D57# AD24 1K_0402_5%
H_RESET# B11 AF20 H_D#58
<7> H_RESET# RESET# D58#
1" ~ 6.5" AE21 H_D#59

2
D59#

1
AD21 H_D#60
<7> H_RS#[0..2] D60#
H_RS#0 H1 AF25 H_D#61 R266
H_RS#1 RS0# D61# H_D#62
K1 RS1# D62# AF22 56_0402_5%
H_RS#2 L2 AF26 H_D#63
RS2# D63# PROCHOT# <29>
H_TRDY# M3
<7> H_TRDY#

2
TRDY#

1
R253 C
D25 56_0402_5% 2 Q29
DINV0# H_DINV#0 <7> B
J26 2SC2411K_SOT23
DINV1# H_DINV#1 <7> E
XDP_BPM#0 C8 T24 H_DINV#2 <7>

3
XDP_BPM#1 BPM0# DINV2#
B8 AD20 H_DINV#3 <7>

2
XDP_BPM#2 BPM1# DINV3#
A9 BPM2#
B XDP_BPM#3 B
C9 BPM3# H_DSTBN#[0..3] <7>
C23 H_DSTBN#0 H_PROCHOT#
XDP_DBRESET# DSTBN0# H_DSTBN#1
<19> XDP_DBRESET# A7 DBR# DSTBN1# K24
H_DPRSLP will change to H_DBSY# M2 W25 H_DSTBN#2
<7> H_DBSY# DBSY# DSTBN2#
H_DPSLP# B7 AE24 H_DSTBN#3
H_DPRSTP in future <18> H_DPSLP#
H_DPRSLP# G1
DPSLP# DSTBN3#
C22 H_DSTBP#0
H_DSTBP#[0..3] <7>
<18> H_DPRSLP# DPRSTP# DSTBP0#
collateral version. <7> H_DPWR# C19 DPWR# DSTBP1# L24 H_DSTBP#1
XDP_BPM#4 A10 MISC W24 H_DSTBP#2
XDP_BPM#5 PRDY# DSTBP2# H_DSTBP#3
B10 PREQ# DSTBP3# AE25
H_PROCHOT# B17
H_PWRGOOD_R R2009 2 PROCHOT#
1 1K_0402_5%
<18> H_PWRGOOD E4 PWRGOOD
H_CPUSLP# A6
<7,18> H_CPUSLP# SLP#
XDP_TCK A13
XDP_TDI TCK H_A20M#
C12 TDI A20M# C2 H_A20M# <18>
XDP_TDO A12 D3 H_FERR#
TDO FERR# H_FERR# <18>
TEST1 C5 A3 H_IGNNE#
TEST1 IGNNE# H_IGNNE# <18>
TEST2 F23 B5 H_INIT#
TEST2 INIT# H_INIT# <18>
XDP_TMS C11 D1 H_INTR
TMS LINT0 H_INTR <18>
XDP_TRST# B13 D4 H_NMI
TRST# LINT1 H_NMI <18>
LEGACY CPU
THERMAL
H_THERMDA B18 C6 H_STPCLK#
<13> H_THERMDA
H_THERMDC THERMDA DIODE STPCLK# H_SMI#
H_STPCLK# <18>
R32
<13> H_THERMDC A18 THERMDC SMI# B4 H_SMI# <18> Add pullups for PWRGOOD and THERMTRIP per INTEL
C17 200_0402_5%
<7,18> H_THERMTRIP# THERMTRIP#
+VCCP 1 2 H_PWRGOOD

TYCO_1612365-1_Dothan

R251
A TEST2 A
1 2

@ 1K_0402_5%
R35
TEST1 1 2

@ 1K_0402_5%

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Dothan Processor(1/2) Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 4 of 43
5 4 3 2 1
5 4 3 2 1

+CPU_CORE
U15C
R181 U15B
@ 54.9_0402_1% F20 T26
VCCSENSE VCC VSS
1 2 AE7 VCCSENSE VSS A2 F22 VCC VSS U2
+1.5VS 1 2 VSSSENSE AF6 A5 G5 U6
R178 VSSSENSE VSS VCC VSS
VSS A8 G21 VCC VSS U22
@ 54.9_0402_1% A11 H6 U24
VSS VCC VSS
F26 VCCA0 VSS A14 H22 VCC VSS V1
B1 VCCA1 VSS A17 J5 VCC VSS V4
D D
N1 VCCA2 VSS A20 J21 VCC VSS V5
AC26 VCCA3 VSS A23 K22 VCC VSS V21
+VCCP VSS A26 U5 VCC VSS V25
P23 VCCQ0 VSS B3 V6 VCC VSS W3
W4 VCCQ1 VSS B6 V22 VCC VSS W6
VSS B9 W5 VCC VSS W22
B12 W21 W23
D10 Dothan VSS
B16 Y6
VCC VSS
W26

C340
1 1
C341
D12
VCCP
VCCP
VSS
VSS B19 Y22
VCC
VCC
Dothan VSS
VSS Y2
D14 VCCP VSS B22 AA5 VCC VSS Y5
0.01U_0402_16V7K 10U_1206_6.3V6M D16 B25 AA7 Y21
2 2 VCCP VSS VCC VSS
E11 VCCP VSS C1 AA9 VCC VSS Y24
E13 VCCP VSS C4 AA11 VCC VSS AA1
E15 C7 AA13 AA4

POWER, GROUNG, RESERVED SIGNALS AND NC


VCCP VSS VCC VSS
F10 VCCP VSS C10 AA15 VCC VSS AA6
F12 VCCP VSS C13 AA17 VCC VSS AA8
F14 VCCP VSS C15 AA19 VCC VSS AA10
F16 VCCP VSS C18 AA21 VCC VSS AA12
K6 VCCP VSS C21 AB6 VCC VSS AA14
L5 VCCP VSS C24 AB8 VCC VSS AA16
L21 VCCP VSS D2 AB10 VCC VSS AA18
M6 VCCP VSS D5 AB12 VCC VSS AA20
M22 VCCP VSS D7 AB14 VCC VSS AA22
N5 VCCP VSS D9 AB16 VCC POWER, GROUND VSS AA25
N21 VCCP VSS D11 AB18 VCC VSS AB3
P6 VCCP VSS D13 AB20 VCC VSS AB5
P22 VCCP VSS D15 AB22 VCC VSS AB7
R5 VCCP VSS D17 AC9 VCC VSS AB9
R21 VCCP VSS D19 AC11 VCC VSS AB11
T6 VCCP VSS D21 AC13 VCC VSS AB13
T22 VCCP VSS D23 AC15 VCC VSS AB15
U21 VCCP VSS D26 AC17 VCC VSS AB17
C C
VSS E3 AC19 VCC VSS AB19
+CPU_CORE VSS E6 AD8 VCC VSS AB21
D6 VCC VSS E8 AD10 VCC VSS AB23
D8 VCC VSS E10 AD12 VCC VSS AB26
D18 VCC VSS E12 AD14 VCC VSS AC2
D20 VCC VSS E14 AD16 VCC VSS AC5
D22 VCC VSS E16 AD18 VCC VSS AC8
E5 VCC VSS E18 AE9 VCC VSS AC10
E7 VCC VSS E20 AE11 VCC VSS AC12
E9 VCC VSS E22 AE13 VCC VSS AC14
E17 VCC VSS E25 AE15 VCC VSS AC16
E19 VCC VSS F1 AE17 VCC VSS AC18
E21 VCC VSS F4 AE19 VCC VSS AC21
F6 VCC VSS F5 AF8 VCC VSS AC24
F8 VCC VSS F7 AF10 VCC VSS AD1
F18 VCC VSS F9 AF12 VCC VSS AD4
VSS F11 AF14 VCC VSS AD7
VSS F13 AF16 VCC VSS AD9
PSI# E1 F15 AF18 AD11
<37> PSI# PSI# VSS VCC VSS
VSS F17 VSS AD13
+VCCP CPU_VID0 E2 F19 AD15
<37> CPU_VID0 VID0 VSS VSS
CPU_VID1 F2 F21 AD17
<37> CPU_VID1 VID1 VSS VSS
CPU_VID2 F3 F24 AD19
<37> CPU_VID2 VID2 VSS VSS
1

Spacing 1:2 CPU_VID3 G3 G2 AD22


<37> CPU_VID3 VID3 VSS VSS
CPU_VID4 G4 G6 M4 AD25
<37> CPU_VID4 VID4 VSS VSS VSS
R248 CPU_VID5 H4 G22 M5 AE3
<37> CPU_VID5 VID5 VSS VSS VSS
1K_0402_1% G23 M21 AE6
VSS VSS VSS
Spacing 25mil G26 M24 AE8
2

V_CPU_GTLREF VSS VSS VSS


AD26 GTLREF VSS H3 N3 VSS VSS AE10
VSS H5 N6 VSS VSS AE12
VSS H21 N22 VSS VSS AE14
1

1 1 CPU_BSEL0 C16 H25 N23 AE16


B <16> CPU_BSEL0 BSEL0 VSS VSS VSS B
C626 C627 CPU_BSEL1 C14 J1 N26 AE18
<16> CPU_BSEL1 BSEL1 VSS VSS VSS
R247 J4 P2 AE20
2K_0402_1% 1U_0603_10V4Z 220P_0402_50V7K COMP0 VSS VSS VSS
P25 COMP0 VSS J6 P5 VSS VSS AE23
2 2 20 mils COMP1 P26 J22 P21 AE26
2

5 mils (55 Ohm) COMP2 COMP1 VSS VSS VSS


AB2 COMP2 VSS J24 P24 VSS VSS AF2
20 mils(27.4Ohm) COMP3 AB1 K2 R1 AF5
5 mils(55 Ohm) COMP3 VSS VSS VSS
VSS K5 R4 VSS VSS AF9
VSS K21 R6 VSS VSS AF11
Resistor placed within VSS K23 R22 VSS VSS AF13
1

T10 PAD B2 K26 R25 AF15


0.5" of CPU pin.Trace C3
RSVD VSS
L3 T3
VSS VSS
AF17
T7 PAD RSVD VSS VSS VSS
R249 R250 R41 R40 should be at least 25 E26 L6 T5 AF19
T20 PAD RSVD VSS VSS VSS
27.4_0402_1% 54.9_0402_1% AF7 L22 T21 AF21
T12 PAD
27.4_0402_1% 54.9_0402_1%miles away from any AC1
RSVD VSS
L25 T23
VSS VSS
AF24
T11 PAD
2

RSVD VSS VSS VSS


Layout close CPU other toggling signal. VSS M1

TYCO_1612365-1_Dothan
Layout Note: TYCO_1612365-1_Dothan

500 mil max length


Spacing 25mil

A A

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Dothan Processor(2/2) Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 5 of 43
5 4 3 2 1
5 4 3 2 1

+CPU_CORE +CPU_CORE

1 1 1 1 1 1 1 1 1 1
C84 C87 C90 C93 C97 C99 C83 C86 C89 C92
10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M
2 2 2 2 2 2 2 2 2 2
D D

+CPU_CORE +CPU_CORE

1 1 1 1 1 1 1 1 1 1
C259 C265 C81 C82 C100 C101 C102 C98 C260 C267
10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M
2 2 2 2 2 2 2 2 2 2

+CPU_CORE +CPU_CORE

1 1 1 1 1 1 1 1 1 1
C274 C280 C293 C301 C273 C279 C292 C300 C257 C256
10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M
2 2 2 2 2 2 2 2 2 2

+CPU_CORE

1 1 1 1 1
C303 C302 C282 C283 C272
10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M
C 2 2 2 2 2 C

Near VCORE regulator.


+CPU_CORE

1 1 1 1
ESR <= 3m ohm
6/21 + + + +
C94 C286 C95 C285

B 330U_D2E_2.5VM 330U_D2E_2.5VM
Capacitor > 880 uF B
2 330U_D2E_2.5VM
2 2 2
@ 330U_D2E_2.5VM

+VCCP

1
C70 1 1 1 1 1 1 1 1 1 1
+ 150U_D2_6.3VM
C85 C88 C91 C96 C103 C104 C78 C80 C105 C79
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2 2

A A

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Dothan Bypass Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 6 of 43
5 4 3 2 1
5 4 3 2 1

U5A
<4> H_A#[3..31] H_D#[0..63] <4>
H_A#3 G9 E4 H_D#0
H_A#4 C9
HA3#
HA4#
Alviso HD0#
HD1# E1 H_D#1
H_A#5 E9 F4 H_D#2 U5B
H_A#6 HA5# HD2# H_D#3
B7 HA6# HD3# H7
H_A#7 A10 E2 H_D#4 DMI_TXN0 AA31 G16 CFG0
HA7# HD4# <19> DMI_TXN0 DMIRXN0 CFG0
H_A#8 F9 F1 H_D#5 DMI_TXN1 AB35 H13 MCH_CLKSEL1
HA8# HD5# <19> DMI_TXN1 DMIRXN1 CFG1 MCH_CLKSEL1 <16>
H_A#9 D8 E3 H_D#6 DMI_TXN2 AC31 G14 MCH_CLKSEL0
HA9# HD6# <19> DMI_TXN2 DMIRXN2 CFG2 MCH_CLKSEL0 <16>
H_A#10 B10 D3 H_D#7 DMI_TXN3 AD35 F16 T27 PAD
D HA10# HD7# <19> DMI_TXN3 DMIRXN3 CFG3 D
H_A#11 E10 K7 H_D#8 F15 T28 PAD
H_A#12 HA11# HD8# H_D#9 DMI_TXP0 CFG4 CFG5
G10 HA12# HD9# F2 <19> DMI_TXP0 Y31 DMIRXP0 CFG5 G15
H_A#13 D9 J7 H_D#10 DMI_TXP1 AA35 E16 CFG6
HA13# HD10# <19> DMI_TXP1 DMIRXP1 CFG6
H_A#14 E11 J8 H_D#11 DMI_TXP2 AB31 D17 CFG7
HA14# HD11# <19> DMI_TXP2 DMIRXP2 CFG7
H_A#15 F10 H6 H_D#12 DMI_TXP3 AC35 J16
HA15# HD12# <19> DMI_TXP3 DMIRXP3 CFG8
H_A#16 G11 F3 H_D#13 D15 CFG9
H_A#17 HA16# HD13# H_D#14 DMI_RXN0 CFG9
G13 HA17# HD14# K8 <19> DMI_RXN0 AA33 DMITXN0 CFG10 E15 CFG[17:3]: internal pull-up
H_A#18 C10 H5 H_D#15 DMI_RXN1 AB37 D14
<19> DMI_RXN1

DMI
H_A#19 HA18# HD15# H_D#16 DMI_RXN2 DMITXN1 CFG11 CFG12
C11 HA19# HD16# H1 <19> DMI_RXN2 AC33 DMITXN2 CFG12 E14 CFG[19:18]: internal pull-down +VCCP
H_A#20 D11 H2 H_D#17 DMI_RXN3 AD37 H12 CFG13
HA20# HD17# <19> DMI_RXN3 DMITXN3 CFG13
H_A#21 C12 K5 H_D#18 C14
H_A#22 HA21# HD18# H_D#19 DMI_RXP0 CFG14 CFG0 R149 2 1 10K_0402_5%

CFG/RSVD
B13 HA22# HD19# K6 <19> DMI_RXP0 Y33 DMITXP0 CFG15 H15
H_A#23 A12 J4 H_D#20 DMI_RXP1 AA37 J15 CFG16
HA23# HD20# <19> DMI_RXP1 DMITXP1 CFG16
H_A#24 F12 G3 H_D#21 DMI_RXP2 AB33 H14 CFG0 R709 1 2 @ 1K_0402_5%
HA24# HD21# <19> DMI_RXP2 DMITXP2 CFG17
H_A#25 G12 H3 H_D#22 DMI_RXP3 AC37 G22 CFG18
HA25# HD22# <19> DMI_RXP3 DMITXP3 CFG18
H_A#26 E12 J1 H_D#23 G23 CFG19 CFG5 R127 1 2 @ 1K_0402_5%
H_A#27 HA26# HD23# H_D#24 CFG19
C13 HA27# HD24# L5 CFG20 D23
H_A#28 B11 K4 H_D#25 M_CLK_DDR0 AM33 G25 CFG6 R124 1 2 1K_0402_5%
HA28# HD25# <12> M_CLK_DDR0 SM_CK0 RSVD21
H_A#29 D13 J5 H_D#26 M_CLK_DDR1 AL1 G24
HA29# HD26# <12> M_CLK_DDR1 SM_CK1 RSVD22
H_A#30 A13 P7 H_D#27 AE11 J17 CFG7 R117 1 2 @ 1K_0402_5%
H_A#31 HA30# HD27# H_D#28 SM_CK2 RSVD23
F13 HA31# HD28# L7 AJ34 SM_CK3 RSVD24 A31
T29 PAD J3 H_D#29 AF6 A30 CFG9 R119 1 2 @ 1K_0402_5%
TP_H_PCREQ# HD29# H_D#30 SM_CK4 RSVD25
A11 P5 AC10 D26
HOST
<4> H_REQ#[0..4] HPCREQ# HD30# SM_CK5 RSVD26
H_REQ#0 A7 L3 H_D#31 D25 CFG12 R710 1 2 @ 1K_0402_5%
H_REQ#1 HREQ#0 HD31# H_D#32 M_CLK_DDR#0 RSVD27
D7 HREQ#1 HD32# U7 <12> M_CLK_DDR#0 AN33 SM_CK0#

DDR MUXING
H_REQ#2 B8 V6 H_D#33 M_CLK_DDR#1 AK1 CFG13 R711 1 2 @ 1K_0402_5%
HREQ#2 HD33# <12> M_CLK_DDR#1 SM_CK1#
H_REQ#3 C7 R6 H_D#34 AE10
H_REQ#4 HREQ#3 HD34# H_D#35 SM_CK2# CFG16 R712 1
A8 HREQ#4 HD35# R5 AJ33 SM_CK3# 2 @ 1K_0402_5%
H_ADSTB#0 B9 P3 H_D#36 AF5 CFG18 R641 1 2 @ 1K_0402_5%
<4> H_ADSTB#0 HADSTB#0 HD36# SM_CK4#
H_ADSTB#1 E13 T8 H_D#37 AD10 CFG19 R642 1 2 @ 1K_0402_5%
<4> H_ADSTB#1 HADSTB#1 HD37# SM_CK5#
R7 H_D#38
HD38# H_D#39 DDR_CKE0_DIMMA
C <16> CLK_MCH_BCLK# AB1
AB2
HCLKN HD39# R8
U8 H_D#40
<12> DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
AP21
AM21
SM_CKE0 6/07 C
<16> CLK_MCH_BCLK HCLKP HD40# <12> DDR_CKE1_DIMMA SM_CKE1
R4 H_D#41 AH21 Chage CFG18 and CFG19 to PU +2.5VS for SI
<4> H_DSTBN#[0..3] HD41# SM_CKE2
H_DSTBN#0 G4 T4 H_D#42 AK21
H_DSTBN#1 HDSTBN#0 HD42# H_D#43 SM_CKE3
K1 HDSTBN#1 HD43# T5 Layout Note: BM_BUSY# J23 PM_BMBUSY# <19>
H_DSTBN#2 R3 R1 H_D#44 DDR_CS0_DIMMA# AN16 J21 PM_EXTTS#0
H_DSTBN#3 V3
HDSTBN#2 HD44#
T3 H_D#45 Rote as short <12> DDR_CS0_DIMMA#
DDR_CS1_DIMMA# AM14
SM_CS0# EXT_TS0#
H22 PM_EXTTS#1
<4> H_DSTBP#[0..3] HDSTBN#3 HD45# <12> DDR_CS1_DIMMA# SM_CS1# EXT_TS1#
H_DSTBP#0 G5 HDSTBP#0 HD46# V8 H_D#46 as possible AH15 SM_CS2# THRMTRIP# F5 H_THERMTRIP# <4,18>
H_DSTBP#1 K2 U6 H_D#47 AG16 AD30
HDSTBP#1 HD47# SM_CS3# PWROK +VCCP_PWRGD <29>
H_DSTBP#2 R2 W6 H_D#48 AE29

CLK PM
HDSTBP#2 HD48# RSTIN# PLTRST_MCH# <17,21,23>
H_DSTBP#3 W4 U3 H_D#49 @ 40.2_0402_1% R136 1 2 M_OCDOCMP0 AF22
HDSTBP#3 HD49# H_D#50 @ 40.2_0402_1% R147 1 M_OCDOCMP1 SM_OCDCOMP0
<4> H_DINV#0 H8 HDINV#0 HD50# V5 2 AF16 SM_OCDCOMP1
K3 W8 H_D#51 M_ODT0 AP14 A24
<4> H_DINV#1 HDINV#1 HD51# +VCCP <12> M_ODT0 SM_ODT0 DREF_CLKN DREFCLK# <16>
T7 W7 H_D#52 M_ODT1 AL15 A23
<4> H_DINV#2 HDINV#2 HD52# <12> M_ODT1 SM_ODT1 DREF_CLKP DREFCLK <16>
U5 U2 H_D#53 AM11 D37
<4> H_DINV#3 HDINV#3 HD53# SM_ODT2 DREF_SSCLKP SSC_DREFCLK <16>
U1 H_D#54 AN10 C37
HD54# SM_ODT3 DREF_SSCLKN SSC_DREFCLK# <16>
Y5 H_D#55 R159 80.6_0402_1%
H_RESET# HD55# H_D#56 SMRCOMPN
<4> H_RESET# H10 HCPURST# HD56# Y2 +1.8V 1 2 AK10 SMRCOMPN
1

1
54.9_0402_1%

54.9_0402_1%
V4 H_D#57 1 2 SMRCOMPP AK11 AP37
H_ADS# HD57# H_D#58 V_DDR_MCH_REF SMRCOMPP NC1
<4> H_ADS# F8 HADS# HD58# Y7 AF37 SMVREF0 NC2 AN37
R163

R164
H_TRDY# B5 W1 H_D#59 R157 80.6_0402_1% AD1 AP36
<4> H_TRDY# HTRDY# HD59# SMVREF1 NC3
G6 W3 H_D#60 AE27 AP2
<4> H_DPWR# HDPWR# HD60# SMXSLEWIN NC4
H_DRDY# F7 Y3 H_D#61 AE28 AP1
<4> H_DRDY#
2

H_DEFER# HDRDY# HD61# H_D#62 SMXSLEWOUT NC5


<4> H_DEFER# E6 HDEFER# HD62# Y6 AF9 SMYSLEWIN NC6 AN1
TP_H_EDRDY# F6 W2 H_D#63 AF10 B1 R141 +2.5VS
T30 PAD HEDRDY# HD63# SMYSLEWOUT NC7
H_HITM# D6 A2 10K_0402_5%
<4> H_HITM# HHITM# NC8
H_HIT# D4 J11 H_VREF B37 PM_EXTTS#0 2 1
<4> H_HIT# HHIT# HVREF NC9
H_LOCK# H_XRCOMP R137

NC
<4> H_LOCK# B3 HLOCK# HXRCOMP C1 NC10 A36
H_BR0# E7 C2 H_XSCOMP A37 10K_0402_5%
<4> H_BR0# HBREQ0# HXSCOMP NC11
H_BNR# A5 T1 H_YRCOMP PM_EXTTS#1 2 1
<4> H_BNR# HBNR# HYRCOMP
H_BPRI# D5 L1 H_YSCOMP
<4> H_BPRI# HBPRI# HYSCOMP
H_DBSY# C6 D1 H_SWNG0 ALVISO_BGA1257
<4> H_DBSY# HDBSY# HXSWING
H_CPUSLP# G8 P1 H_SWNG1
B <4,18> H_CPUSLP# HCPUSLP# HYSWING B
H_RS#0 A4 Refer to sheet 19 for FSB
HRS0#
24.9_0402_1%

24.9_0402_1%

H_RS#1 C5 CFG[2:0]
HRS1#
1

H_RS#2 B4 frequency select


HRS2#
<4> H_RS#[0..2]
R165

R170

ALVISO_BGA1257
Low = DMI x 2
CFG5
High = DMI x 4
*
2

PM-C0-SA0091501D0(R3)&SA0091501E0(R1)
10/20 mils
Low = DDR-II
GM-B1-SA0091500A0(R3)&SA009150070(R1)
CFG6 *
High = DDR-I
Low = DT/Transportable CPU
CFG7
High = Mobile CPU
*
Low = Reverse Lane
CFG9
High = Normal Operation
*
+VCCP +VCCP +VCCP +1.8V 00 = Reserved
01 = XOR Mode Enabled
CFG[13:12] 10 = All Z Mode Enabled
11 = Normal Operation (Default)
*
1
221_0603_1%

221_0603_1%
1

1
200_0402_1% 100_0402_1%

R174 CFG16
1

R173

R168

10K_0402_1% Low = Disabled


(FSB Dynamic
R156

100mil ODT) High = Enabled


*
2
V_DDR_MCH_REF
<12> V_DDR_MCH_REF
2

0.1U_0402_16V4Z

H_VREF H_SWNG0 H_SWNG1 CFG18 Low = 1.05V (Default)


*
2
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

A (VCC Select) A
0.1U_0402_16V4Z

1 1 1 High = 1.5V
1

1
100_0402_1%

100_0402_1%

1 1 R172
C237

R160

R169

R167

C22

C252

10K_0402_1% CFG19 Low = 1.05V (Default)


2 2 2 (VTT Select)
*
C253

C247

High = 1.2V
2

2 2
2

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Alviso(1 of 5) Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 7 of 43
5 4 3 2 1
5 4 3 2 1

D D

U5C U5D
DDR_A_D[0..63] <12>
DDR_A_BS#0 AK15 AG35 DDR_A_D0 AJ15 AE31
<12> DDR_A_BS#0 SA_BS0# SADQ0 SB_BS0# SBDQ0
DDR_A_BS#1 AK16 AH35 DDR_A_D1 AG17 AE32
<12> DDR_A_BS#1 SA_BS1# SADQ1 SB_BS1# SBDQ1
DDR_A_BS#2 AL21 AL35 DDR_A_D2 AG21 AG32
<12> DDR_A_BS#2 SA_BS2# SADQ2 SB_BS2# SBDQ2
AL37 DDR_A_D3 AG36
<12> DDR_A_DM[0..7] SADQ3 SBDQ3
DDR_A_DM0 AJ37 AH36 DDR_A_D4 AF32 AE34
DDR_A_DM1 SA_DM0 SADQ4 DDR_A_D5 SB_DM0 SBDQ4
AP35 SA_DM1 SADQ5 AJ35 AK34 SB_DM1 SBDQ5 AE33
DDR_A_DM2 AL29 AK37 DDR_A_D6 AK27 AF31
DDR_A_DM3 SA_DM2 SADQ6 DDR_A_D7 SB_DM2 SBDQ6
AP24 SA_DM3 SADQ7 AL34 AK24 SB_DM3 SBDQ7 AF30
DDR_A_DM4 AP9 AM36 DDR_A_D8 AJ10 AH33
DDR_A_DM5 SA_DM4 SADQ8 DDR_A_D9 SB_DM4 SBDQ8
AP4 SA_DM5 SADQ9 AN35 AK5 SB_DM5 SBDQ9 AH32
DDR_A_DM6 AJ2 AP32 DDR_A_D10 AE7 AK31
DDR_A_DM7 SA_DM6 SADQ10 DDR_A_D11 SB_DM6 SBDQ10
AD3 SA_DM7 SADQ11 AM31 AB7 SB_DM7 SBDQ11 AG30
AM34 DDR_A_D12 AG34
<12> DDR_A_DQS[0..7] SADQ12 SBDQ12
DDR_A_DQS0 AK36 AM35 DDR_A_D13 This Symbol as same AF34 AG33
DDR_A_DQS1 AP33 SA_DQS0 SADQ13 DDR_A_D14 SB_DQS0 SBDQ13
SA_DQS1 SADQ14 AL32 as Intel CRB AK32 SB_DQS1 SBDQ14 AH31
DDR_A_DQS2 AN29 AM32 DDR_A_D15 AJ28 AJ31
DDR_A_DQS3 AP23 SA_DQS2 SADQ15
AN31 DDR_A_D16 schematic, So Layout AK23
SB_DQS2 SBDQ15
AK30
DDR_A_DQS4 AM8 SA_DQS3 SADQ16 DDR_A_D17 Guide will show these SB_DQS3 SBDQ16
SA_DQS4 SADQ17 AP31 AM10 SB_DQS4 SBDQ17 AJ30
DDR_A_DQS5 AM4 AN28 DDR_A_D18 signals routed AH6 AH29
DDR_A_DQS6 SA_DQS5 SADQ18 DDR_A_D19 SB_DQS5 SBDQ18
AJ1 SA_DQS6 SADQ19 AP28 differentially. AF8 SB_DQS6 SBDQ19 AH28
DDR_A_DQS7 AE5 AL30 DDR_A_D20 AB4 AK29
SA_DQS7 SADQ20 DDR_A_D21 SB_DQS7 SBDQ20
<12> DDR_A_DQS#[0..7] SADQ21 AM30 SBDQ21 AH30
DDR_A_DQS#0 AK35 AM28 DDR_A_D22 AF35 AH27

DDR SYSTEM MEMORY B


DDR_A_DQS#1 SA_DQS0# SADQ22 DDR_A_D23 SB_DQS0# SBDQ22
AP34 AL28 AK33 AG28

DDR MEMORY SYSTEM A


DDR_A_DQS#2 SA_DQS1# SADQ23 DDR_A_D24 SB_DQS1# SBDQ23
AN30 SA_DQS2# SADQ24 AP27 AK28 SB_DQS2# SBDQ24 AF24
DDR_A_DQS#3 AN23 AM27 DDR_A_D25 AJ23 AG23
C DDR_A_DQS#4 SA_DQS3# SADQ25 DDR_A_D26 SB_DQS3# SBDQ25 C
AN8 SA_DQS4# SADQ26 AM23 AL10 SB_DQS4# SBDQ26 AJ22
DDR_A_DQS#5 AM5 AM22 DDR_A_D27 AH7 AK22
DDR_A_DQS#6 SA_DQS5# SADQ27 DDR_A_D28 SB_DQS5# SBDQ27
AH1 SA_DQS6# SADQ28 AL23 AF7 SB_DQS6# SBDQ28 AH24
DDR_A_DQS#7 AE4 AM24 DDR_A_D29 AB5 AH23
SA_DQS7# SADQ29 DDR_A_D30 SB_DQS7# SBDQ29
<12> DDR_A_MA[0..13] SADQ30 AN22 SBDQ30 AG22
DDR_A_MA0 AL17 AP22 DDR_A_D31 AH17 AJ21
DDR_A_MA1 SA_MA0 SADQ31 DDR_A_D32 SB_MA0 SBDQ31
AP17 SA_MA1 SADQ32 AM9 AK17 SB_MA1 SBDQ32 AG10
DDR_A_MA2 AP18 AL9 DDR_A_D33 AH18 AG9
DDR_A_MA3 SA_MA2 SADQ33 DDR_A_D34 SB_MA2 SBDQ33
AM17 SA_MA3 SADQ34 AL6 AJ18 SB_MA3 SBDQ34 AG8
DDR_A_MA4 AN18 AP7 DDR_A_D35 AK18 AH8
DDR_A_MA5 SA_MA4 SADQ35 DDR_A_D36 SB_MA4 SBDQ35
AM18 SA_MA5 SADQ36 AP11 AJ19 SB_MA5 SBDQ36 AH11
DDR_A_MA6 AL19 AP10 DDR_A_D37 AK19 AH10
DDR_A_MA7 SA_MA6 SADQ37 DDR_A_D38 SB_MA6 SBDQ37
AP20 SA_MA7 SADQ38 AL7 AH19 SB_MA7 SBDQ38 AJ9
DDR_A_MA8 AM19 AM7 DDR_A_D39 AJ20 AK9
DDR_A_MA9 SA_MA8 SADQ39 DDR_A_D40 SB_MA8 SBDQ39
AL20 SA_MA9 SADQ40 AN5 AH20 SB_MA9 SBDQ40 AJ7
DDR_A_MA10 AM16 AN6 DDR_A_D41 AJ16 AK6
DDR_A_MA11 SA_MA10 SADQ41 DDR_A_D42 SB_MA10 SBDQ41
AN20 SA_MA11 SADQ42 AN3 AG18 SB_MA11 SBDQ42 AJ4
DDR_A_MA12 AM20 AP3 DDR_A_D43 AG20 AH5
DDR_A_MA13 SA_MA12 SADQ43 DDR_A_D44 SB_MA12 SBDQ43
AM15 SA_MA13 SADQ44 AP6 AG15 SB_MA13 SBDQ44 AK8
AM6 DDR_A_D45 AJ8
DDR_A_CAS# AN15 SADQ45 DDR_A_D46 SBDQ45
<12> DDR_A_CAS# SA_CAS# SADQ46 AL4 AH14 SB_CAS# SBDQ46 AJ5
DDR_A_RAS# AP16 AM3 DDR_A_D47 AK14 AK4
<12> DDR_A_RAS# SA_RAS# SADQ47 SB_RAS# SBDQ47
T21 PAD~D TP_MA_RCVENIN# AF29 AK2 DDR_A_D48 AF15 AG5
T22 PAD~D TP_MA_RCVENOUT# AF28 SA_RCVENIN# SADQ48 DDR_A_D49 SB_RCVENIN# SBDQ48
SA_RCVENOUT# SADQ49 AK3 AF14 SB_RCVENOUT# SBDQ49 AG4
DDR_A_WE# AP15 AG2 DDR_A_D50 AH16 AD8
<12> DDR_A_WE# SA_WE# SADQ50 SB_WE# SBDQ50
AG1 DDR_A_D51 AD9
SADQ51 DDR_A_D52 SBDQ51
SADQ52 AL3 SBDQ52 AH4
AM2 DDR_A_D53 AG6
SADQ53 DDR_A_D54 SBDQ53
SADQ54 AH3 SBDQ54 AE8
AG3 DDR_A_D55 AD7
SADQ55 DDR_A_D56 SBDQ55
SADQ56 AF3 SBDQ56 AC5
AE3 DDR_A_D57 AB8
B SADQ57 DDR_A_D58 SBDQ57 B
SADQ58 AD6 SBDQ58 AB6
AC4 DDR_A_D59 AA8
SADQ59 DDR_A_D60 SBDQ59
SADQ60 AF2 SBDQ60 AC8
AF1 DDR_A_D61 AC7
SADQ61 DDR_A_D62 SBDQ61
SADQ62 AD4 SBDQ62 AA4
AD5 DDR_A_D63 AA5
SADQ63 SBDQ63

ALVISO_BGA1257 ALVISO_BGA1257

A A

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Alviso(2 of 5) Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 8 of 43
5 4 3 2 1
5 4 3 2 1

D D

+1.5VS_PCIE
R125
U5G 24.9_0402_1%
R5 1 2 @ 0_0402_5% H24 D36 PEGCOMP 1 2
SDVOCTRL_DATA EXP_COMPI
H25 SDVOCTRL_CLK EXP_ICOMPO D34
T46 PAD AB29

MISC
<16> CLK_MCH_3GPLL# GCLKN
<16> CLK_MCH_3GPLL AC29 GCLKP EXP_RXN0/SDVO_TVCLKIN# E30
EXP_RXN1/SDVO_INT# F34
EXP_RXN2/SDVO_FLDSTALL# G30
1 2 COMPS A15 H34
150_0402_1% R334 1 LUMA TVDAC_A EXP_RXN3
2 C16 TVDAC_B EXP_RXN4 J30
150_0402_1% R335 1 2 CRMA A17 K34
150_0402_1% R336 TVDAC_C EXP_RXN5
J18 TV_REFSET EXP_RXN6 L30

4.99K_0603_1%
B15 TV_IRTNA EXP_RXN7 M34

1
B16 TV_IRTNB EXP_RXN8 N30
B17 P34

TV
TV_IRTNC EXP_RXN9

R392
EXP_RXN10 R30
EXP_RXN11 T34
C C
TV Enable: R334,R335,R336 :75 ohm U30

2
EXP_RXN12
EXP_RXN13 V34
TV Disable: R334,R335,R336 :150 ohm EXP_RXN14 W30
CRT_SMBCLK E24 Y34
<15> CRT_SMBCLK DDCCLK EXP_RXN15
CRT_SMBDAT E23
<15> CRT_SMBDAT DDCDATA
<15> CRT_BLU E21 BLUE EXP_RXP0/SDVO_TVCLKIN D30
D21 BLUE# EXP_RXP1/SDVO_INT E34
<15> CRT_GRN C20 GREEN EXP_RXP2/SDVO_FLDSTALL F30
B20 GREEN# EXP_RXP3 G34
<15> CRT_RED A19 RED EXP_RXP4 H30
B19 RED# EXP_RXP5 J34
H21 K30

VGA
<15> VSYNC VSYNC EXP_RXP6
<15> HSYNC G21 HSYNC EXP_RXP7 L34

PCI - EXPRESS GRAPHICS


1 2 J20 REFSET EXP_RXP8 M30
R143 N34
EXP_RXP9
EXP_RXP10 P30
255_0402_1% R34
+2.5VS EXP_RXP11
EXP_RXP12 T30
EXP_RXP13 U34
EXP_RXP14 V30
EXP_RXP15 W34
BIA E25
<14> BIA LBKLT_CTL
BK_EN F25 E32
<14,29> BK_EN LBKLT_EN EXP_TXN0/SDVOB_RED#
C23 LCTLA_CLK EXP_TXN1/SDVOB_GREEN# F36
1 2 LCD_CLK C22 G32
R133 2.2K_0402_5% LCD_CLK LCTLB_DATA EXP_TXN2/SDVOB_BLUE#
<14> LCD_CLK F23 LDDC_CLK EXP_TXN3/SDVOB_CLKN H36
1 2 LCD_DAT LCD_DAT F22 J32
<14> LCD_DAT LDDC_DATA EXP_TXN4/SDVOC_RED#
R140 2.2K_0402_5% EN_LCDVDD F26 K36
<14> EN_LCDVDD LVDD_EN EXP_TXN5/SDVOC_GREEN#
2 1 C33 LIBG EXP_TXN6/SDVOC_BLUE# L32
C31 LVBG EXP_TXN7/SDVOC_CLKN M36
R128 1.5K_0402_1% F28 N32
LVREFH EXP_TXN8
F27 LVREFL EXP_TXN9 P36
B B
EXP_TXN10 R32
LVDSAC- B30 T36
<14> LVDSAC- LACLKN EXP_TXN11
LVDSAC+ B29 U32
<14> LVDSAC+ LACLKP EXP_TXN12
LVDS

LVDSBC- C25 V36


<14> LVDSBC- LBCLKN EXP_TXN13
LVDSBC+ C24 W32
<14> LVDSBC+ LBCLKP EXP_TXN14
EXP_TXN15 Y36
LVDSA0- B34
<14> LVDSA0- LADATAN0
LVDSA1- B33
<14> LVDSA1- LADATAN1
LVDSA2- B32 D32
<14> LVDSA2- LADATAN2 EXP_TXP0/SDVOB_RED
EXP_TXP1/SDVOB_GREEN E36
EXP_TXP2/SDVOB_BLUE F32
LVDSA0+ A34 G36
<14> LVDSA0+ LADATAP0 EXP_TXP3/SDVOB_CLKP
LVDSA1+ A33 H32
<14> LVDSA1+ LADATAP1 EXP_TXP4/SDVOC_RED
LVDSA2+ B31 J36
<14> LVDSA2+ LADATAP2 EXP_TXP5/SDVOC_GREEN
EXP_TXP6/SDVOC_BLUE K32
EXP_TXP7/SDVOC_CLKP L36
EXP_TXP8 M32
LVDSB0- C29 N36
<14> LVDSB0- LBDATAN0 EXP_TXP9
LVDSB1- D28 P32
<14> LVDSB1- LBDATAN1 EXP_TXP10
LVDSB2- C27 R36
<14> LVDSB2- LBDATAN2 EXP_TXP11
EXP_TXP12 T32
EXP_TXP13 U36
EXP_TXP14 V32
LVDSB0+ C28 W36
<14> LVDSB0+ LBDATAP0 EXP_TXP15
LVDSB1+ D27
<14> LVDSB1+ LBDATAP1
LVDSB2+ C26
<14> LVDSB2+ LBDATAP2

ALVISO_BGA1257

A A
08/09 Add B channel

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Alviso(3 of 5) Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 9 of 43
5 4 3 2 1
5 4 3 2 1

U5F

K13 VTT0 VCCSM0 AM37 V2.5_DDR_CAP1 +VCCP W=20 mils


J13 AH37 V2.5_DDR_CAP2
VTT1 VCCSM1 V2.5_DDR_CAP5 U5E
K12 VTT2 VCCSM2 AP29
W11 VTT3 VCCSM3 AD28
V11 VTT4 VCCSM4 AD27 T29 VCC0 VCCA_TVDACA0 F17
U11 VTT5 VCCSM5 AC27 R29 VCC1 VCCA_TVDACA1 E17
T11 VTT6 VCCSM6 AP26 N29 VCC2 VCCA_TVDACB0 D18

10U_0805_6.3V6M

0.1U_0402_16V4Z
R11 AN26 V2.5_DDR_CAP1 M29 C18
P11
N11
VTT7
VTT8
VTT9
POWER VCCSM7
VCCSM8
VCCSM9
AM26
AL26
V2.5_DDR_CAP2
V2.5_DDR_CAP5 1 1
K29
J29
VCC3
VCC4
VCC5
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
F18
E18

C212

C202
M11 VTT10 VCCSM10 AK26 1 1 1 V28 VCC6
D D

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
L11 AJ26 U28 H18
VTT11 VCCSM11 VCC7
POWER VCCA_TVBG

C192

C23

C24
K11 VTT12 VCCSM12 AH26 T28 VCC8 VSSA_TVBG G18
2 2 +2.5VS +2.5VS
W10 VTT13 VCCSM13 AG26 R28 VCC9
2 2 2
V10 VTT14 VCCSM14 AF26 P28 VCC10 VCCD_TVDAC D19
+VCCP U10 AE26 N28 H17
VTT15 VCCSM15 VCC11 VCCDQ_TVDAC +1.5VS

0.01U_0402_16V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z
T10 VTT16 VCCSM16 AP25 M28 VCC12

10U_0805_6.3V6M

10U_0805_6.3V6M
R10 VTT17 VCCSM17 AN25 L28 VCC13 VCCD_LVDS0 B26 +1.5VS
P10 VTT18 VCCSM18 AM25 K28 VCC14 VCCD_LVDS1 B25

0.1U_0402_16V4Z
N10 VTT19 VCCSM19 AL25 J28 VCC15 VCCD_LVDS2 A25 1 1 1 1 1 1

C182

C185

C38

C40
4.7U_0805_10V4Z

2.2U_0603_6.3V4Z

M10 VTT20 VCCSM20 AK25 H28 VCC16

C249
K10 VTT21 VCCSM21 AJ25 G28 VCC17 VCCA_LVDS A35 +2.5VS

C206
1 1 J10 VTT22 VCCSM22 AH25 Note : All VCCSM pin V27 VCC18 2 2 2 2 2 2
C217

C232

Y9 AG25 U27 B22 +2.5VS


W9
VTT23 VCCSM23
AF25 shorted internally. T27
VCC19 VCCHV0
B21 +2.5VS
VTT24 VCCSM24 VCC20 VCCHV1
2 2
U9 VTT25 VCCSM25 AE25 R27 VCC21 VCCHV2 A21 VCCA_LVDS VCCHV
R9 AE24 P27 C196 1 1 VCCD_LVDS
VTT26 VCCSM26 VCC22 4.7U_0805_10V4Z C195
P9 VTT27 VCCSM27 AE23 N27 VCC23 VCCTX_LVDS0 B28
N9 AE22 V1.8_DDR_CAP6 M27 A28 0.1U_0402_16V4Z
VTT28 VCCSM28 V1.8_DDR_CAP4 VCC24 VCCTX_LVDS1 +1.5VS_DDRDLL L7 +1.5VS
M9 VTT29 VCCSM29 AE21 L27 VCC25 VCCTX_LVDS2 A27
2 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
L9 AE20 V1.8_DDR_CAP3 K27 BLM18PG600SN1_0603
VTT30 VCCSM30 VCC26
J9 VTT31 VCCSM31 AE19 1 1 1 J27 VCC27 VCCA_SM0 AF20 2 1

C248

C246

C239

0.1U_0402_16V4Z
N8 VTT32 VCCSM32 AE18 H27 VCC28 VCCA_SM1 AP19
+1.5VS_PCIE +1.5VS

100U_D2_6.3VM
0.1U_0402_16V4Z
M8 AE17 K26 AF19 1 L1
VTT33 VCCSM33 VCC29 VCCA_SM2 BLM18PG600SN1_0603
N7 VTT34 VCCSM34 AE16 H26 VCC30 VCCA_SM3 AF18 1 1
2 2 2

C222
M7 AE15 K25 + 2 1
VTT35 VCCSM35 VCC31

C44

C243
0.47U_0603_16V7K

0.1U_0402_16V4Z
N6 VTT36 VCCSM36 AE14 J25 VCC32 VCC3G0 AE37
+1.5VS_3GPLL +1.5VS

10U_0805_6.3V6M

10U_0805_6.3V6M
0.22U_0603_10V7K
M6 AP13 K24 W37 R13 L3
VTT37 VCCSM37 VCC33 VCC3G1 2 2 2

220U_D2_4VM
A6 AN13 K23 U37 1 0.5_0805_1% BLM18PG600SN1_0603 1
VTT38 VCCSM38 VCC34 VCC3G2
N5 VTT39 VCCSM39 AM13 Note: Place near chip. K22 VCC35 VCC3G3 R37 1 1 1 1 23GRLL_R2 1

10U_0805_6.3V6M
+

C547

C16

C17

C18
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 M5 VTT40 VCCSM40 AL13 K21 VCC36 VCC3G4 N37
C65

N4 VTT41 VCCSM41 AK13 W20 VCC37 VCC3G5 L37


+1.8V 2

C28
M4 VTT42 VCCSM42 AJ13 U20 VCC38 VCC3G6 J37 1 1 1
2 2 2 2

C21
C C
N3 VTT43 VCCSM43 AH13 T20 VCC39
2

C193

C194
M3 VTT44 VCCSM44 AG13 K20 VCC40
N2 VTT45 VCCSM45 AF13 V19 VCC41 2 2 2
10U_0805_6.3V6M

10U_0805_6.3V6M

M2 AE13 @ U19 Y29


VTT46 VCCSM46 VCC42 VCCA_3GPLL0
330U_D2E_2.5VM
B2 VTT47 VCCSM47 AP12 1 K19 VCC43 VCCA_3GPLL1 Y28
V1 VTT48 VCCSM48 AN12 1 1 W18 VCC44 VCCA_3GPLL2 Y27
+2.5VS_3GBG +2.5VS
C201

C236

C35

N1 AM12 + V18 L2
VTT49 VCCSM49 VCC45 CHB1608U301_0603
M1 VTT50 VCCSM50 AL12 T18 VCC46
G1 VTT51 VCCSM51 AK12 K18 VCC47 VCCA_3GBG F37 2 1
2 2 2
VCCSM52 AJ12 K17 VCC48 VSSA_3GBG G37 1 1
1 1 1 VCCSM53 AH12
C245

C244

C254
0.47U_0603_16V7K

0.22U_0603_10V7K

0.22U_0603_10V7K

AG12 +1.5VS AC1 H20 +2.5VS C20 C19


VCCSM54 VCCD_HMPLL1 VCC_SYNC L21 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VCCSM55 AF12 AC2 VCCD_HMPLL2 1
+2.5VS_CRT_DAC 2 2
VCCSM56 AE12 +1.5VS_DPLLA B23 VCCA_DPLLA VCCA_CRTDAC0 F19 1 2
2 2 2 CHB1608U301_0603 + C443
VCCSM57 AD11 +1.5VS_DPLLB C35 VCCA_DPLLB VCCA_CRTDAC1 E19
@150U_D2_6.3VM

0.1U_0402_16V4Z
VCCSM58 AC11 +1.5VS_HPLL AA1 VCCA_HPLL VSSA_CRTDAC G19
VCCSM59 AB11 +1.5VS_MPLL AA2 VCCA_MPLL C220 2
VCCSM60 AB10
VCCSM61 AB9 1 1 0.022U_0402_16V7K
+2.5VS

C221
AP8 V1.8_DDR_CAP6 ALVISO_BGA1257
VCCSM62 V1.8_DDR_CAP4
VCCSM63 AM1
V1.8_DDR_CAP3
Route VSSA3GBG gnd from GMCH to
VCCSM64 AE1
2 2 decoupling cap ground lead and

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_6.3V6M
ALVISO_BGA1257
then connect to the gnd plane.
@ 1 1 1

C216

C214

C215
+1.8V CRTDAC: Route caps within
L6 +1.5VS_DPLLA 250mil of Alviso. Route FB 2 2 2
CHB1608U301_0603
+VCCP within 3" of Alviso.
+1.5VS 1 2
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

B B
0.1U_0402_16V4Z

1 1 1 1 1 1 Route VSSACRTDAC gnd from GMCH to


1 1 1 1 1 1 VCC_SYNC
decoupling cap ground lead and then
C230

C211

C235

C234

C199

C198

1
C209

C205 +
470U_D2_2.5VM 2 2 2 2 2 2 C542 C543 C544 C545 C546
connect to the gnd plane.
2 2 2 2 2
2 2
10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z
10U_0805_6.3V6M 0.1U_0402_16V4Z

L5 +1.5VS_DPLLB L9 +1.5VS_HPLL L8 +1.5VS_MPLL


CHB1608U301_0603 CHB1608U301_0603 CHB1608U301_0603
+1.5VS 1 2 +1.5VS 1 2 +1.5VS 1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1
1 1 1 R714
C186

C250

+ + +
C242

C188 C73 C145 D30 10_0805_1%


470U_D2_2.5VM 470U_D2_2.5VM 470U_D2_2.5VM 2 1 +VCCP_CRTDAC_D 1 2 +2.5VS_CRTDAC
+VCCP
2 2 2 2 2 2 RB751V_SOD323
PJP13
+2.5VS 2 1
A PAD-SHORT 2x2m A

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Alviso(4 of 5) Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 10 of 43
5 4 3 2 1
5 4 3 2 1

+VCCP U5H +1.8V

D D
L12 VTT_NCTF17 VCCSM_NCTF31 AB12
M12 VTT_NCTF16 VCCSM_NCTF30 AC12
N12 VTT_NCTF15 VCCSM_NCTF29 AD12
P12 VTT_NCTF14 VCCSM_NCTF28 AB13
R12 VTT_NCTF13 VCCSM_NCTF27 AC13
T12 VTT_NCTF12 VCCSM_NCTF26 AD13
U12 VTT_NCTF11 VCCSM_NCTF25 AC14
V12 VTT_NCTF10 VCCSM_NCTF24 AD14
W12 VTT_NCTF9 VCCSM_NCTF23 AC15
L13 AD15 U5I U5J
VTT_NCTF8 VCCSM_NCTF22
M13 VTT_NCTF7 VCCSM_NCTF21 AC16
N13 VTT_NCTF6 VCCSM_NCTF20 AD16 Y1 VSS271 AL24 VSS267
P13 VTT_NCTF5 VCCSM_NCTF19 AC17 D2 VSS270 VSSALVDS B36 AN24 VSS266 VSS67 AC32
R13 VTT_NCTF4 VCCSM_NCTF18 AD17 G2 VSS269 A26 VSS265 VSS66 AD32
T13 VTT_NCTF3 VCCSM_NCTF17 AC18 J2 VSS268 VSS195 AA11 E26 VSS264 VSS65 AJ32
U13 VTT_NCTF2 VCCSM_NCTF16 AD18 L2 VSS260 VSS194 AF11 G26 VSS263 VSS64 AN32
V13 VTT_NCTF1 VCCSM_NCTF15 AC19 P2 VSS259 VSS193 AG11 J26 VSS262 VSS63 D33
W13 VTT_NCTF0 VCCSM_NCTF14 AD19 T2 VSS258 VSS192 AJ11 B27 VSS261 VSS62 E33
VCCSM_NCTF13 AC20 V2 VSS257 VSS191 AL11 E27 VSS129 VSS61 F33
VCCSM_NCTF12 AD20 AD2 VSS256 VSS190 AN11 G27 VSS128 VSS60 G33
Y12 VSS_NCTF68 VCCSM_NCTF11 AC21 AE2 VSS255 VSS189 B12 W27 VSS127 VSS59 H33
AA12
Y13
AA13
L14
M14
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VCCSM_NCTF10
VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
AD21
AC22
AD22
AC23
AD23
AH2
AL2
AN2
A3
C3
VSS254
VSS253
VSS252
VSS251
VSS
VSS188
VSS187
VSS186
VSS185
D12
J12
A14
B14
F14
AA27
AB27
AF27
AG27
AJ27
VSS126
VSS125
VSS124
VSS123
VSS VSS58
VSS57
VSS56
VSS55
J33
K33
L33
M33
N33
VSS_NCTF63 VCCSM_NCTF6 VSS250 VSS184 VSS122 VSS54
N14 VSS_NCTF62 VCCSM_NCTF5 AC24 AA3 VSS249 VSS183 J14 AL27 VSS121 VSS53 P33
P14 VSS_NCTF61 VCCSM_NCTF4 AD24 AB3 VSS248 VSS182 K14 AN27 VSS120 VSS52 R33
R14 VSS_NCTF60 VCCSM_NCTF3 AC25 AC3 VSS247 VSS181 AG14 E28 VSS119 VSS51 T33
T14 VSS_NCTF59 VCCSM_NCTF2 AD25 AJ3 VSS246 VSS180 AJ14 W28 VSS118 VSS50 U33
U14 VSS_NCTF58 VCCSM_NCTF1 AC26 C4 VSS245 VSS179 AL14 AA28 VSS117 VSS49 V33
V14 VSS_NCTF57 VCCSM_NCTF0 AD26 H4 VSS244 VSS178 AN14 AB28 VSS116 VSS48 W33
C C
W14 VSS_NCTF56 L4 VSS243 VSS177 C15 AC28 VSS115 VSS47 AD33
Y14 VSS_NCTF55 VCC_NCTF78 L17 +VCCP P4 VSS242 VSS176 K15 A29 VSS114 VSS46 AF33
AA14 VSS_NCTF54 VCC_NCTF77 M17 U4 VSS241 VSS175 A16 D29 VSS113 VSS45 AL33
AB14 VSS_NCTF53 VCC_NCTF76 N17 Y4 VSS240 VSS174 D16 E29 VSS112 VSS44 C34
L15 VSS_NCTF52 VCC_NCTF75 P17 AF4 VSS239 VSS173 H16 F29 VSS111 VSS43 AA34
M15 T17 AN4 K16 G29 AB34
NCTF

VSS_NCTF51 VCC_NCTF74 VSS238 VSS172 VSS110 VSS42


N15 VSS_NCTF50 VCC_NCTF73 U17 E5 VSS237 VSS171 AL16 H29 VSS109 VSS41 AC34
P15 VSS_NCTF49 VCC_NCTF72 V17 W5 VSS236 VSS170 C17 L29 VSS108 VSS40 AD34
R15 VSS_NCTF48 VCC_NCTF71 W17 AL5 VSS235 VSS169 G17 P29 VSS107 VSS39 AH34
T15 VSS_NCTF47 VCC_NCTF70 L18 AP5 VSS234 VSS168 AF17 U29 VSS106 VSS38 AN34
U15 VSS_NCTF46 VCC_NCTF69 M18 B6 VSS233 VSS167 AJ17 V29 VSS105 VSS37 B35
V15 VSS_NCTF45 VCC_NCTF68 N18 J6 VSS232 VSS166 AN17 W29 VSS104 VSS36 D35
W15 VSS_NCTF44 VCC_NCTF67 P18 L6 VSS231 VSS165 A18 AA29 VSS103 VSS35 E35
Y15 VSS_NCTF43 VCC_NCTF66 R18 P6 VSS230 VSS164 B18 AD29 VSS102 VSS34 F35
AA15 VSS_NCTF42 VCC_NCTF65 Y18 T6 VSS229 VSS163 U18 AG29 VSS101 VSS33 G35
AB15 VSS_NCTF41 VCC_NCTF64 L19 AA6 VSS228 VSS162 AL18 AJ29 VSS100 VSS32 H35
L16 VSS_NCTF40 VCC_NCTF63 M19 AC6 VSS227 VSS161 C19 AM29 VSS99 VSS31 J35
M16 VSS_NCTF39 VCC_NCTF62 N19 AE6 VSS226 VSS160 H19 C30 VSS98 VSS30 K35
N16 VSS_NCTF38 VCC_NCTF61 P19 AJ6 VSS225 VSS159 J19 Y30 VSS97 VSS29 L35
P16 VSS_NCTF37 VCC_NCTF60 R19 G7 VSS224 VSS158 T19 AA30 VSS96 VSS28 M35
R16 VSS_NCTF36 VCC_NCTF59 Y19 V7 VSS223 VSS157 W19 AB30 VSS95 VSS27 N35
T16 VSS_NCTF35 VCC_NCTF58 L20 AA7 VSS222 VSS156 AG19 AC30 VSS94 VSS26 P35
U16 VSS_NCTF34 VCC_NCTF57 M20 AG7 VSS221 VSS155 AN19 AE30 VSS93 VSS25 R35
V16 VSS_NCTF33 VCC_NCTF56 N20 AK7 VSS220 VSS154 A20 AP30 VSS92 VSS24 T35
W16 VSS_NCTF32 VCC_NCTF55 P20 AN7 VSS219 VSS153 D20 D31 VSS91 VSS23 U35
Y16 VSS_NCTF31 VCC_NCTF54 R20 C8 VSS218 VSS152 E20 E31 VSS90 VSS22 V35
AA16 VSS_NCTF30 VCC_NCTF53 Y20 E8 VSS217 VSS151 F20 F31 VSS89 VSS21 W35
AB16 VSS_NCTF29 VCC_NCTF52 L21 L8 VSS216 VSS150 G20 G31 VSS88 VSS20 Y35
R17 VSS_NCTF28 VCC_NCTF51 M21 P8 VSS215 VSS149 V20 H31 VSS87 VSS19 AE35
Y17 VSS_NCTF27 VCC_NCTF50 N21 Y8 VSS214 VSS148 AK20 J31 VSS86 VSS18 C36
AA17 VSS_NCTF26 VCC_NCTF49 P21 AL8 VSS213 VSS147 C21 K31 VSS85 VSS17 AA36
AB17 VSS_NCTF25 VCC_NCTF48 T21 A9 VSS212 VSS146 F21 L31 VSS84 VSS16 AB36
B B
AA18 VSS_NCTF24 VCC_NCTF47 U21 H9 VSS211 VSS145 AF21 M31 VSS83 VSS15 AC36
AB18 VSS_NCTF23 VCC_NCTF46 V21 K9 VSS210 VSS144 AN21 N31 VSS82 VSS14 AD36
AA19 VSS_NCTF22 VCC_NCTF45 W21 T9 VSS209 VSS143 A22 P31 VSS81 VSS13 AE36
AB19 VSS_NCTF21 VCC_NCTF44 L22 V9 VSS208 VSS142 D22 R31 VSS80 VSS12 AF36
AA20 VSS_NCTF20 VCC_NCTF43 M22 AA9 VSS207 VSS141 E22 T31 VSS79 VSS11 AJ36
AB20 VSS_NCTF19 VCC_NCTF42 N22 AC9 VSS206 VSS140 J22 U31 VSS78 VSS10 AL36
R21 VSS_NCTF18 VCC_NCTF41 P22 AE9 VSS205 VSS139 AH22 V31 VSS77 VSS9 AN36
Y21 VSS_NCTF17 VCC_NCTF40 R22 AH9 VSS204 VSS138 AL22 W31 VSS76 VSS8 E37
AA21 VSS_NCTF16 VCC_NCTF39 T22 AN9 VSS203 VSS137 H23 AD31 VSS75 VSS7 H37
AB21 VSS_NCTF15 VCC_NCTF38 U22 D10 VSS202 VSS136 AF23 AG31 VSS74 VSS6 K37
Y22 VSS_NCTF14 VCC_NCTF37 V22 L10 VSS201 VSS135 B24 AL31 VSS73 VSS5 M37
AA22 VSS_NCTF13 VCC_NCTF36 W22 Y10 VSS200 VSS134 D24 A32 VSS72 VSS4 P37
AB22 VSS_NCTF12 VCC_NCTF35 L23 AA10 VSS199 VSS133 F24 C32 VSS71 VSS3 T37
Y23 VSS_NCTF11 VCC_NCTF34 M23 F11 VSS198 VSS132 J24 Y32 VSS70 VSS2 V37
AA23 VSS_NCTF10 VCC_NCTF33 N23 H11 VSS197 VSS131 AG24 AA32 VSS69 VSS1 Y37
AB23 VSS_NCTF9 VCC_NCTF32 P23 Y11 VSS196 VSS130 AJ24 AB32 VSS68 VSS0 AG37
Y24 VSS_NCTF8 VCC_NCTF31 R23
AA24 VSS_NCTF7 VCC_NCTF30 T23
AB24 VSS_NCTF6 VCC_NCTF29 U23
Y25 V23 ALVISO_BGA1257 ALVISO_BGA1257
VSS_NCTF5 VCC_NCTF28
AA25 VSS_NCTF4 VCC_NCTF27 W23
AB25 VSS_NCTF3 VCC_NCTF26 L24
Y26 VSS_NCTF2 VCC_NCTF25 M24
AA26 VSS_NCTF1 VCC_NCTF24 N24
AB26 VSS_NCTF0 VCC_NCTF23 P24
VCC_NCTF22 R24
V25 VCC_NCTF10 VCC_NCTF21 T24
W25 VCC_NCTF9 VCC_NCTF20 U24
L26 VCC_NCTF8 VCC_NCTF19 V24
M26 VCC_NCTF7 VCC_NCTF18 W24
N26 VCC_NCTF6 VCC_NCTF17 L25
P26 VCC_NCTF5 VCC_NCTF16 M25
A A
R26 VCC_NCTF4 VCC_NCTF15 N25
T26 VCC_NCTF3 VCC_NCTF14 P25
U26 VCC_NCTF2 VCC_NCTF13 R25
V26 VCC_NCTF1 VCC_NCTF12 T25
W26 VCC_NCTF0 VCC_NCTF11 U25

ALVISO_BGA1257
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Alviso(5 of 5) Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 11 of 43
5 4 3 2 1
A B C D E

+1.8V +1.8V
+1.8V +1.8V DDR_A_D[0..63]
V_DDR_MCH_REF <8> DDR_A_D[0..63]
V_DDR_MCH_REF <7> DDR_A_DM[0..7]
<8> DDR_A_DM[0..7]

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 1 JP44
C562 1 2 DDR_A_DQS[0..7]
C563 VREF VSS DDR_A_D4 <8> DDR_A_DQS[0..7]
3 VSS DQ4 4 1 1
1 220P_0402_50V7K 220P_0402_50V7K DDR_A_D0 5 6 DDR_A_D5 DDR_A_MA[0..13] 1
2 2 DQ0 DQ5 <8> DDR_A_MA[0..13]

C564

C565
DDR_A_D1 7 8
DQ1 VSS DDR_A_DM0 DDR_A_DQS#[0..7]
9 VSS DM0 10 <8> DDR_A_DQS#[0..7]
DDR_A_DQS#0 2 2
11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D6 Layout Note:
DQS0 DQ6 DDR_A_D7
15 16
DDR_A_D2 17
VSS DQ7
18 +1.8V Place near DIMM
+1.8V +1.8V DDR_A_D3 DQ2 VSS DDR_A_D12
19 DQ3 DQ12 20
21 22 DDR_A_D13
DDR_A_D8 VSS DQ13
23 DQ8 VSS 24
1 1 DDR_A_D9 25 26 DDR_A_DM1
C566 DQ9 DM1
27 VSS VSS 28 1 1 1 1 1
C567 DDR_A_DQS#1 29 30 M_CLK_DDR0 C568 C569 C570 C571 C572
DQS1# CK0 M_CLK_DDR0 <7>
220P_0402_50V7K 220P_0402_50V7K DDR_A_DQS1 31 32 M_CLK_DDR#0
2 2 DQS1 CK0# M_CLK_DDR#0 <7>

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z
33 VSS VSS 34
DDR_A_D10 DDR_A_D14 2 2 2 2 2
35 DQ10 DQ14 36
DDR_A_D11 37 38 DDR_A_D15 +1.8V
DQ11 DQ15
39 VSS VSS 40
@ 10U_0805_10V4Z @ 10U_0805_10V4Z @ 10U_0805_10V4Z
+1.8V
1 1 1 1 1 1 1
41 42 C573 C574 C575 C576 C577 C578 C579
DDR_A_D16 VSS VSS DDR_A_D20
43 DQ16 DQ20 44

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 DDR_A_D17 45 46 DDR_A_D21
C580 DQ17 DQ21 2 2 2 2 2 2 2
47 VSS VSS 48 1 1 1 1

C581

C582

C583

C584
DDR_A_DQS#2 49 50 @ 10U_0805_10V4Z @ 10U_0805_10V4Z @ 10U_0805_10V4Z @ 10U_0805_10V4Z
220P_0402_50V7K DDR_A_DQS2 DQS2# NC DDR_A_DM2
51 DQS2 DM2 52
2
53 VSS VSS 54
DDR_A_D18 DDR_A_D22 2 2 2 2
55 DQ18 DQ22 56
DDR_A_D19 57 58 DDR_A_D23
DQ19 DQ23
59 VSS VSS 60
DDR_A_D24 61 62 DDR_A_D28
DDR_A_D25 DQ24 DQ28 DDR_A_D29 +1.8V
63 64
2 0304 EMI DDR_A_DM3
65
DQ25
VSS
DQ29
VSS 66
DDR_A_DQS#3
2
67 DM3 DQS3# 68
69 70 DDR_A_DQS3 1 1
NC DQS3
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D30 + +
DDR_A_D27 DQ26 DQ30 DDR_A_D31 C585 C586
75 DQ27 DQ31 76
77 78 150U_D2_6.3VM 150U_D2_6.3VM
DDR_CKE0_DIMMA VSS VSS DDR_CKE1_DIMMA 2 2
<7> DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA <7>
81 VDD VDD 82
83 NC NC/A15 84
DDR_A_BS#2 85 86
<8> DDR_A_BS#2 BA2 NC/A14
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7 +1.8V
91 A9 A7 92
DDR_A_MA8 93 94 DDR_A_MA6
A8 A6
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4 1 1 1 1 1 1 1 1 1
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0 C587 C588 C589 C590 C591 C592 C593 C594 C595
A1 A0 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
103 VDD VDD 104
DDR_A_MA10 DDR_A_BS#1 2 2 2 2 2 2 2 2 2
105 A10/AP BA1 106 DDR_A_BS#1 <8>
DDR_A_BS#0 107 108 DDR_A_RAS#
<8> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <8>
DDR_A_WE# 109 110 DDR_CS0_DIMMA# 0.1U_0402_16V4Z
<8> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
<8> DDR_A_CAS# CAS# ODT0 M_ODT0 <7>
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
<7> DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
M_ODT1 119 120 +0.9VS
<7> M_ODT1 NC/ODT1 NC
121 VSS VSS 122
DDR_A_D32 123 124 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37
125 DQ33 DQ37 126

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
127 VSS VSS 128
3 DDR_A_DQS#4 DDR_A_DM4 3
129 DQS4# DM4 130
DDR_A_DQS4 131 132 1 1 1 1 1 1 1 1 1 1 1 1 1
DQS4 VSS DDR_A_D38
133 VSS DQ38 134
DDR_A_D34 135 136 DDR_A_D39
DDR_A_D35 DQ34 DQ39
137 DQ35 VSS 138
DDR_A_D44 2 2 2 2 2 2 2 2 2 2 2 2 2
139 VSS DQ44 140

C596

C597

C598

C599

C600

C601

C602

C603

C604

C605

C606

C607

C608
DDR_A_D40 141 142 DDR_A_D45
DDR_A_D41 DQ40 DQ45
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150 Layout Note:
DDR_A_D42 151 152 DDR_A_D46
DDR_A_D43 153
DQ42 DQ46
154 DDR_A_D47 Place one cap close to every 2 pullup
DQ43 DQ47
155 VSS VSS 156 resistors terminated to +0.9VS
DDR_A_D48 157 158 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
161 162 +0.9VS
VSS VSS M_CLK_DDR1
163 NC,TEST CK1 164 M_CLK_DDR1 <7>
165 166 M_CLK_DDR#1 R645 1 2 56_0402_5% DDR_A_MA0 Layout Note:
VSS CK1# M_CLK_DDR#1 <7>
DDR_A_DQS#6 167 168 R646 1 2 56_0402_5% DDR_A_MA1 Place these resistor
DDR_A_DQS6 DQS6# VSS DDR_A_DM6 DDR_A_MA2 R647 1
169 DQS6 DM6 170 2 56_0402_5% closely DIMM0,all
171 172 DDR_A_MA4 R648 1 2 56_0402_5% R649 1 2 56_0402_5% DDR_A_MA3
DDR_A_D50 VSS VSS DDR_A_D54 R650 1 trace length<750 mil
173 DQ50 DQ54 174 2 56_0402_5% DDR_A_MA6
DDR_A_D51 175 176 DDR_A_D55 DDR_A_MA5 R651 1 2 56_0402_5%
DQ51 DQ55 DDR_A_MA8 R652 1
177 VSS VSS 178 2 56_0402_5% R653 1 2 56_0402_5% DDR_A_MA7
DDR_A_D56 179 180 DDR_A_D60 R654 1 2 56_0402_5% DDR_A_MA9
DDR_A_D57 DQ56 DQ60 DDR_A_D61 DDR_A_MA10 R655 1
181 DQ57 DQ61 182 2 56_0402_5%
183 184 DDR_A_MA11 R656 1 2 56_0402_5% R657 1 2 56_0402_5% DDR_A_MA12
DDR_A_DM7 VSS VSS DDR_A_DQS#7 R658 1 DDR_A_MA13
185 DM7 DQS7# 186 2 56_0402_5%
187 188 DDR_A_DQS7 DDR_A_BS#0 R659 1 2 56_0402_5% Layout Note:
DDR_A_D58 VSS DQS7 DDR_A_BS#2 R660 1
189 DQ58 VSS 190 2 56_0402_5% R661 1 2 56_0402_5% DDR_A_BS#1 Place these resistor
DDR_A_D59 191 192 DDR_A_D62 R662 1 2 56_0402_5% DDR_A_WE#
4 DQ59 DQ62 DDR_A_D63 DDR_A_RAS# R663 1
closely DIMM0,all 4
193 VSS DQ63 194 2 56_0402_5%
CK_SDATA 195 196 DDR_CKE0_DIMMA R664 1 2 56_0402_5% R665 1 2 56_0402_5% DDR_A_CAS# trace length
<16> CK_SDATA SDA VSS Max=1.3"
CK_SCLK 197 198 R666 1 2 10K_0402_5% R667 1 2 56_0402_5% DDR_CS0_DIMMA#
<16> CK_SCLK SCL SAO
+3VS 199 200 R668 1 2 10K_0402_5% DDR_CKE1_DIMMA R669 1 2 56_0402_5%
VDDSPD SA1 M_ODT1 R670 1 DDR_CS1_DIMMA#
2 56_0402_5% R671 1 2 56_0402_5%
1 2 R672 1 2 56_0402_5% M_ODT0
C609 FOX_ASOA426-M4R-TR
0.1U_0402_16V4Z CONN@ Compal Electronics, Inc.
Title
DDR2-SODIMM SLOT0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3361P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 12 of 43
A B C D E
5 4 3 2 1

C 1

B E 2 3

2222 SYMBOL(SOT23-NEW)

D D

+3VS

2
C1449

0.1U_0402_16V4Z
1
U40
H_THERMDA 1 8 SMB_EC_CK2
<4> H_THERMDA VDD SCLK
1
2 7 SMB_EC_DA2
C1450 D+ SDATA
H_THERMDC 2200P_0402_50V7K 3 6
<4> H_THERMDC 2 D- ALERT#
THERM# 4 5
THERM# GND
C R1919 C

+3VS 1 2 ADM1032AR_SOP8

10K_0402_5%

<29> SMB_EC_CK2 SMB_EC_CK2


SMB_EC_DA2
<29> SMB_EC_DA2

PWM Fan Control circuit


+5VS

JP50

1
1 1 1

1
B D38 C1451 C1452 B
2
R2011 RB751V_SOD323 4.7U_0805_10V4Z 0.1U_0402_16V4Z ACES_85205-0200
@ 10K_0402_5% 2 2 CONN@

2
2
+3VS FAN

1
2
5
6

1
5

U41 D Q48 @ ZD1


1 G
P

<29> FAN_PWM INB


4 3 SI3456DV-T1_TSOP6 RLZ5.1B_LL34
THERM# O S
2

2
INA
G

TC7SH00FU_SSOP5
3

A A

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Thermal sensor and Fan Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 13 of 43
5 4 3 2 1
5 4 3 2 1

+LCDVDD

1 1
C12 C13

0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2

D D

LVDS connector
JP3

INVPWR_B+ 1 2 LVDSA2+ LVDSA2+ <9>


3 4 LVDSA2-
5 6 LVDSA2- <9>
7 8 LVDSA1+
+LCDVDD 9 10 LVDSA1+ <9>
LVDSA1-
11 12 LVDSA1- <9>
+3VS 13 14 LVDSA0+
15 16 LVDSA0+ <9>
LVDSBC+ LVDSA0-
<9> LVDSBC+ 17 18 LVDSA0- <9>
LVDSBC-
<9> LVDSBC- 19 20 LVDSAC+
LVDSB0+ 21 22 LVDSAC- LVDSAC+ <9>
<9> LVDSB0+ 23 24 LVDSAC- <9>
LVDSB0-
<9> LVDSB0- 25 26 INVTPWM
27 28
Aviso LCD/PANEL BD. CONN.
C1533

C1534

C1535

LVDSB1+ DISPLAYOFF#
<9> LVDSB1+ 29 30
LVDSB1- DAC_BRIG
<9> LVDSB1- 31 32 DAC_BRIG <29>
LCDP_CLK +LCDVDD
LVDSB2+ 33 34 LCDP_DAT +LCDVDD +3VS
<9> LVDSB2+ 35 36
LVDSB2- +5VALW
<9> LVDSB2- 37 38
680P_0402_50V7K

680P_0402_50V7K

680P_0402_50V7K

680P_0402_50V7K

680P_0402_50V7K
39 40
1 8/18
1

1
ACES_88107-4000G

S
1 3

D
C CONN@ R102 C

2
Q1
2

2
2 100_0402_5% R8 SI2301BDS_SOT23

G
2
C1536

C1537
47K_0402_5%

2
0809 Change pin define

1
1
D
0711 EMI request Q3 2
0711 EMI request 2N7002_SOT23 G

1
S

3
1 1
R2016 C2
1 2 2 C1532 C31
<9> EN_LCDVDD
4.7U_0805_10V4Z 4.7U_0805_10V4Z
0_0402_5% 0.047U_0402_16V7K 2 2
B+ INVPWR_B+ Q2
C1551 DTC124EK_SC59

3
L34 1 2 0_0805_5% 8/18
8/18 @ 0.01U_0402_16V7K
@ L35
1 2
FBMA-L11-201209-221LMA30T_0805

0711 EMI request

B B

+3VS
1

R14 R10
2.2K_0402_5% 2.2K_0402_5%
2006/08/09 +3VS
Q5
2

BSS138_SOT23 R1

2
+3VALW C117 @ 1 2
R9 <29> INVT_PWM
S

3 1 LCDP_CLK 0.1U_0402_16V4Z R120


<9> LCD_CLK +3VS
2 1 2 1 3.3K_0402_5% 0_0402_5%
14

+2.5VS U13A
G
2

1
100K_0402_5%

5
LCD EEPROM 1 U1
P

<9,29> BK_EN A
3 DISPLAYOFF# R2

P
O
2
G

2 1 2 2 4 INVTPWM
<29> BKOFF# B <9> BIA A Y
G

G
3 1 LCDP_DAT @ SN74LVC08APW_TSSOP14 0_0402_5%
<9> LCD_DAT
7

@ NC7SZ14M5X_SOT23-5
S

3
2 1
BSS138_SOT23 R22 @ 100K_0402_5%
Q6 R2014
1 2

0_0402_5%

A A

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
LVDS connector Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 14 of 43
5 4 3 2 1
5 4 3 2 1

CRT CONNECTOR +2.5VS

1
D D21 D22 D23 D

DAN217_SC59DAN217_SC59DAN217_SC59

3
CRT_VCC

@ @ @
JP45
MSEN# SUYIN_070112FR015S222XU
<29> MSEN#
6
11
CRT_RED L26 1 2 BK2125LL121_0805 CRTL_R 1
<9> CRT_RED
7
SMBDAT 12 16
CRT_GRN L27 1 2 BK2125LL121_0805 CRTL_G 2 17
<9> CRT_GRN
8
13
CRT_BLU L28 1 2 BK2125LL121_0805 CRTL_B 3
<9> CRT_BLU
9

1
1 1 1 1 1 1 14
+5VS C610 C611 C612 C613 C614 C615 4
R673 R674 R675 10
75_0402_1% 75_0402_1% 75_0402_1% SMBCLK 15
2 2 2 2 2 2
5

2
5

U35 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J22P_0402_50V8J


L29 CONN@
P

OE#

HSYNC 2 4 R46 2 1 0_0402_5% 1 2 CRT_HSYNCRFL


<9> HSYNC A Y FBMA-L11-160808-800LMT_0603
G

C 74AHCT1G125GW_SOT353-5 L30 C
3

R47 2 1 0_0402_5% 1 2 CRT_VSYNCRFL


1 FBMA-L11-160808-800LMT_0603

C616 +5VS
0.1U_0402_16V4Z
2
1 1 1
5

2
U36 C617 C618 C619
D24 D25
P

OE#

VSYNC 2 4 10P_0402_50V8J 10P_0402_50V8J 220P_0402_25V8K


<9> VSYNC A Y 2 2 2
G

74AHCT1G125GW_SOT353-5 @ DAN217_SC59 @ DAN217_SC59


3

1
+2.5VS
B +5VS R_CRT_VCC CRT_VCC B

D26 F1
2 1 1 2

1
RB411D_SOT23 1A_6VDC_MINISMDC110
1 R676 R677
R679
C620 2.2K_0402_5% 2.2K_0402_5%
0.1U_0402_16V4Z R680 4.7K_0402_5%

2
2 Q44
2N7002_SOT23
4.7K_0402_5%
SMBDAT CRT_SMBDAT

S
1 3 CRT_SMBDAT <9>

Q45

G
2
2N7002_SOT23

SMBCLK CRT_SMBCLK

S
1 3 CRT_SMBCLK <9>

G
2
1 1
C621 C622

220P_0402_25V8K 220P_0402_25V8K
2 2

A A
+3VS

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
CRT Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3361P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 15 of 43
5 4 3 2 1
5 4 3 2 1

+3VS +CK_VDD_MAIN
L31
+3VS

0.1U_0402_16V4Z
1 2

10K_0402_5%

10K_0402_5%
KC FBM-L11-201209-221LMAT_0805 2 1 1 1 1 CLK_MCH_BCLK 2 1

1
1 C483 C478 R332 49.9_0402_1%
C432 C473 C435 0.047U_0402_16V4Z CLK_MCH_BCLK# 2 1

R330

R349

C474
0713 EMI Request 10U_0805_10V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z R333 49.9_0402_1%
1 2 2 2 2 CLK_CPU_BCLK 2 1
2 R321 49.9_0402_1%

2
CLK_CPU_BCLK# 2 1
ICH_SMBDATA CK_SDATA R322 49.9_0402_1%

S
<19> ICH_SMBDATA 1 3 CK_SDATA <12>
Q36 CLK_ITP 2 1
2N7002_SOT23 R319 49.9_0402_1%
CLK_ITP# 2 1
Place near each pin

G
2
R320 49.9_0402_1%
D D
+3VS
L32
+CK_VDD_MAIN2 W>40 mil

2
G
1 2
Q38 KC FBM-L11-201209-221LMAT_0805 CLK_PCIE_ICH 1 2
<19> ICH_SMBCLK
ICH_SMBCLK 1 3 2N7002_SOT23 CK_SCLK
CK_SCLK <12>
2
C469
1 1
Place near ICS954226 R420 49.9_0402_1%
C429 C477 CLK_PCIE_ICH# 1 2

S
0713 EMI Request 10U_0805_10V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z R421 49.9_0402_1%
1 2 2 CLK_MCH_3GPLL 1 2

0.047U_0402_16V4Z
D R367 R345 49.9_0402_1%
CK_VDD_A CK_VDD_48 CK_VDD_REF 2.2_0603_5% CLK_MCH_3GPLL# 1 2

0.047U_0402_16V4Z
1 1 1 1 1 1 1 2 CK_VDD_A R346 49.9_0402_1%

4.7U_0805_10V4Z

4.7U_0805_10V4Z

0.047U_0402_16V4Z
U28
G 2 3 S

C444

C434

C460
21 VDDPCIEX_0
2 2 2 2 2 R390 49.9_0402_1%
28 VDDPCIEX_1 VDDA 37

C475

C433
34 SSC_DREFCLK 1 2
2N7002 VDDPCIEX_2
GNDA 38 R391 49.9_0402_1%
1 SSC_DREFCLK# 1 2
VDDPCI_0
7 VDDPCI_1
55 H_STP_PCI# DREFCLK R418
1 2 49.9_0402_1%
PCI/SRC_STOP# H_STP_PCI# <19>
0 0 1 for Dothan-B 533Mhz Place crystal within 54 H_STP_CPU# DREFCLK# 1 2
CPU_STOP# H_STP_CPU# <19,37>
R419 49.9_0402_1%
1 0 1 for Dothan-B 400Mhz C428
500 mils of CKGEN
42 VDDCPU
33P_0402_50V8J 1 2CK_VDD_REF
48 VDDREF
2 1 CK_XTAL_IN R338
1_0603_5% 41 CK_CPU1 1 2 CLK_MCH_BCLK
FSC FSB FSA CPU SRC PCI CPUCLKT1 CLK_MCH_BCLK <7>

1
X1 14.318MHZ_20P_1BX14318BE1A 1 2CK_VDD_4811 R356 33_0402_5%
R368 VDD48 CK_CPU1# CLK_MCH_BCLK#
CLKSEL0 CLKSEL1 CLKSEL2 MHz MHz MHz CPUCLKC1 40 1 2 CLK_MCH_BCLK# <7>
2.2_0603_5% R357 33_0402_5%
C431 50

2
C 33P_0402_50V8J X1 C
0 0 0 266 100 33.3 CK_XTAL_OUT CK_CPU0 CLK_CPU_BCLK
2 1 49 X2 CPUCLKT0 44 1 2 CLK_CPU_BCLK <4>
R341 33_0402_5%
0 0 1 133 100 33.3 43 CK_CPU0# 1 2 CLK_CPU_BCLK#
* <19> CLK_48M_ICH
CLK_48M_ICH
CLKSEL0
R415 2 1 33_0402_5% CLKSEL2 12
53
FS_A/USB_48MHz
REF1/FSLC/TEST_SEL
CPUCLKC0 R342 33_0402_5%
CLK_CPU_BCLK# <4>

0 1 0 200 100 33.3 PS: When CB714 unpop, R415 12 Ohm change to 33 Ohm
CLKSEL1 16 36 CK_CPU2 1 2 CLK_ITP
FSLB/TEST_MODE CPUCLKT2_ITP/PCIEXT6 CLK_ITP <4>
0 1 1 166 100 33.3 R343 @ 33_0402_5%
35 CK_CPU2# 1 2 CLK_ITP#
CPUCLKC2_ITP/PCIEXC6 CLK_ITP# <4>
R344 @ 33_0402_5%
1 0 0 333 100 33.3 CLK_33M_CBS 2 1 PCICLK5 5
<23> CLK_33M_CBS PCICLK5
R375 33_0402_5%
4 PCICLK4 PEREQ1#/PCIEXT5 33
1 0 1 100 100 33.3 CLK_33M_MPCI PCICLK3
<24> CLK_33M_MPCI 2 1 3 PCICLK3 PEREQ2#/PCIEXC5 32
R377 33_0402_5%
1 1 0 400 100 33.3 56 PCICLK2/REQ_SEL
PCIEXT4 31
CLK_33M_ICH 2 1 PCICLKF1 9
<17> CLK_33M_ICH SELPCIEX_LCDCLK#/PCICLK_F1
1 1 0 RESERVED R379 33_0402_5% 30
CLK_33M_LPCEC PCIEXC4
<29> CLK_33M_LPCEC 2 1
Table : ICS 954226 R376 33_0402_5%
+3VS 1 2 PCICLKF0 8 26
R385 10K_0402_5% ITP_EN/PCICLK_F0 SATACLKT
CK_SCLK 46 27
SCLK SATACLKC

+VCCP CK_SDATA 47 24 SRC5 1 2 CLK_MCH_3GPLL


SDATA PCIEXT3 CLK_MCH_3GPLL <9>
R352 33_0402_5%
25 SRC5# 1 2 CLK_MCH_3GPLL#
B PCIEXC3 CLK_MCH_3GPLL# <9> B
1 2 CLKIREF 39 R353 33_0402_5%
IREF
2

R329 R323 475_0402_1%


PCIEXT2 22
10K_0402_5%
R451 R331
PCIEXC2 23
CLKSEL0 1 2 2 1 MCH_CLKSEL0 <7>
1

19 SRC1 1 2 CLK_PCIE_ICH
4.7K_0402_5% 1K_0402_5% PCIEXT1 CLK_PCIE_ICH <19>
R410 33_0402_5%
1 2 20 SRC1# 1 2 CLK_PCIE_ICH#
<5> CPU_BSEL0 PCIEXC1 CLK_PCIE_ICH# <19>
13 R411 33_0402_5%
GND_0
2

R339 +3VS
0_0402_5% R340 29 17 SRC0 1 2 SSC_DREFCLK
GND_1 LCDCLK_SS/PCIEX0T SSC_DREFCLK <7>
R382 33_0402_5%
2

@ 10K_0402_5% 2 18 SRC0# 1 2 SSC_DREFCLK#


GND_2 LCDCLK_SS/PCIEX0C SSC_DREFCLK# <7>
R389 R383 33_0402_5%
1

10K_0402_5% 45 GND_3 DOTCLK R408 1


DOTT_96MHz 14 2 33_0402_5% DREFCLK DREFCLK <7>
51 15 DOTCLK#R409 1 2 DREFCLK# +3VS
DREFCLK# <7>
1

CLKSEL2 GND_4 DOTC_96MHz 33_0402_5%


+VCCP 6 GND_5
2

1
R416 R398
2

@ 10K_0402_5% 10K_0402_5%
<19,37> VGATE
R401
1

2
10K_0402_5% 10
VTT_PWRGD#/PD
R400
1

1
CLKREF CLK_14M_ICH D
REF0 52 1 2 CLK_14M_ICH <19>
CLKSEL1 2 1 R355 33_0402_5% 2
MCH_CLKSEL1 <7>
1 2 CLK_14M_SIO Q42 G
CLK_14M_SIO <29>
ICS954226AGT_TSSOP56 R2010 33_0402_5% 2N7002_SOT23 S

3
A 1K_0402_5% A
<5> CPU_BSEL1 1 2 Table : ICS 954226
R394
2

0_0402_5%
R395
@ 10K_0402_5%

Compal Electronics, Inc.


1

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Clock Generator Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 16 of 43
5 4 3 2 1
5 4 3 2 1

Change to DAU00 REQ/GNT# Setting


REQ/GNT#0 for MINI PCI
RP45 REQ/GNT#2 for Cardbus
+3VS 1 8 PCI_SERR#
2 7 PCI_FRAME# U9B
<23,24> PCI_AD[0..31]
3 6 PCI_TRDY# PCI_AD0 E2 L5 PCI_REQ0#
AD[0] REQ[0]# PCI_REQ0# <24>
PCI_STOP# PCI_AD1 PCI_GNT0#
4 5
PCI_AD2
E5
C2
AD[1] PCI GNT[0]# C1
B5 PCI_REQ1#
PCI_GNT0# <24> +3VALW
8.2K_0804_8P4R_5% PCI_AD3 AD[2] REQ[1]#
F5 AD[3] GNT[1]# B6
PCI_AD4 PCI_REQ2#

14
F3 AD[4] REQ[2]# M5 PCI_REQ2# <23>
D PCI_AD5 PCI_GNT2# U13D D
E9 AD[5] GNT[2]# F1 PCI_GNT2# <23>
PCI_AD6 F2 B8 PCI_REQ3# 12

P
PCI_AD7 AD[6] REQ[3]# A
D6 AD[7] GNT[3]# C8 O 11
RP43 PCI_AD8 E6 F7 PCI_REQ4# 13
AD[8] REQ[4]#/GPI[40] B

G
PCI_AD9 D3 E7
+3VS PCI_PERR# PCI_AD10 AD[9] GNT[4]#/GPO[48] PCI_REQ5# @ SN74LVC08APW_TSSOP14
1 8 A2 E8

7
PCI_DEVSEL# PCI_AD11 AD[10] REQ[5]#/GPI[1]
2 7 D2 AD[11] GNT[5]#/GPO[17] F6
3 6 PCI_PLOCK# PCI_AD12 D5 B7 EC_SCI#
AD[12] REQ[6]#/GPI[0] EC_SCI# <29>
4 5 PCI_IRDY# PCI_AD13 H3 D8
PCI_AD14 AD[13] GNT[6]#/GPO[16]
B4 AD[14]
8.2K_0804_8P4R_5% PCI_AD15 J5 J6 PCI_C_BE0#
AD[15] C/BE[0]# PCI_C_BE0# <23,24> +3VALW
RP44 PCI_AD16 K2 H6 PCI_C_BE1#
AD[16] C/BE[1]# PCI_C_BE1# <23,24>
PCI_AD17 PCI_C_BE2#

14
K5 AD[17] C/BE[2]# G4 PCI_C_BE2# <23,24>
+3VS 1 8 PCI_PIRQC# PCI_AD18 D4 G2 PCI_C_BE3# U13B
AD[18] C/BE[3]# PCI_C_BE3# <23,24>
2 7 PCI_PIRQH# PCI_AD19 L6 PLTRST# 4 R63 33_0402_5%

P
PCI_PIRQD# PCI_AD20 AD[19] PCI_IRDY# A PCIRSTB2#
3 6 G3 AD[20] IRDY# A3 PCI_IRDY# <23,24> O 6 1 2 PLTRST_MCH# <7,21,23>
4 5 PCI_PIRQB# PCI_AD21 H4 E1 PCI_PAR 5
AD[21] PAR PCI_PAR <23,24> B

G
PCI_AD22 H2 R2 PCI_PCIRST#
8.2K_0804_8P4R_5% PCI_AD23 AD[22] PCIRST# PCI_DEVSEL#
H5 C3 PCI_DEVSEL# <23,24>

7
PCI_AD24 AD[23] DEVSEL# PCI_PERR# @ SN74LVC08APW_TSSOP14
B3 AD[24] PERR# E3 PCI_PERR# <23,24>
PCI_AD25 M6 C5 PCI_PLOCK#
PCI_AD26 AD[25] PLOCK# PCI_SERR#
B2 AD[26] SERR# G5 PCI_SERR# <23,24>
RP47 PCI_AD27 K6 J1 PCI_STOP# R48 2 1 0_0402_5%
AD[27] STOP# PCI_STOP# <23,24>
PCI_AD28 K3 J2 PCI_TRDY#
AD[28] TRDY# PCI_TRDY# <23,24>
1 8 PCI_PIRQA# PCI_AD29 A5
PCI_REQ4# PCI_AD30 AD[29] +3VALW
2 7 L1 AD[30]
3 6 PCI_PIRQG# PCI_AD31 K4
PCI_REQ1# AD[31] PLTRST#

14
4 5 PLTRST# R5
G6 CLK_33M_ICH U13C R61
PCICLK CLK_33M_ICH <16>
8.2K_0804_8P4R_5% PCI_FRAME# J3 P6 ICH_PME# PCI_PCIRST# 9 33_0402_5%

P
<23,24> PCI_FRAME# FRAME# PME# ICH_PME# <24,29> A
O 8PCIRSTB3# 1 2 PCIRST# <23,24,29>
RP48 Interrupt I/F 10 B

G
C PCI_PIRQA# PCI_PIRQE# C
N2 PIRQ[A]# PIRQ[E]#/GPI[2] D9 PCI_PIRQE# <24>
+3VS 1 8 PCI_REQ0# PCI_PIRQB# L2 C7 PCI_PIRQF#
PCI_PIRQF# <24>

7
PCI_PIRQF# PCI_PIRQC# PIRQ[B]# PIRQ[F]#/GPI[3] PCI_PIRQG# @ SN74LVC08APW_TSSOP14
2 7 <23> PCI_PIRQC# M1 PIRQ[C]# PIRQ[G]#GPI[4] C6
3 6 PCI_PIRQE# PCI_PIRQD# L3 M3 PCI_PIRQH# Change to DAU00 IRQ Setting
PCI_REQ3# PIRQ[D]# PIRQ[H]#/GPI[5]
4 5
RESERVED PCI_PIRQC# for Cardbus
8.2K_0804_8P4R_5% AC5 R49 2 1 0_0402_5%
8.2K_0402_5% SATA[1]RXN/RSVD[1]
1 2 R276 PCI_REQ2# AD5 SATA[1]RXP/RSVD[2] PCI_PIRQEF# for Mini PCI
AF4 SATA[1]TXN/RSVD[3]
AG4 SATA[1]TXP/RSVD[4]
AC9 SATA[3]RXN/RSVD[5]
AD9 SATA[3]RXP/RSVD[6]
+3VS 8.2K_0402_5% 1 2 R244 PCI_REQ5# AF8
8.2K_0402_5% EC_SCI# SATA[3]TXN/RSVD[7]
1 2 R261 AG8 SATA[3]TXP/RSVD[8]
U3 TP[3]/RSVD[9]
+3VALW 1 2 ICH_PME#
R254 @ 10K_0402_1% ICH6_BGA609
CLK_33M_ICH
PME# signal has an integrated pull-up of 18 k to 42 k SA8280108G0 S IC 030 FW82801FBM B2 BGA 609P ICH6-M ->
SA8280108E0(R3)/SA8280108D0(R1) S IC 030 FW82801FBM QS ICH6-M BGA 609P

2
R264
@ 10_0402_5%

1
1
C348
@ 8.2P_0402_50V
2

B B

A A

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
ICH6(1/4) Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 17 of 43
5 4 3 2 1
5 4 3 2 1

C115
15P_0402_50V8J
+RTCVCC 2 1 ICH_RTCX1
Y2

10M_0402_5%
1
2 NC IN 1
1

R65
R69 3 4
D NC OUT U9A D
LPC_LAD[0..3] <29>
1M_0402_5% 32.768KHZ_12.5P_1TJS125DJ2A073 C113

2
15P_0402_50V8J Y1 P2 LPC_LAD0 H_FERR# close as ICH6 0.5"+VCCP
2

RTCX1 LAD[0]/FWH[0]

RTC
INTRUDER# 2 1 ICH_RTCX2 Y2 N3 LPC_LAD1
RTCX2 LAD[1]/FWH[1] LPC_LAD2 R203
LAD[2]/FWH[2] N5
1 2 ICH_RTCRST# AA2 N4 LPC_LAD3 56_0402_5%

LPC
+RTCVCC +RTCVCC RTCRST# LAD[3]/FWH[3]
R67 H_FERR# 2 1
20K_0402_5% INTRUDER# AA3 N6 LPC_LDRQ0#
+3VALW INTRUDER# LDRQ[0]# LPC_LDRQ0# <29>
6/21 INTVRMEN AA5 P4 R202
JOPEN1 INTVRMEN LDRQ[1]#/GPI[41] @ 56_0402_5%
1

1 2 U42 P3 LPC_LFRAME# H_DPRSLP# 2 1


LFRAME#/FWH[4] LPC_LFRAME# <29>
R81 8 1 EEP_CS D12
SHORT PADS VCC CS EEP_SK EE_CS
7 NC SK 2 B12 EE_SHCLK
@ 330k_0402_5% C114 1 6 3 EEP_DOUT D11 AF22 GATEA20
NC DI EE_DOUT A20GATE GATEA20 <29>
1U_0603_10V4Z C1508 5 4 EEP_DIN F13 AF23 H_A20M#
H_A20M# <4>
2

INTVRMEN GND DO EE_DIN A20M#


1 2

LAN
0.1U_0402_16V4Z AT93C46-10SI-2.7_SO8 LAN_JCLK CPUSLP# R45 1 @ 0_0402_5% H_CPUSLP#

CPU
<22> LAN_JCLK F12 LAN_CLK CPUSLP# AE27 2 H_CPUSLP# <4,7>
1

2
R50 LAN_RSTSYNC B11 AE24 H_DPRSLP#
<22> LAN_RSTSYNC LAN_RSTSYNC DPRSLP#/TP[4] H_DPRSLP# <4>
0_0402_5% AD27 H_DPSLP#
DPSLP#/TP[2] H_DPSLP# <4>
<22> LAN_RXD0 LAN_RXD0 E12
LAN_RXD1 LANRXD[0] H_FERR#
<22> LAN_RXD1 E11 AF24 H_FERR# <4> MAINPWON <34,38>
2

LAN_RXD2 LANRXD[1] FERR#


<22> LAN_RXD2 C13 LANRXD[2]
6/21 AG25 H_PWRGOOD R193
CPUPWRGD/GPO[49] H_PWRGOOD <4>

1
LAN_TXD0 C12 @ 330_0402_5% C
<22> LAN_TXD0 LANTXD[0]
LAN_TXD1 C11 AG26 H_IGNNE# 1 2 2 Q21
<22> LAN_TXD1 LANTXD[1] IGNNE# H_IGNNE# <4> +VCCP B
LAN_TXD2 E13 AE22 @ 2SC2411K_SOT23
<22> LAN_TXD2 LANTXD[2] INIT3_3V#
AF27 H_INIT# 1 2 E
EMI H_INIT# <4>

3
C623 2 INIT#
1 1 R697 210_0402_5% INTR AG24 H_INTR
H_INTR <4>
@ C264
EEP_SK <25> AC97_BITCLK @ 10P_0402_25V8K AC97_BITCLK C10 @ 1U_0603_10V4Z
ACZ_BIT_CLK

AC-97/AZALIA
<25> AC97_SYNC AC97_SYNC B9 AD23 KBRST# 1 2 H_THERMTRIP#
ACZ_SYNC RCIN# KBRST# <29> +VCCP
1

C R194 C
R80 33_0402_5% 2 R703 1 AC97RST#A10 AF25 H_NMI 75_0402_5%
<25> AC97_RST# ACZ_RST# NMI H_NMI <4>
AG27 H_SMI#
SMI# H_SMI# <4>
20K_0402_5% AC97_SDIN0 F11
<25> AC97_SDIN0 ACZ_SDIN[0] <4,7> H_THERMTRIP#
F10 AE26 H_STPCLK#
H_STPCLK# <4>
2

ACZ_SDIN[1] STPCLK#
B10 ACZ_SDIN[2]
AE23 THRMTRIP_ICH# 1 2 R201 H_THERMTRIP#
AC97_SDOUT THRMTRIP# 56_0402_5%
<25> AC97_CODEC_SDOUT 1 2 C9 ACZ_SDO
R6 33_0402_5% R201 place within 2" from ICH
AC16 IDE_HDA0
Check list rev1.701 DA[0] IDE_HDA1
IDE_HDA0 <21> R194 place within 2" from R201
AC19 SATALED# DA[1] AB17 IDE_HDA1 <21>
AC17 IDE_HDA2
DA[2] IDE_HDA2 <21>
LAN_TXD0 AE3 AD16 IDE_HDCS1#
SATA[0]RXN DCS1# IDE_HDCS1# <21>
LAN_TXD1 AD3 AE17 IDE_HDCS3#
SATA[0]RXP DCS3# IDE_HDCS3# <21>
LAN_TXD2 AG2 SATA[0]TXN
33_0402_5%

AF2 SATA[0]TXP IDE_HDD[0..15] <21>


2

R2025 2
33_0402_5%

33_0402_5%

AD14 IDE_HDD0
DD[0]

SATA
AD7 AF15 IDE_HDD1
SATA[2]RXN DD[1]

PIDE
R2023

1R2024

0915 AC7 AF14 IDE_HDD2


SATA[2]RXP DD[2] IDE_HDD3
AF6 SATA[2]TXN DD[3] AD12
AG6 AE14 IDE_HDD4
1

+3VS +3VS SATA[2]TXP DD[4] IDE_HDD5


Colse to SB 1 1 1 DD[5] AC11
AC2 AD11 IDE_HDD6
SATA_CLKN DD[6]
C1554

33P_0402_50V8J

C1555

33P_0402_50V8J

C1556

33P_0402_50V8J

AC1 AB11 IDE_HDD7


SATA_CLKP DD[7] IDE_HDD8
DD[8] AE13
1

2 2 2 IDE_HDD9
AG11 SATARBIAS# DD[9] AF13
R187 R190 AF11 AB12 IDE_HDD10
@ 4.7K_0402_5% @ 8.2K_0402_5% SATARBIAS DD[10] IDE_HDD11
DD[11] AB13
AC13 IDE_HDD12
DD[12] IDE_HDD13
AE15
2

DD[13] IDE_HDD14
DD[14] AG15
B IDE_HIORDY IDE_HIRQ IDE_HIORDY IDE_HDD15 B
<21> IDE_HIORDY AF16 IORDY DD[15] AD13
IDE_HIRQ AB16
<21> IDE_HIRQ IDEIRQ
IDE_HDACK# AB15
<21> IDE_HDACK# DDACK#
IDE_HDIOW# AC14 AB14 IDE_HDREQ
<21> IDE_HDIOW# DIOW# DDREQ IDE_HDREQ <21>
IDE_HDIOR# AE16
<21> IDE_HDIOR# DIOR#

ICH6_BGA609

9/05
+3VLP
+RTCVCC
JP55

D42

1
2
R1923
BATT1.1
+ - BATT1

3 1 2 1 + - 2
W=20mils
2 DAN202U_SC70 1K_0402_5%

C1458 CR2032 RTC BATTERY


1U_0603_10V4Z
1 SUYIN_060003FA002TX00NL~D

A A

Compal Electronics, Inc.


Title
ICH6(2/4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LA-3361P 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 18 of 43
5 4 3 2 1
5 4 3 2 1

+3VALW +3VALW

+3VALW

2.2K_0402_5%

2.2K_0402_5%

10K_0402_5%

10K_0402_5%
+3VS

10K_0402_5%
1
RP2

R291

R289

R292

R290
1 8

R272
Reserve 2 7

1
3 6

1
Inform BIOS team 4 5

2
D U9C D
ICH_SMBDATA @ 10K_1206_8P4R_5% ICH_RI# T2 H25
<16> ICH_SMBDATA RI# PERn[1] PAD T31
ICH_SMBCLK RP1 H24
<16> ICH_SMBCLK PERp[1] PAD T33
ICH_SMLINK0 1 8 AF17 G27
SATA[0]GP/GPI[26] PETn[1] PAD T32
ICH_SMLINK1 2 7 AE18 G26
SATA[1]GP/GPI[29] PETp[1] PAD T34
3 6 AF18 SATA[2]GP/GPI[30]
+3VS 4 5 AG18 K25
SATA[3]GP/GPI[31] PERn[2]
PERp[2] K24
100_1206_8P4R_5%ICH_SMBCLK Y4 J27
SMBCLK PETn[2]

1
ICH_SMBDATA W5 J26

PCI-EXPRESS
LINKALERT# SMBDATA PETp[2]
Y5 LINKALERT#
R209 ICH_SMLINK0 W4 M25
SMLINK[0] PERn[3]

GPIO
8.2K_0402_5% ICH_SMLINK1 U6 M24
MCH_SYNC# SMLINK[1] PERp[3]
AG21 L27
2

SB_CLKRUN# SPKR MCH_SYNC# PETn[3]


5/30 <25> SPKR F8 SPKR PETp[3] L26

Requires a PU Resistor to Vcc3_3(CRB uses 8.2K to Vcc3_3) SUS_STAT# W3 P24


<30> SUS_STAT# SUS_STAT#/LPCPD# PERn[4]
CLK RUN no work to pull down PERp[4] P23
XDP_DBRESET# U2 N27
<4> XDP_DBRESET# SYS_RESET# PETn[4]
PETp[4] N26
PM_BMBUSY# AD19
<7> PM_BMBUSY# BM_BUSY#/GPI[6]
CLK_14M_ICH T25 DMI_RXN0
<16> CLK_14M_ICH DMI[0]RXN DMI_RXN0 <7>
GPI7 AE19 T24 DMI_RXP0
GPI[7] DMI[0]RXP DMI_RXP0 <7>
EC_SMI# R1 R27 DMI_TXN0
<29> EC_SMI# GPI[8] DMI[0]TXN DMI_TXN0 <7>
CLK_48M_ICH R26 DMI_TXP0
<16> CLK_48M_ICH DMI[0]TXP DMI_TXP0 <7>
<29> OVP_OV# 1 2 W6 SMBALERT#/GPI[11]

DIRECT MEDIA INTERFACE


R1924 0_0402_5% V25 DMI_RXN1
DMI[1]RXN DMI_RXN1 <7>
ICH6 VER1.5 GPI12 +3VS plan GPI12 M2 V24 DMI_RXP1
GPI[12] DMI[1]RXP DMI_RXP1 <7>
2

R6 U27 DMI_TXN1
<29> LID_SWOUT# GPI[13] DMI[1]TXN DMI_TXN1 <7>
2

U26 DMI_TXP1
DMI[1]TXP DMI_TXP1 <7>
R238 R186 H_STP_PCI# AC21
<16> H_STP_PCI# STP_PCI#/GPO[18]
Y25 DMI_RXN2
C DMI[2]RXN DMI_RXN2 <7> C
@ 10_0402_5% @ 10_0402_5% SB_INT_FLASH_SEL# AB21 Y24 DMI_RXP2
<30> SB_INT_FLASH_SEL# DMI_RXP2 <7>
1

GPO[19] DMI[2]RXP DMI_TXN2 OVCUR#0


W27 DMI_TXN2 <7> 1 2 USB_OC# <28>
1

H_STP_CPU# DMI[2]TXN DMI_TXP2 R17 @ 0_0402_5%


<16,37> H_STP_CPU# AD22 STP_CPU#/GPO[20] DMI[2]TXP W26 DMI_TXP2 <7>
2 2 OVCUR#1 1 2
C327 C269 AB24 DMI_RXN3 R18 @ 0_0402_5%
DMI[3]RXN DMI_RXN3 <7>
+3VS R210 1 2 @ 10K_0402_5% AD20 AB23 DMI_RXP3
GPO[21] DMI[3]RXP DMI_RXP3 <7>
@ 4.7P_0402_50V8C @ 4.7P_0402_50V8C AD21 AA27 DMI_TXN3
1 1 GPO[23] DMI[3]TXN DMI_TXN3 <7>
DMI_TXP3
GPIO 23 PLTRST_VGA# Delete 5/16 XMIT# V3
DMI[3]TXP AA26 DMI_TXP3 <7>
<24> XMIT# GPIO[24]
AD25 CLK_PCIE_ICH#
DMI_CLKN CLK_PCIE_ICH# <16>
P5 AC25 CLK_PCIE_ICH
GPIO[25] DMI_CLKP CLK_PCIE_ICH <16>
R3 GPIO[27]
T3 +1.5VS
<30> EC_FLASH# GPIO[28]
1 2 SB_CLKRUN# AF19 F24
<23,24,29> CLKRUN# CLKRUN#/GPIO[32] DMI_ZCOMP
R19 0_0402_5% AF20 R199 24.9_0402_1%
GPIO[33] DMI_IRCOMP
AC18 GPIO[34] DMI_IRCOMP F23 1 2
closed to 500 mils
+3VS ICH_PCIE_WAKE# U5 C23 OVCUR#4
WAKE# OC[4]#/GPI[9] OVCUR#5 +3VALW
OC[5]#/GPI[10] D23
+3VALW SIRQ AB20 C25 OVCUR#6
<23,29> SIRQ SERIRQ OC[6]#/GPI[14]
C24 OVCUR#7
THERM_SCI# OC[7]#/GPI[15] RP42
<29> THERM_SCI# AC20 THRM#
2 1 GPI7 C27 OVCUR#0 OVCUR#2 4 5
VGATE OC[0]# OVCUR#1 OVCUR#6
<16,37> VGATE AF21 VRMPWRGD OC[1]# B27 3 6
R23 10K_0402_5% B26 OVCUR#2 OVCUR#7 2 7
OVP_OV# OC[2]#
1 2 2 1 GPI12 +3VS power plan CLK_14M_ICH E10 CLK14 OC[3]# C26 OVCUR#3 OVCUR#5 1 8
R734 10K_0402_5%
R24 10K_0402_5% CLK_48M_ICH USBP0- 10K_1206_8P4R_5%

CLOCK
A27 CLK48 USBP[0]N C21 USBP0- <28>
T35 D21 USBP0+
USBP[0]P USBP0+ <28>
PAD ICH_SUSCLK V6 A20 USBP1-
SUSCLK USBP[1]N USBP1- <28> +3VALW
B20 USBP1+
USBP[1]P USBP1+ <28>
SLP_S3# T4 D19 USBP2-
B <29> SLP_S3# SLP_S3# USBP[2]N B
SLP_S4# T5 C19 USBP2+ RP46
<29> SLP_S4# SLP_S4# USBP[2]P

USB
SLP_S5# T6 A18 USBP3- OVCUR#0 4 5
<29> SLP_S5# SLP_S5# USBP[3]N
B18 USBP3+ OVCUR#3 3 6
ICH_PWRGD USBP[3]P OVCUR#1
<29> ICH_PWRGD AA1 PWROK USBP[4]N E17 2 7

POWER MGT
D17 08/10 OVCUR#4 1 8
PM_DPRSLPVR USBP[4]P
<37> PM_DPRSLPVR AE20 DPRSLPVR/TP[1] USBP[5]N B16
A16 10K_1206_8P4R_5%
Support wake on LAN R70 @ ICH_BATLOW# USBP[5]P
V2 BATLOW#/TP[0] USBP[6]N C15
Support wake on LAN R71 0 ohm
R271 PWRBTN_OUT# U1
USBP[6]P D15
A14
06/23 change R to RP
<29> PWRBTN_OUT# PWRBTN# USBP[7]N
10K_0402_5% B14
LINKALERT# USBP[7]P
+3VALW 1 2 <23,29> RSMRST# 1 2 V5 LAN_RST#
R70 0_0402_5% A22 USBRBIAS 1 2
R66 RSMRST# USBRBIAS#
Y3 RSMRST# USBRBIAS B22 USBPN/USBPP impedance 45 Ohm
10K_0402_5% 1 2 R51
<29> EC_LANRST#
+3VALW 1 2 XDP_DBRESET# @ R71 0_0402_5% ICH6_BGA609 22.6_0402_1%

1
10K_0402_5%

10K_0402_5%
JP59
1
2

2
1
R284

R278
R64 PM_DPRSLPVR USBP3+ 2
8.2K_0402_5% USBP3- 2
3 3
+3VALW 1 2 ICH_BATLOW# +5VALW 4 4
1

5 5
R267 R208 USBP2- 6
680_0402_5% USBP2+ 6
7 7
+3VALW 1 2 ICH_PCIE_WAKE# 100K_0402_5% 8
SYSON# 8
<28,31> SYSON# 9 11
2

OVCUR#2 9 G11
1 2 10 10 G12 12
R2017 @ 0_0402_5%
OVCUR#3 1 2 ACES_87212-10G0
A R2018 @ 0_0402_5% 08/14 A
CONN@
Signal has integrated pull-down in ICH
May need pulldown for DPRSLPVR in case
R205 08/10 Add two USB port to subboard
10K_0402_5% the ICH6m does not set this value in time
+3VS 1 2 MCH_SYNC# for boot.
R211
10K_0402_5% Compal Electronics, Inc.
+3VS 1 2 SIRQ Title
ICH6(3/4)
8.2 k pull-up to Vcc3_3(CRB uses 10 k) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LA-3361P 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 19 of 43
5 4 3 2 1
5 4 3 2 1

+1.5VS

C322
@ 0.1U_0402_16V4Z
Near PIN F27(C968), +1.5VS
1 2

L10 0_0603_5% P27(C949), AB27(C950) U9E C325


@ 0.1U_0402_16V4Z U9D
+1.5VS 1 2 +1.5VRUN_L AA22 VCC1_5[1] VCC1_5[98] F9 1 2 E27 VSS[172] VSS[86] F4
1 AA23 VCC1_5[2] VCC1_5[97] U17 Y6 VSS[171] VSS[85] F22
2 2 2 AA24 U16 C319 Y27 F19
+ VCC1_5[3] VCC1_5[96] @ 0.1U_0402_16V4Z VSS[170] VSS[84]
AA25 VCC1_5[4] VCC1_5[95] U14 Y26 VSS[169] VSS[83] F17
AB25 VCC1_5[5] VCC1_5[94] U12 1 2 Y23 VSS[168] VSS[82] E25
C261 C270 C268 C277 AB26 U11 W7 E19
D 2 1 1 1 VCC1_5[6] VCC1_5[93] C330 VSS[167] VSS[81] D
AB27 VCC1_5[7] VCC1_5[92] T17 W25 VSS[166] VSS[80] E18
220U_D2_4VM 0.1U_0402_16V4Z F25 T11 0.1U_0402_16V4Z W24 E15
0.1U_0402_16V4Z 0.1U_0402_16V4Z VCC1_5[8] VCC1_5[91] VSS[165] VSS[79]
F26 VCC1_5[9] VCC1_5[90] P17 1 2 W23 VSS[164] VSS[78] E14
+5VS +3VS
F27 VCC1_5[10] VCC1_5[89] P11 W1 VSS[163] VSS[77] D7
G22 M17 C334 V4 D22

CORE
D15 VCC1_5[11] VCC1_5[88] 0.1U_0402_16V4Z VSS[162] VSS[76]
G23 VCC1_5[12] VCC1_5[87] M11 V27 VSS[161] VSS[75] D20
2

G24 VCC1_5[13] VCC1_5[86] L17 1 2 V26 VSS[160] VSS[74] D18


R215 G25 L16 V23 D14
10_0402_5% VCC1_5[14] VCC1_5[85] C335 VSS[159] VSS[73]
H21 VCC1_5[15] VCC1_5[84] L14 U25 VSS[158] VSS[72] D13
H22 L12 0.1U_0402_16V4Z U24 D10
RB751V_SOD323 VCC1_5[16] VCC1_5[83] VSS[157] VSS[71]
J21 L11 1 2 U23 D1
1

VCC1_5[17] VCC1_5[82] VSS[156] VSS[70]


J22 VCC1_5[18] VCC1_5[81] AA21 U15 VSS[155] VSS[69] C4
ICH_V5REF_RUN K21 AA20 C339 U13 C22
VCC1_5[19] VCC1_5[80] 0.1U_0402_16V4Z VSS[154] VSS[68]
2 2 2 K22 VCC1_5[20] VCC1_5[79] AA19 T7 VSS[153] VSS[67] C20

PCIE
C310 C309 L21 1 2 T27 C18
1U_0603_10V4Z 0.1U_0402_16V4Z C312 VCC1_5[21] VSS[152] VSS[66]
L22 VCC1_5[22] T26 VSS[151] VSS[65] C14
@0.1U_0402_16V4Z M21 AA10 +3VS C346 T23 B25
1 1 1 VCC1_5[23] VCC3_3[21] VSS[150] VSS[64]

0.1U_0402_16V4Z

0.1U_0402_16V4Z
M22 AG19 0.1U_0402_16V4Z T16 B24
VCC1_5[24] VCC3_3[20] VSS[149] VSS[63]
N21 VCC1_5[25] VCC3_3[19] AG16 2 2 1 2 T15 VSS[148] VSS[62] B23

C317

C323
N22 VCC1_5[26] VCC3_3[18] AG13 T14 VSS[147] VSS[61] B21
N23 AD17 C296 T13 B19
VCC1_5[27] VCC3_3[17] 0.1U_0402_16V4Z VSS[146] VSS[60]
N24 VCC1_5[28] VCC3_3[16] AC15
1 1 Near PIN T12 VSS[145] VSS[59] B15
N25 AA17 1 2 T1 B13

IDE
P21
VCC1_5[29] VCC3_3[15]
AA15 AG13, AG16 R4
VSS[144] VSS[58]
AG7
+5VALW +3VALW VCC1_5[30] VCC3_3[14] C305 VSS[143] VSS[57]
P25 VCC1_5[31] VCC3_3[13] AA14 R25 VSS[142] VSS[56] AG3
P26 AA12 0.1U_0402_16V4Z R24 AG22
D14 VCC1_5[32] VCC3_3[12] VSS[141] VSS[55]
P27 VCC1_5[33] 1 2 R23 VSS[140] VSS[54] AG20
2

R21 VCC1_5[34] R17 VSS[139] VSS[53] AG17


R212 R22 P1 +3VS C281 R16 AG14
VCC1_5[35] VCC3_3[11] VSS[138] VSS[52]

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
10_0402_5% T21 M7 2 2 2 0.01U_0402_16V7K R15 AG12
VCC1_5[36] VCC3_3[10] VSS[137] VSS[51]

C343
RB751V_SOD323 T22 VCC1_5[37] VCC3_3[9] L7 1 2 R14 VSS[136] VSS[50] AG1

C360

C354
U21 L4 R13 AF7
1

C ICH_V5REF_SUS VCC1_5[38] VCC3_3[8] VSS[135] VSS[49] C


U22 VCC1_5[39] VCC3_3[7] J7
1 1 1 Near PIN A25 R12 VSS[134] VSS[48] AF3
2 2 V21 VCC1_5[40] VCC3_3[6] H7 R11 VSS[133] VSS[47] AF26
C299 C297 C307

PCI
V22 VCC1_5[41] VCC3_3[5] H1 P22 VSS[132] VSS[46] AF12
1U_0603_10V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K

GROUND
W21 VCC1_5[42] VCC3_3[4] E4 P16 VSS[131] VSS[45] AF10
1 1
W22 VCC1_5[43] VCC3_3[3] B1 Near PIN 1 2 P15 VSS[130] VSS[44] AF1
Y21 A6 P14 AE7
Y22
VCC1_5[44] VCC3_3[2] A2-A6, D1-H1 Near PIN AA19 P13
VSS[129] VSS[43]
AE6
VCC1_5[45] VSS[128] VSS[42]
VCCSUS1_5[3] U7 P12 VSS[127] VSS[41] AE25
+1.5VS AA6 VCC1_5[46] VCCSUS1_5[2] R7 +1.5VALW N7 VSS[126] VSS[40] AE21

0.1U_0402_16V4Z

0.1U_0402_16V4Z
AB4 VCC1_5[47] N17 VSS[125] VSS[39] AE2
0.1U_0402_16V4Z

AB5 VCC1_5[48] 2 1 N16 VSS[124] VSS[38] AE12

USB
2 AB6 VCC1_5[49] VCCSUS1_5[1] G19 +1.5VALW N15 VSS[123] VSS[37] AE11

0.1U_0402_16V4Z
AC4 VCC1_5[50] N14 VSS[122] VSS[36] AE10
+3VALW +1.5VALW
C333

C338

C342
AD4 VCC1_5[51] VCC1_5[78] G20 1 N13 VSS[121] VSS[35] AD6
1 2
AE4 VCC1_5[52] VCC1_5[77] F20 N12 VSS[120] VSS[34] AD24
U18 APL5301-15DC_3P 1
Near PIN AG5 AE5 VCC1_5[53] VCC1_5[76] E24 N11 VSS[119] VSS[33] AD2

SATA
AF5 VCC1_5[54] VCC1_5[75] E23 N1 VSS[118] VSS[32] AD18
2

C308
USB CORE
2 3 AG5 E22 M4 AD15
GND

Vin Vout VCC1_5[55] VCC1_5[74] VSS[117] VSS[31]


1 1 VCC1_5[73] E21 M27 VSS[116] VSS[30] AD10
+1.5VS AA7 VCC1_5[56] VCC1_5[72] E20 Near PIN U7 M26 VSS[115] VSS[29] AD1
0.1U_0402_16V4Z

C314 C298 AA8 D27 M23 AC6


1

0.1U_0402_16V4Z 0.1U_0402_16V4Z VCC1_5[57] VCC1_5[71] VSS[114] VSS[28]


AA9 VCC1_5[58] VCC1_5[70] D26 M16 VSS[113] VSS[27] AC3
2 2
2 AB8 VCC1_5[59] VCC1_5[69] D25 M15 VSS[112] VSS[26] AC26
C347

AC8 VCC1_5[60] VCC1_5[68] D24 +1.5VS M14 VSS[111] VSS[25] AC24


Near PIN AG9 AD8 VCC1_5[61] +2.5VS
M13 VSS[110] VSS[24] AC23
AE8 VCC1_5[62] VCC1_5[67] G8 M12 VSS[109] VSS[23] AC22
1
AE9 VCC1_5[63] L25 VSS[108] VSS[22] AC12
AF9 VCC1_5[64] VCC2_5[4] AB18 L24 VSS[107] VSS[21] AC10
AG9 PCI/IDE RBP P7 L23 AB9
VCC1_5[65] VCC2_5[2] VSS[106] VSS[20]

0.1U_0402_16V4Z
L15 VSS[105] VSS[19] AB7
ICH6_VCCPLL AC27 AA18 ICH_V5REF_RUN 1 L13 AB2
VCCDMIPLL V5REF[2] VSS[104] VSS[18]
+3VS E26 VCC3_3[1] V5REF[1] A8 K7 VSS[103] VSS[17] AB19
B B
K27 VSS[102] VSS[16] AB10
0.1U_0402_16V4Z

AE1 F21 ICH_V5REF_SUS K26 AB1


+1.5VS VCCSATAPLL V5REF_SUS 2 VSS[101] VSS[15]

C311
2 +3VS AG10 VCC3_3[22] K23 VSS[100] VSS[14] AA4
C278

VCCUSBPLL A25 +1.5VS K1 VSS[99] VSS[13] AA16


A13 VCCLAN3_3/VCCSUS3_3[1] VCCSUS3_3[20] A24 +3VALW J4 VSS[98] VSS[12] AA13
R15 1 2 0_0402_5% F14 Support wake on LAN R12 @ J25 AA11
1 +3VS @ R16 1 VCCLAN3_3/VCCSUS3_3[2] Support wake on LAN R11 0 ohm VSS[97] VSS[11]
+3VALW 2 0_0402_5% G13 VCCLAN3_3/VCCSUS3_3[3] VCCRTC AB3 +RTCVCC J24 VSS[96] VSS[10] A9
Support wake on LAN R15 @
G14 VCCLAN3_3/VCCSUS3_3[4] Near PIN AB18 J23 VSS[95] VSS[9] A7
G11 R12 1 2 0_0402_5% +1.5VS H27 A4
Support wake on LAN R16 0 ohm VCCLAN1_5/VCCSUS1_5[2] R11 1 VSS[94] VSS[8]
+3VALW A11 VCCSUS3_3[1] VCCLAN1_5/VCCSUS1_5[1] G10 2 0_0402_5% +1.5VALW H26 VSS[93] VSS[7] A26
Near PIN U4 @ H23 A23
VCCSUS3_3[2] VSS[92] VSS[6]
V1 AG23 G9 A21
E26, E27 V7
VCCSUS3_3[3] V_CPU_IO[3]
AD26 +VCCP Near PIN AG23 G7
VSS[91] VSS[5]
A19
VCCSUS3_3[4] V_CPU_IO[2] VSS[90]