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4, APRIL 2007 839

A Nonvolatile 2-Mbit CBRAM Memory Core

Featuring Advanced Read and Program Control
Stefan Dietrich, Michael Angerbauer, Milena Ivanov, Dietmar Gogl, Heinz Hoenigschmid, Michael Kund,
Corvin Liaw, Michael Markert, Ralf Symanczyk, Laith Altimime, Serge Bournat, and Gerhard Mueller

Abstract—A 2-Mbit CBRAM (Conductive Bridging Random

Access Memory) core has been developed utilizing a 90 nm,
VDD = 1 5 V process technology. The presented design uses an
8F2 (0.0648 m2 ) 1T1CBJ (1-Transistor/1-Conductive Bridging
Junction) cell and introduces a fast feedback regulated CBJ
read voltage and a novel program charge control using dummy
cell bleeder devices. Random read/write cycle times 50 ns are
Index Terms—1T1CBJ, CBRAM, program, universal memory.


N THE CONTINUING development of a universal memory

I [1], the emerging CBRAM technology combines key
features of established Flash, SRAM, and DRAM memory
platforms such as small cell size, nonvolatility, high write en-
durance, and fast random access speed. Therefore, the CBRAM
technology offers the potential to become such a new prevalent
future memory technology [2]–[4].
For the first time, a 2-Mbit CBRAM chip architecture and
respective core circuits are described, establishing the main
building blocks for a future CBRAM product. Since the read
and write operation of this emerging memory technology is
fairly new compared to existing memories, some novel circuit
techniques are required. In this paper, it is shown that regulating Fig. 1. (a) Cross section and (b) cell schematic of the 1T1CBJ cell. WL pitch =
BL pitch = 2F = 180 nm. CSL: Column Select Line; M2, M1, M0: hierarchical
the read voltage across the memory cell becomes es- metallization levels; VC: Via Contact; SC: Storage Contact; CC: Cell Contact;
sential for all resistive memory technologies exhibiting a large CB: Contact Bitline; CA: Contact Array device; CN: Contact Node.
off/on resistance ratio. Additionally, by using a novel program-
ming scheme unintended programming charge is significantly
reduced. Applying the proposed concepts random read/write layer M1 and the poly gate word line is not shown in the cross
cycle times 50 ns are shown. section view of Fig. 1(a).
The CBRAM switching mechanism is based on the polarity
II. CBRAM CELL AND OPERATION dependent electrochemical deposition and removal of metal in
Fig. 1 illustrates the cross section and cell schematic of the a thin solid state electrolyte film. In this concept, a fast program
implemented 1T1CBJ cell. In this chart, two CB junction cells operation is achieved by applying a positive bias ( 600 mV,
are displayed, each connected to a common bit line (BL) by an A) at the oxidizable common anode plate [PL in
array device. The connection of the CB cells to the bit line is ac- Fig. 1(a)] which is kept at VDD voltage level and the storage
complished by activation of either word line WL or WL , contact (SC) resulting in a redox reaction driving Ag ions into
respectively. The word line system is realized in a segmented the chalcogenide glass (for example, germanium selenide). This
multilevel metallization scheme with a global master word line leads to the formation of metal-rich clusters, which form a stable
and local word line drivers. The local word line driver con- conductive bridge between both electrodes .
necting the segmented word line implemented in metallization The device can be switched back to the erased state by ap-
plying a reverse bias ( 200 mV, 20 A). In this
Manuscript received August 25, 2006; revised December 19, 2006. case, the concentration of the metal ions is reduced and the con-
M. Angerbauer, M. Ivanov, D. Gogl, H. Hoenigschmid, M. Kund, C. Liaw, ductive bridge is erased . In order to read the
M. Markert, R. Symanczyk, L. Altimime, and G. Mueller are with Qimonda CB junction element a positive read bias 150 mV is applied
AG, 85579 Neubiberg, Germany (e-mail:
S. Bournat is with Altis Semiconductor, 91105 Corbeil Essonnes, France. between plate anode and storage contact and the current flowing
Digital Object Identifier 10.1109/JSSC.2007.892207 through the bit line is detected by a current sense amplifier (SA).
0018-9200/$25.00 © 2007 IEEE

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Fig. 4. CBRAM switching parameters after endurance tests at room tempera-

Fig. 2. CBRAM read/program/erase characteristics. ture (from [2]).

Fig. 3. CBRAM R =R resistance measurement, programmed at a cur-

rent compliance I = 10 A.
Fig. 5. CBRAM data retention measured at elevated temperatures (from [2]).

In Fig. 2, measurements of CBRAM read/write characteristics

are shown. The axis of the chart shows the voltage in volts
applied between the anode plate and the storage contact of the
CBRAM cell whereas on the axis the cell current is displayed
in A. As can be seen from the upper current limitation, the cur-
rent compliance for the program operation was set to 10 A by
the tester.
Measurements of the respective resistance
characteristics are shown in Fig. 3. On the axis the voltage
during a read operation is shown in volts whereas on the
axis the resistance of the memory cell is illustrated in ohms.
When the conductive bridge is established in the germanium
selenide chalcogenide material, an on-resistance of was Fig. 6. CBRAM switching parameters at different operating temperatures
achieved whereas the off resistance measures . This (from [2]).
large difference of seven orders of magnitude generates a large
read signal margin and enables multilevel capability for future
chip designs. values remain at a constant value of , whereas the
The results of endurance measurements performed at room values slightly increase in time. This results in an extrapolated
temperature are presented in Fig. 4. On the axis the number resistance ratio of more than after ten years.
of write operations is shown. Furthermore, the CB junction cell Measurements of the operating temperature in the range from
resistances and in ohms and the threshold voltages 40 C to 110 C are shown in Fig. 6. The resistance
of the switching processes (program and erase) in millivolts are values decrease by one order of magnitude for elevated temper-
illustrated on the axis. The and resistance values atures, whereas the and the threshold voltage values re-
remain within a window of one order of magnitude each, even main constant within the measured range.
after more than 1 million cycles. The threshold voltages for The CBRAM cell array was implemented using a 90-nm
switching the cell from program state to erase state and vice DRAM process with a three-level BEOL add-on module and
versa are observed to be constant within the measured range. uses a shared bit line contact. An F cell size measuring
Fig. 5 shows the results of data retention measurements at ele- 0.0648 m was achieved using a folded bit line architecture
vated temperatures of 50 C and 70 C, respectively. The which is commonly known from DRAM designs.

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Fig. 7. The 128-Kbit segment layout including local WL driver, CSL, and read/
write circuitry.

Fig. 9. Sensing system.

The CBRAM cells connected to the reference bit lines are

pre-programmed to opposite states ( and , respec-
tively) and are shorted together during the read operation. This
complementary reference cell concept ensures that the resulting
reference current is at an ideal midpoint reference.
A segmented word line architecture with power decoded local
word line drivers was designed to enable a relaxed pitch of about
6F for the master word line, which is layed out in a metal layer
above the bit line and driven over the entire length of 1.7 mm of
Fig. 8. Segment architecture (folded BL concept). the sixteen 128-Kb arrays.


In Fig. 9, a cross section of the sensing system is illustrated.
The 2-Mbit chip consists of sixteen 128-Kbit segments
At the bottom, the 1T1CB junction array is shown, represented
(512WL 256BL pairs) connected by local word line drivers.
Fig. 7 illustrates the layout of a 128-Kbit segment including by one CB junction and two reference cells out of 128 bit line
corresponding core circuits like local word line driver, column pairs and 2 reference bit line pairs in total. If the word line (WL)
select line (CSL) decoder, and CSL switch, as well as read/write is activated, the CB junction and reference cells are connected
circuits. These are laid out on pitch and provide respective con- to the bit line (BL) and reference bit lines (RefBL0/RefBL1),
trol signals. Since it is a test chip design, all signal timings respectively. Subject to the chosen column address, column se-
and voltages are externally supplied by the tester (no on chip lect switches (CSL) connect the bit line to the true master bit line
voltage pumps) and no cell redundancy was implemented. The (MBLt) and the reference bit lines to the complement master bit
shown 128-Kb segment measures about 90 m by 90 m, the line (MBLc). The shorting of the reference cells via MBLc is
word line direction is vertical, the bit lines run in horizontal hereby obtained with the help of the appropriate column select
direction. The internal supply voltage for all circuits is 1.5 V; and multiplexer logic and ensures an ideal mid point reference
the word line is boosted to 3 V. Two 64-Kb slices are contained for the sensing operation as described in the chip architecture
within a 128-Kb segment where CSL switches together with overview.
a multiplexer connect 128 bit line pairs and two reference bit In a current sensing concept, the voltage across the memory
line pairs of the memory slice within a segment to the shared cell should be kept constant and the resulting cell current can
master bit line (called MBL in Fig. 8) which finally provides then be detected by a current sense amplifier. As previously dis-
the connection to read and write circuitry. Two current sense cussed, the resistance of the CBRAM cell varies over several
amplifiers are connected to a 64-Kb slice. orders of magnitude and therefore a conventional static pFET

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Fig. 10. V
Fig. 11. settling time (simulated for worst case condition of low resis-
comparison: Feedback regulated versus conventional source-
follower type approach.
tive R =R ).

source-follower approach would not be able to keep the bit line

potential at a constant level over the whole CBRAM cell resis-
tance range. Therefore, in this design, the bit lines are clamped
to the optimum read voltage by feedback regulated pFETs P1/P2
where is applied to the regulator input. The read voltage
at the CB junction can then be calculated as the plate
voltage minus the regulated master bit line voltage .
The resulting cell currents through the CB junctions correspond
to the states of the data and reference cells within the memory
array and are translated into a differential voltage at the load
devices N1 and N2 which are n-channel devices configured as
diodes. Therefore, signals SAN and SAP are the inputs for the
following comparator stage COMP which transforms the read
signal into a digital output DO. The sense amplifier reference is
obtained by averaging the currents of two reference cells written
to the opposite and states.
Fig. 10 displays the CB junction resistance in ohms on the
axis versus the obtained read voltage in volts on the
axis. Using the feedback regulated pFET approach discussed
above an accuracy of 4 mV over a wide CB junction resistance
range (from to ) was obtained. The second graph
in Fig. 10 represents the conventional source follower type ap-
proach which degrades significantly for lower resistance values.
This means that a regulated read voltage is required for memo- Fig. 12. Writing (program/erase) system.
ries which exhibit a large resistance spread between off and on
states in order to guarantee a reliable read signal.
In Fig. 11, the settling time of the feedback regulation circuit device. Activation of the respective column select switch con-
is displayed on the axis in nanoseconds and on the axis the nects the bit line to the corresponding master bit line (MBLt).
obtained read voltage is plotted in volts. The simulation During an erase operation, the signal Erase is at 0 V enabling
was performed for the worst case situation of a low ohmic CB a current flow from the voltage called through the
junction cell in the state of 10 k . As can be seen, the tar- master bit line (MBL) and bit line (BL) network to . During
geted 150 mV read voltage was achieved after a 9 ns settling a program operation, the signal Prog is at VDD V and
time which is key requisite for fast access and cycle times. the current, which is called , flows from through the
master bit line and bit line network to ground. In this case, the
mirror devices N3 and N4 provide a current compliance
to avoid destruction and over-programming of the CB junction.
The write circuitry for erase and programming control is Ideally, is equal to . The write multiplexer (WRITE
shown in Fig. 12. At the lower half of the figure, a cross section MUX) ensures that only one program and erase logic is needed
of the CB junction array is displayed, represented by a CB for writing to true master bit line (MBLt) or complement
junction cell and a dummy bleeder cell. The reference cells are master bit line (MBLc). During reference cell write operation,
not shown in this illustration, the functionality of the bleeder the column select switch and multiplexing circuitry (CSL) is
cell will be explained later. By activating the word line (WL), capable of separating the two reference bit lines (RefBL) which
the CB junction is connected to the bit line (BL) via the array are normally shorted by the master bit line. This guarantees

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Fig. 13. I comparison: Dummy bleeder device versus conventional ap- Fig. 15. Full chip simulation: Erase-Read-Program-Read sequence, V =
proach without bleeder device. 3 V (boosted WL scheme), reference BLs connected to SAP, V = VDD =
1:5 V.

the bidirectional write scheme. During an erase operation the

master bit line is tight to a voltage of 2.3 V generating a re-
verse bias of 2.3 V 800 mV which
guarantees enough margin compared to the necessary bias of
200 mV described in the cell operation overview. During pro-
gram operation the master bit line is discharged to ground, gen-
erating a positive bias of 1.5 V. During read, the master bit
line is tight to 1.35 V through the feedback regulated
circuit explained in the read control section to supply the tar-
geted 150 mV read voltage to the
CBRAM cell. Random read/write cycle times less than 50 ns are
demonstrated while obtaining a sufficient read signal larger than
80 mV. The read signal values are measured between the com-
Fig. 14. Charge comparison: Dummy bleeder device versus conventional ap- parator input nodes SAN/SAP which are illustrated in Fig. 9. A
proach without bleeder device.
read access time of 35 ns measured from addresses valid to data
out was achieved.
the correct setting of the reference cells during
pre-programming. VII. CONCLUSION
However, due to initial charge balancing of the plate capaci-
tance and the capacitances of the bit line and master bit line For the first time, an F 1T1CBJ based 2-Mbit CBRAM
( , ), a critical current peak for occurs during pro- core design using a 90 nm, VDD 1.5 V process technology
gramming before N3/N4 become effective. has been presented. The introduced read voltage regulation
In order to reduce this current peak, a dummy word line achieves 4 mV accuracy over a wide CBJ resistance range from
(DWL, located at array edge) is activated concurrently with to while obtaining a settling time less than 9 ns.
the regular word line which then creates a parallel current path The novel program charge control using dummy cell bleeder
through a CBJ dummy bleeder device. Therefore, this device devices was designed to reduce unintended programming
successfully reduces the unintended charge by more than 50% charge by more than 50%. Full chip simulations demonstrate a
and reaches current compliance at 25 ns. Without the bleeder random read/write cycle time less than 50 ns. Together with the
device the current compliance is reached after 60 ns. Figs. 13 shown endurance ( cycles) and nonvolatility (10 years
and 14 show the respective simulations. at 70 C) measurement data the CBRAM potential as future
universal memory technology was illustrated.


Full chip circuit simulations for an erase-read-program-read [1] G. Müller et al., “Status and outlook of emerging non volatile memory
sequence are shown in Fig. 15. technologies,” in IEDM Tech. Dig., 2004, pp. 567–570.
[2] M. Kund et al., “Conductive bridging RAM (CBRAM): An emerging
On the axis of this figure the time is displayed in nanosec- non-volatile memory technology scalable to sub 20 nm,” in IEDM Tech.
onds whereas on the axis the voltage is illustrated in volts for Dig., 2005, pp. 773–776.
various control signals. During the erase and program opera- [3] R. Symanczyk et al., “Electrical characterization of solid state ionic
memory elements,” in NVMTS Tech. Dig., 2003, pp. 17–1.
tion the master bit line (MBL) is connected to voltage levels [4] M. Kund et al., “Non-volatile memory based on solid electrolytes,” in
above and below the common plate voltage of 1.5 V to enable NVMTS Tech. Dig., 2004, pp. 10–17.

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Stefan Dietrich was born in Munich, Germany, on Michael Kund was born in Cologne in 1965. He re-
May 12, 1965. He received the Diploma in physics ceived the Dipl.-Phys. degree in 1992 and the Dr. rer.
from the Technical University of Munich and the nat. degree in 1995, both from the Technical Univer-
Ph.D. degree from the University of Augsburg, sity of Munich, Germany.
Germany, in 1993 and 1996, respectively. In 1996, he joined Siemens Semiconductors and
In 1996, he joined the Memory Products division in 2001 Infineon Technologies (now Qimonda)
of Infineon Technologies (formerly Siemens Semi- working on production engineering, design analysis
conductors) in Munich, Germany, which became Qi- and design for testability for high-performance
monda AG. Since then, he has been engaged in de- DRAMs. Since 2002, he has been working on
velopment of high-speed graphics dynamic memo- emerging memory technologies. His main research
ries and emerging memory platforms. interests are memory devices, design and characteri-
Dr. Dietrich is a member of the German Physical Society. zation. He holds eight registered patents and has 25 patents pending.
Dr. Kund is a member of the German Physical Society.

Michael Angerbauer was born in Trostberg, Ger-

many, on January 13, 1981. He received the Diploma
in electrical engineering from the University of Ap- Corvin Liaw was born in Ostfildern-Ruit, Germany.
plied Science in Rosenheim in 2005. He received the Dipl.-Ing. degree from the University
In July 2005, he joined Infineon Technologies, of Stuttgart, Germany, in 2003, and a degree as Inge-
Munich, Germany, which became Qimonda AG. nieur from ENST Paris, France, in 2003. He is cur-
Since then, he has worked for the design depart- rently working toward the Ph.D. degree at the Tech-
ment of developing new circuit solutions for new nical University of Munich, Germany.
nonvolatile memories. His current research interests include the electrical
characterization and the core circuit design of the
Conductive Bridging Random Access Memory

Milena Ivanov was born in Vratsa, Bulgaria, on

January 12, 1978. She received the Master degree in
telecommunications from the Technical University
of Sofia, Bulgaria, in 1996, and the Diploma in Michael Markert was born in Spittal a. d. Drau,
electrical engineering from the Technical University Austria, on December 21, 1968.
of Munich, Germany, in 2005. He joined the hardware development group for per-
She joined the Memory Products Division of Infi- sonal computers at Siemens, later Siemens Nixdorf,
neon Technologies in 2005 (now Qimonda AG) and in 1989. Since 1996 he is working for Qimonda (for-
is active in development of emerging memories, in merly Infineon, formerly Siemens Semiconductor).
particular, conductive bridging RAM. He was engaged for about 10 years in development
of high-end graphic memories. In 2005, he changed
to the development group for new memory platforms.

Dietmar Gogl received the Dipl.-Ing. degree in

electrical engineering from the Technical University
of Munich, Germany, in 1993 and the Dr.-Ing. degree
from the Gerhard-Mercator-University, Duisburg, Ralf Symanczyk was born in Bad Bentheim, Ger-
Germany, in 1997. many. He received the Masters degree in physics
From 1994 to 1998, he was with the Fraunhofer from the University of Muenster in 1986, and the
Institute of Microelectronic Circuits and Sys- Ph.D. degree from the University of Duisburg in
tems, Duisburg, Germany, working on embedded 1993.
EEPROM memories for ASIC applications in bulk From 1995 to 2002, he worked at DaimlerChrysler
CMOS and high-temperature SIMOX CMOS tech- Aerospace/Temic (Telefunken microelectronic) on
nology. From 1999 to 2000, he was with Infineon electrical characterization and physical failure
Technologies in Duisburg and Munich, Germany, working on the development analysis of electronic systems and components for
of nonvolatile memory solutions for microcontroller systems and MRAM automotive and military applications. In 2002, he
sensing techniques. In 2000, he joined the MRAM Development Alliance joined the Memory Products Division of Infineon
of IBM and Infineon Technologies in East Fishkill, NY, and Burlington, Technologies, which became Qimonda AG in 2006. His main research interests
VT, where he was engaged in the development of MRAM test chips and are electrical and physical device characterization and new semiconductor
MRAM sensing techniques. Since July 2004, he has been with the Infineon memories.
Technologies/Qimonda development center in Burlington, VT, where he has
been working on nonvolatile memory and DRAM circuit design.

Laith Altimime was born in 1962. After receiving

Heinz Hoenigschmid received the Master degree in the Honours degree in 1989 in applied physics
electrical engineering from the Technical University and semiconductors electronics from Heriot Watt
of Munich, Germany. University in Edinburgh (Scotland), he joined NEC
During his 16 years with Qimonda (formerly Semiconductors—UK as a device yield and integra-
Infineon) he was engaged in memory chip designs tion engineer. He also worked in NEC-Japan and
and project management of advanced DRAM gener- NEC-China.
ations and contributed to circuit, testsite and product In 2002, he moved to Germany as head of fab
demonstrator developments for emerging memories. engineering in a new foundry startup, Communicant.
He is currently a Senior Manager responsible for the He then joined Infineon in 2004 as Project Manager
design of emerging memories. He holds more than for nonvolatile memory technologies development
60 U.S. patents. (CBRAM and MRAM) at Altis Semiconductors (France).

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Serge Bournat was born in Thiers, France, in 1961. Gerhard Mueller received the Diploma in physics
He received the Engineering School diploma in 1984 and the Ph.D. degree from the Technical University
and the ABD in 1985, both from Ecole Supérieure de of Munich, Germany, in 1989 and 1992, respectively.
Physique et Chimie de Paris. After working for AT&T Bell Laboratories,
In 1986, he joined IBM Microelectronics working Murray Hill, NJ, and Philips Research, Eindhoven,
in semiconductor production engineering. In 2000, The Netherlands, in 1996 he joined the Memory
he joined Altis Semiconductor, an IBM/Infineon joint Products division of Infineon Technologies (for-
venture. Since 2003, he has been in charge of the de- merly Siemens Semiconductors, now Qimonda)
velopment program of future memory technologies. in Munich, Germany. He is currently a Senior Di-
rector responsible for the development of emerging
memory technologies. His past roles included being
the team leader of a product design department. Within this role in the DRAM
Development Alliance (Hopewell Junction, NY) he was working on 512 Mb
and 1 Gb DRAM product demonstrators. After that, he was a Project Manager
responsible for Infineon’s MRAM activities in Germany and then within the
MRAM Development Alliance.

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