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A C ircu it for All Seasons

Behzad Razavi

The Bootstrapped Switch

F
Field-effect transistors (FETs) have the voltage headroom occupied by the an on-resistance, R on, approxi-
been used as switches, particularly source follower and its bias current mately equal to [n n C ox (W/L)
for analog signals, since the 1950s. source limited the allowable input (VDD - Vin - VTH)] -1 . Since R on " 3
In the early days of analog sampling, range as the supplies scaled down. It as Vin approaches VDD - VTH, the
it was discovered that such devices was time to devise a more versatile input range is quite limited. To rem-
exhibit an input-dependent on-resist- passive level shift arrangement that edy the situation, we can resort to
ance, thereby introducing distortion. would consume no static power. the complementary topology shown
This issue can be resolved by boot- The notion of realizing the level in Figure 2(b), where M 2 accommo-
strapping, a circuit technique that shift battery by a precharged capaci- dates higher input levels. Due to MOS
minimizes the switch on-resistance tor can be traced to [4]. A number of nonidealities (notably, degradation of
variation in the presence of large modifications followed [5], [6], cul- mobility with the vertical field in the
input and output voltage swings. minating in the topology described channel), the net on-resistance of this
In this article, we study the boot- in [7] in 2001, which forms the foun- structure still varies considerably
strapped switch topology and appre- dation for our study here. with Vin . Plotted in Figure 2(c) is an
ciate its role in nanometer designs. example for (W/L) 1 = 5 nm/40 nm
Switch Nonidealities and (W/L) 2 = 25 nm/40 nm, so
Brief History Nanometer MOS switches suffer from chosen to minimize the variation.
To maintain a relatively constant on- a number of imperfections, but we The nearly sevenfold change in R on
resistance for a switch, we wish to fix focus here on two that can be allevi- modulates the phase shift of the cir-
its gate-source voltage as the input ated through bootstrapping. In the cuit in Figure 2(b), distorting the sig-
varies. In a patent filed in 1966 [1], simple circuit of Figure 2(a), CK is nal that appears across C 1 . This can
Russell proposes the circuit shown at VDD when M 1 is on, leading to be seen by expressing the input as
in Figure 1, where the P -type source
follower 15 shifts the input up by a
relatively constant amount, | VGS15 | ,
and drives the gate of the N -type
switch, 10. Thus, VGS10 = Vin +| VGS15 | 11 12
- Vin = | VGS15 | , and the switch acts 16 13 14
15
as a linear resistance. We can view
the source followers role as a bat- 20 17 18 10
tery that sets VGS15 .
The idea of a continuous-time 26 Vdc +26 Vdc
21
level shift between Vin and the gate 19 22 23
of the switch became popular in the 26
1970s and appeared in other patents
[2], [3] in forms similar to Russells. 24
But as analog CMOS circuits employed 28 29
increasingly more switches, the
27
power dissipated by the level shift cir-
cuit, which cannot be shared among 25
switches, proved undesirable. Also,
26 Vdc

Digital Object Identifier 10.1109/MSSC.2015.2449714


Date of publication: 15 September 2015 Figure 1: An early bootstrapped switch.

12 s u m m e r 2 0 15 IEEE SOLID-STATE CIRCUITS MAGAZINE


Vin (t) = V0 + V0 cos ~ in t and approxi-
mating the output as CK 400

M1 350
Vin Vout
Vout (t) = V0 + V0 cos
C1 300
[~ 0 t - tan -1 (R on C 1 ~ in)] (1)
. V0 + V0 cos ~ 0 t 250

Ron( )
(a)
+ V0 R on C 1 ~ in sin ~ in t, (2) 200
CK

M1 150
where the signal attenuation is Vin Vout 100
neglected and the phase shift is
C1
assumed much lower than 1 rad. M2 50
0.0 0.2 0.4 0.6 0.8 1.0 1.2
For a periodic input, R on also var-
CK Vin(V)
ies periodically and can therefore
(b) (c)
be expanded as a Fourier series. In
fact, the roughly symmetric behav-
Figure 2: (a) A simple sampling circuit, (b) a sampling circuit with complementary switches,
ior depicted in Figure 2(c) suggests
and (c) simulated on-resistance of complementary switches as a function of input voltage.
that R on completes two cycles for
one input cycle. Writing the Fourier
series of R on as R 0 + R 1 cos 2~ in t What if we make the switches in dependence by fixing VGS (but VTH is a
+ R 2 cos 4~ in t + g, we obtain the Figure 2(b) much wider so that R on function of the input due to body effect).
following output: and R 1 scale down proportionally?
Then, the drain junction capacitance Basic Bootstrapping
of these switches contributes a sig- We have surmised that a battery
Vout (t) . V0 + V0 cos ~ in t + V0 nificant nonlinear component to C 1, tied between the gate and source
#C 1 ~ in (R 0 +R 1 cos 2~ in t +g) causing distortion. These observa- of a switch can keep the device on
sin ~ in t. tions indicate that a complementary with a constant VGS . As shown in
(3) switch proves inadequate for lineari- Figure 3(a), such an arrangement
ties above approximately 6 b. bootstraps the gate to the source,
The third harmonic in the output Another issue in the sampling allowing the two to change in unison.
assumes an amplitude of V0 C 1 ~ in R 1 /2 circuits of Figure 2(a) and (b) relates Interestingly, VG can rise above the
and, if normalized to the first har- to the inversion layer charge stored supply voltage in this case, a valu-
monic, yields in the transistors when they are on. able property in low-voltage design.
Upon turning off, the MOSFETs inject Let us approximate the battery by
Normalized Third Harmonic some of this charge onto C 1, thus a precharged capacitor as depicted

. R 1 C 1 ~ in . (4) adding an error to the sampled sig- in Figure 3(b). In the sampling mode,
2
nal. The principal difficulty is that C b keeps M 11 on. In the hold mode,
As an example, for a distortion this charge is a function of Vin; two actions must be completed:
level below 60 dB, we must ensure e.g., Q ch = WLC ox (VGS - VTH) = WLC ox M 11 must be turned off and C b
~ in12000/(R 1 C 1), facing severe (VDD - Vin - VTH) for the NMOS device. must be recharged, e.g., to VDD . We
bandwidth limitations. Bootstrapping also suppresses this therefore add five switches to the

VDD M3 M8 M10
VDD
Cb
+ +
VDD t Cb V
DD
Vin Vout Vin Vout M12 M9
M11 M11 Vout
C1 C1 Vin M11
t C1

(a) (b) (c)

Figure 3: (a) Bootstrapping the gate to the input by a battery, (b) the use of a capacitor to approximate the battery, and (c) the addition of other
switches to allow M 11 to turn off and C b to recharge.

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circuit [Figure 3(c)]: M 10 turns M 11 be turned off by raising its gate to drawback: when VX rises above VDD
off, M 8 and M 9 disengage C b from VDD, yielding the simplified circuit in the sampling mode, M 10 experi-
M 11, and M 3 and M 12 precharge C b of Figure 4(b) in the sampling mode. ences drain-source and drain-gate
to VDD . We observe that each sam- Recall that Vp can rise above VDD voltages greater than VDD . The re-
pling circuit requires at least five because it contains both the pre- sulting stress shortens the device
more transistors and one capacitor charge voltage and the input swing. lifetime and must be avoided. This
for bootstrapping. Consequently, as Vp rises, the source can be accomplished by shield-
and drain of M 3 exchange roles, ing M 10 through the use of a cas-
Complete Bootstrapped Switch the new source reaches a voltage code device [Figure 4(d)] [7]. Now,
We now determine the type of exceeding the gate voltage by more M 14 limits VDS10 and VGS10 to about
MOSFETs that can be used for the than one threshold, and M 3 turns VDD - VTH14 (when M 10 is off).
switches in Figure 3(c). Since M 10 on. To avoid this difficulty, we boot- The bootstrapping topology stud-
and M 12 connect their respective strap the gate of M 3 to Vin as shown ied above has been used in a number
drains to ground, they must be real- in Figure 4(c). of analog-to-digital converters with
ized as NMOS devices. Also, since Transistor M 9 senses the input in resolutions ranging from 8 b to 12 b
M 8 ties the top plate of C b (a high the sampling mode and must there- [8], [9]. It has proved to be a robust
voltage) to the gate of M 11, it must fore be the same type as M 11 . If the solution affording both high linear-
use a PMOS transistor. We assume gate voltage of M 9 is at VDD in this ity and high speed.
these three switches are driven by mode, then the transistor turns off or
CK [Figure 4(a)], and hence the cir- at least exhibits a large on-resistance Questions for the Reader
cuit enters the hold mode when CK for high values of Vin . We address 1) In Figure 2(c), R 1 . R 0 . Suppose we
falls and CK rises. this issue by bootstrapping the gate define the small-signal bandwidth
The choice of M 3 and M 9 entails of this switch as well, arriving at the of the sampler as (2rR 0 C 1) -1 . De-
interesting points. Precharging the topology illustrated in Figure 4(c). termine the ratio of ~ in to this
top plate of C b to VDD, M 3 must be While performing well and pro- bandwidth if the third-order dis-
a PMOS switch, but can we drive its viding a high linearity, the sam- tortion given by (4) must remain
gate by CK ? In such a case, M 3 must pling circuit of Figure 4(c) entails one lower than 60 dB. This example

CK CK
VDD
VDD M3 VDD
P X P
VDD
M8 M10 M3
+
CK Cb VDD
Cb
t
M12 M9
Vout Vout
Vin M11 Vin M11
C1 C1
t
(a) (b)

CK CK CK CK
VDD
VDD VDD
P P
M3 M8 M10 M3 M8 M14 M10
X X
CK Cb CK Cb

M12 M9 M12 M9
Vout Vout
Vin M11 Vin M11
C1 C1

(c) (d)

Figure 4: (a) A bootstrapping circuit with some switches implemented by MOSFETs, (b) a turn-on issue of M 3, (c) avoiding M 3 turn-on by tying its
gate to X, and (d) the use of M 14 to minimize stress on M 10 .

14 su m m e r 2 0 15 IEEE SOLID-STATE CIRCUITS MAGAZINE


demonstrates the severity of the
variable on-resistance. VDD
2) To which node(s) should the n-wells
CK M5 M6 CK
of M 3 and M 8 in Figure 4(d) be
S1 S3 S4 S2
connected?
Vout
3) How high can VX in Figure 4(d) X Y
go to avoid stressing M 14 ?
M3 M4
Answers to Last Issues Questions
P Q
1) Do VP and VQ in Figure 5 reach 0 V
at the end of the regeneration phase? Vin1 M1 M2 Vin2
Yes, they do. We observe that
M 1 M 3 are on but with zero drain
CK M7
current because both M 3 and M 6
(or M 4 and M 5 ) are off. Nodes P and
Q are therefore discharged to zero.
2) Explain why M 3 and M 4 in Figure 5 Figure 5: The StrongARM latch.
can be omitted if the inputs have
rail-to-rail swings.
With rail-to-rail input swings, begins in the deep triode region, [5] M. Dessouky and A. Kaiser, Input switch
configuration suitable for rail-to-rail op-
either M 1 or M 2 is off, cutting off with C GD7 . C GS7 , exhibiting a eration of switched op amp circuits, Elec-
the path from VDD to ground. By greater feedthrough. tron. Lett., vol. 35, pp. 810, Jan. 1999.
[6] A. M. Abo and P. R. Gray, A 1.5-V 10-bit,
contrast, if | Vin1 - Vin2 | is small, 14.3 MS/s CMOS pipeline analog-to-digital
then both M 1 and M 2 remain on. References converter, IEEE J. Solid-State Circuits, vol.
34, pp. 599606, May 1999.
3) Explain why the coupling through [1] D. D. Russel, Field effect switching cir-
[7] M. Dessouky and A. Kaiser, Very low-
cuit, U.S. patent 3,448,293, Oct. 7, 1966.
C GD7 in Figure 5 is less on the ris- [2] M. Kikushi and M. Takeda, Distortionless
voltage digital audio TR modulator with
88-dB dynamic range using local switch
ing edge of CK than on the fall- switching circuit, U.S. patent 3,942,039,
bootstrapping, IEEE J. Solid-State Circuits,
May 20, 1974.
ing edge of CK . [3] G. Pollitt, Constant impedance MOSFET
vol. 36, pp. 349355, Mar. 2001.
[8] H. Wei and B. Razavi, An 8-bit 4-GS/s 120-
On the rising edge of the clock, switch, U.S. patent 4,093,874, Dec. 29,
mW CMOS ADC, IEEE J. Solid-State Cir-
1976.
M 7 begins from the off state and [4] B. Brandt, P. Ferguson, and M. Rebesehini,
cuits, vol. 349, pp. 17511761, Aug. 2014.
[9] J. Mathew and B. Razavi, A 12-bit 200-MS/s 3.4-
its C GD is primarily due to the Analog circuit design for RT ADCs, in
mW CMOS ADC with 0.85-V supply, in Symp.
Delta-Sigma Data Converters, S. Norswor-
gate-drain overlap capacitance. thy, R. Schreier, and G. Temes, Eds. Pisca-
VLSI Circuits Tech. Dig., June 2015, pp. 3031.
On the falling edge, the transistor taway, NJ: IEEE Press, 1997. 

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