Professional Documents
Culture Documents
NACIONAL
ESCUELA DE INGENIERA
Gabriel Arrobo
CERTIFICACIN
Certifico que el presente trabajo fue desarrollado por Vctor Hugo lvarez Castillo
y Gabriel Eduardo Arrobo Vidal, bajo mi supervisin.
<^__ _ _
DIRECTOR DE PROYECTO
AGRADECIMIENTO
Gabriel Eduardo
RESUMEN
Para que un equipo pueda ser controlado por computador, necesita que se
le adicionen ciertas modificaciones, ya sea internas o externas para que se pueda
comunicar con el computador, lo que se conoce como la interfaz hardware. El
manejo de este interfaz se lo realiza mediante un software residente en el
computador que tambin se lo conoce como interfaz software.
1.1 INTRODUCCIN 2
1.2 AMPLIFICADORES DE POTENCIA 4
7.2.7 DIAGRAMA DE BLOQUES 5
1.2.1.1 Etapa De Entrada 5
1.2.1.2 Etapa Excitadora 6
1.2.1.3 Etapa De Potencia o De Salida 6
1.2.1.4 Realimentacin 7
1.2.1.5 Fuente De Alimentacin 15
1.3 CLASES DE AMPLIFICADORES DE POTENCIA 18
7.5.7 GLASEA 18
1.3.2 CLASE B 19
1.3.3 CLASE AB 21
1.3.4 CLASE C 21
1.3.5 CLASE D 22
1.3.6 GLASEE 23
1.3.7 CLASE G 24
1.3.8 GLASEE 24
1.4 PARMETROS CARACTERSTICOS DE LOS AMPLIFICADORES DE
POTENCIA 24
1.4.1 POTENCIA ENTREGADA POR LA FUENTE DE ENERGA 24
1.4.2 POTENCIA TIL ENTREGADA A LA CARGA 25
1.4.3 RENDIMIENTO DEL AMPLIFICADOR 26
1.4.4 DISTORSIN 26
1.4.4.1 Distorsin armnica 26
1.4.4.1.1 Distorsin Armnica Total (THD)' 27
. 1.5 AMPLIFICADORES DE AUDIO 27
7.5.7 AMPLIFICADOR DE AUDIO EN CONTRAFASE CUASI-
COMPLEMENTARIO 28
1.5.1.1 ParDarlington 29
1.5.1.2 ParRetroalimentado 32
1.6 CIRCUITOS INTEGRADOS 37
1.6.1 ESTR UCTUR INTERNA DE UN CIRCUITO INTEGRADO
AMPLIFICADOR DE A UDIO 38
1.6.1.1 Fuentes de Corriente 39
1.6.1.2 Espejos de Corriente 41
1.6.1.3 Amplificadores Diferencales 42
1.6.1.4 STK4141 46
1.7 MODOS DE CONEXIN A LA SALIDA 54
MODO ESTREO 54
1.7,1 MODO PARALELO O MONO 55
1.8 CARACTERSTICAS PRINCIPALES DE LOS AMPLIFICADORES
COMERCIALES 56
1.8.1 POTENCIA DE SALIDA 56
1.8.1.1 Potencia Nominal 56
1.8.1.2 Potencia Musical o Dinmica 56
1.8.2 RESPUESTA EN FRECUENCIA. 57
1.8.3 SLEWRATE 58
1.8.4 SENSIBILIDAD DE ENTRADA ' * 59
1.8.5 IMPEDANCIA DE ENTRADA 60
1.8.6 IMPEDANCIA DE SALIDA 60
1.8.7 FACTOR DE AMORTIGUAMIENTO (FA) 61
1.8.8 RENDIMIENTO 62
1.9 PRBAMPLIFICADORES Y MEZCLADORES 63
1.9.1 PREAMPLIFICADORES 63
1.9.1.1 Amplificadores de Voltaje 64
1.9.1.1.1 Amplificador No Inversor 64
1.9.1.1.2 Amplificador Inversor 66
1.9.2 MEZCLADORES 69
1.9.2.1 Mezclador No Inversor 69
1.9.2.2 Mezclador Inversor 70
1.10 PROTECCIONES DE DISPOSITIVOS Y DE CIRCUITOS 70
1.10.1 ENFRIADORES Y DISIPADORES DE CALOR 71
1.10.2 TRANSITORIOS DEL LADO DE LA ALIMENTACIN Y DEL LADO DE
LA CARGA 72
1.10.3 PROTECCIONES CONTRA SOBRE CORRIENTE 74
1.10.4 PROTECCIONES CONTRA TENSIN CONTINUA 75
1.11 DISEO DEL SISTEMA DE AUDIO 75
LILI DISEO DLOS PREAMPLIFICAD ORES 76
1.11.1.1 Requerimientos y especificaciones 76
1.11.1.2 Diseo de Preamplicadores para Micrfonos 77
1.11.1.3 Diseo de Preamplifcadores para Entradas Auxiliares 80
U 1.2 DISEO DEL AMPLIFICADOR DE POTENCIA 81
1.11.2.1 Requerimientos y especificaciones 81
1.11.2.2 Diseo del amplificador: 82
1.11.3 DISEO DEL MEZCLADOR 101
1.12 MONTAJE E MPLEMENTACION 101
1.12.1 Fuente de Alimentacin 101
1.12.2 Etapa de preamplificacin 102
1.12.2.1 Caractersticas Principales: 103
1.12.2.2 Estructura Fsica: 104
1.12.2.3 Estructura Interna: 104
1.12.3 Etapa de Potencia ' 105
1.13 PRUEBAS Y RESULTADOS 106
1.13.1 Fuente de alimentacin 106
1.13.2 Etapa de preamplificacin 106
1.13.3 Etapa de Amplificacin 107
La seal que se obtiene a la salida, tiene igual forma de onda que la seal
que se percibi inicialmente a la entrada, pero varan las magnitudes, En lugar de
tensiones de decenas de milivoltios (mV), se obtiene a la salida tensiones de
decenas de voltios (V) y corrientes de varios amperios (A).
La seal que ingresa al amplificador se mide en milivatios, es decir, tiene
una potencia de aproximadamente 1000 veces menos que la que tendr a la
salida.
Voltaje de Voltaje de
Entrada Salida
Vn Vo
Puede estar constituida por alguna clase de amplificador de voltaje, tal como
un amplificador diferencial, cuya principal caracterstica es tener una alta
impedancia de entrada y muy baja distorsin, aunque su ganancia de voltaje no
sea tan elevada.
Al poseer una alta impedancia de entrada, proporciona la independencia
entre el circuito de realimentacin y el mdulo precedente al amplificador de
potencia, evitando cualquier tipo de influencia sobre la unidad anterior, como
puede ser el ecualizador.
Esta etapa tiene una,alta importancia, razn por la cual,' otorga el nombre a
todo el conjunto. sta es la encargada de dotar de potencia a la seal de salida,
puesto que la seal que recibe tiene mucho voltaje, pero muy poca intensidad de
corriente.
4 r> A <-, +!
i i i i
Rif Ri Ro Rof
Vf Red de Vo
n
B
A = Ec. 1.1
v V,
Ec. 1.2
V
En la entrada del amplificador bsico hay un circuito sumador S, el mismo
que otorga una seal de salida V o I, proporcional a la suma de las seales de
la fuente y del circuito de retroamentacin, como lo demuestra la figura 1.4.
V s = V , + V f Ec. 1.3
Vo.
V,
A vr = y-y" Ec ' 1 - 5
+
vt v,
Av
R VA
b Av ECl ' 6
tiene que:
A
A Vf Ec. 1.7
1-BVAV
Vsi RL
Isff) :RL
a R,.
B r = - Ec. 1.9
B ! = ^- Ec, l.ll
Impedancia de entrada (Z )
lin
Vs Vi
Zn Rin
Vf
V,=R,n.I,n
V O =V,.A V
Vf=Bv.V0 - Vf=Av.Bv.V,
Z ln = 3- Ec. 1.12
V, + V f
Zin = ^-!- Ec. 1 13
V, + V , . B V .A V
,n
1n
V- ( 1 + Bv . A v )
Zn = -^-^--- ^ Ec. 1.15
'in
Impedancia de Salida ( Z 0 )
IH
Ro
hAV
Vi Vx
Ro Zo
vr Vx
Ec.1.18
z -o ~~ Ec.1.19
Ec. 1.20
R
15
Vx + B V . A v . Vx
Ix - ~- Ec. 1.21
R,' O
Zn = Ec. 1.22
1+ A B V
Una etapa de potencia estreo tiene que duplicar las tres etapas (entrada,
excitadora y potencia) y puede utilizar una fuente de alimentacin para todos.
FUSIBLE
110V,
LM337
Las variaciones que se tenga en el valor del voltaje del secundario del
transformador, debido a las fluctuaciones en la red de alimentacin elctrica
(100V - 120V) deben ser tomadas en cuenta, por lo cual se debe tomar un valor
de voltaje Vc que salvaguarde las condiciones que se requieren. Sin embargo la
utilizacin de Cl's reguladores de voltaje nos ayudan a pasar por alto estas
fluctuaciones (de acuerdo al rango permitido), ya que estos permiten un cierto
rango de voltaje de entrada para entregar un voltaje "fijo" a la salida.
Los capacitores C3 y C4 se los utiliza para eliminar algn tipo de ruido que se
presente y sus valores son bajos y para tener R 0 d l a fuente bajo para altas
frecuencias.
A 360 25% a 50 %
B 180 78.5%
AB 180 A 360 Entre 25% (50%) y 78.5%
Elevado rendimiento, pero elevada
C Menor a 180 (tpicamente 120o)2
distorsin
1.3.1 GLASEA
1 Tomado del libro: Grob Basic Electronics, 1992, 7ma edicin, Capitulo 30, pgina 762
sin sobrepasar la regin de corte y/o saturacin, obtenindose como resultado un
ngulo de conduccin de 360 en la seal de salida.
c(max)-" 36
'35
'C=IQ
IcCmn)
v>t
1.3.2 CLASE B
Vn ,c
i
] \\
RL
/ m *
11
vcc 2
Para DC, un componente activo en clase AB tiene una corriente de base por
encima del nivel de corriente de base de la clase B (Ib = 0) y no sobrepasa la
mitad de la corriente de base de la clase A, esta es la razn para que este tipo de
amplificador tome este nombre.
1.3.4 CLASE C
Este tipo de operacin est limitado para usarse a una frecuencia fija, por
ejemplo, en un circuito de comunicaciones.
1.3.5 CLASE D
Para esta conversin se debe modular a la seal de entrada con una onda
cuadrada (o diente de sierra) como portadora, luego se amplifica la seal
t
23
SEAL DE SALIDA
1.3.6 GLASEE
1.3.7 CLASE G
1.3.8 CLASE H
La potencia ser:
Ec. 1.25
-JP Ec.1.26
7t
Ec. 1.27
KL
26
p
-^-.100 % Ec. 1.28
r ce
1.4.4 DISTORSIN
La distorsin tambin puede suceder debido a que los elementos de! circuito
y los dispositivos responden en forma diferente a la seal de entrada de las
diferentes frecuencias, siendo sta una distorsin por frecuencia.
02
NPN
Q3
, PNP,
NPH
Darlington
I Ib
Via
>RL
Segn la figura 1.17 se tiene que la corriente de base (Ib) a travs de r es:
V, - V,
Ec. 1.31
Ec. 1.32
Reemplazando se obtiene:
Ec. 1.33
31
Despejando V, se obtiene:
Ec. 1.34
Ec. 1.36
Impedancia de Salida ( Z 0 )
Ix
-o +
Vx
BD . Ib.
L= Ec. 138
RE r r
-R Ec.1.39
Z Ec. 1.40
vcc
Re
El
C2
B1 01
PHP
B2
C1 NPN
E2
RB
B1 Cl B2 C2
E2
Vo
B1 C2
-0 +
Vi Ra
E2
En donde:
V. - V
I b 1 = -! *- Ec.1.42
Entonces se obtiene:
Ibl.rI1+B2.(B1.Ibl}Rc=V, Ec.1.45
Impedancia de Salida ( Z 0 )
lx
C2
2/b2 Ic
Zo
E2
/ Ec. 1.48
~ i "x
Ec. 1.50
Ec. 1.51
P1 Rc
ru 11 ri Ec. 1.53
.0 , v j.
36
~ Ec ' 1<54
La ganancia de corriente para este circuito segn la figura 1.22 est dada
por:
A =
O
=
O U1 I j
Ec. 1.55
r-l
I0 = 6 2 . I b 2 - 6 1 . I b l - I b l Ec. 1.56
1. Ec. 1.58
Ganancia de Voltaje (A v )
Av - ^ Ec. 1.61
V,
37
V 0 =-I R C .R c = B2.B1.Ibl.Rc
Ec. 1.62
Debido a que:
v. - v
Ih1 = 2- Ec. 1.63
Se tiene:
V O = V. - ^bV'll
L, r-, = V.I -2 i-> r Ec. 1.64
vI r. n 11
A = i - e - c .^ Ecl65
Afortunadamente estas desventajas no son para todos los Cl, pero para el
caso de los CI amplificadores de audio se han presentado estos inconvenientes.
Par Darlington
Par retroalimentados
Fuentes de corriente
Espejos de corriente
Amplificadores Diferenciales
Q1
R1 < RE
Ec. 1.67
Ec. l.
va Q1
r>
>> R 1
r
rJi
^ J4 RE
+ Vcc
Para deducir que Ix =1, se supone que la corriente de emisor (!E) para
ambos transistores es la misma (siendo Q1 y Q2 fabricados uno junto al otro en el
mismo microcircuito). El sentido de las corrientes se muestra en la figura 1.27.
42
+ Vcc
O
IH
Rx
|2lE
1 10
Q1 Q2
NPN NPN
!E _ IE Ec. 1.69
Asumiendo que
Ic ^1
E'.
X E
Ec. 1.70
P P
T T T T
colector de 2.
t
44
3, = 6 2 = 6
MODO DE
ENTRADAS SALIDAS GANANCIA
OPERACIN
Se aplica una seal
a cualquiera de las
Una misma seal de salida
Un terminal entradas estando A V Rc
en ambos colectores. Av V u - 2.re
la otra conectada a
tierra.
Se aplican seales Se tiene en cada colector la
Doble V0 Rc
de entrada amplificacin de la diferencia
terminal '"" VIl-Vll-2.ra
diferentes de las seales de entradas.
1.6.1.4 STK4141
TR17
7o
TR9
7o
Estructura 1
Las resistencias R-i y R9 as como el diodo D-i, que forman parte de la fuente
de corriente se encargan polarizar a TRS y fijar el valor de corriente que entrega la
fuente.
Estructura 2
Cabe hacer notar que la estructura tal como se muestra no tiene un buen
grado de amplificacin, por lo que se hace indispensable conectar dispositivos
perifricos (resistencias) que fijen el valor de la ganancia de voltaje que se
necesitar para poder proporcionar la potencia requerida, ya que en las etapas
posteriores se amplifica nicamente el nivel de corriente.
3 La red de realimentacin no consta en la figura 1.33, ya que esta se forma en la parte exterior al
CISTK4141.
50
Estructura 3
Estructura 4
El par Darlington est formado por TRS y T R9j este par trabaja solo en el
semiciclo positivo de la seal proveniente del colector del TR7, es decir reproduce
en el emisor de TR9 el semiciclo positivo de la seal que ingres a la base de T R8j
con niveles de corriente mayores.
La resistencia R6 se encarga de limitar la corriente que ingresa a la base del
transistor TR9 y adems mejora la impeancia de entrada del circuito Darlington.
El par retroalimentado est formado por TRIO y TR-M, este trabaja solamente
en el semiciclo negativo de la seal que proviene del emisor de TR/, al igual que
el par Darlington, amplifica el nivel de corriente.
Estructura 5
-Vcc
RX
TR12
TR13
V < Vc y VB^VE
SATURACIN: (TBJ = corto circuito)
Para evitar que cualquier sea! parsita que haya ingresado a este circuito
afecte al voltaje DC que se obtiene en la salida (terminal 7), se coloca un
capacitor de un valor pequeo dividiendo a la resistencia de colector R x en dos,
de tal manera que si existe alguna seal de este tipo se dirija a tierra y no a la
salida. El circuito que describe lo antes mencionado es el siguiente:
53
-Vcc
RX1
RX2
TRIZ
TR13
RGURA 1.35) Estructura 6 con un capacitor de desvo para evitar seales parsitas
ib 7.2RF
Entrada o-*N^ Entrah
Canal i
o,
/Opf SS
irtuling
FIGURA 1.36) Circuito de un amplificador de audio estreo de 25 Vatios basado en el C.I. STK
4141
54
MODO ESTREO
Este modo se caracteriza por tener un doble proceso para una misma
fuente, tal es as que, en cada canal se realiza la respectiva amplificacin de la
seal de entrada independientemente del otro canal, y adicionalmente mantiene
sus salidas independientes.
Canal 1
Canal 2
A menudo se requiere que los dos canales lleven la misma seal, sin
independencia entre s. Esto se consigue poniendo las entradas de los canales en
paralelo, conectadas a la seal ya amplificada.
Entrada
de
-12
-24
500 1.0 l 3.0 l 10.0K Hz
1.8.3 SLEWRATE
Cuanto mayor sea el valor del Slew rate del equipo, mejor ser ste. El
problema que se genera cuando el equipo tiene un slew rate insuficiente, es que
no puede seguir las variaciones grandes de seal, provocando el efecto de
triangulacin, es decir, deformando la seal y generando distorsin.
V
Seal de Salida del Amplificador IDEAL
20 V
-27
En a figura 1,40 se muestra una seal con lnea continua que representa
una forma de onda hipottica que tiene que presentar el amplificador de potencia
a la salida, y en lnea punteada la forma de onda que muestra al estar limitado el
valor del slew rate y no poder seguir esa onda.
PA _ Resistencia de Carga
teorico~ Resistencia de Salida ' 1>71
cual se puede despejar que la impedancia de salida a 1 kHz es 8/150 = 0.053 Q..
FA Resistencia de Carga
rear Resistencia de Salida + Resistencia del Cable
Un cable malo, tendr un valor de resistencia alto, que se multiplicar por los
metros de cable, haciendo que disminuya el Factor de Amortiguamiento, es decir,
a la carga le llegar menos potencia. S el cable tiene una resistencia total de 1,
se tendra que FA = 8/(0. 053+1 ) que es casi lo mismo que 8/1 , con lo que FA = 8;
lo que significa que de cada nueve partes de potencia, una se consume antes de
llegar a la carga y ocho en la carga. De 100W, slo 88.8 se consumen en la
carga.
1.8.8 RENmMIENTO
1.9.1 PREAiMPLIFICADORES
Micrfono (600 Q) 1 mV
Micrfono (10 Kl) 2.5 mV
Casetera, CD, DVD, DAT, etc. 150mV
TABLA 1.4) Niveles de voltaje entregados por distintas fuentes
Por otro lado los circuitos amplificadores de audio, no pueden trabajar con
seales de niveles muy bajos a la entrada, puesto que ia amplificacin depende
de las resistencias de retroaiimentacin las mismas que no deben sobrepasar ios
KQ , debido a que resistencias de valores mayores, son muy ruidosas y en los
sistemas de audio es lo menos que se quiere obtener.
Estos son amplificadores de voltaje (figura 1.41) con. una seal de salida
idntica en forma a la de la entrada cuya ganancia de voltaje en lazo cerrado est
dada por la expresin:
a, 1.74
AV
R2
Rl
Zin Ro Zo
R2
Vout
FIGURA 1.42) Diagrama que muestra las impedancias en los diferentes puntos de un amplificador
No inversor.
v
Z,n = -- Ec. 1.75
En donde:
n ~~ error v out
in error v v error
Z = 1
1++AA,.
R .D.. EC 1>78
_ Ec 1.79
Vn Kl
] >
Este tipo de amplificador de voltaje tiene una realimentacin negativa del tipo
RPDP (Retorno Paralelo Derivacin Paralelo).
Ec 1.80
i V J
Ec 1.81
= A,,+1
Z.n =
Ec 1.82
Ec 1.83
69
1.9.2 MEZCLADORES
>Uiut
R2
] >V3Ut
Rjc Res
Ti
PA RSA
Ec. l.
1
72
TA = temperatura ambiente
R-,c y R cs son valores que por lo general son especificados por el fabricante
del dispositivo. Una vez que se conoce la prdida de potencia del dispositivo, P A ,
se puede calcular la resistencia trmica requerida del disipador de calor
asumiendo un valor de Tj segn las hojas de datos del fabricante del elemento y
de acuerdo a las condiciones con las que se desea trabajar. El siguiente paso es
seleccionar el disipador de calor de una dimensin que cumpla con el requisito de
la resistencia trmica.
FIGURA 1.48) Capacitor y resistencia conectados en el secundario para eliminar voltaje transitorio
I0 = corriente de magnetizacin
co = 2nf
Lm = inductancia de magnetizacin
\}s
RGURA 1.50) Capacitor y resistencia conectados en paralelo a la carga para eliminar voltaje
transitorio
Se las utiliza a la entrada de los circuitos para evitar que cualquier voltaje DC
proveniente de la fuente de alimentacin trate de circular hacia la entrada, esto
producto de algn error o desperfecto. Si ocurriere algunos de estos errores o
desperfectos y no se dispone de este tipo de proteccin se ocasionara un
cortocircuito a la entrada averiado al generador de la seal.
MCI
SALDA 1
Por e lado de las seales provenientes de ios micrfonos, se tiene que est
en el orden de 1 mV, la mnima, valor que es 150 veces menor que la seal
proveniente de una entrada auxiliar.
Este valor es mayor que 150 mV, que fcilmente se lo puede obtener con un
amplificador inversor. Para las entradas de micrfonos se necesitar una etapa de
amplificacin de 300, que usualmente se suele obtener mediante dos etapas, pero
por las caractersticas del Cl con el que se va a trabajar (TL084) se lo puede
realizar con una sola etapa solamente sin tener deformaciones en la seal
amplificada.
78
Av = 300
Enirada MIC1
Salida al
Mezclador
m Diseno
Datos:
VIn=lmV
Vout - 300 mV
A v =300
R 2 = 300 KQ (Ideal)
R 2 =300KQ
El valor de la resistencia R3 es igual al paralelo de las resistencias R2 y
decir:
R 3 -996.67 i (Ideal)
R3 =
Por las condiciones propuestas se puede asumir que XC1 = 10 , cuyo valor
X C 1 = n.-.Vr- EC'L90
Ec.1.91
2'Tff-lxlO 3
G! = 7.95[JF
C1=10MF
Enirada MIC1 cl Hi
150 rnV I >JI
Salida al
Mezclador
Datos:
VIn = 150 mV
Vout = 300 mV
u 9
*
R2 = 2 .
El valor de R3 sera;
R 3 =687.5 (Ideal)
R 3 = 680 f
El control del amplificador para que sea capaz de efectuar este trabajo, se lo
realiza mediante computador a travs de una Tarjeta de Adquisicin de Datos y
varios potencimetros digitales con la circuitera correspondiente, cuyos detalles
se los mencionar posteriormente.
82
Datos
Etapa de potencia:
Elemento Tipo VCBO (V) Vc,0 00 VEBO (V) Icmax (A) Pomax (W) Ft (MHz) P
ECG 130 NPN
NPN
180
130
180 5 16
:150) 6 (70>
ECG291 120 5 4 40 4 75
ECG 292 PNP 130 120 5 4 40 4 75
T \*-\2.Po
- ' " msx r- .. n-,
1Lmax
L max - -J
-, Ec. 1.97
[/
vOUTmax
- 14 14 W
t-J-t V
ILmax =3.53 A
R R
Kl -K T o ro
i Lmax -J-J-J
V / 2?
p = pR2 -
rRl r
v R1/D ; =- iJ..UO
m wVV
85
Entonces:
R! =0. 3 3 ^ / 5 W
R 2 -0.
T
BTRI ~ n
P TR\a que los transistores TRS y TR4 trabajen en clase A
siguiente condicin:
T
CTR3 100
Entonces:
49.71 mA A
mA
la corriente que ingresa a las bases de TR1 y T^ . Para hacer cumplir este
requerimiento se debe seguir la siguiente condicin:
R3
R3 < 307.4Q
86
valores encontrados anteriormente para que la corriente que ingrese a las bases
de TR1 y TR2 sea la mitad de la corriente que circula por las resistencias R3 y R5,
respectivamente. Estos valores son los siguientes:
R 3 =150f
R 5 =150Q
i
Se escoge como T^ y TR4 a los elementos ECG291 y ECG292
la siguiente manera:
2 ICTR3 2 0.497mA n 00 A
IR3 = --^ = --- = 0.33mA
=> ! =0.33mA
87
I R4 0.33mA
Etapa excitadora:
Rc -""n i i -7 omax
K c I I inp
VRC
Entonces:
T KL __ ' '^~ __ -3
RC~ R c ~ 6.6K2 ~
Con los datos dados se puede calcular el valor del voltaje de la fuente de
alimentacin (V^), con la siguiente expresin:
Vcc = 28V
este circuito est conformado por dos diodos, los cuales sern los encargados de
mantener los voltajes de base-emisor de cada transistor a 0.7 Voltios. Para
asegurar el voltaje de polarizacin de los diodos se coloca en serie una
resistencia (R 8 ).
Con este dato y asumiendo que la corriente que ingresa a la base de TR3 es
despreciable en comparacin a la corriente que circula por el circuito de
polarizacin (IRC = Ip) se tiene que la resistencia del circuito de polarizacin es la
siguiente:
89
R-
p 3.99mA
3.99mA
= 3,99mA
0.5V
= 125.3152
" ~ 3.99mA
R9 =
mucho menor que R g , de tal manera que para una seal alterna sta circule por
1
X ci < 150
2-n'f-C i
1
1 2-7T-M50
G! = 100 y?
Etapa de Entrada
Elemento Tipo VCBO (V) VCEO (v) VEBO (V) Qnax (/O PDmax (W) Ft (MHz) P
ECG
PNP 100 80 5 0.5 0.5 120 100
290A
Los datos que se tiene para disear esta etapa es la corriente de Base de
TR5 (IBTRS) y el voltaje que cae sobre la resistencia R1S. Para encontrar el valor de
91
la resistencia R 15 , se asume que la corriente que atraviesa por R1S es mayor que
T - T*c - 3""mA = ^q
BTR5 pTO5 + l 100 + 1 y'
IR1S = 0.4mA
V R1S =1.3V
ls=*lL= = 32500
15 IR15 0,4mA
R1S =
R14 = 3300 f
TR6 y T R7 . A ests resistencias se las escoge de valores muy pequeos para que
R13 = 100
t
La resistencia Rn viene a ser la resistencia de emisor del amplificador
diferencial, y cuyo valor debe ser muy elevado, de tal manera que se reduzca la
ganancia en modo comn y se obtenga tener poca distorsin.
Para dimensionar esta resistencia se asume que sobre esta resistencia cae
aproximadamente un voltaje igual a Vcc - VEB (tomando como despreciable a
VR12), entonces el voltaje en R u es 27. 3V. La corriente que circula por esta
resistencia es igual a la suma de las corrientes de los emisores de TR5 y TR7 , es
decir :
Entonces:
^
I
= 0.88mA
D11
^U Bi.oz Kf
Rn = 33 K2
T R7
zln = 32.138 kf
" Etapa de Realimentacin
Avn =
D 2.r
En donde: r = = 26mV
r 0.44mA
__ no
Av n = - - = 27.92
D 2-59. m
26mV
En donde: STRS ^ 3,99mA b - l
i
Av = A v D . A v E
A v = 27.92x355.4 = 9923
Avf=
sea menor que 1 voltio pico, entonces el factor B v tiene que ser igual a 1 .4x1 0"2.
Para obtener este factor se puede dar los siguientes valores para R f y R h :
R h = 560
Av f = 70.64
95
Etapa de proteccin
tensiones.
ECG29H
TR3
C1 1
01'
Rl 1 EMISOR
ECG13O
TR
TRl'
R2'
-vw-
C2ld= R51 ^
OUT
CARGA
TR21
R3'
R41 CCX.ECTOR
ECQ13O
Q2
C31
BASE
ECQ292 4 A
TR4
corrientes y que ni los transistores de salida como los de excitacin sufran algn
dao.
Los diodos D3, y D4, se los utiliza para evitar que ingrese alguna seal por la
Los diodos D:, y D2, se los coloca para restringir el paso de la sea! de
acuerdo a su sentido de flujo, lo permitido es que la seal fluya como muestran
las flechas de la figura anterior, lo contrario provocara una distorsin en la seal
de salida.
en los puntos 5 y 6 para el caso en que TR1, y TR2. deban conducir casi
simultneamente, acelerando su conmutacin para seales de alta frecuencia.
Elementos Adicionales
C4
tomar una porcin de la seal de salida para equilibrar las seales en los puntos 1
y 2 (figura 1.54). La reactancia de este capacitor a una frecuencia de 20 Hz debe
ser despreciable con respecto a R 6 (10.Xa = R 6 /10 = 330 Q ), para que se logre
2-7C-20HZ-3302
C 3 = 47 uF
R 6 ^3.3k;
R 7 = 3.3k
v R 2 = 5 SI
Cz = 0 , 4 i
5 http://www.mcmantom.com/SP/utility/
Para un anlisis terico acerca de las redes de Zobel remitirse a la siguiente fuente: introduction
to Elecroacoustics and Audio Amplifier Desig, Second Edition, Revsed Printing, by W. Marshall
Leach, Jr published by Kendai/Hun, 2001.
99
R17 = 1
Rf =
que filtre cualquier seal parsita que se pueda adquirir. El valor de este capacitor
debe ser muy bajo para que no disminuya a la seal de entrada.
C 6 = 470 pF
C 7 =10|JF
t27V
7819
-O+1BV
1HTERHUFTDR I
HQV 1 . Cl
29 V
1100UF/50V
6A
-O.27V
Debido a que se trabaja con seales de audio se escogi el Cl TL084 por las
siguientes razones:
iour r i U "lour
IIN-f 2 13 "UlN-
un* r 3 12 "UlN-i-
VCE* r 4 11 ~| Vcc-
2INf|~ 5 10 "J3IH-I-
2IN-P 6 3 IsiN-
aourT 7 9 ~J30UT
<< Q9 -f Q10
Q12
l
O1
[ 013 ;;;u
'; wu
Q14
! L,
fQ5 ] r II Q15
J~
J i r
c. .
Q^j {^Q6 D2
laaou ;
hi
v<i- 1
Mas informacin acerca del esquemtico, de] ruteo y de las hojas de datos
del TL084 se encuentran en el anexo C.
105
Los transistores deben estar en contacto con el disipador para que el calor
que se introduce en su interior fluya o escape por el disipador, pero a su vez
deben estar aislados elctricamente del disipador. Para poder cumplir con ambas
condiciones se usan separadores de mica y adems pasta aislantes, que tiene la
propiedad de conducir el calor rpidamente.
Ganancia de
ELEMENTO Canal
Voltaje
MIC 2 1 300,00
1 304,52
MIC1
2 289,77
PREAMPLIFICADOR 1 2,20
AUX1
2 2,20
1 2,20
AUX2
2 2,20
Canal 1 Canal 2
Carga 3,7 f Carga 6,8 Carga 7,3 f Carga 3,7 O Carga 6,8 f Carga 7,3 f
Vin (mV) 126,9 185,9 189,9 108,8 190,6 182,2
Vo (V) 9,7 13,03 13,5 9,6 13,04 13,5
Sensibilidad (mV) 126,9 185,9 189,9 108,8 190,6 182,2
Ganancia de voltaje 76,43 70,09 71,09 88,23 68,41 74,09
Potencia 25,42 24,96 24,96 24,90 25,00 24,96
Factor de
42,04 77,27 82,95 42,04 77,27 82,95
amortiguamiento (FA)
CAPITULO 2:
INTERFAZ HARDWARE
109
2.1 INTRODUCCIN
2.2 DEFINICIN
2.3 DESCRIPCIN
Acondicionamiento
de Seal
Hardware de
Computador
Adquisicin
Fenmeno
Fsico Anlisis
de datos
2.3.1.2.1 Amplificacin
2.3.1.2.2 Filtrado
2.3.1.2.3 Aislamiento
2.3.1.2.4 Muitiplexacin
Es una tcnica que se usa cuando se requiere adquirir varias seales con un
dispositivo de una sola entrada. Primero toma una muestra de la primera entrada
y conmuta a la segunda entrada, toma la muestra y conmuta nuevamente a la
siguiente entrada y as sucesivamente hasta hacer un muestreo todas las
seales, para luego repetir el proceso. La velocidad de muestreo de cada canal es
igual a la velocidad de muestreo del conversor A/D dividido para el nmero de
seales de entrada (canales) muestreadas.
2.3.1.2.5 Fuentes de Excitacin
Entrada Analgica
Salida Analgica
Entrada / Salida Digital
Contador / Temporizador
( Subsistema:^ { , . .
0 i
c . . Subsistema:
Entrada ... . , , .
0
. . . . Salida Anabgica
1 Analgica J \ J
( Subsistema: j
inrada / Salida
Analgica J
f Subsistema: ^
\r j
Contador /
Los subsistemas entrada / salida digital (DIO: Digital Input / Output) estn
diseados para tomar o enviar valores digitales (niveles lgicos) hacia el hardware
o del hardware, tpicamente se los puede usar como bits (lneas) o como un
puerto, el cual tpicamente est conformado de 8 lneas.
2.3.1.5 Software
Software ]
Controlador I CBI
i
T
PARLANTE
a) Adquirir datos.
b) Enviar datos.
2.5 DISEO
entradas analgicas = 8
salidas analgicas = 2
16 entradas/salidas digitales
DAQ= 8 entradas analgicas
2 salidas analgicas
8 Las siete entradas se distribuyen de la siguiente forma; 2 para la entrada de micrfono estreo, 1
para la entrada de micrfono monofnico y 2 para cada una de las entradas auxiliares.
2.6 ELEMENTOS UTILIZADOS
a) Computador personal;
2.6.1.1 Caractersticas
U-
Conector
r-
In-
IGHD
Conectar
1 Conversin analgico-digital
Las seales por su naturaleza son del tipo analgico; es decir, continuas,
variando constantemente con el tiempo: y = f(t). Las seales pueden ser muy
lentas como la variacin de temperatura de un tanque figura 2.7) o muy rpida
como una seal de audio figura 2.8).
Vo Vi
DC ADC
A. A -A A A
TTTTTTTT
D7 DO D7 DO
Voltaje
Re solucin =
2 n -1
10
24 1
10
15
= 0.667
Voltaje Cdigo
0,000 0000
0.667 0001
1.333 0010
1.999 0011
10.000 1111
TABLA 2.1) Relacin voltaje - cdigo
Mtodo Secuencia!
-i n v
1 \J V . . - . .
i-
c; \V
\J ^, >- -<_ _ _ ^.
n \ ..
5 V "" f
Unipolar Bipolar Unipolar
C/J iL
(D J
tn i
tu *
ro Primer muesreo
c Segundo muestreo n-simo muestreo
CU
'o ~0 "O
0 0 O
o O o
o 0 o
...
0 0 o
o o o
o o 0
p p p
>
^ Periodo de muesreo'
Tiempo
Salida Analgica
V
/ C100FF-X
/
FIGURA 2.18) Cable para interconexin entre Tarjeta PCI y el conector terminal
137
Consumo de Potencia
Voltaje: +5 V Corriente: Tpica 0.8 A, Mxima 1 A
Entrada Analgica |
Tipo de conversor A/D ADS 7800
Resolucin 12 bits
Nmero de Canales 8 diferenciales o 16 simples
Rangos de Entrada 10 V, 5 V, 2.5 V, 1.25 V, 0 a 10 V, 0 a 5 V,
(programable) O a 2 . 5 V , O a 1.25V
Polaridad Unipolar o Bipolar
Velocidad Mxima de Muestreo 250 KHz
Automtica, los datos se almacenan en una
Calibracin memoria RAM no voltil que se encuentra en la
tarjeta.
Impedancia de Entrada 10 MQ
Tiempo de conversin A/D 3 jis
Canales de 1 al 15: -40V a + 55V
Mximo voltaje de entrada
Canal 0:15V
Buffer 1024 palabras de tipo FIFO
138
Contadores
Tipo de contador 82C54
2 dispositivos 82C54, 3 contadores
Configuracin descendentes por cada 82C54, cada contador
de 16 bits
1L: 3.0 V mnimo
Voltaje de Salida
OL; 0.4 V mximo
1 L: 2. 0 V mnimo
Voltaje de Entrada
OL; 0.8 V mximo
Frecuencia de Entrada Mximo 10 MHz
Entrada/Salida Digital
Tipo de Interfaz 82C55A
2 grupos de 8 bits y 2 grupos de 4 bits,
Configuracin programable por grupos como entradas o
salidas
Nmero de Canales 24 Entradas/Salidas
1L: 3.0 V mnimo
Voltaje de Salida
OL: 0.4 V mximo
1L: 2.0 V mnimo, 5.5 V mximo
Voltaje de Entrada
OL: 0.8 V mximo, -0.5 V mnomo
TABLA 2.2) Caractersticas generales de la PCI-DAS 1000
2.6.1.2.2 Configuracin
ADC
c CTH2
CTRt
cirio
V
r
<S
CTR2
1 INT CIRl
3
C
ln*x
Cotnle
s
Uief
CTRO
1 CA
PAI7C)
2.6.1.2.4 Interfaz82C55
Modo O, las 24 lneas son divididas en dos grupos de ocho lneas y dos
grupos de 4 lneas, cada grupo puede ser configurado mediante software
como todas entradas o todas salidas.
PA3 3 PA4
FA2 3 PA5
PA1 3 PA<>
3 PA7
RD
"CS 2 RESEl
3 DO
Al _3 DT
AO 3 2
O ^3
2g tx
PC5 ] D5
pom-
peo 2TJ D7
PO1 1 VCC
PC2 i PB7
PC3 3
RBO PBS
3 PB4
PB3
1 Tabla de Verdad
4 4 RD WR es
Operacin: Entrada (Lectura)
0 0 0 1 0 Datos Puerto A=> Bus de Datos
0 1 0 1 0 Datos Puerto B => Bus de Datos
1 0 0 1 0 Datos Puerto C => Bus de Datos
Operacin: Salida (Escritura)
0 0 1 0 0 Bus de Datos n> Datos Puerto A
0 1 1 0 0 Bus de Datos => Datos Puerto B
1 0 1 0 0 Bus de Datos => Datos Puerto C
1 1 1 0 0 Bus de Datos => Datos a Control
Operacin: Desabilitacin
X X X X 1 Bus de Datos => 3 estados
1 1 0 1 0 Condicin Ilegal
X X 1 1 0 Bus de Datos => 3 estados
2 Diagrama de Bloques
-
Control
Grupo A ^ "A"" ^
(8 bus} 1
de Dalos
Icaccional Bufferdel
Bus de
!
Grupo
10
Datos A - PC.
Bus de Puerto
Dalos C
Interno
(B bits)
(4 bits)
Grupo no
B
; ; Puerto
C
(4 bits)
Lgica de
Control
Lectura /
Escritura Grupo 110
Control
sel
Grupo B
= =>
B
Puerto
B
r'
(8 bits)
W
D7 [T 2\C
22] "RD
D4
03 |T
m^
20| Al
DI 18] CLK 2
DO 171 OUT 2
CLK O g 16] GATE 2
GUTO[1_0 15J CLK1
GATE O [TT 14] GATE 1
GMD 12 3l OUT 1
GND 12 Tierra
OUT1 13 O Salida del contador 1
GATE 1 14 I Compuerta de entrada del contador 1
CLK 1 15 I Reloj de entrada del contador 1
GATE 2 16 I Compuerta de entrada de! contador 2
OUT2 17 O Salida del contador 2
CLK 2 18 I Reloj de entrada del contador 2
AO.A1 19- I ADORES S: Selecciona con cual de ios tres contadores se
20 va a trab ajar o las operaciones de read/write en el Control
Word Re gister.
A1 AO Seleccin
0 0 Contador 0
0 1 Contador 1
1 0 Contador 2
1 1 Control Word
Register
CS 21 I CHIPSELECT: habilitacin o deshabilitacin del 82C54
RD 22 I READ: durante operaciones de lectura
WR 23 1 WRITE: Durante operaciones de escritura
Vcc 24 Voltaje de alimentacin
TABLA 2.4) Tabla de verdad del 82C54
IM1 E 13 v.
1N2 [T 2 <v's
REF I o
22] '"-'o
AGND l BUSY
D11 1 20] GS
D9 IZ 18] HBE
] o
D8 17] DO
D7 L ig D1
Qo MI
i
D6 D2
D5 [TT T] D3
D4 n DGND
1 Diagrama de Bloques
Qutput
Lotch9s
And
Triree
State
Olivera
2V
Re eren ce o
Out
2.6.2.1 Smbolo:
- ^
~ -S.. C~$<^''* 'h? 'W'^^%.-^
"^
pypwiv 4 ^^-%^te&
5' iQJi v^^^-^^mm
vc;c
V
v H /P
/r\
Up/Down
U/D
>
<
Increment Control y > V /P
v w /r S/v
i (INC) Memoria ^^
>
<
Device
olo i~t
oeieci
\\ /D
/ r\ L/ r,L
(CS)
or D
NJI
S Circuito de control
s Decoder
S Arreglo de transistores
Arreglo de resistencias
148
II
Memoria No-
Voltil de 7 Decoder
bits
Circuito de
v cc- Control
GND-
3. Tapar el computador;
Salida Digital
# Puerto Ou[V] 1L[V]
1 AO 0.001 5.120
2 A1 0.001 5.120
3 A2 0.003 5.120
4 A3 0.001 5.120
5 A4 0.001 5.120
6 A5 0.001 5,120
7 A6 0.001 5.120
8 A7 0.001 5.120
2.8 FUNCIONAMIENTO
CAPTULOS:
INTERFAZ SOFTWARE
152
3.1 INTRODUCCIN
Existen tres puntos de vista distintos en una IU: el del usuario, el del
programador y el del diseador. Cada uno tiene un modelo mental propio de la
interfaz, que contiene los conceptos y expectativas acerca de la misma,
desarrollados a travs de su experiencia.
diseador, razn por la cual, cuando el producto final es usado por el usuario es
posible que se presenten una gran cantidad de problemas en su aplicacin.
3.2 DEFINICIN
La interfaz del usuario permite comunicarnos con los sistemas y que los
sistemas nos indiquen los resultados y/o las necesidades que surjan de esa
comunicacin.
3.3 DESCRIPCIN
Esta herramienta est conformada por tres componentes, los cuales son:
funciones (almacenadas en archivos de extensin ".m"), el motor de adquisicin
de datos y de un adaptador para el manejo del hardware.
MatLab
Funciones y Datos
Adquisicin de datos
Archivos
Controlador
del Hardware
Valores de Propiedades, datos y
eventos
Sensores
Hardware
Actuadores
3.3.1.1 Funciones
daq= daqhuinf o
daq =
12
Para el caso de las tarjetas de sonido de Windows el nombre del adaptador es "winsound"
157
daq. InatalledAdap-tora
ans =
FIGURA 3.3) Comando para obtener informacin cuales son las DAQ que se encuentran instaladas
daq=daqhwinfo('cbi'}
daq =
daq=daqh*iino ( 'winaound 1 ) .
daq =
Para saber cuales son los subsistemas con los que cuenta ia tarjeta de
adquisicin de datos o la tarjeta de sonido se escribe la siguiente lnea de
comando:
ans =
digitalio('cbi',1)
FIGURA 3.6) Comando para obtener informacin de los subsistemas con los que cuenta la DAQ
UCBI"
daq, Ob j ectConstructorNome ( : )
ana =
FIGURA 3.7) Comando para obtener informacin de los subsistemas con los que cuenta la DAQ
"Winsound"
A/D
PC Board List
Ready NUM
FIGURA 3.8) Software fnstaca/para instalacin y configuracin de las DAQ de Computer Boards
160
, 1 j- -t -. 1 r,.- 1 / ,1 -n"
j - -
PD04-CTR1CWD
PC104-DC06
PC104-DAS08 ; i
PC104-DAS16Jr/12
PC104-DAS16Jf/16
PCI04-DI4S
PC104-DI048
PCI 04-0 Q4BH v
Ready r -...r- A
i -J&lnslacal
F3e InstaH Caforate Test Help
sHI asa'
A/D
3fj A/D
'
m
PCI-DAS1QOQ(!fot#3)|
BaseAddress:
[nlenupl Levet 11
Aceptar Cancelar
H'i-" e :@M
. - - . . : :.._,- '. . i -,.
PlPlPl^NGliMI
a CBosdlt
: l'f. II -;7.:1^:T
1 Cancel I
FIGURA 3.14) Ejecucin de la calibracin del ADC para los diferentes rangos de entrada
163
S La amplitud de la seal,
BoardTcs1;PC!-DAS1000at dfSOh
NC 35 85 CTR5CLK
Complete the conneclionx ahown and NC 35 8E CTR5GATE
veiify a iquaie ave t m the plol wndow. NC 37 87 CTR5
NC 33 83 NC
CTR4CLK 39 89 GND
CTR4 GATE 40 90 +12V
CTR4 41 91 GND
FIGURA 3.15) Pruebas con la DAQ: generacin de seales y adquisicin de las mismas
En las pruebas tambin se puede obtener los datos de una o varias seales
muestreadas, referirse a la siguiente figura.
164
ai = analoginpuf^wi'nsoun")
addchannel(ai,l : 2)
set(ai,lSampleRate'A4WO')
s tari (ai)
getdata(ai)
delete(ai)
ao ~ analogoutpitt(<winsoimds')
166
addcha?mel(ao3l: 2)
set(ao,lSampleRate't44lQG)
4. Envo de datos:
delete(ao)
clea?'(lao1}
addline(diofl : l,*out')
putvahie(dio3 [l O 1 1 O O 1 0])
o
putvalue(dio,U8)
getvahie(dio)
13 La tarjeta de sonido de Windows solo cuenta con dos subsistemas, un subsistema de entrada
analgica y un subsistema de salida analgica.
168
delete(dio)
ai=analoginput( 'cbi',1)
set(ai,'SompleRate1,10)
aet(ai,'SemplesPerTrigger1,5
FIGURA 3.19) Matlab: Configurar la velocidad de muestreo y las muestras que se toman en cada
canal de una entrada analgica
atartfai'
i FIGURA 3.20) Matlab: Comenzar a adquirir datos con la entrada analgica
Amplitud *
ciempo =
0
0.1000
0.2000
0.3000
0.4000
FIGURA 3.22) Matlab: Grfico de las muestras adquiridas con la entrada analgica
Informacion=daqhiffinfo (ai)
Informacin =
AdaptorName: 'cbi1
Bits: 12
Coupling: {'DC Coupled1}
Devicelame: ' PCI-DAS1000 '
DiffierencialIDs: [01234567]
Gains: []
ID: "I1
InputRanges: [8x2 double]
HaxSampleRace: 2SOOOO
Ilin.SampleRa'Ce: 1
HativeDataType: 'uintl6'
Polarity: {'Bipolar'}
Samplel^pe: 'Scanning1
SingleEndedIDs: [01234567]
SubsystemType: 'Analoglnpuc1
TocalChannels: 8
VendorDriverDescripton: 'Computer Boarda Universal
YendorDriverVeraion: ' 5'
i
171
valtaje=InfGemacin.InputRangea
voltaje =
O 1.2500
O 2.5000
Q 5.0000
O 10.0000
-1.2500 1.2500
-2.5000 2.5000
-5.0000 5.0000
-10.0000 10.0000
FIGURA 3.24) Matlab: Informacin de los voltaje de entrada mximos permitidos por la DAQ
FIGURA 3.25) Comunicacin entre los subsistemas y los objetos de la herramienta de Adquisicin
de Datos
untillod.fig
Fe dt Uyout Tools Help
D e y i * 3} e
50 100 110 ZOO SO 300 350 100 450 100 O *
I ^ Select
Q Frame
ELlstbox
GiSPopupMenu
*s Push buttons
^ Toggle button
s Radio button
s Checkbox
Las acciones se relaciones con las funciones, las cuales son almacenadas en archivos .m
173
S Edittext
^ StaticText
S Slider
S Frame
S List box
S Popup men
S Axes
1 Push Button
Este control ejecuta una accin cuando es presionado. Para ejecutar alguna
accin predefinida en este control se debe hacer un clic sobre dicho botn,
despus de realizarse el mencionado clic el botn vuelve a su posicin original
(botn sin presionarse).
Botn sn piesbnaise
3 Radio Button
Este control sirve para ejecutar solo una accin de un grupo de acciones.
\r_ Accin 1
1*1 Accin 2
r Accin 3
FIGURA 3.29) Matlab: representacin grfica de Radio Button
4 CheckBox
Este control sirve para ejecutar una, varias o todas las acciones de un grupo
de acciones.
p Accin 1
r Accin ~L
p Accin 3
FIGURA 3.30) Matlab: representacin grfica de CheckBox
5 Edit Text
6 Static Text
7 Slider
8 Frame
FIGURA 3.34) Matlab: representacin grfica de Frame, frame contiene varios controles
mencionados anteriormente
9 List Box.
Este control se utiliza para seleccionar una accin de una lista de acciones,
en el ejemplo siguiente se muestra lo siguiente: de la lista de acciones (Accin 1,
Accin 2, Accin 3 y Accin 4) se selecciona realizar la tercera accin (Accin 3).
Accin 1 |
Accin 2
$0
Accin 4
10 Popup men
Este control tiene una funcionalidad semejante al control anterior (List Box),
se diferencia del control anterior cmo se muestra grficamente, como ejemplo se
ha seleccionado que realice la Accin 2,
11 Axes
Este control sirve para mostrar grficamente datos que se han obtenido de
una adquisicin de datos o graficar una seal que se ingrese mediante software.
10 20 30 40 50 BO 70 90 100
Los controles tienen propiedades que pueden ser configuradas, entre las
propiedades ms importantes estn:
1 BackGoundColor
Esta propiedad sirve para configurar e! color que el usuario desea que tenga
el control.
2 CallBack
Esta propiedad sirve para que cuando se realice alguna accin (por ejemplo
un clic) sobre el control este ejecute un programa (accin almacenada en archivos
3 Enable
... Esta propiedad sirve para habilitar o deshabilitar un control; es decir, que el
usuario pueda o no acceder a ejecutar alguna accin sobre un control.
4 Font ame
Con esta propiedad se puede seleccionar el tipo de letra que se desea que
tenga el control, esto es cuando el control cuente con letras como es el caso de
un push bution o un static text, pero no es el caso de un slider.
5 Font Size
7 Horizontallisnment
Sirve para configurar la alineacin de las letras, esto puede ser alineado a la
izquierda, a la derecha o al centro.
S Posion
9 Strns
10 Stvle
Indica el tipo de control, como por ejemplo si es toggle buton, checkbox, etc.
11 Visible
*,* untitled.fig
Re Edit Layout Tools Help
FIGURA 3.38) Matlab: representacin varios controles en la pantalla para crear interfaces de
usuario
Donde Units, Color, Menubar, etc. son las propiedades que caracterizarn la
pantalla donde se encuentren los controles, como por ejemplo el cdigo anterior
indica: Creacin de una pantalla (figura) donde la unidades de la pantalla estn
normalizadas15. Adems indica el color que va a tener la pantalla, no va a tener
barra de mens, el nombre de la pantalla es "Pantalla 1", la pantalla no va a estar
numerada ya que MATLAB numera las pantallas que grfica de forma secuencia!,
adems indica la posicin que va a ocupar la pantalla en el monitor del
computador, no va a contar con barra de herramientas, va a poder cambiar de
tamao y va a ser visible al usuario.
uicontrolCUnits'.normalized,...
'BackgroundColorM/l O 1],...
'FontSize',18,...
'ForegroundCoIor'/fO 1 1]',...
'HorizontalalignmentYcenter',...
Position'.fO.ISO.GO.TO.S],...
'StringYEjemplo para crear un control1,...
Style'/text1);
Donde Styie, String, Position, etc. son las propiedades que caracterizarn el
control, como por ejemplo el cdigo anterior indica: Creacin de un control donde
la unidades estn normalizadas; indica el color que va a tener el control, el
tamao de la letra, el color de las letras; el alineamiento de las letras (las letras
van a estar centradas respecto al control), la posicin que va a ocupar en la
pantalla, las letras que va a tener el control, en este caso va a indicar "Ejemplo
para crear un control" e indica el estilo; es decir, indica el tipo de control.
3.5 DISEO
El nterfaz de usuario debe contar con cuatro elementos para manipular los
valores de las entradas, esto se refleja en el interfaz de usuario como cuatro
barras que variando la posicin actan sobre las entradas / salidas digitales
enviando pulsos hacia los potencimetros digitales y de esta forma se varan los
niveles de la seal adquirida por las entradas analgicas.
Adems el interfaz cuenta con otras dos barras para manipular los valores
de las salidas analgicas; es decir, se manipula la amplitud de voltaje que se
enva hacia el amplificador de potencia de audio.
Se debe contar tambin con dos ejes en los cuales se grfica las distintas
seales que se tiene ya sean seales de entrada como las seales de salida,
cabe recalcar que las grficas de las diferentes seales puede ser en el dominio
del tiempo como en el dominio de la frecuencia.
Adems el interfaz debe tener cuadros de texto los cuales indiquen los
valores de potencia de salida del amplificador y valor de la impedancia del
parlante.
El interfaz tambin tiene una barra de mens la cual permite acceder a
ciertas funciones especiales del software como son: cerrar la aplicacin, inhabilitar
ciertos controles, llamar a una pantalla la cual permita realizar la funcin de
ecualizacin, detener la adquisicin de datos y ayuda, se debe programar de tal
forma que se pueda tener accesos a estas funciones con teclas de funcin como
por ejemplo; para ejecutar la accin de cerrar la aplicacin se debera presionar
las teclas ctrl. + Q, se utiliza la letra Q para que junto con la tecla ctrl. cierren la
aplicacin ya que en el software MatLab no se puede usar las letras "C", "X" o "V"
para usarlas como funciones especiales ya que por valores de defecto del sistema
esas letras estn destinadas a Copiar, Cortar y Pegar respectivamente (Copiar =
ctrl. + C, Cortar = ctrl. + X, Pegar = ctrl, + V)
3.6 IMPLEMENTACION
x|
AMPLIFICADOR DE
POTENCIA CONTROLADO
POR COMPUTADORA
figini=figure(...
'Units'.uni,...
'Coor'.colorfondo,...
'Menubar'/none1,...
'NameYInicio1,..,
'NumberTitle'/off,...
'Position'.posicionfig,...
ToolBar'/none',...
'ResizeYoff1,...
Visible1, 'off1,...
'WindowStyle1,'Modal');
uicontrol(...
'Units'.uni,...
'BackgroundColor'.colorfondo,...
'FontSize',18,...
'FontWeight'/bold1,...
'ForegroundColor'/b1,...
'HorizontalalignmentVcener',...
'Posiion',[0.15 0.6 0.7 0.3],... .
'StringYAMPLIFICADOR DE POTENCIA CONTROLADO POR
COMPUTADORA1,...
'Style'/text');
donde; uicontrol sirve para crear un objeto (en este caso un cuadro
de texto), este es un control que est conformado por varias
propiedades
'BackgrondColor' es para configurar el color del fondo
(relleno) del cuadro de texto
'FontSize1 es para configurar el tamao de la letra que
contiene el cuadro de texto
'FontWeight1 es para configurar el grosor de las letras, este se
puede configurar como: light, normal (valor por defecto), demi
o bold, para esta propiedad se puede hacer una analoga con
Microsoft Windows el cual permite como 'FontWeight1 a las
letras: normal o negrilla
'ForegroundColor' es para configurar el color de las letras que
se encuentran en el cuadro de texto
187
Entradas
|cbil
Salidas
Analgicas
Entra/Sal
Digitales fcb
16
El cdigo para realizar todo lo que se describe acerca de la pantalla GrafCONF se indica en el
anexo B.
189
) Configurar
Entradas
Analgicas
Digitales
OK
17 La tarjeta de Sonido WinSound cuenta con dos subsistemas (Entradas Analgicas y salidas
Analgicas) y cada subsistema cuenta con dos canales.
190
Si No
OK
FIGURA 3.44) Matlab: Mensaje de advertencia por la no seleccin de los diferentes subsistemas
3.6.1 CREACIN DE LAS ENTRADAS Y SALIDAS ANALGICAS
ai=analoginput('cbi',1)
addchannel(ai ) 0:9)
ao-analogoutput('winsoundj)
Luego de haber creado la salida analgica se debe agregar canales, con los
cuales se realiza la adquisicin de datos.
addchannel(ao,1;2)
set(ai,'lnputType1,tSinglel)
set(ao,rStandardSampleRatesVOff);
i
velocidad de muestreo mxima de la DAQ (en el caso de la tarjeta con la que se
est trabajando en este proyecto es 250 KHz)
V _ 'MAX
i CAMAL
r ~ M 7
# canales
_ 250000
^ CANAL ~~ ,
VCMAL = 25000
Ecuacin 3.1 Calculo de la velocidad mxima de muestreo por canal
setai/SampleRate'.^SOOO);
se^ao/SampleRate'^SOOO);
se^ai/SamplesPerTrigger'Jnf);
Con la siguientes instrucciones se indica que cada vez que se enve 2500
valores al subsistema de Salida Analgica se ejecuta una accin, la cual es llamar
llamar a la funcin actualizar, la cual se encuentra almacenada en el archivo
actualizar.m.
datos. ai^ai
datos. ao^ao
pru=datos.ai;
se^datos.ao/SamplesOutputAction'.l'actualizar'.pru});
datos. muestras=2500;
194
set(datos.ao,'SamplesOutputActionCount',datos.muestras);
set([datos.ai datos.aoJ/StopAction'/daqaction');
t
La instruccin que se indica a continuacin inicia la adquisicin de datos
start([datos.ai datos.ao]);
dQ-dgitalo('cbi',1)
Luego de haber creado la entrada / salida digital se debe agregar lneas, las
cuales se las utiliza para tomar datos digitales o enviar datos d igitales a algn
elemento externo de la tarjeta de adquisicin de datos.
addline(dio,0:6,fOut');
Para crear la pantalla de usuario se escribe varias lneas (ver Anexo 3.1), las
cuales son para crear los diferentes elementos con los que cuenta la pantalla de
usuario como son: cuadros de texto, ejes para grficos, barra de mens de la
pantalla, botones, etc.
CONTROLADOR
ijj
O D 103
") fS*t>*
100 1K 10K
f r r
r r r
FIGURA 3.46) Matlab: Grfica del ecualizador
-20
Convert aitudmft.,.J
Fdsr
Somcc Oewgrwd
Orcfer 4
Stab!:. Yw
Sectbn: 1 -80
Quanlialcn-
-100
2000 4CXJO 6000 BOOQ 1DOOO 12000
F" Tun quantiatbn on
Frequency (Hz)
DiugnFllei SctQiisrJirationPwflrnefa
iFteqjency 5pecificaliofw_
1 Lowpats UntefH
HIghpetJ f* Spwcifji wdet; [iTi
Bandpaw Fs
Bndriop t*1 Mirimumcfde
Ftlopl: 1 1000 Artopl: J <0
r ]DSfwenalor
Todo software debe estar acompaado por ayudas, para de esta forma
hacer ms fcil su utilizacin al usuario, el software desarrollado cuenta con
ayudas, las cuales son: ayuda del funcionamiento, ayuda acerca de conceptos,
ayuda acerca de cdigo y otras.
3.7 PRUEBAS
Las pruebas realizadas son las de utilizacin del software por parte de
diferentes usuarios, los usuarios han sido: un Ingeniero en electrnica y
telecomunicaciones; una persona con muchos aos de experiencia en sonido en
vivo y un individuo que no tiene relacin alguna con lo referente al sonido.
Cada una de las personas mencionadas en el prrafo anterior han dado sus
opiniones:
"El software permite al usuario tener conocimiento de lo que est sucediendo con
respecto a las entradas de los preamplificadores y las salidas del amplificador de
potencia, es una ayuda adicional a la experiencia obtenida durante toda la carrera
en el sonido en vivo"
"El software no le pareci tan sencillo pero con los archivos de ayuda con los que
cuenta el software permiti continuar con el uso pero con un poco de dificultad"
3.8 UTILIZACIN
18 En caso de correr el programa con MATLAb versin 5.3 (R11) o una versin ms antigua el
programa s e ejecutar p ero a [ I legar a I a p antalla p ara s eleccionar I a t arjeta de a dquisicin d e
datos a utilizar para las entradas analgicas o para las entradas / salidas digitales no reconocer
la tarjeta PCI-DAS 1000.
199
o
3
Tambin se cuenta con un archivo el cual contiene ayuda para el manejo del
software.
CAPITULO 4:
PRUEBAS EN CONJUNTO
202
4.1 INTRODUCCIN
El bus de datos es del tipo SCSI sirve para la interconexin entre el equipo
amplificador y el computador.
Entradas Interruptor
Pfeainplifcador
Amplificador
Fuomo do Alimentacin
Transistores do Poionca
Terminales de Terminales ce
salida salida
4.4 PRUEBAS
Con ayuda del generador de seal se introdujo una seal de 1 KHz la cual
se la filtr mostrndose los resultados tanto en el osciloscopio como en el
software.
4.5 RESULTADOS
y* . ^- J.,.~-.~-,-.~- *
'-- n&j
\U S4"-
-Ti a, u
1 ,. J '
Etapa de Proteccin
Cantidad Elementos Costos(USD)
2 Placas 10
4 Diodos 1N4007 1
2 ECG 1
2 ECG 1
Resistencias 1
Otros 2
TOTAL 16
TABLA 4.5) Costo de los elementos que conforman la etapa de proteccin
210
Interfaz Hardware
Cantidad Elemento Costo (USD)
1 Tarjeta de Adquisision de Datos (con extras) 600
Envi (MiddleBoro-Quito) 200
2 Conectores de 50 pines 10
4 Someras 6
Otros 10
TOTAL 826
CAPTULO 5:
CONCLUSIONES Y RECOMENDACIONES
212
5.1 CONCLUSIONES
5.2 RECOMENDACIONES
BIBLIOGRAFA
[7] http://www.ecgproducts.com
[8] http://www.national.com
[9] http://www.shure.com
[10] http://www.xicor.com
II1] http://www.ni.com
[12] http://www.measurementcomputing.com
A.1
ANEXO A:
ESQUEMTICOS Y RUTEO DE LA PLACAS
A.2
xr x>
19 En el esquemtico mostrado en la figura A.2 solo se muestra la fuente a partir del secundario
del transformador, no se toma en consideracin el primario del transformador, ni el fusible del
primario, ni tampoco del interruptor ya que estos elementos no van conectados directamente en
la baquelita.
A.4
: 20
Figura A.4 Ruteo del Preamplficador de Micrfono Estereofnico
20 Cabe Indicar que en los preamplificadores los elementos que se denominan X_# son
cortocircuitos que se los puso la baquelita para poder realizar el ruteo completo en un solo
lado.
A.6
x-
..j / " 1 "^ m
35
i' 1
*---
SL
;' T;6
.,
iS tr
uiy
_
r?
eH
Jlf
Hl
tL
t=A>
><^~
63
*.
F
I
|
1
1
|
ff 1
^
* \S
A
3
5z
tM 4
IZ T1 o
^- o
2N39Q4 Q^S
_ CN
""I > i r^ D3
^ 1N4004
J
d
O I
12 = 1
h
a
2N3SQ6 47nj[J^
^ I tf
L L 1N4QQ4 ,^
^ < ^
J D4 l<]
a
/O i/
^o L- r ,
o /
7
r y \J
M r:
^ V
^
ro f^_
TJ-^ r^l
o Q
o
Tt
, "ir " 68
IZ
i V
I ! I j
A
R6 4
CM) <
GNU
+5V
Ai(8)
T
VoutAMP
OM
N
Q
Z
ANEXO B:
CDIGO DE LOS PROGRAMAS
INICIO
'Style'/text');
GRAFCONF
% Figura y Elementos =:
figconf=figure(...
'Units'.uni,...
'Color'.colorfondo,...
'MenubarYnone',...
'ame','Configurar1,...
'NumberTitle'/otf,...
B.5
'Position1,datos.pos.CONF,...
'Resize'.'off,...
TooIBar'/none1,...
VisibleVoff1,...
'WindowStyle'/Modal1);
datos. conf.confl=uicontrol(...
'Units'.uni,...
'BackgroundColor',colorfondo,...
'HorizontalAIignmen'/left1,...
'PosiionT,[0.45 0.65 0.25 0.05],...
'String'.tarjetasl,...
'Syle'/popup');
'FontAngleVnormal1,...
'FontNameYArial1,...
'FontSize',9,...
'Foregroundcolor'.colortxt,...
'Horizontalalignment'/left',...
'Units'.uni,...
'Position',[0.25 0.23 0.2 0.12],...
'StringYEntra/Sali Digitales1,...
'Style'/text');
CONTROLADOR
COEFICIENTES
function coeficientes
global datos
datos.Num1=[0.099564306302893 -0.398093004959703 0.597057413580654 -
0.3980930049597030.099564306302893];
datos.Den1 =[1.000000000000000 -3.989827426102192 5.970386749947586 -
3.9712871480843550.990727986894077];
datos.Num2=[0.234367946945844 -0.571235248455397 0.499826684482913 -
0.606921088200406 0.887923547132343 -0.606921088200407
0.499826684482914 -0.571235248455398 0.234367946945845];
datos.Den2=[1.000000000000000 -4.188996762017442 8.004492217889990 -
10.301174613315027 10.317178707320686 -7.645814936021341
3.951492399075484-1.4323036956116040.295128049761257];
datos.Num3=[0.106469385462474 0.336402454184126 0.563146783887494
0.636513293464167 0.454940820173147 0.000000000000004
0.454940820173139 -0.636513293464160 -0.563146783887489
0.336402454184124-0.106469385462474];
datos.Den3=[1.000000000000000 4.107541668351901 10.044701658271228
17.168594861959061 22.731186954276094 23.514473717350178
19.456595376341092 12.568942460825333 6.236759866487948
2.1175647963951370.431709115812180];
datos, barr =1;
datos.barr2=1;
datos.barr3=1;
1.11
DIGITAL
ANALGICO
set(datos.ai)lManuaITriggerHwOnl,Triggerl)
set(datos.ai,'SamplesPerTrgger',inf);
datos.muestras^SQOS;
%datos.muestras=2500;
va!ores=zeros(4*datos.muestras,2);
putdata(datos.ao, valores);
pru=datos.a;
set(datos.ao/SamplesOutputAction\{'actualizar',pru});
setdatos.ao/SampIesOutputActionCount'.datos.muestras);
set([datos.ai datos.aoJ/StopActionVdaqaction1);
start([datos.ai datos.ao]);
trgger([datos.ai datos.ao]);
datos.empo-zeros(datos.muestras^);
datos.bar=Q;
datos.barraco;
datos.cheq^O;
datos.det^O;
datos. pantalIa-0;
datos.pun=ni
datos.texto^O;
datos.va!=Q;
ACTUALIZAR
datos.tiempo(:)1)*get(datos,bar.bar2lValuel)+datos.tempo(:I2)*get(datos.bar.bar1l
Value')+daos.tempo(:)4)*get(datos.bar.bar4,VaIuel)+datos.tiempo(:I6)*get(datos.
barbara/Valu 1 )];
datos. valor-[datos.mezcla(:,1)*get(datos.bar.bar5, Valu1)
datos. me2cla(:,2)*get(datos.bar.bar6J Valu1)];
datos.filtrar(:,1)=datos. barr *filter(datos.Num1Jdatos.Den1 .datos. valor(:,1))+datos.
barr2*fIter(datos.Num2,datos.Den2datos.vaIor(:l1))+datos.barr3*filter(datos.Num
3,datos.Den3,datos.valor(:,1));
datos.fItrar(:,2)=datos. barr *filter(datos.Num1 .datos. Den1,datos.valor(:I2))+datos.
barr2*flter(datos.Num2ldatos.Den2,datos.valor(:l2))+datos.barr3*filter(datos.Num
3,datos.Den3,datos.valor(:,2));
if datos, ref O
mpedancia;
datos. ref=1
end
datos. Vx1=max(datos.filtrar(:,1));
datos.Vx2=max(datos.filtrar(:,2));
switch round(datos.imped)
case 2
f datos.Vx1>0.186
end
fdaos.Vx2>0.186
datos.filtrar(:,2)^(0.186/datos,Vx2)*datos.fItrar(:,2);
end
B.14
case 4
fdatos.Vx1>0.263
datos.fItrar(:,l)=(0.263/datos.Vx1)*datos.fItrar(:l1);
end
ifdatos.Vx2>0.263
datos.fltrar(:,2)^(0.263/datos.Vx2)*daos.f[trar(:)2)
end
case 6
fdatos.Vx1>0.322
datos.filtrar(:)1)=(0.322/datos.Vx1)*datos.filtrar(:,1);
end
fdatos.Vx2>0.322
datos.filtrar(:l2)=(0.322/datos.Vx2)*datos.filtrar(:,2);
end
case 8
ifdatos.Vx1>0.372
datos.fItrar(:,1)=(0.372/datos.Vx1)*datos.fiItrar(:)1);
end
ifdatos.Vx2>0.372
datos.fItrar(:12)=(0.372/datos.Vx2)*datos.fiItrar(:)2);
end
case 16
fdatos.Vx1>0.526
datos.filtrar(:J1)=(0.526/datos.Vx1)*datos.fiItrar(:l);
end
ifdatos.Vx2>0.526
datos.fltrar(:]2)=(0.526/datos.Vx2)*datos.fltrar(:,2);
end
end
putdata(obj,datos.fltrar);
potencia;
B.15
%EJE 1
if datos.vec(3)==1
set(eje(1 ),1XLiml,[1 datos. muestras]);
if datos. vec(1)<=2
set(linea(1 ),lYDatal,datos.filtrar(:,datos.vec(1 )));
else
set(Iinea(1 ),'YDatalldatos.canal(:Jdatos.vec(1 )-
end
else
[f,mag]=Frecuencia(1 );
maxF-max(f);
minF=mn(f);
xax=get(eje(1 ),'
if minF<xax(1)
xax(1)=mnF;
end
if maxF>xax(2)
xax(2)=maxF;
end
maxM:rmax(mag);
minM=min(mag);
yaxl =get(eje(1 ),
if mnM<yax1(1)
end
f maxM>yax1(2)
yax1(2)=maxM;
end
set(eje(1),'YLim',yax1)
set(linea(1)/XData')f)lYDatal,mag);
end
B.16
%EJE 2
if datos.vec(4)==l
set(eje(2)JlXLiml,[1 datos. muestras]);
fdatos,vec(2)<=2
set(]inea(2)/YData\datos.filtrar(:,datos.vec(2)));
else
set(inea(2),'YData1)datos.canal(:)datos.vec(2)-2));
end
else
[f,mag]=Frecuencia(2);
maxF=max(f);
mnF=min(f);
xax=get(eje(2);XLim');
if minF<xax(1)
xax(1)=minF;
end
if maxF>xax(2)
xax(2)-maxF;
end
set(eje(2))lXLm')xax);
maxM^max(mag);
minM=min(mag);
yax1=get(eje(2)JlYLiml);
f mnM<yax1(1)
end
f maxM>yax1(2)
yax1(2)=maxM;
end
set(eje(2)I'YLml,yax1 );
set(]inea(2) J 'XData lJ f ll YData' I mag);
end
drawnow;
B.17
GRFICO
'BackgroundColor'.coIorfig,...
'Callback'/Potenciomero("pot1")',...
'Position',[(0.03+2.25*espab) ab 0.15 0.03],...
'Min1,mnimo,...
'Max1,mximo,...
'SliderStep'.pasos,...
Valu1,valor,...
'Style'/slider');
Value'.valor,...
Style'/slider1);
'Style'/text');
'HorizontalAlignment'/left',...
'Position',[0.095 (ab-13*espab) 0.11 0.04],.
'String'.combol,...
'Style'/popup',...
Value',2);
'Style'.'popup');
B.23
'HorizonalAlignmentYleft',...
'Position',[0.095 (ab-15*espab) 0.11 0.04],..
'String'lcombo2J...
'StyleYpopup');
'Style'/push1);
'Color'.colortxt,...
'Parent',ej'e(1),".
'XData',1:datos. muestras,...
l YData',datos.tiempo(: J 1 ));
'YData',datos.tempo(:,1));
Archivo=uimenu(lParent']datos.pantalla.figura,...
'Labe!1,'Archivo');
Cerra=umenu(Archvo,...
'LabelYSalir1,...
'Callback','Cerrar',...
'Separator'/On1,...
'Accelerator'/S');
Frase=uimenu(Parent\datos.pantalla/figura,...
'Label','Funciones');
datos.ecualiza=uimenu(Frase,...
'Label'/Ecualizador1,...
'CalIbackYGrafEQ',...
'Acceleraor'/E');
datos.detener-umenu(Frase,...
'Laber/lniciar',...
'Callback'/Detener',...
'Separator'.'On',...
'Accelerator'.'D');
datos. impedancia=uimenu(Frase,...
'Label'/Impedancia',...
'Callback',Impedancia',...
'Accelerator'/P');
datos.inhabilta=umenu(Frase,...
'Labe!','Inhabilitar Controles',...
'CalIbackYInhabilitar1,...
'Accelerator1/!');
Ayu=uimenu('Parent', datos, pantalla/figura,...
'Label'/Ayuda');
AyuO=uimenu(Ayu,...
B.26
'LabeP/Ayuda1,...
'CalIbackYAyudaC'AyudaA'1)1,...
'Accelerator'.'H');
Ayu01=umenu(Ayu,...
'LabeP/Ayuda General1,...
'Separator'/On');
Ayud3=uimenu(Ayu01,...
'Label'/Codigo1,...
'CalIback'/AyudaC'AyudaB' 1 )');
Ayud1=uimenu(Ayu01,.,.
'LabeP,'Conceptos1,...
'Callback'/AyudaC'AyudaC'1)1);
Ayud2~umenu(Ayu01,...
'Label'.'Funcionamiento1,...
'Callback'/AyudaC'AyudaF1')1):
Ayud4 ~ umenu(Ayu01,...
'LabeP/Informacion 1 ,..-
'CalIback'.'AyudaC'Ayudal'1)1);
set(daos.pantalla.fgura, Visible1, 'on');
datos.pantalla.ejes^eje;
datos, pantalla. lineas=linea;
TEXTO
'FontWeight'/demi',...
'ForegroundColor'.colortxt,...
'Position'.fO.SS 0.94 0.3 0.06],...
'StringYCONTROLADOR1,...
Valu1,1,...
'Enable'/lnactive1,...
'Style'/togglebutton');
postxt={ab,ab-espab,ab-2*espab,ab~3*espab,ab-4*espab,ab-5*espab};
strtxt={'Micrfono 1 '/Micrfono 2','Auxiliar 1 '/Auxiliar 2','Master A'/Master B'};
fori=1:6
uicontrolCUnits'.uni,...
'HorizontalAlignment'/left1,...
'BackgroundColor'.colorfig,...
'ForegroundColor'.colortxt,...
'Position'.p.OS postxt{}0.11 0.03],...
'String'.strtxtffi,...
'Style'/text');
end
'Style'/text');
end.
uicontroICUnits'.uni,...
'HorizontalAlgnment'/left',...
'BackgroundCoIor^colorfig,...
'ForegroundCoIor'.coIortxt,...
'Positon',[0.03 postxt{} 0.14 0.03],...
'String',strtxt{},...
'Style'/text');
end
CERRAR
putvalue(datos.dio.line(k+2),0);
end
end
for =0.1:0.1:2*datos.valores(2)
k=4;
if getvalue(datos.dio.line(k))==0 % Contador (INC)
putvalue(datos.dio.line(k)]1);
putvalue(datos.do.line(k+2),1);
else
putvalue(datos,dio.line(k),0);
putvalue(datos.dio.Iine(k+2)J0);
end
end
for =0.1:0,1 ;2*datos.valores(3)
k=15;
if getvalue(datos.dio.line(k))==0 % Contador (INC)
putvalue(datos.do.line(k),1);
putvalue(datos.do.line(k+2),1);
else
putvalue(datos.dio.line(k),0);
putvalue(datos.dio.lne(k+2),0);
end
end
fori=0.1:0.l:2*datos.valores(4)
k=18;
if getva[ue(datos.dio.Ine(k))O % Contador (INC)
putvalue(datos,dio.lne(k),1);
puva]ue(datos.dio.line(k+2),1);
else
putvalue(datos.dio.lne(k)J0);
putvalue(datos.dio.ne(k+2),0);
end
end
B.31
if isvalid(datos.ai)
if strcmptge^datos.ai/Running'VOn1) % Comparacin de String's
stop([datos.ai datos.ao]);
end
delete([datos.ai datos.ao datos.dio]);
end
cise all
ce
GRAFEQ
'Position'.posicionfig,...
ToolBar'/none',...
'Resize'/off1,...
Visible'/off);
'BackgroundCoor'.colorfondo,...
'FontAngle'/normal1,...
'FontName'/Arial1,...
'FontSize',8,...
'ForegroundColor'.colortxt,...
'Horizontalalignment'/center1,...
'Units'.uni,...
lPosition',[(3*espancho+2*ancho~0.02) espalto espa 0.08],
'String'/IOK',...
'Style'/text');
minimo=-3;
maximo=3;
pasos=[1/(maximo-minimo) 0.18/(maximo-minimo)];
valor-O;
'Min'.minimo,...
B.34
'Max'.maximo,...
'SliderStep', pasos,...
Value'.valor,...
'Units'.uni,...
lPosition',[(2*espancho+ancho) alto ancho 0.5],.
'StyleVslider');
'Max1, mximo,...
'SliderStep'.pasos,...
Value'.valor,...
'Units'.uni,...
'Position'.^espancho+Z^ancho) alto ancho 0.5],.
'Style'/slider1);
datos.texto.texto2-uicontrol(...
'BackgroundColor'.colorfondo,...
'FontAngle1,'normal1,...
'FontName'/Arial1,...
'FontSize',8,...
'ForegroundColor'.coIortxt,...
'Horizontalalignment'/center1,...
'Units'.uni,...
'Position',[(2*espancho+ancho-0.02) espabajo espa 0.08],...
'String',get(datos.barra.barra2I'Valuet)1...
'Style'/text1);
'Callback'/closegcf)1,...
'String'/CERRAR');
set(figeq/Visible'/on'); % Pantalla Visible
POTENCIMETRO
calculo(str2num(get(datos.val.val2/Stringr))lstr2num(sprintf(l%3.1fIget(datos.bar.b
ar2/Value t )))j,k);
set(datos.vaI.vaI2/Stringlsprintf(l%3.1f,get(datos.bar.bar2/Value1)));
set(datos.bar.bar2/Valu1,str2num(get(datos.val.vaI2/String')));
case 'potS1
j=11; % Pin 11 de la tarjeta para contador U/D
k=15; % Pin 15 de la tarjeta para contador INC
B.37
calculo(str2num(get(datos.val.val3llStringl)))str2num(sprintf(I%3.1f)get(datos.bar.b
ar3/Va[ue')))j,k);
setdatos.val.valS/String'.sprintfCyoS.lf.gedatos.bar.barS/Value1)));
set(datos.bar.bar3)'ValueIlstr2num(get(datos.val.vaI3,'Strng1)));
case 'pot4'
j=14; % Pin 14 de la tarjeta para contador U/D
k-18; % Pin 18 de la tarjeta para contador INC
calculo(str2num(get(datos.val.val4)lString'))Istr2num(sprintf(I%3.1fJget(datos.bar.b
ar4,Value l )))j ) k);
set(datos.vaLval4,IStrngl,sprntf(1%3.1flget(datos.bar.bar4)lVa[ue1)));
set(datos.bar.bar41Va[uerIstr2num(get(datos.va[.vaI4,lStrng1)));
case 'potS1
seXdatos.val.valS/String'.sprintfCyoS.lf.ge^datos.bar.barS/Value 1 )));
set(datos.barbar51IVaIuel]str2num(get(datos.va[.vaI5l'String1)));
case 'potG'
setdatos.val.valG/Stnng'.spnntfCyoS.lf.getdatos.bar.barG/Value 1 )));
set(daos.bar.bar6,lVaIuellstr2num(get(datos.val.vaI6,1String1)));
end
CALCULO
putvalue(datos.dio.line(k+2),1);
else
putvalue(datos.dio.!ine(k),0);
putva!ue(datos.dio.Iine(k+2),0);
end
end
elseif c--0
else
putvalue(datos.dio.lineG),0); % Down
c=-c;
for i=0.1:0.1:2*c
if getvalue(datos.dio.line(k))==0 % Contador (INC)
putvalue(datos.dio.line(k),1);
putvalue(datos.dio.line(k+2),1);
else
putvalue(datos.dio.!ine(k),0);
putvalue(datos.dio.line(k+2),0);
end
end
end
DETENER
start([datos.a datos.ao]);
%trigger([datos.ai datos.ao]);
set(datos.detener,'Laber,'Detener');
set(daos.pantalla.detener/String','Detener Adquisicin1);
datos.det-0;
end
DOMINIO
FRECUENCIA
case 2
if datos.vec(2)<=2
xFFT=fft(datos.filtrar);
else
xFFT-fft(datos.canal);
end
end
xfft-abs(xFFT);
ndice=find(xfft==0);
xfft(indice)=1e-17;
mag=xfft;
[a,b]=size(mag);
switch evento
case 1
f b==2
mag=mag(1 tdatos.muestras.datos.vecl));
else
mag=mag(1 :datos.muestras,datos.vec(1 )-2);
end
case 2
f b=^2
mag=mag(1:datos.muestras]datos.vec(2));
else
mag-mag(1:datos.muestrasJdatos.vec(2)-2);
end
end
f=(0;Iength(mag)-1)*25000/datos.muestras;
B.41
INHABILITAR
SALIDA
IMPEDANCIA
POTENCIA
if datos.imped~~0
p-Vx*Vx/datos.imped
else
P=0;
end
P1=num2str(P);
set(datos.potencia.pot/String'.strca^PI,' (vatios)1));
ECUALIZADOR
AYUDA
openCAyudaPnncipaI.htm1)
case 'AyudaC1
open('AyudaConceptos.htm')
case AyudaF1
open(AyudaFunconamiento.htrn')
case 'AyudaB1
open(AyudaCodigo.htm')
case 'Ayudal1
openCAyudalnformacion.htm1)
end
C.1
ANEXO C:
HOJAS DE DATOS
C.2
PCI-DAS1000,
PCI-DAS1001
&
PCI-DAS1002
Multifunction
Analog & Digital I/O
User's Manual
MEASUREMEIMT
COMPUTING,
MEGA-FIFO, the CIO prefix to data acquisiion board model numbers, the PCM prefix to data
acquisition board model numbers, PCM-DASOS, PCM-D24C3, PCM-DAC02, PCM-COM422,
PCM-COM485, PCM-DMM, PCM-DAS16D/12, PCM-DAS16S/12, PCM-DAS16D/16, PCM-
DASlS/16, PCI-DAS6402/16, Universal Library, InsiaCzl, Harsh Environment Warranty and
Measurement Computing Corporation are regstered trademarks of Measurement Compuing
Corporation.
IBM, PC, and PC/AT are trademarks of International Business Machines Corp. Windows s a
trademark of Microsoft Corp. All other rademarks are the property of their respective owners.
Information furnshed by Measurement Computing Corp, is beeved to be accurate and reable.
However, no responsibity is assumed by Measurement Computing Corporation neither for its use;
or for any infringements of patents or other rights of third paries, which may result from its use.
No license is granted by mplication or otherwse under any patent or copyrights of Measurement
Computing Corporation.
Ail rights reservad. No part of this publication may be reproduced, stored in a rereval
system, or transmitted, in any form by any means, electronic, mechanica, by
photocopying, recording or othenvise without the prior written permssion of
Measurement Computing Corporation.
NOTICE
Measurement Computing Corporation does not authorze any Measurement
Computing Corporation product for use in Ufe support systems andlor
devices without the written approval of the Presdent of Measurement
Computing Corporation Life support devicesisystems are devices or
systems which, a) are intended forsurgcal implantation nto the body, or b)
support or sustain Jife and whose failure to perform can be reasonably
expected to result in injury. Measurement Computing Corp, producs are not
designed with the components required, and are not subject to the testing
required to ensure a level of reliability sutable for the treatment and
diagnosis of people.
HMPCI-DAS100#.doc
C.4
Table of Contents
1 Introduction 1-1
2 Installation 2-1
2.1 Software Installation 2-1
2.2 Hardware Installation 2-1
2.3 Connector Pinout Diagrams 2-2
2.4 Connecting Signis to he PCI-DAS1000.. 2-7
3 Programming & Applications 3-1
3.1 Programming Languages 3-1
3.2 Packaged Application Programs 3-1
3.3 Register Level Programming 3-1
4 Calibration 4-2
4.1 Calibration Configuracin - Analog Inputs 4-2
4.2 Calibration Confguration - Analog Outputs (PCI-DAS1001 & PCI-DAS1002
Only) 4-3
5 Specifications: PCI-DAS1000 & 1001 5-1
f
C.6
1 Introduction
The PCI-DAS1000, PCI-DAS1001 and PCI-DAS1002 are multifunction analog and
digital I/O boards designed to oprate n computers with PCI bus accessory slots. The
boards have the following capabilities:
The PCI-DASIOOO seres is fully plug-and-play wih no switches orjumpers to set. The
boards are self-calibrating with no potentiometers to adjust. All calibration is performed
va software and on-board trm D/A converters.
The PCI-DASIOOO series is fully supported by the powerful Universal Library software as
well as a wide variety of appiicaion software packages including SoftWIRE.
NOTE:
Unless a specifc mode code is required, ths manual references the PCI-DASIOOO as a
general term.
1-1
C.7
2 Installation
2.1 Software Installation
The board has no switches or jumpers to set. The simplest way to configure your board s
to use the InstaCal program provided on the CD (or floppy disk). InstaCal will crate
a configuration file that your application software (and the optional Universal Lbrary)
will refer to so the software you use will automatcaly have access to the exact
configuration of the board.
Please refer to the Software Installation Manual regarding the installaton and operation of
InstaCal.
WARNING
Do not unplug the computer when nstaliing the board.
Doing so removes the computer's ground.
1. Turn your computer off, open it up, and insert the PCI-DAS1000 board into
any available PCI slot.
2. Cise your computer up and turn it on,
3. If you are using an operating system with support for Plug and Play (such as
Windows 95 or 98), a dialog box will pop up as the system loads indicating
that new hardware has been detectad. If the information file for this board is
not already loaded onto your PC, you will be prompted for a disk contaning
it. The InstaCal software supplied with your board contains this file. Insert
the disk or CD and click OK.
2-1
PCI-DAS1000, 1001 & 1002 User's Manual Installation
2-2
C.9
2-3
C.10
2-4
C.11
2-5
C.12
2-6
C.13
2-7
C.14
PCI-DAS 1000, 1001 & 1002 User's Manual Programmmg & Applications
Some application drivers are included with the Universal Library package, but not with
the Application package. If you have purchased an application package directly rom the
software vendor, you may need to purchase our Universal Library and drivers. Please
contact us for more information on this topic.
Although the PCI-DASIOOO is part of the larger DAS family, there is no correspondence
between register locations of the PCI-DASIOOO and boards in the CIO-DAS16 family.
Software written at the register level for the other DAS boards will not work with the PCI-
DAS 1000. However, software based on the Universal Library should work with the PCI-
DASIOOO with few or no changes.
If you decide that register level programming is required for your application, information
on the register functions can be found at
http://www.rneasurementcornputing.com/registermaps/.
3-1
C.15
4 Calibration
The PCI-DAS1000 is shipped fully-calibratedfrom the factory with calibraton
coeffcients stored in nvRAM. At run time, these caibration factors are loaded into system
memory and are automaticaily retrieved each time a different DAC/ADC range is
specifed. The user has the option to recalibrate with respect to the factory-measured
voltage standards at any time by selecting the "Calbrate" option in InstaCal. Full
caibration typcally requires less than two minutes and requires no other user intervention.
A variety of methods are used to calbrate the different elements on the board. The analog
front-end has several software "knobs" to tum. Offset caibration is performed in the
instrumentation amplifier gain stage. Front-end gain adjustment is performed via a
variable attenuator/gain stage.
Figure 4-1 is a block diagram of the anaog input front-end caibration system:
Variable Gain
4-2
C.16
Analog Out
4-3
C.17
PCr-DASlOOO, 1001 & 1002 User's Manual Specifications: PCI-DASIOOO & i 001
Power Consumption
+5V Operating (A/D converting to FIFO) | 0.8A typical, l.OA max
5-1
C.18
PCI-DAS1000, 1001 & 1002 User's Manual Specifcations: PCI-DASiOOO & 1001
Throughput
PCI-DAS1001 ISOkHz
PCI-DASIOOO 250 kHz
Reative Accuracy 1.5 LSB
Differental Linearty error: 0.75 LSB
Integral Linearity error 0.5 LSB typ, 1.5 LSB max
Gain Error (reative to calibration
reference)
O.OlVRange 0.4% of reading Max
Al I other Ranges 0.02% ofreading Max
No missing codes guaranteed 12 bits
Calibration Auto-calibration, calibration factors for
each range stored on board in non-
volatile RAM
Gain drifc (A/D specs) 6ppm/C
Zero drift (A/D specs) lppm/C
Common Mode Range 10V
CMRR @ 60Hz 70dB
Input leakage current 200nA
Input impedance lOMeg OhmsMin
Absolute mximum input voltage
PCI-DAS1001 35V
PCI-DASIOOO Channels 1-15: -40V to -H55V power on
or off
ChannelO:15V
Noise Distrbution (Rate = I-250KHz3
Average % 2 bins, Average % 1 bin,
Average # bins)
PCI-DASIOOO
All Bipolar ranges 1 00% / 99.5% / 4 bins
AI1 Unipolar ranges 1 00% / 99% / 5 bins
PCI-DAS1001
10V Ranges 3 bins (100%)
IV Ranges 4 bins (100%)
0. IV Ranges 10 bins (100%)
Bipolar O.OlVRange 20 bins (100%)
Unipolar O.OlVRange 32 bins (100%)
5-2
C.19
PCI-DAS1000, 1001 &, 1002 User's Manual Specfcations: PCI-DAS1000 & 1001
Throughput PC-dependent
Settling time (to 0.01% of 10V step): 4us typ
Slew Rate 7V/uS
5-3
C.20
Counter section
Counter type 82C54
Confguration Two 82C54 devces. 3 down counters per 82C543 16
bits each
82C54A: Counter 0: ADC residual sample counter.
Source: ADC Clock Gate: Internal
programmable source
Output: End-of-Acquisition interrupt
Counter 1: ADC Pacer Lower Divider
Source: 10 MHz oscillator
Gate: Tied to Counter 2 gate, programmable
source.
Output: Chained to Counter 2 Clock.
Counter 2: ADC Pacer Upper Divider
Source: Counter 1 Output.
Gate: Tied to Counter 1 gate,
programmable source.
Output: ADC Pacer clock (if
software selected),
availabe at user
connector (A/D
Interna! Pacer Output).
5-4
C.21
PCI-DAS1000, 1001 & 1002 User's Manual Specifcations: PCI-DAS1000 & 1001
5-5
C.22
Environmental
Operating temperature range 0 to 70C
Storage temperature range -40tolOOC
Humidity 0 to 90% non-condensing
5-6
C.23
6 Specifications: PCI-DAS1002
Typical for 25C unless ohenvise specified.
Power consumption
+5V 0.8A typica!, l.OA max
Analog inputsection
A/D converter type ADS7800 or equivalen!
Resolution 12 bits
Number of channels 16 single-ended / 8 differential, software
seiectable
Input ranges 10V, 5V, 2.5V, 1.25V, 0 to 10V, 0 to 5V, 0
to 2.5V, 0 to 1.25V software programmabe
A/D pacng Interna! counter- 82C54.
(software programmabe) Extemal source (A/D Externa! Pacer) software
programmabie for rising or falling edge
Software polled
A/D trigger sources Externa! edge trigger (A/D Externa! Trigger)
A/D triggering modes Rising or falling edge trigger - software
selectable
A/D pre-trigger mode Unlimited pre- and post-trigger samples. Total
number of samples must be greaterthan 512.
Burst mode Software selectable option, burstrate ~ 150kHz
Data ransfer From 1024 sample FIFO via REPINSW
Programmed I/O
A/D conversin time 3jis max
Analog front end settling time 6us for a rull scale step to 1 LSB
Calibrated throughput 200KHz
Calibraton Auto-calibration, calibration factors for each
range stored on board in nonvolatile RAM
6-1
C.24
Accuracy
Accuracies are listed for a 200KHz sarnpling rate, 100 sample average, single channel
operation, a 15 minute warm-up, and operational temperatures \vithin 2degC of internal
calibraion temperature. The calibrator test source high side is tied to Channel O In and the
low side tied to AGND.
Crosstalk
Crosstalk is defined here as the influence of one channel upon another when scanning two
channels at the mximum rate. A ful! scale lOOHz trangle wave is input on Channel 1;
Channel O is tied to Analog Ground at the 100 pin user connector. The table below
summarizes the influence of Channel 1 on Channel O with the effects of noise removed.
The residue on Channel zero is described in LSB's.
Condition Crosstalk Per channel Rate ADCRate
All Ranges 2 LSB pk-pk lOOKHz 200 KHz
6-2
C.25
Noise Performance
Table 3 below summanzes the noise performance for the PCI-DAS1002. Noise
distribution is determined by gathering 50K samples at 200kHz with inpus tied to ground
at the user connector.
Table 3 Board Noise Performance
Range % within 2 LSB % within 1 LSB LSBs LSBrms*
Oto 1.250V 100% 99% 4 0.61
All other ranges 100% 100% 3 0.45
RMS noise s defmed as the peak-to-peak bin spread divided by 6.6
6-3
C.26
Absoluta Accuracy
Ail Ranees 3 LSB
Total board error is a combination of Gain, Offset, Integral Linearity and Differential
Linearity error. The theoretical worst-case error of the board may be calculated by
summing these component errors. Worst case error is realizad only in the unlikely event
that each of the component errors are at their mximum level, and causng error in he
same direction. Although an examination of the chart and a summation of the mximum
theoretical errors shows that the board could theoretically exhibit a 3,5 LSB error, our
testing assures this error is never realized in a board that we ship.
Monotonicity Guaranteed monotonic over temperature
Overall Analog Output drift 0.03 LSB/C max
Settling time 4usto0.01%of lOVstep
Slew Rate 7V/us min
Current Drive 5 mA min
Output short-circuit duration Indefnite @25mA
Output coupling DC
Output impedance 0.1 ohms max
Miscellaneous Double buffered output latches
Output voltage on power up and reset: 200mV
6-4
0.21
Counter section
Counter type 82C54
Configuration Two 82C54 devices, 3 down counters per S2C54,
16 bits each
Counter 1 - ADC residual Source: ADC cock
sample counter Gate: Intemal programrnable source
Output: End of acquisitlon interrupt
Counter 2 - ADC Pacer Lower Source: 10 MHz interna! source
Divder Gate: Internal, programrnable on/off
Output: Chained to Counter 3 Clock
Counter 3 - ADC Pacer Upper Source: Counter 2 Output
Divider Gate: Interna!, programmabie on/off
Output: Programmabie as ADC Pacer clock.
Available at user connector (ADC
Pacer out)
Counter 4 - Pre-trigger mode Source: ADC clock for pre-trigger mode
Gate: Extemal trgger for pre-trigger mode
Output: End of acquisition interrupt for pre-
trigger mode
Counter 4 - Non-Pre-Trigger Source: Extemal at connector (CTR4 CLK)
mode Gate: Externa! at connector (CTR4 GATE)
Output: Available at connector (CTR4 OUT)
Counter 5 - User counter Source: External at connector (CTR5 CLK)
Gate: Extemal at connector (CTR5 GATE)
Output: Available at connector (CTR5 OUT)
Counter 6 - User couner Source: Externa! at connector (CTR6 CLK)
Gate: Extemal at connector (CTR6 GATE)
Output: Available at connector (CTR6 OUT)
Clock input frequency 1 OMhz max
High pulse width (clock input) 30ns min
Low pulse width (clock input) 50ns min
Gate width high 50ns min
Gate width low 50ns min
Input low voltage O.SVmax
Input high voltage 2.0V min
Ouput low voltage 0.4V max
6-5
C.28
6-6
C.29
Interrupt section
Interrupts PCI INTA# - mapped to IRQn va PCI BIOS
atboot-time
Interrupt enable Programmable. Default = disabled.
Interrupt sources Residual sample counter
A/D End-of-channel-scan
A/D FIFO-not-empty
A/D FIFO-half-full
A/D Pacer
Miscellaneous
+5 Volts Available at I\ connector (PC+5V)
+12 Volts Available at I\ connector (PC +2V)
-i 2 Volts Available at I\ connector (PC -12V)
Environmental
Operatng Temperature Range O t o 70C
Storage Temperature Range -40 to 100C
Humidity O t o 95% non-condensing
Mechanical
Card dimensions PCI half card: 174.63mm(L) x 106.S6mm(H)
x l4.4Smm(D)
6-7
C.30
6-9
C.32
EC Declaration of Conformity
description
The TLOSx JFET-nput operational amplifier family is designad o offer a wider selection than any prevously
developed operational amplifier family. Each of these JFET-input operational amplfiers incorporates
well-matched, high-voltage JFET and bipolar ransistors n a monolithic integrated circui. The devices feature
high slew rates, low npu bias and offset currents, and low offset voltage temperatura coeffcient. Offset
adjustment and external compensation options are avaiiable within the TLOSx family.
The C-suffix devices are characterized for operaiion from 0C to 70C. The l-suffix devices are characterized
for operation from -40C to 85C. The M-suffix devices are characterized for operation over the full miltary
temperature range of-55C o 125C.
symbols
TL081 TL082 (EACH AMPLIFIER)
TL084 (EACH AMPLIFIER)
IN +
OUT OUT
IN-
Please be aware that an mportant notice concerning availability, standard warranty, and use In critical applicatons of
Texas Instruments semiconductor producs and discaimers thereto appears at ihe end of this data sheet.
PRQQUCTION DATA Information Is curnnt ai of ptibllcatlun dale. Copyright 1996, Texas Instruments Incorporated
Products confom to 9 pacifica to ni per th la mis ofTeai lnstrumnts On poducts compilan! to MIL-PRF-3S53S, all parametf i are teited
sbndard warranty. Ptoductlan p roce i sin g does not nscessarlly [n elude
tasting of atl pacaoietan. TEXAS unleii othsrvls notad. On all othr poducts, ptoduellon
proctjslng does not necessarlly Includa esng o[ atl pramele n.
INSTRUMENTS
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
C.35
TLOBI.TLOSIA.TLOaiB TL082,TL082A,TL082B
D, JG, P, OR PW PACKAGE D, JG, P, OR PW PACKAGE
(TOP VIEW) (TOP VIEW)
OFFSET N1 [ 10UT [ CC +
IN- [ ]20UT
IN+ [ ]OUT ]2IN-
VCG-[ ] OFFSET N2 J2IN--
t- +
o
UJ o o
^
00
-z. > -z.
~Z-
U_
o O O \II 1 I II I
-z. O 'Z.'Z. -Z. 2 1 20 19 r
/ I 11 \ 1 II I NC -iJ 4 3 NC
-1
NC ] 43
2 1 20 19r
NC 1IN- ] 5 17[ 2OUT
NC ] s ie[ NC
IN- ] 5 17[ VCC +
1IN + ] 7 15[ 2IN-
NC ] 6 16[ NC
NC 1 8 14f NC
IN + ] 7 15[ OUT 9 10 11 12 13
NC ~j s 14f NC nIIIIfim
10 11 12 13 I 0 + o
11IIi lifi z: o ^ 'Z. ~Z-
o I O O o C
-z. O ~z. - ~z.
o (U
U) TL084M ... FK PACKAGE
u.
U- (TOP VIEW)
o
TL084,TL084A,TL084B I !
O, J, N, PW, OR W PACKAGE
|
O o^ o 5I
(TOP VIEW)
11iii iii
10UT[ 1
u 14 ]40UT 1IN + J 4
-. 3 2 1 20 19 r
4IN +
1 1 [\ r 2 13 ]4IN-
NC ] 5 17[ NC
i IM + r 3 12 ] 4IN + v cc+ ] 6 vcc-
VCG+ [ NC ] 7 NC
4 11 ]v cc - <
2IN+ [ 5 2IN + ] 8 14f 3IN +
10 ]3IN + 9 10 11 12 13
2!N-[ 6 9 ]3!N- i1f( (11iri
20UT[ 7 8 J30UT 1 l- 0 ^ 1
g
rvl O ^oi
NC - No nternal connection
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
C.36
Q. S OJ
>
= o p co 03
se- o o
H
2
< U g"
CQ
u. cu *" O
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TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
C.37
vcc+
IN +
IN-
OUT
VCG-
OFFSETNl OFFSET N2
TL081 Only
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
C.38
1IN +
(1)
10UT
1IN-
2IN +
2OUT
2lN-
-I 61 .(4)
VGC-
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4x4 MNIMUM
Tjmax = 150C
TOLERANCES ARE10%.
ir TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 " DALLAS, TEXAS 75265
C.39
1IN +
10UT
1IN-
2IN +
2OUT
2IN-
31N +
3OUT
3IN-
1= 62
4IN +
40UT
4IN-
105- CHIPTHICKNESS:15TYPICAL
TOLERANCESARE10%.
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
C.40
absoluta mximum ratings over operating free-air temperature range (uniess otherwise noted)t
TL08_C
TL08_AC TL08J TL08_M UNIT
TI_08_BC
D, N, P, or
Lead temperature 1,6 mm (1/1 6 inch) from case for 10 seconds
PW package
260 260 c
t Stresses beyond those listed under"absolute mximum ratings" may cause permanent damage to the device. These are stress ratings on!y, and
functional operation of the device at these or any oiher condiions beyond those indicated under "recommended operating condiions" is no
rnplied. Exposure o absolute-maxirnum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage vales, except differential voltages, are wih respect to the rnidpoint between VCG + and VQC
2. Differential voltages are at IN+ wih respect to IN-.
3. The magnitude of the input voltage rnust never exceed the magniude of the supply voltage or 15 V, whichever s less.
4. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the
dissipation rating s not exceeded.
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
C.41
Tmplate Relase Date: 7-11-94
TL081, TL081A, TL081B, TL082, TL082A, TL082B
TL082Y, TL084, TL084A, TL084B, TL084Y
JFET-INPUTOPERATIONALAMPLIFIERS
SLOSOB1C - FEBRUARY 1977 - REVISED 5EPTEMBER 1996
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o: o: o; >> <
cu
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4+ DI
,g o 2Q. o.
cu
01 44- a. C TJ 0)
Unity-gain bandwi
Common-mode in
coefficient ofinpul
Crosstalk attenual
Input bias current:
differential volage
Inpu offset curren
i O -S E
(AVCC/AV!0)
Input resistance
Common-mode
Mximum peak
Supply voitage
Supply current
" [T-
=0 UJ ,-
(per amplifier)
volage range
rejection ratio
rejection ratio
offset voitage
Temperature
Large-signal
amplification
_o
ARAMETER
o
ncti
ofa
ra
i !
ro
srislics
.c
-
o
"ra 0.
T
o CM
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a CQ
co" c- o CO _o
+-
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303- DALLAS, TEXAS 75265
C.42
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
C.43
-12
VICR Common-made input voiage range 11 to V
15
VQM Mximum peak output voitage svving RL=10kfi, 12 13.5 V
AVD Large-signai differential voitage amplifcation vo = iov, R L > 2kn 25 200 V/mV
B-] Unity-gain bandwidth 3 MHz
r Input resistance 1012 n
VIC = VjORmin, VO = 0, 70 86
CMRR Common-mode rejecton ratio dB
RS = so n 70 86
Vcc = 1 5 V o 9 V , 70 86
^SVR Supply voitage rejection ratio (AVfjc+/A,Vjo) dB
vo = o, RS = son 70 86
IGC Supply current (per amplifier} Vo = 0, No load 1.4 2.8 mA
VO1/VO2 Crosstalk attenuation AVD = 100 120 dB
t All characterisics are measured under open-loop conditions with zero common-mode voitage unless otherwise specified.
$ Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive as shown in
Figure 17. Pulse techniques must be used hat mainain the junction temperature as cise o he ambient temperature as possible.
TEXAS
10
INSTRUMENTS
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
C.44
10 kO
* 1 OUT i kn
OUT
R[_ = 2
= 100 pF
T
Figure 2
TL081
IN--
OUT
IN + N2
N1
IN- lookn
-AA/V-
OUT
11.5 kn
VGC-
Figure 3 Figure 4
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
C.45
TYP1CAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Frequency 5,6,7
vs Free-air temperature 8
VOM Mximum peak output voltage
vs Load resstanos 9
vs Supply voltage 10
vs Free-air temperature 11
Large-signal differenial voltage amplficaton
AVD vs Frequency 12
Differential voltage amplificaron vs Frequency wih feed-forward compensation 13
12.5 \ 7A = 2-
c ee Fiejure
2 I
(U
12.5
\ f\-r.L = -
"P4 5V
TA = 23C
S e e F(jur 3 2 -
o
10
'cc = 10 V
ra
3
1 1
0.
^("T"-
j^j .
0V
\1 O
7-5 7.5
5 I/GC+ V
ra
cu
Q.
5
\
"x ^(T- :~ ^:-5 V
ra -1 2
2.5 I 2.5
N O
X
v- n ^i-
oo 1k 10 k 100k 1M 10 M 100 1k 10 k 1ook 1M 10
f- Frequency - Hz f- Frequency - Hz
Figure 5 Figure 6
TEXAS
12
INSTRUMENTS
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
C.46
TYP1CAL CHARACTERISTICSt
>
RL =2 k1 1
"A
i+
See F 3U rt 2
i <1 *\ D)
-
,,
ro --^
|o RL = 2k.1
"
\
U
3 'U
-1
V
Q.
T;\~" 55C
"S
1
w
O
.+
,\ \ o
.-i !l
B-
0.
- -19
E
TA 1 . D
<"
-
'x
,+
ra
5
O
V 1
o
1+
E O
t-"
Figure 7 Figure 8
I , = 25C
12.5
10
+7 e
X / .3
>0
Figure 9 Figure 10
t Data al high and low temperaturas are applicable only within the raied operating free-air temperature ranges of the various devices.
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 13
C.47
TYPICAL CHARACTERISTICSf
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
1000
700
400
. 200
100
; 70
| 40
20
Am
10
O; 7
<>:
= 15V
Figure 11
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREQUENCY
106
VCC; = 5
RL = iokn
">
105
\ 'A = 25C
o >
te l
104 \e SI
103
^ Differentl al Volta ge
Amplf 1 catin
(lefts cale)
. \t
ra E
102
\1 90 C
p
101 (f ght scs \V 135
10 100 1k 10k 1 0 0 k 1M
\^ 10M
180
f-Frequency-Hz
Figure 12
t Data at high and low temperaturas are applicable only within the rated operating free-air temperature ranges of the various devices.
T TEXAS
14
INSTRUMENTS
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
C.48
TYPICALC JSTICSt
.3-
*tf> "^
i
5 125 ^
O
| 100
CO
\= o
Q.
TL082.T L083
~~-^ -^t
-j.
75 75
-~~-
\V
O
- -^
H
N)
T -081
I 50 .
J.
O
Q. -.
O
25
\F n
x
Figure 13 Figure 14
*"
1.2 ^ 1.2
"^
O
1.0 -^ >. 1.0
Q.
Q.
0-8
I
0.6 ** 0.6
O
o U
0.4 0.4
0.2 0.2
n
-75 -50 -25 O 25 50 75 100 125 4 6 8 10 12 14 16
TA Free-AirTemperature C |V C C|-SupplyVoItage-V
Figure 15 Figure 16
t Data ai hlgh and low emperatures are applicable only within the rated operating free-air temperature ranges of the varous devices.
T TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 15
C.49
TYPICAL CHARACTERISTICSt
INPUTBIASCURRENT
vs VOLTAGE-FOLLOWER
FREE-AIR TEMPERATURE LARGE-SIGNAL PULSE RESPONSE
1UU
~ VGC = 15 v
/
/
10
/ Output
=F
/
/
/
1
/
/
/ -2
0.1
/ Input
~^ ^ -4
0.01
50 -25 0 25 50 75 100 12 O 0.5 1 1.5 2 2.5 3.5
- Free-Ar Temperatura -C t-Tme-[is
Figure 17 Figure 18
RL = 1 o
>
E
87
= 100pF 86
TA = 25C
See Figure 1
O
I 85
o
tu 84
o;
83
O 0.2 0.4 0.6 0.8 1.0 1.2 - 75 - 50 - 25 O 25 50 75 100 125
t-Elapsed Tme-p.s TA Free-Air Temperature - C
Figure 19 Figure 20
t Data at high and low temperaturas are appcable only within the rated operating free-air temperaure ranges of the various devices.
TEXAS
16
INSTRUMENTS
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
C.50
TYPICAL CHARACTERISTICSt
\
A VD ~ "1C A\ /D
0.4
1 RS = 20 1 (Rr<1S ) = G V
T 40 T \ 25 1 i.= 2 C
0) c
DI o
ra
o ' 0.1 -f '
izi
30
Q
.u 0.04
/-
\
'o 1
c
o
E 1
1 20
X
/
t
"c
ro
>r^~
i- 1 -^-r~~^
UJ X
I H
c
J n.no-1
10 40 100 400 1 k 4 k 10 k 40 k 100 k 10 400 1k 4k 10 k 40 k 100k
f-Frequency-Hz f- Frequency ~ Hz
Figure 21 Figure 22
t Data at high and low tempera tures are applicable only within the rated operating free-air temperature ranges of the various devices.
APPLICATION INFORMATION
Ouput
Input Output
Cp = 3.3
Rl = R 2 = 2(R3)-1.5MO
C1 = C 2 = 3- = 1 1 0 P F
f 1
2n: R1 Cl
Figure 23 Figure 24
TEXAS
INSTRUMENTS 17
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
C.51
APPLICATION INFORMATION
Outpu A
Input
Ouput B
Output C
6 sin tt 1N4148
-15V
* 6 eos )t
88.4
TEXAS
18
INSTRUMENTS
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
C.52
APPLICATION INFORMATION
Output
Output A
Output A Output B
2 kHz/div 2 kHz/div
Second-Order Bandpass Filter Cascaded Bandpass Rler
f0 = 100kHz,Q = 30, GAIN = 4 f0 = 100 kHz, Q = 69, GAIN = 16
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 DALLAS. TEXAS 75265 19
C.53
IMPORTANTNOTICE
Texas Instruments (TI) reserves the right to make changes o is products or to discontinu any semiconductor
product or sen/ice without notice, and advises its customers to obtain he lates versin of relevant informaion
io verify, before placing orders, that he information beng relied on s current.
TI warrants performance of ts semiconductor products and related software to the specifications applicable at
the time of sale in accordance wih TI's standard warranty. Testing and other quality control techniques are
uilized to the exent TI deems necessary to support his warranty. Specific estng of all parameters of each
device is not necessarily performed, excep those mandated by government requirements.
Certain appcations using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage ("Critical Applications"),
Inclusin of TI products in such applications is understood to be fully ai the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a loca] SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assisance, customer product design, software performance, or
infringement of patents or servces described herein. or does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work righ, or oher inellecual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor producs
or services might be or are used.
X I COR'
FEATURES DESCRIPTION
Sod-state potentiometer The X9Cxxx are Xicor digitally controlled (XDCP)
3-wire serial interface potentiometers.The device consists of a resistor array,
100 wiper tap points wiper switches, a control section, and nonvolatile
Wiper position stored in nonvolatile memory memory. The wiper position is controlled by a three-
and recalled on power-up wire interface.
99 resistiva elements
Temperatura compensated The potenomeier is irnplemented by a resistor array
'End to end resistance, 20% composed of 99 resisive elements and a wiper switch-
Terminal voltageSj 5V ing network. Between each element and at either end
Low power CMOS are tap points accessible o the wiper terminal. The
-Vcq = 5V posiion of ihe wiper elemen is controlled by the CS,
'Active current, 3mA max. U/, and INC inpus. The position of ihe wiper can be
Standby current, 750uA max. stored n nonvoatile memory and hen be recalled
High reliability upon a subsequent power-up operation.
Endurance, 100,000 data changas per bit The device can be used as a three-terminal potentiom-
Register data retention, 100 years eter or as a two-terminal variable resistor in a wide
X9C102 = 1 kQ variey of applications ncluding:
X9C503 = - control
kQ - parameter adjustments
Packages
- signa! processing
8-lead SOIC and DIP
BLOCKDIAGRAM
RH/VH
Up/Down
(U/D)
Increroent
Vss (Ground)
General
Detailed
X9C102/103/104/503
PIN CONFIGURATION
DIP/SOIC
TC 1 8
2 7 I US
X9C102/103/104/503
3 6 i vL/RL
I VW/RW
ORDERING INFORMATION
X9C102/103/104/503
PIN DESCRIPTIONS
Pin Symbol Brie Description
1 Increment . The INC npui is negative-edge triggered.Toggling INCwill move the wiper and either
increment or decrement the counter in the drecton indcated by the logic level on the U/D input.
2 U/ Up/Down. The U/ inpu contros he direction of the wiper movemen and whether the
counter is incremented or decremened.
3 RH/VH RH/VH. The high (VH/RH) terminis of the X9C1 02/1 03/1 04/503 are equivalent to the fixed
terminis of a mechanical poteniometer. The minimum voiage s -5 V and the mximum is
fSV.The erminoiogy of VH/RH and VL/R. references the_relaive position of the terminal in
reiation to wiper movement direction seleced by the U/D input and not the voltage potential
on the terminal.
4 vss Vss
5 VW/RW V W /R W , VW/RW 's ne wiper terminal, and is equivalent to the movable terminal of a mechan-
ical potentiometer.The postion of the wiper withn he array is determined by the control inpus.
The wiper terminal series resstance is typically 40fi.
6 RL/vL RL/VL- The low (V,/R.) terminis of the X9C1 02/1 03/1 04/503 are equivalent o the fixed
terminis of a mechanical poentiomeer.The minimum voltage is -5V and the mximum is
+5V. The erminoiogy of VH/RH and V,/RL references the_relative posiion of he terminal in
relation o wiper movement direction seleced by the U/D input and not the volage potential
on he terminal.
7 3 CS. The device s selected when he 5 input is LOW. The curren counter valu is stored in
nonvolaile memory when 5" is returned HIGH while the INC input s also HIGH. After the store
operaion is complete the X9C1 02/1 03/1 04/503 device will be placed in he low power standby
rnode untl the device is selected once again.
8 Vcc Vcc
X9C102/103/104/503
Notes: (1) Absolute linearity is utilizad io determine actual wiper volage versus expected voltage = [Vvv(n)(actua]}~vW{n){expected)] = 1 MI Mximum.
(2) Relative linearity isa measureof the error in step size
(3) 1 MI = Mnimum Incremen = RTOT/"
(4} Typical vales are forTA = 25G and nominal supply voltage.
(5) This parameter s not 100% tesed.
X9C102/103/104/503
D.C. OPERATING CHARACTERISTICS (Over recommended operating condiions unless otherwise speciied.)
Limts
Symbol Parameter Min. Typ.<4> Max. Unit Test Conditions
IGC VCG active current 1 3 mA CS = VIL) U/D = VIL or VIH and
T= 0.4V to 2.4V @ max. tCYc
'SB Sandby supply curren 200 750 MA US = Vcc - 0.3V, U/D and T = Vss
or vcc - 0.3V
ILI US, T, U/D input leak- 10 MA VIN = VSS o VCC
age current
VIH CS, INC, U/D input HIGH 2 VCG + I V
volage
VIL US, T, U/D inpu LOW -1 0.8 V
voltage
C,N(2) US, , U/D input 10 pF VGC = 5V, V,N = VSSl TA = 25C, f 1 MHz
capacitance
Macro Model
, Vn/Ru
vR/nH
v s (^
~>\ oTest Pont
]>
<>_*
I Test Pain
RiLhu
n
|C L =
j10pF
=
RTOTAL
v
'
cw
v ft Current |
i
= L: - c
R\F
N I
X9C102/103/104/503
A.C. OPERATING CHARACTERISTICS {Over recommended operang condtions unless otherwise specified)
Limits
Symbol Parameter Min. Typ.(s> Max. Unit
tci CS to INC setup 100 ns
t|D INC HIGH to U/D change TOO ns
toi - U/DtoIseup 2.9 US
A.C. TIMING
IR
u/
Notes: (6) Typical vales are forT^ = 25C and nominal supply voltage,
(7) This parameter Is periodcally sampled and not 100% ested.
(8) MI in the A.C. timing diagram refers o the mnimum ncrernental change in the V w outpu due to a change n the wiper position.
X9C102/103/104/503
X9C102/103/104/503
INSTRUCTIONS AND PROGRAMMING The sate of U/D may be changed while CS rernains
LOW. This alows the host system to enable he device
The INC, U/D and CS nputs control hejnovement of
and hen move the wiper up and down until the proper
the wiper along the resistor array. With CS set LOW trie
trim is attained.
deviceis selected and enabled to respond to the U/D
and TC inputs. HIGH o LOW transiions on T will MODESELECTION
increment or decrement (depending on the stae of he
CS INC U/D Mode
U/D input) a seven-bit couner. The output of this
couner is decoded to select one of one-hundred wiper L ~\ H Wiper Up
positions along the resisive array. L "X_ L Wiper Down
The valu of he counter is stored in nonvolatile mem- _r~ H X Store Wiper Position
ory whenever CS transiions HIGH while he INC inpu H X X Standby Curren
isalsoHIGH.
j~ L X No Store, Return to Standby
The system may selec he X9Cxxx, move the wiper,
and deselec the device withou having o sore the lat- SYMBOL TABLE
est wiper posiion in nonvolatile memory. After the
wiper movement is performed as described above and
WAVEFORM INPUTS OUTPUTS
once the new position is reached, the sysem mus
keep WC LOW while taking CS HIGH.The new wiper Must be Will be
position will be maintained until changed by the sysem steady steady
or unil a power-down/up cycle recalled the previously
May change Will change
sored data. from Lov to rom Lov to
High High
This procedure alows the system to always power-up May change Will change
to a preset valu stored in nonvolatile memory; then from High to frorn High to
Low Low
durng sysem operation minor adjustments could be
made.The adjustments mght be based on user prefer- Don't Care: Changing:
Changes Sate Not
ence: system parameer changes due to temperaure Allowed Known
drift, ec... N/A Center Line
s High
Impedance
X9C102/103/104/503
PERFORMANCE CHARACTERISTICS
Contact the factory for more informaiion.
APPLICATIONS INFORMATION
Electronic digitally controlled (XCDP) potentiomeers provide three powerful applcation advantages; (1) the vari-
abiiity and reabily of a solid-state potentiometer, (2) the flexibiliy of compuer-based digital controls, and (3) he
retenivty of nonvolatile memory used for the sorage of mltiple potentiomeer settings or daa.
~l
VW/RW
Basic Circuits
Buffered Reference Voltage CascadingTechnques Nonnvertlng Amplifer
+5V
-fV +V
LM308A
+5V
OUT
(b)
X9C102/103/104/503
PACKAGING INFORMATION
0.430(10.92)
0.360(9.14)
0.260 (6.60)
0.240(6.10)
Pin 1 Index-
Pinl LjJ LJ LJ
L 0.300 J 0.060(1.52)
r t7_fi?\ 1
(7.62) 0.020(0.51)
Half ShoulderWdthOn
All End Pins Optonal
NOTE:
1, ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
X9C102/103/104/503
PACKAGING INFORMATION
0.15
0.150(3.80} 0.228 (5.80)
0.15
0.158(4.00) 0.244(6.20)
Pin 1 ndex ~0
/ '
"'ti ttiti
0.014(0.35)
0.019(0.49)
0.188(4.78)
(4X) 7
I F
0.004(0,19)
0.050(1.27) 0.010 (0.25)
I- 0.020 (0.50)
X45
lili 1T0.050"
\)Ja
Typical
0.0075(0.19}
0.010(0.25) 0250'
0.037 (0.937)
X9C102/103/104/503
REV 1.1,6 6/23/03 WWW.XCOT. COm Charactesllcs subject to changa without nolca. 12 O 12
C.66
Ordering number: EN 1649C I
STK4141V
Specifications
STK4141V
Noles. For power supply at the time of lest, use a consant-voltage power suppiy 700^*2
unless otherwse specified. o VCC
For measurement of the avalable time for load short-drcuit and output
noise voltage, use the specified transformer power supply shown below.
The output noise voltage is represented by the peak valu on rms scale
(VTVM) of average valu indcating type. For AC power supply, use an AC Q-VCC
Unh (resist tica; fl capacitan ce: F)
stabized power supply (50Hz) to eliminate the effect of fcker noise n AC
primary une. Specified Transformer Power Supply
(Equivalent to RP-25)
Equivalen! Circuit
?2 O U
TR17
No. 16492/5
(* t*
Ld [
0 < <
C a o QC O O
o o 1
II ?r II II 11 13 oII oII
^
r- ? H-H-
o. w to o. -- hf H-
to to
\t powcr, P0 -W a co --"* .P -0
\
O S CO S5 o
1)
j\ r^
o'
\ D
V
O
~l
\ o
c
;\
i
\\c gain, VG - dB 3 // Ti CO
D
^
y T
O O)
H
\
o1
c <"
o
<
a \
^ "
-*1
CO
K .*
N en
ro
s /
O
a>
co
C.69
STK4141V
Pd - Po THD
&ror=
THD - PO
Q
H
0.1 I.O 2 3 5 lo 20 24 73 32 36
Output powcr, PO - W Suppiy voltagc, Vcc - V
ICCO.VN - Te
O 20 40 50 80 100 120 24 Z6 32 36
IC substrate tcmpcrature, Te - CC Suppiy voltagc, Vcc- 1
No. 16494/5
C.70
STK4141V
Po - f
v c c=27v/8n
V c c =24V/4n
THD = O.OS%/8n
THD = 0.2%/4fl
Frcquency, f- Hz
No producs described or'contained herein are ntended for use in surgical implants, life-suppor systems, aerospace equpmen, nuclear
power control systems, vehcles, dsaster/crime-prevention equipment and the like, he failure of whch may directly or indirecly cause injury,
death or property loss.
Anyone purchasing any producs described or contained herein for an above-mentioned use shall:
Accept full responsibilty and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliaes, subsidiarias and distribuors and all their
officers and employees, jointly and severally, against any and al! claims and litlgaton and all damages, cos and expenses associated
with such use:
o Not impose any responsibiliy for any fault or negligence which may be cied n any such claim or litigaton on SANYO ELECTRIC CO.,
LTD., its affiliates, subsidiarles and distributors or any of their officers and employees, joinly or severally.
Information {ncluding circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO
believes Information herein is accurate and reliable, bu no guaranees are made or implied regarding its use or any infringements of
intellectual property rights or other rights of hrd parties.
This catalog provides information as of June, 1997. Specifications and Information herein are subj'ec to change without notice.
No. 16495/5
C.71
BURR-BROWN'
ADS7800
I 1
12-Bit3j^s Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES DESCRIPTION
333k SAMPLES PER SECOND The ADS7800 is a complete 12-bt samplng analog-
STANDARD+10V AND+5VINPUT to-digital converter using state-of-the-art CMOS struc-
RANGES tures. Jt contains a complete i2-bt successive ap-
proximation A7D converter with interna! sampie/hold,
DC PERFORMANCE OVERTEMP: rcferencc, clock, digital interface for microprocessor
No Missing Codes control, and three-state output drivers.
1/2LSB Integral Unearity Error
3/4LSB Differential Linearity Error The ADS7SOO is specifed at a 333kHz sampling rate.
Conversin time is factory set for 2.70|is max over
AC PERFORMANCE OVER TEMP: temperatura, and the hgh speed sampling nput sage
72dB Signal-to-Noise Rato insures a total acquisition and conversin time of 3p.s
80dB Spurious-free Dynamic Range max over temperature. Precisin, aser-trmmed scal-
-80dB Total Harmonio Dstortion ing resistors provde industry-standard input ranges of
INTERNALSAMPLE/HOLD,REFERENCE, 5Vor10V.
CLOCK, AND 3-STATE OUTPUTS AC and DC performance are completeiy specifed.
POWER DISSIPATION: 215mW max Two grades based on lnearity and dynamic perform-
ance are available to provide the optimum price/
PACKAGE: 24-Pn Single-wide DIP
performance t in a wide range of applicaions.
24-Lead SOIC
The 24-pin ADS7800 is available in plstic and side-
braze hermetic 0.3" wide DIPs, and in an SOIC
package, It operates from a +5V supply and either a
-12V or-15V supply. The ADS7800 is availabe in
grades specified over 0C to +70C and -40C to
+85C temperature ranges.
BUSY
Output
Latches
And Three
Three Siate
State Parallel
Dfivers Output
Data
Bus
International Alrport Industria] Part Mailing AddessiPO Box 114DO,Tucson, A2B5734 Street Address: 6730 S.Tucson Blvd., Tucson, AZ 35706 Tel: (520) 746-1H1 Twx: 910-952-1111
Inlsmeh httpJwV'w.burr-brown.comJ FAXUne; (600) 54S-6133 (US/Canad On\y] Cabla: BBRCDRP Telex: 065-6491 FAX: (520) 889-1510 Immadiala Product Info: (BOO) 548-6132
SPECIFICATIONS
ELECTRICAL
Al TA = TW|N to TMAX. Sampling Frequency, fs. = 333kHz. -Vs = -15V, Vs = +5V, unless olnerwise specified.
ADS7800JP/JU/AH ADS7800KP/KU/BH
PA RAM TER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
RESOLUTION 12 Bits
ANALOG INPUT
Voltage Ranges 10V/SV * V
Impedance 10V Range 4.4 6.3 8.1 * * kd
5V Range 2.9 4.2 5.4 ' * * kn
THROUGHPUT SPE6D
Conversin Time Conversin Alone 2.5 2.7 * P*
Complete Cycle Acquisition + Conversin 2.6 3.0 ps
Throughpul Rale 333 380 * * kHz
DC ACCURACY
Full Scale Error!') +0.50 0.35 %
Full Scale Error Drit 6 ppm/C
Integral Linearily Error 1 1/2 LSBP)
Dfferenlial Linearily Error =1 3/4 LSB
No Misslng Codes Guaranleed Guaranteed
Bipolar Zerol' 4 2 LSB
Bipolar 2ero Dril 1 ppm/c
Power Supply Sensillvly
-6.5V<-V S <-13.5V 1/2 * LSB
-12.6V <-V s <-11.4V 1/2 LSB
+4.75V < Vs < H-5.25V 1 1/2 LSB
Transtlon NoiseP 0.1 LSB
AC ACCURACY
Spurious-Free Dynarnlc Range f,N = 47kHz 74 77 77 80 dBW
Total Harmonlc Dslorlion f,N = 47kHz -77 -74 -80 -77 dB
Two-lone Inlerrnodulalion Distorlion fw, = 24.4kHz (-5dB) -77 -74 -80 -77 dB
f W2 = 28.5kHz (-6dB)
Signal-to-(Nose + Dislorton) Rallo f1N = 47kHz 67 70 69 72 dB
SignaMo-Noise Ratio (SNR) f(M = 47kHz 68 71 70 73 dB
SAMPUHG DYNAMICS
Aperture Delay 13 ns
Apertura Jtter 150 ' ps, rms
Translent Responsel5! 130 ' ns
OvervoHage Recovery'6' 150 " ns
IHT6RNAL REFERENCE VOLTAGE
Voltage 1.9 2.0 2.1 V
Source Currenl Available 10 uA
for Exernal Loads
DIGITAL INPUTS
Logic Levis
V,u -0.3 +0.8 V
V,H +2.4 +5.3 V
'n. -5 HA
+5 " MA
"M
DIGITAL OUTPUTS
Data Formal Parallel. 12-bit or 8-b]t/4-b[|
Daa Codlng Blnary Offset Binary
VOL ISINK = 1-6rnA 0.0 +0.4 " " V
VOH ISOURCE = 50liA +2.4 +5.0 " V
ILEAKAM (HIgh-Z State) 0.1 5 " jiA
POWER SUPPLIES
Rated Voltage
-vs -11.4 -15 -16.5 * " " V
Vs (VSA and Vso) +4.75 +5.0 +5.25 V
Currenl
-s 3.5 6 mA
la 18 25 " mA
Power Consumplion 135 215 ' ' mW
BURR-BROWN*
1 ADS7800
C.73
SPECIFICATIONS (CONT)
ELECTRICAL
At TX = TU(H lo TWAX, Sampling Frequency, fs, = 333kHz, -Vs = -15V, Vs = +5V, uniess olherwse specified.
ADS7800JP/JU/AH ADS7800KP/KU/BH
PACKAGE/ORDERING INFORMATION
INTEGRAL SlGNAL-TO- SPECIFICATION
LINARITY (NOISE+DISTORTION) TEMPERATURE PACKAGE DRAWING
PRODUCT ERROR (LSB) RATIO (dB mln) RANGEfC) PACKAGE N M SER!')
ADS7BOOJP 1 67 0 to +70 24-Pin Plstic DIP 243
ADS7SOOKP 1/2 69 0 lo +70 24-Pn PlaslicDIP 243
ADS7800JU 1 67 0 to +70 24-Pn Plstic SOIC 239
ADS7800KU 1/2 69 0 to +70 24-Pin Plstic SOIC 239
ADS7800AH 1 67 -40 lo +85 24-Pn Ceramic DIP 245
ADS7800BH 1/2 69 -40 to +85 24-Pin Ceramic DIP 245
NOTE: (1) For detaled drawing and dimensin table, please see end of data sheet, or Appendix C of Burr-Brown IC Dala Book.
The Information provlded herein is belleved to be relable; however, BURR-BROWN assumes noresponsibility for inaccuraces oromlssions. BURR-BROWN assumes
noresponsibiltyfortheuseofthsinformalion, and alluse ofsuchinformationshall be entirely al he user"s ownrisk. Pnces and specifications aresubject lochange
withoul notice. No palent righls orlicenses lo any of the crculls described herein are mplled orgranted lo any thfrd party. BURR-BROWN does nol authorize orwarrant
any BURR-BROWN product for use n Ufe support devices and/or systems.
BURR-BROWN
ADS7800 I
C.74
BURR-BRQWNO
ADS7800
C.75
_ fw = SQkHz
f*^25DC
3 -80 5 -80
-100 -100
-120
50 100 150 165 50 100 150 165
Frequency (kHz} Frequency (kHz)
90
n>
ce 85
-55'C .y
70 | 80
Q
u
75
10 50 150 10 50 150
Input Frequency (kHz) Input Frequency (kHz)
OdB
-20dB
40
_60dB
10 150
Input Frequency (kHz) Input Frequency (kHz)
BURR-BRDV/N
ADS7800 I
C.76
BURR.BROWN
ISEEII ADS7800
C.77
THEORY OF OPERATION
The ADS7SOO combines the advantages of advanced CMOS
technology (logic density, stable capacitors, and good
analog switches) with Burr-Brown's proven skills in laser-
trimmed thin-flm resistors to provide a complete sampling
A/D converer. AGND BUSY
A basic charge-redistribution successive approximation
architecture converts analog input voltages into digital D11 (MSB) CS
and S3) are sct to position "R" to provide an accurate bipolar 04 DGND
offset from the refercnce source REF. At the same time,
switch Sc is atso n the closed position to auto-zero any 00
offset errors in the CMOS comparator. (LSB)
Dala Out
When a convert command is received, switch S is opened
to trap a charge on the MSB capacitor proportionai to the FIGURE 2. Basic 1OV Operation.
inpu levei at the time of the sampling command, switches
S-, and S3 are opened to trap an offset charge, and switch
Sc s opened o float the comparator input. The charge
trapped on the capacitor array can now be moved between OPERATION
the three capacitors in the array by connecting switches S[} BASIC OPERATION
S2 and S3 to positions "R" (to connect to REF) or "G" (to
connect to GND) successively, changing he voltage gener- Figure 2 shows the simple hookup circu required to oprate
ated at the comparator input node. he ADS7SOO in a 10V range in he Convert Mode. A
convert command arriving on pin 19, R/C, (a pulse taking
The first approximation connects the MSB capacitor via pin 19 LOW for a mnimum of 40ns) puts the ADS780Q in
switch S t to REF, whie switches S2 and S3 are connected the hoid mode, and a conversin is started. Pin 21, BUSY,
to GND. Depending on whether the comparaor output is will be heldLO W during the conversin, and rises only after
HIGH or LOW, the logic will then latch S t in position "R" the conversin is compleed and the data has been trans-
or "G", and moves on o make the next approximation by ferred to the output latches. Thus, the rising edge of the
connecting S2 o REF and S3 to GND. When the three signal on pin 21 can be used o read the data from the
successive approximation steps are made for ths simple conversin, Aiso, during conversin, the BUSY signal puts
converter, the voltage level at the comparator will be within the output data Unes in Hi-Z states and inhibits input lines.
1/2LSB of GND, and the data output word wili be based on This means that pulses on pin 19 are ignored, so that new
reading the positions of S|, S2 and S3. conversions canno be initiated during a conversin, eiher
as a result of spurious signis or to short-cycle the
ADS7800.
Jn the Read Mode, he input to pin i 9 is kept normally LOW,
Sc / Co mparator
and a HIGH pulse is used to read daa and_ initiate a
Input
T ^\ 0 -] conversin. In this mode, the rising edge of R/C on pin 19
2C cT 9 ->Out
4CL
Signal < will enabie he output data pins, and he daa from the
f
-^/-"/S' Switches
c
V
previous conversin becomes valid, The falling edge then
pus the ADS7800 in a hoid mode, and initates a new
R TG R TG
4 R
conversin.
V V
The ADS7SOO will begin acquirng a new sample as soon
3 Re
as the conversin is completed, even before the BUSY
output rises on pin 21, and will track the input signal until
he next conversin is started, whether in the Convert Mode
or the Read Mode.
FIGURE 1. 3-Bit Charge Redistribution A/D.
BURR - BROWN B
ADS7800 E
C.78
BURR-BROWNa
ADS7800
C.79
INTERNAL CLOCK
The ADS7SOO has an intemal clock that is factory trimmed
to achieve a ypcal conversin time of 2.47^15, and a
ADS7BOO
mximum conversin ime over he fill operating tempera-
tura range of 2.7ls. No external adjustments are required, 5V (
Input
and wih the guaranteed mximum acquisiion time of
300ns, throughput performance is assured with conver
pulses as cise as 3p.s.
FIGURE 5. 5V Range Without Trims.
READING DATA CALIBRATION PROCEDURE
After conversin s nitiaed, the outpu buffers remain in a First, trim offset, by applying at the input (pin 1 or 2) the
Hi-Z state unl the foilowing three logic conditions are mid-pont transition voltage (-2.44mV for theiOV range,,
simultaneously met: R/C is HIGH, BSY is HIGH andS -1.22mV for the5V range.) With the ADS7800 converting
is LOW. Upon satisfacon of these conditions, the data lines continually, adjustpotentiometerR, untii the MSB (DI I on
are enabled according to the stae of HBE. See Figure 9 and pin 5) is toggng aternately HfCH and LOW.
Tabie III for timing relationships and specifications.
Next adjust full scale, by appiying at the input a DC input
signal that is 3/2LSB below the nominal full scale voitage
CALIBRATION (+9.9927V for the 10V range, +4.9963V for he 5V
range.) With the ADS7SOO converting continually, adjust
OPTIONAL EXTERNAL GAIN AND OFFSET TRIM R2 until the LSB (DO on pin 17) is toggiing HIGH and LOW
Offset and fuli-sca!e errors may be trimmed to zero using with all of the other bits HIGH.
externa! offset and fu-scaie trim potentiometers conneced
to the ADS7800 as shown in Figures 10 and I I .
LAYOUT CONSIDERATIONS
If adjustment of offset and full scale is not required,
connections as shown in Figures 4 and 5 should be used. Because of the high resoluton and nearity of the ADS7800,
system design probiems such as ground path resistance and
contact resistance become very important,
R/C
BUSY
.. ,
Uode
BUS
FIGURE 6. Conver Mode: R/C Pulse LOW Outputs Enabled After Conversin.
BURR-HROWN"
ADS7800 I
C.80
R/C
V
Convert Y Acqure
and U.
H-Z State Hi-2 State
BUS
FIGURE 7. Rcad Modc: R/C Pulse HIGH Outputs Enabled Oniy When R/C is High.
UP Apertura Delay 13 ns
W Apertura JUter 150 ps, rrns
te Conversin Time 2.47 2.70 fis
IDBE BUSY from End of Conversin 100 ns
'oa BUSY Delay after Data Valid 25 75 200 ns
tA Acqulsltion Time 130 300 ns
IA+IC Throughput Time 2.6 3.0 US
SURR-BROWN*
1 ADS7800 10
C.81
Extemal lnputJ_R2
2
"HOT SOCKET" PRECAUTION Gain Adj'ust
icn 3
Two seprate +5V Vs pins, 23 and 24, are used to minimize
noise caused by dgita! ransiens. If one pin is powered and +5Vn 4
the other is not, the ADS7800 may "Latch Up" and draw Bipolar
Ri i 5
excessive current, In normal operation, his is no a problem Zero lOknj 30.1kO J
6
because both pins will be soldered together. However, Adjust 10kfl > s
I I 7
during evaluaron, incoming inspection, repair, etc., where -15V 0 \
the potential of a "Hot Socket" exists, care shouid be taken
to power the ADS7800 only after i has been sockeed,
FIGURE 11. 5V Range With External Trims.
BURR-BROWN*
11 ADS7800
C.82
Next, although the data outputs are forced into a Hi-Z state Finally, in multiplexed systems, the iming on when the
during conversin, fast bus transients can still be capaci- multiplexer is swched may affec the analog performance
tively coupled ino the ADS7800. If the data bus experiences of the system. n most appcations, the multiplexer can be
fast transients during conversin, these ransients can be switched as soon as R/C goes LOW (wth appropriate
attenuated by adding a logic buffer o the data outputs. The deiays), but his may affect the conversin f the switched
BUS Y output can be used o enabie the buffer. signal shows glitches or significant ringing at the ADS7800
Naturaiiy, transiens on the analog input sgnal ar_e to be input. Whenever possibie, it is safer to wait until the
avoided, especially at times vvihin 20ns of R/C going conversin is completed before switching the muiiplexer.
LOW, when they may be trapped as par of the charge on the The extremely fast acquisition time and conversin time of
capacitor array. This requires careful layout of he circuit in he ADS7800 make mis praccal in many appiications.
frontoftheADS7SOO.
BLJRR-BROWN
J ADS7800 12
C.83
Semiconductor
82C54
March1997 CMOS Programmable Interval Timer
Fe atures Description
SMHzto 12MHzClocklnput Frequency The Harris 82C54 is a high performance CMOS Programma-
ble Interval Timer manufacturad using an advanced 2 micron
Compatible with NMOS 8254
CMOS process.
- Enhanced Versin of NMOS 8253
The 82C54 has three independently programmable and
Three Independent 16-Bit Counters
functional 16-bt couners, each capable of handling clock
Six Programmable CounterModes inpu frequencies of up to 8MHz (82C54) or 10MHz
Status Read Back Command (82C54-10) or 12MHz (82C54-12).
Binary or BCD Counting The hgh speed and industry standard configuraion of the
FuIlyTTL Compatible 82C54 make it compatible with the Harris 80C86, 80C88,
and 80C286 CMOS micro process o rs along with rnany other
Single 5V Power Supply
industry standard processors. Six programmable Hmer
Low Power modes allow the 82C54 to be used as an event counter,
- ICCSB 10(lA elapsed tirne indicator, programmable one-sho, and many
- ICCOP .lOmA at 8MHz other applicaions. Staic CMOS circuit design insures low
power operaion.
Operatng Temperature Ranges
The Harris advanced CMOS process results in a significant
- C82C54 0C to +70C
reductio in power wih performance equal to or greaer than
- I82C54 -40C to +85C
existng equivalent producs.
- M82C54 -55C to +125C
Pinouts
82C54 (PDIP, CERDIP, SOIC) 82C54PLCC/CLCC)
TOP VIEW TOP VIEW
D3 [T 20] A1 D3 [T 24] C5
D2 [T 19J AO D2 T A1
CAUTION: These devices are sensiflve to elecrostatic discharge. Users should follow proper IC Handling Procedures. FileNumber 2970.1
Copyright Harris Corporation 1997 ,j
C.84
82C54
Orderng Information
PARTNUMBERS TEMPERATURE
SMHz 10MHz 12MHz RANGE PACKAGE PKG. NO.
CP82C54 CP82C54-10 CP82C54-12 0C to +70C 24 Lead PDIP E24.6
IP82C54 IP82C54-10 IP82C54-12 -40C o -f85C 24 Lead PDIP E24.6
CS82C54 CS82C54-10 CS82C54-12 0C io +700C 28 Lead PLCC N28.45
1S82C54 IS82C54-10 IS82C54-12 -40C to + 85C 28 Lead PLCC N28.45
CD82C54 CD82C54-10 CD82C54-12 0C to +70C 24 Lead CERDIP F24.6
ID82C54 1D82C54-10 [D82C54-12 -40C to -i-850C 24 Lead CERDIP F24.6
MD82C54/B MD82C54-10/B MD82C54-12/B -55Cto+125C 24 Lead CERDIP F24.6
MR82C54/B MR82C54-10/B MR82C54-12/B -55Cto+125C 28 Lead CLCC J28.A
SMD#84650UA - 8406502JA -55Cto+125C 24 Lead CERDIP F24.6
SMD# 8406501 3A - 84065023A -55Cto+125C 28 Lead CLCC J28.A
CM82C54 CM82C54-10 CM82C54-12 0C to + 70C 24 Lead SOIC M24.3
Functional Diagram
D7-D0
Pin Description
DIP PIN
SYMBOL NUMBER TYPE DEFINITION
D7-DO 1-8 I/O DATA: B-directional three-state data bus unes, connected to system data bus.
CLKO 9 I CLOCK 0: Clock nput of Counter 0.
CUTO 10 O OUT 0: Output of Counter 0.
GATEO 11 I GATE 0: Gate nput of Counter 0.
GND 12 GROUND: Power supply connection.
OUT1 13 O OUT 1: Output of Counter 1.
GATE1 14 I GATE 1 : Gate nput of Counter 1 .
CLK1 15 I CLOCK 1 : Clock nput of Counter 1 .
GATE2 16 I GATE 2: Gate nput of Counter 2.
OUT2 17 O OUT 2: Output of Counter 2.
4-2
C.85
82C54
Pin (Conmued)
DIP PIN
SYMBOL NUMBER TYPE DEFINITION
CLK2 18 ] CLOCK 2: Clock nput of Counter 2.
AO, A1 19-20 I ADDRESS: Select inputs for one of the Ihree counters or Control Word Register for read/write
operations. Normally connected o the system address bus.
Al AO SELECTS
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register
es 21 ! CHIP SELECT: A low on this nput enables the 82C54 to respond to RD and WR signis. RD and
WR are ignored otherwise.
RD 22 I READ: This input is low during CPU read operations.
WR 23 I WRITE: This input is low during CPU write operations.
VGC 24 Vcc: The +5V power supply pin. A 0.1 jiF capacitor between pins VCC and GND is recommended
for decoupling.
Functiona! Description
General
The 82C54 is a programmable interval Hmer/counter
designed for use with microcomputer systems. It is a general
purpose, multi-timing element that can be treaed as an
array of I/O pors in the system software.
The 82C54 solves one of he most common problems in any
microcomputer system, the generation of accurae time
delays under software control. Insead of setting up timing
loops in software, he programmer configures he 82C54 to
match his requirements and programs one of the couners
for the desired delay. After he desired delay, the 82C54 will
interrupt the CPU. Software overhead is mnimal and vari-
able length delays can easily be accommodated.
Some of he ohercomputer/timerfuncions common to micro-
computers which can be Implemented with he 82C54 are:
Data Bus Buffer The Read/Wrie Logic acceps inputs from the system bus and
generates control signis for the oher funcional blocks of he
This three-stae, bi-directional, 8-bit buffer is used to inter- 82C54. Al and AO select one of he three counters or the Con-
face the 82C54 to the system bus (see Figure 1). trol Word Regiser to be read from/written no. A "low" on he
RD inpu ells the 82C54 that the CPU is reading one of the
counters. A "low" on he WR input tells the 82C54 hat the CPU
is writing either a Control Word or an nitial count. Both RD and
WR are quafied by US; RD and WR are ignored unless the
82C54 has been selected by holding CS low.
4-3
C.86
82C54
D7-D0
GATE n.
CLKn OUTn
The actual counter is labeled CE (for Counting Element). It is The 82C54 is treated by the sysem software as an array of
a 16-bi presettable synchronous down counter. peripheral I/O ports; three are counters and the fourth is a
control register for MODE programming.
Basically, the seiect inputs AO, A1 connect to the AO, A1
address bus signis of he CPU. The CS can be derived
directly from the address bus using a linear selec mehod or
i can be connected to he ouput of a decoder.
4-4
C.87
82C54
After power-up, the stae of the 82C54 s undefined. The 0 0 Select Counter 0
Mode, coun valu, and ouput of all Counters are undefined. 0 1 Select Couner 1
How each Couner operates is deermined when i s pro- 1 0 Select Couner 2
grammed. Each Counter rnust be programmed before it can 1 1 Read-Back Command (See Read Operaons)
be used. Unused counters need not be programmed.
RW - Read/Write
Programmng the 82C54
RW1 RWO
Couners are programmed by writing a Control Word and
then an iniial coun. 0 0 Counter Latch Command (See Read Operations)
All Control Words are writen into the Conroi Word Register, 0 1 Read/Write least significant byte only.
which s seiected when A1, AO = 11. The Control Word spec- 1 0 Read/Write most significant byte only.
fies which Couner is being programmed. 1 1 Read/Write least significant byte first, then most
By contrast, initia counts are written into the Counters, not significan byte.
the Control Word Register. The A1, AO inputs are used o
M - Mode
selec he Counter to be written into. The format of the iniial
counUs determined by the Control Word used. M2 M1 MO
0 0 0 ModeO
ADDRESSBUS (16) "
0 0 1 Mode 1
A1 AO
X 1 0 Mode 2
CONTROL BUS /
I/OR i/oW X 1 1 Mode 3
DATA BUS (B) 1 0 0 Mode 4
1 0 1 Mode 5
t future producs.
only, or least significant byte and then most significant byte). Control Word - Counter 2 1 1
Since the Control Word Regiser and he three Counters have LSB of Count - Couner 2 1 0
seprate addresses (seiected by the Al, AO inpus), and each MSB of Count - Counter 2 1 0
Control Word specifies he Couner it applies to (SCO, SC1 bis),
no special insruction sequence s required. Any programming Possible Programming Sequence
sequence that follows the conventions above is acceptable,
A1 AO
Control Word Format
Control Word - Counter 0 1 1
4-5
C.
82C54
Possible Programming Sequence {Continuad) explained later. The second is a simple read operaion of the
Counter, which is seleced with he Al, AO inputs. The only
A1 AO
requiremen is tha the CLK inpu of the selected Counter
LSB of Count - Counter 1 0 1 must be inhibited by using either the GATE input or externa!
0 0 logic. Otherwise, the count may be in process of changing
LSB of Count - Counter 0
when i is read, giving an undefned result.
MSB of Count - Couner 0 0 0
Counter Latch Command
MSB of Count - Couner 1 0 1
MSB of Count - Counter 2 1 0 The oher method for reading the Counters involves a spe-
cial software command called the "Counter Latch Com-
Possible Programming Sequence mand". Like a Control Word, this command is wriien to the
Control Word Regser, which is selected when A1, AO = 11.
A1 AO Also, like a Control Word, the SCO, SC1 bits select one of
Control Word - Counter 2 1 1 the three Counters, bu wo other bits, D5 and D4, distin-
guish ths command from a Control Word.
Control Word - Counter 1 1 1
4-6
C.89
82C54
1. Read leas significan bye. The read-back command may also be used to lach saus
2. Write new leas signifcant byie. inforrnaon of selected counter(s) by setting STATUS bi D4
= 0. Status must be lached to be read; status of a counter is
3. Read most signifcant byte. accessed by a read from that counter.
4. Write new most signifcant byte.
The counter staus forma is shown in Figure 6. Bus D5
If a counter is programmed to read or write two-bye counts,
through DO contain the couner's programmed Mode exactly
the following precaution applies: A program MUST NOT
as written n he last Mode Control Word. OUTPUT bit D7
transfer control beween reading the firs and second byte to
contains the current state of he OUT pin. This allows the
another routne which also reads from ha same Counter.
user o monior the counter's output via sofware, possibly
Otherwise, an incorrect count will be read.
eliminaing some hardware from a sysem.
Read-Back Command
D7 D6 D5 D4 D3 D2 D1 DO
The read-back command allows the user to check he count OUTPUT NULL RW1 RWO M2 M1 MO BCD
valu, programmed Mode, and current sate of the OUT pin COUNT
and Nuil Count flag of the selected counter(s).
D7: 1 =Outpnis1
The command is written ino the Control Word Regiser and O =Out pinisO
has the format shown in Figure 5. The command applies to D6: 1 = Nuil count
the counters selected by setting their corresponding bits D3, O = Count available for reading
D2, D1 = 1. D5 - DO = Counter programmed mode (See Control Word Formis)
COMMANDS
D7 D6 D5 D4 D3 D2 D1 DO DESCRIPTION RESULT
1 1 0 0 0 0 1 0 Read-Back Count and Status of Counter 0 Coun and Status Latched for Counter 0
1 1 1 0 0 1 0 0 Read-Back Status of Counter 1 Status Latched for Counter 1
1 1 1 0 1 1 0 0 Read-Back Status of Counters 2, 1 Staus Latched for Counter 2,
But Not Counter 1
1 1 0 1 1 0 0 0 Read-Back Count of Counter 2 Count Latched for Couner 2
1 1 0 0 0 1 0 0 Read-Back Count and Status of Counter 1 Count Latched for Counter 1 ,
But Not Staus
1 1 1 0 0 0 1 0 Read-Back Status of Counter 1 Command Ignored, Status Already
Latched for Counter 1
FIGURE 7. READ-BACK COMMAND EXAMPLE
4-7
C.90
82C54
Boh couni and status of the seleced counter(s) may be If a new count Is writen to the Counter t will be loaded on
latched simultaneously by setting both COUNT and STATUS the nex CLK pulse and counting will continu from the new
bits D5, D4 = 0. This is functionally he same as ssuing wo count. If a wo-byte coun s writen, he following happens:
seprate read-back commands at once, and the above dis-
(1}Writing the first byte disables couning. Ou s set low
cussions apply here also. Specifically, If mltiple count
immediately (no clock pulse required).
and/or status read-back commands are issued to the same
counter(s) without any intervening reads, all but the frs are (2)Writing he second bye allows the new count to be
ignored. This is illustraed in Figure 7. loaded on he next CLK pulse.
If both count and status of a counter are latched, the first This allows the couning sequence to be synchronized by
read operation of that counter will return latched status, software. Again OUT does not go high unil N + 1 CLK
regardless of which was lached first. The next one or two pulses after the new coun of N is writen.
reads (depending on whetherhe counter is programmed for
one or two type couns) return latched count. Subsequent If an initial count is writen while GATE = O, it will stlll be
reads return unlatched count. loaded on he nex CLK pulse. When GATE goes high, OUT
will go high N CLK pulses later; no CLK pulse is needed to
es RD WR A1 AO load he counter as his has already been done.
CW = 10 I_SB=4
0 1 0 0 0 Write into Counter 0
0 1 0 0 1 Write into Couner 1
0 1 0 1 0 Write into Counter 2
0 1 0 1 1 Write Control Word
0 0 1 0 0 Read from Counter 0
0 0 1 0 1 Read from Counter 1
0 0 1 1 0 Read from Counter 2
0 0 1 1 1 No-Operation (Three-Sate)
1 X X X X No-Operation {Three-Sate) WR
0 1 1 X X No-Operation (Three-State)
CLK
FIGURE 8. READ/WRITE OPERATIONS SUMMARY
CLK PULSE: FF
TRIGGER:
A rising edge of a Counter's Gae inpu.
COUNTER LOADING:
The transfer of a coun from he CR o the CE (See "Func-
ional Description")
Mode 0: Interrupt on Terminal Count
Mode O is typicaliy used for event counting. After the Control FIGURE 9. MODE O
Word is written, OUT is initialiy low, and will remain low until NOTES: The following conventions apply to all mode timing dagrams.
he Counter reaches zero. OUT hen goes hgh and remains 1. Counters are programmed for binary (not BCD) counting and for
hign until a new count or a new Mode O Control Word is writ- reading/writng least significan byte (LSB) only.
ten to he Counter. 2. The counter is always selected (CS always low).
3. CW stands for "Control Word"; CW =10 means a control word of
GATE = 1 enables couning; GATE = O disables couning.
10, Hex is written to the counter.
GATE has no effect on OUT.
4. LSB stands for Least significant "byte" of count.
After the Control Word and initial count are written o a 5. Numbersbelowdiagrams are count vales. The lowernumberis
Counter, he nitial count will be loaded on the next CLK the least significant byte. The upper number s the most signifi-
pulse. This CLK pulse does not decrement he coun, so for cant bye. Since the counter s programmed to read/write LSB
an initial coun of N, OUT does no go high until N + 1 CLK only, the most significan byie cannot be read.
pulses after the iniial count is writen. 6. N stands for an undefined count.
7. Vertical unes show transitions between count vales.
C.95
82C54
OUT will be intally high. OUT will go low on the CLK pulse This Mode functions like a dvide-by-N counter. It is typically
following a trigger Eo begin the one-shot pulse, and will remain used to genrate a Real Time Clock Interrupt. OUT will ini-
low until he Counter reaches zero. OUT will then go high and ially be high. When the nial count has decremented to 1,
remain high until the CLK pulse after the next trigger. OUT goes low for one CLK pulse. OUT then goes high
again, the Couner reloads the iniial count and the process
Afer writing the Control Word and initial count, the Couner is is repeaed. Mode 2 is periodic; ihe same sequence is
armed. A rigger results In loading the Counter and setting
repeated ndefiniely. For an iniial count of N, the sequence
OUT low on the next CLK pulse, thus staring ihe one-shot repeas every N CLK cycles.
pulse N CLK cycles in duration. The one-shot is rer Ig ge rabie,
henee OUT will rernain low for N CLK pulses after any rigger. GATE = 1 enables counting; GATE = O disables counting. If
The one-shot pulse can be repeated wihout rewriting the GATE goes low during an output pulse, OUT is set high
same count Into ihe couner. GATE has no effect on OUT. immediaely. A trigger reloads the Counter with he initial
count on the next CLK pulse; OUT goes low N CLK pulses
If a new coun is written to the Counter during a one-shot
after the rigger. Thus the GATE inpu can be used to syn-
pulse, he current one-shot is no affected unless the
chronze the Counter.
Counter is retriggerable. In that case, the Counter is loaded
with the new count and the one-shot pulse contines unil After writing a Control Word and initial count, the Counter will
the new count expires. be loaded on he next CLK pulse. OUT goes low N CLK
pulses after the nitia coun is written. This allows he
CW = 12 LSB = 3 Counter to be synchronized by software also.
Wriiing a new count while counting does not affeci he curren
counting sequence. If a trigger is received after wriing a new
count bu before the end of he current period, the Counter will
JirLn/UVUm/lAJLr be loaded with the new count on the nex CLK pulse and coun-
ing will coninue from the end of the current counting cycle.
GATE -n -n LSB=3
OUT WR
CLK
OUT
WR
0 0
GATE WR
OUT CLK
N N N N GATE
CW = 12 LSB = OUT
CLK
GATE
i/i
OUT
4-9
C.96
82C54
Mode 3 is ypically used for Baud rate generation. Mode 3 is EVEN COUNTS: OUT is nitially high. The initial count is
similar to Mode 2 excep for he duty cycle of OUT. OUT wltl ioaded on one CLK pulse and then is decremented by two
nitially be high. When half the initial coun has expired, OUT on succeeding CLK pulses. When he coun expires, OUT
goes low for the remainder of he coun. Mode 3 is periodic; changes valu and he Counter is reloaded with the initlal
the sequence above is repeated indefinitely. An initial count count. The above process is repeated ndefiniely.
of N results n a square wave with a period of N CLK cycles.
ODD COUNTS: OUT is initially high. The Initlal count is loaded
GATE = 1 enables counting; GATE = O disables counting. If on one CLK pulse, decremented by one on the next CLK pulse,
GATE goes low while OUT is low, OUT s set high immedi- and hen decremented by wo on succeeding CLK pulses.
aely; no CLK pulse is required. A trigger reloads the When he coun expires, OUT goes low and he Couner is
Counter with the initial count on the nex CLK pulse. Thus reloaded with he Initlal count. The count is decremented by
the GATE inpu can be used o synchronize the Counter. three on he nex CLK pulse, and hen by wo on succeeding
CLK pulses. When he coun expires, OUT goes high again and
After writing a Control Word and initial count, the Counter wlll
he Couner is reloaded wih the Initlal coun. The above pro-
be loaded on the next CLK pulse. This allows the Counter o
cess is repeaed indefinieiy. So for odd counts, OUT will be
be synchronized by software also.
high for (N + 1)/2 couns and low for (N - 1)/2 counts.
Wriing a new count while counting does not affect the cur-
Mode 4: Software Triggered Mode
rent counng sequence. If a trigger is received after writing a
new count but before the end of the current half-cycle of the OUT will be initially high. When the initial count expires, OUT
square wave, the Counter will be loaded with the new coun will go iow for one CLK pulse then go high again. The count-
on the next CLK pulse and counting will continu from the ing sequence is "Triggered" by writing he initial count.
new count. Otherwise, the new coun will be loaded ai he
GATE = 1 enables counting; GATE = O disables counting.
end of the current half-cycle.
GATE has no effect on OUT.
CW = 16 LSB = 4 Afterwrrting a Conrol Word and nial count, the Counerwill be
"\_TLJ loaded on he next CLK pulse. This CLK pulse does no decre-
men the count, so for an initial count of N, OUT does not srobe
low until N + 1 CLK pulses after the initial coun s wrien.
OUT
5 4 2 s 2
CW = 16 LSB = <
WR~LJ~L_r~
CLK
GATE
OUT
01 0|
4 I 2I
FIGURE 12. MODE 3
4-10
C.97
82C54
WR
CLK
GATE
GATE
OUT
I M I u I u I I I t I FF I FF I FF I
I N I N I N I 3 I 2 I 1 I O I FF I FE I FD I
| N | N | N I N | N I S m; u isis
CW = 1A LSB =3
GATE
0 | 0 | O i O i O | O i F F OUT
OUT GATE
FF
OUT
J LJ
FIGURE13. MODE4 i
| N | N | N | N [ N | I S I ? |Sl
FFgFE
r I 5
Mode 5: Hardware Triggered Strobe (Retriggerable)
FIGURE 14. MODES
OUT will intially be high. Couning s triggered by a rising
edge o GATE. When the nitial coun has expired, OUT will Operation Common to Al! Modes
go low for one CLK pulse and then go high again.
Programming
After writing the Control Word and nitial count, the couner
When a Conrol Word is writen to a Counter, all Control
will not be loaded until the CLK pulse after a trigger. This
Logic, is irnmediately rese and OUT goes to a known nitial
CLK pulse does no decrement the count, so for an nitial
state; no CLK pulses are required for this.
coun of N, OUT does not strobe low until N + 1 CLK pulses
after trgger. Gate
A rgger results in the Counter being loaded with the iniiial The GATE input s always sampled on the rising edge of
coun on he nex CLK pulse. The couning sequence is rig- CLK. In Modes O, 2, 3 and 4 the GATE input is level sensi-
gerable. OUT will no strobe low for N + 1 CLK pulses after ive, and logic level is sampled on he rising edge of CLK. In
any ngger GATE has no effec on OUT. modes 1, 2, 3 and 5 the GATE input is rising-edge sensitive.
In these Modes, a rising edge of Gate (trigger) sets an edge-
If a new coun is writen during counting, the curren count-
sensitive flip-flop n the Counter. This flip-flop is then sam-
ing sequence will not be affected. If a trigger occurs afer the
pled on he next rising edge of CLK. The flip-flop is reset
new count is writen but before he current count expires, he
immediateiy after it s sampled. In his way, a trigger will be
Counter will be loaded with new count on the next CLK pulse
deected no matter when it occurs - a high logic level does
and counting will continu from here.
not nave to be maintaned unil the nex rising edge of CLK.
Note hat in Modes 2 and 3, he GATE inpu s both edge-
and level-sensitive.
4-11
C.98
82C54
Counter
New counts are [oaded and Couners are decremented on MODE MIN COUNT MAX COUNT
thefalling edgeof CLK.
"1R 0 1 0
The larges possible initial count is 0; this is equivalent to 2'
for binary counting and 104 for BCD counting. 1 1 0
4-12
C.99
82C54
Die Characteristics
Gate Count 2250 Gates
CAUTION: Stresses above those Usted in 'Absoluta Mximum Ratlngs' may cause permanent damage to the device. This /s a stress only rating and operatlon
ofthe device at these orany other conditlons above those indicatedin the operatlonal secthns of this specfication is not mped.
ICCSB Standby Power Supply Current 10 HA VGC = 5.5V, VIN = GND or VCc.
Outputs Open, Counters
Programmed
4-13
C.100
82C54
READ CYCLE
WRITE CYCLE
CLOCKANDGATE
(27) TWO OUT Delay from Mode Write - 260 - 240 - 240 ns 1
(30) TCL CLK Setup for Count Latch -40 40 -40 40 -40 40 ns 1
NOTE:
1. Not testad, but characterzed at initial design and at maj'or process/design changes.
4-14
C.101
82C54
Timing Waveforms
AO - A1
X
(9)
tAW tWA(H)
._
CS
tsw
DATA BUS VALID
(13}
K
tDW tWD (14)
(12)
AO - A1
s X
tSR {4}
tRR
RD
(5)
tRD tDF
DATA BUS
< VA LID
P-
FIGURE 18. READ
(8) (15}
tRV
R,WR /
COUNT
MODE (SEENOTE)
tCL(30)
CLK
GATE
4-15
C.102
82C54
Burn-ln Circuits
MD 82C54CERDIP
Vcc
MR82C54CLCC
VCC
GND OPEN
GND
VCC/2
NOTES:
8. R4 = 1.8kn5%
2. GND^OV 9. R5 = 1.2kn5%
3. V!H = 4.5V10% 10. C1 =O.Ol[iFMn
4. VIL = -0.2Vto0.4V 11. FO=100kHz10%
5. R1 = 47kn 5% 12. F1=FO/2, F2 = F1/2,...F12=F11/2
6. R2=1.0kl5%
7. R3 = 2.7KH 5%
4-16
C.103
82C54
Die Characteristcs
DIEDIMENSIONS: Thickness: Metal 1: 8kA 0.75k
129mils x 155mils x 19mils Metal2:12kA1.0kA
(3270jim x 3940fim x GLASSIVATION:
METALLIZATION: Type: Nitrox
Type: Si-AI-Cu Thickness: 10k3.0k
D5 D6 07 VCC WR RD
D1 CLKZ
OUT2
CLKO GATE2
4-17
C.104
>/ Semiconductor
82C55A
CMOS Programmable
June 1998 Peripheral Interface
Pinouts
B2C55A(DIP) 82C55A(CLCC) 82C55A(PLCC)
TOP VI EW TOP VIEW TOP VIEW
PA3 [T JDJPA4
PA2 PA5 Ib!5!4! - J ^ l l H - 1 MJS4 41 MU * nnnnnnnnnnn
PA1 PAG " 6 5 4 3 2 1 4 4 4 3 4 2 4 1 40
GND 71 E: NC
PAO NC RESET cs 3 9 3 RESET
RD WR A1
GND 8 38 ^ DO
D0
CSQT 3g RESET A1 9
2 D1 10
GND [T DO PC7 D2 11 35303
A1 33 01 pee
AO QT D2
EH D3 diz
PC5 D4 13 33 HD4
PC7 [TD D3 a: PC5 14 32 JDS
pee rn jg 04 3 D6 PC4 C 15
D5 PCI at 07 PCO C 16
PC4 D6 PC2 PCI ni7
2S NC 29^VCC
PCO [fl 27J D7
181920212223242526 2728
PC1 zgv cc UUULJULJUUUUU
PC2 [TE m m CD CQ CD m m u
PC3 7 0.0.0.0.0.0.0.0,0. D. CL O. Q. O.
PB6
PBO [n 23] PB5
PB1 [TE PB4
PB2 ZT] PB3
CAUTION: These devices are sensitive to eleclrostatic dscharge. Users should follow proper IC Handling Procedures. FileNumber 2969.2
Copyright Harris Corporation 1998 ,
C.105
82C55A
Pin Descrption
PIN
SYMBOL NUMBER TYPE DESCRPTION
VCG 26 VCG: The +5V power supply pin. A O.ljiF capacitor between pns 26 and 7 is
recommended fordecoupling.
GND 7 GROUND
DO-D7 27-34 I/O DATA BUS; The Daa Bus Unes are bidirectional three-state pins conneced o the
system data bus.
RESET 35 i RESET; A high on this input clears the control register and all ports (A, B, C) are set
to the inpu mode wih the "Bus Hold" circuitry turned on.
CS 6 I CHIP SELECT: Chip select is an active [ow input used to enable the 82C55A onto the
Data Bus for CPU Communications.
RD 5 I READ: Read is an active low input control signal used by the CPU o read status
Information or data via the data bus.
WR 36 I WRITE: Write is an active low input control signal used by the CPU to load control
words and data into the 82C55A.
AO-A1 8,9 ] ADDRESS: These input signis, n conj'unction with the R and WR inputs, control
the selection of one of the three ports or he control word register. AO and A1 are
normally conneced to he leas significant bits of he Address Bus AO, A1 .
PAO-PA7 1-4, 37-40 I/O PORT A: 8-bit nput and output port. Both bus hold high and bus hold low circuitry are
present on his port.
PBO-PB7 18-25 I/O PORT B: 8-bit nput and output port. Bus hold high circuitry is present on this port.
PCO-PC7 10-17 I/O PORT C: 8-bit input and output port. Bus hoid circuitry is presen on this port.
Functonal Diagram
POWER
SUPPLIES
K +5V
* GNO
>
GROUP A
CONTROL
H<=>
GROUP A
PORTA
8)
/
N
I/O
' PA7-PAO
4-
GROUP A
. I/O
Bl-DIRECTIONAL
PORTO
UPPER <= PC7-PC4
DATA BUS
DATA BUS 4 K
rJ
D7-DO, BUFFER >
S-8ITK GROUP B
INTERNAL PORTC /i , I/O
. PC3-PCO
DATA BUS LOWER N
(4) '
H
t
READ
WRITE GROUP B
CONTROL CONTROL GROUP B / ^ i/o
LOGIC PORTB \rr > P87-PBO
PO '
CS
C.106
82C55A
DISABLE FUNCTION
82C55A
OUTPUT MODE
MODE2
T
FIGURE 2A. PORT A BUS-HOLD CONFIGURATION j a r i/o DIRECTIONAL
PB7-PBO PA7-PAO
CONTROL
CONTROL WORD
D7|D6 05 n4 n3 n? r 1 nn
"1' '
PORT C (LOWER)
0 = OUTPUT
OUTPUT MODE
PORTB
82C55A
The modes for Por A and Por B can be separately defined, This function allows he programmer to enable or disable a
while Port C is divided nto two porions as required by the CPU inerrupt by a specific I/O device without affecting any
Port A and Port B definiions. All of the output regisers, other device in the interrupt strucure.
ncludng the status flip-flops, will be reset whenever the
mode is changed. Modes may be combined so that their INTE Flip-Flop Definition
functional definiion can be "tailored" to almost any I/O (BIT-SET)-INTE is SET - Interrupt Enable
strucure. For insance: Group B can be programmed n
Mode O to monitor simple switch closings or display compu- (BIT-RESET)-INTE is Reset- inerrup Disable
ational resuls, Group A could be programmed n Mode 1 to
NOTE: All Mask flip-flops are auomatically reset during mode se-
monitor a keyboard or tape reader on an nerrupi-driven lection and device Reset.
basis.
The mode definitions and possible mode combinations may Operating Modes
seem confusing at first, but afer a cursory review of he
complete device operaton a simple, logical I/O approach will Mode O (Basic Input/Output). This functional configuration
provides simple input and ouput operations for each of the
surface. The design of the 82C55A has taken into account
hree ports. No handshaking is required, data is simply writ-
things such as efficient PC board layou, control signa! defi-
nition vs. PC layout and complee funcional flexibility to sup- en to or read frorn a specific por.
port almos any peripheral device with no exernal logic. Mode O Basic Funcional Definiions:
Such design represents the mximum use of he available
pins. Two 8-bit ports and wo 4-bit ports
82C55A
[H . tAR 1. <
f
IRA 1\
es, AI.AO Njr*
, i
D7-DO _ : . :
< X J/r
iV
. tRD . t
XI x' 1
U tAW >
I
CS,A1,AO \f-
-k i
OUTPUT
L tWB |
Mode 0 Confgurations
D7 06 D5 D4 D3 D2 DI DO 07 06 D5 04 03 D2 01 DO
1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0
/
82C55A 82C55A
,4
c-
*- ,4
D7 06 D5 D4 D3 02 D1 DO 07 D6 05 D4 D3 02 D1 DO
1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1
B2C55A B2C55A
, 4
07 DO
uu *
4 *
t C"
A ^ Cl
C.110
82C55A
D7 06 D5 D4 03 02 01 DO 07 06 05 04 D3 D2 01 DO
1 O O O O O
- PA7 - PAO
D7-DQ-4- D7-DO-4-
>-PC3-PCO
>-PB7-PBO
07 D6 05 04 D3 D2 D1 DO 07 06 D5 04 D3 D2 D1 DO
1 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1
A
xa v-
'
PA7 - PAO A ,
1 /
x8 - PA7 - PAO
82C55A 82C55A
X 4
4 X4 -PC7-PC4
* y / *
<{ ,
* S
X4 -PC3 - P C O f <
< /
X4 -PC3-PCO
,8
B X8 ,-PB7-PBO
^ B
/ **-PB7-PBO
07 06 D5 D4 D3 D2 D1 DO 07 06 D5 04 03 D2 D1 DO
1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0
C- C-
X4 ,-PC3-PCO x4 t
8
B -PB7-PBO B < /a
'
D7 D6 D5 D4 03 02 DI DO D7 06 D5 D4 D3 02 D1 DO
0 0 1 0 0 1 o 0 1 1
- PA7 - PAO A ,
* s
X8
82C55A 82C55A
-PC7-PC4 x4 t
y ' -PC7-PC4
D7-DO-*- C-
-PB7-PBO B 4* x8
y
C.111
82C55A
D7 D6 D5 D4 D3 D2 01 DO D7 D6 D5 D4 D3 02 01 DO
1 0 0 1 1 0 0 0 1 0 0 1 1 0 1 0
A <* /
X 8 - PA7 - PAO A ,
' /*
X8 - PA7 - PAO
B2C55A 82C55A
, X4 -PC7-PC4 < x4 -PC7-PC4
1 y ' /
C- 07 - D O C-
x4 ,
'- P C 3 - P C O
/ ,
'-PC3-PCO
4
X S
D7 D6 D5 04 D3 D2 D1 DO D7 D6 D5 D4 03 D2 01 DO
0 1 1 0 0 1 0 0 1 1 0 1 1
- PA7 - PAO A , xa
' ^
82C55A
-PC7-PC4 , x4 -PC7-PC4
4 s
D7-DO-4-
-PC3-PCO f *, ^ / 4
-PB7-P80 B , x8 -PB7-PBO
' /
IBF(lnputBufferFullF/F)
A "high" on this ouput ndicates tha the data has been FIGURE 6. MODE1 INPUT
82C55A
STB
INTR
RD
INPUTFROM
PERIPHERAL
82C55A
WR
OBF
OUTPUT
PA7-PAO PA7-PAO
PC4 WR PC7
CONTROL WORD CONTROL WORD
PCS PC6
07 D6 05 D4 D3 D2 D1 DO D7 D6 D5 D4 03 D2 D1 DO
1 0 1 1 1/0 1 0
X PC3 1 0 1 0 1/0 1 1
X PC3
PC2 PC1
PCO PCO
Combinaons of Mode 1: Port A and Port B can be individually defined as input or output n Mode 1 to support a wde variety of strobed i/O
applcations.
FIGURE 10. COMBINATIONS OFMODE1
Operating Modas
Mode 2 fStrobed Bi-Directional Bus I/O) Output Operations
The funconal configuration provides a meaos for cornmun- OBF - (Ouput Buffer Full). The OBF output will go "low" to
cating with a peripheral device or structure on a single 8-bi indcate that he CPU has writen data out to por A.
bus for both ransmiting and recelving data (bi-direconal
bus I/O), "Hand shaking" signis are provided to maintain ACK - (Acknowledge). A low" on this input enables ihe
proper bus flow discipline similar to Mode 1. Interrupt gener- three-state outpu buffer of port A to send out the data. Oh-
aion and enable/dsable functions are also available. erwise, the outpu buffer will be n the high impedance state.
Mode 2 Basic Functional Defnitions: INTE 1 - (The INTE flip-flop associaed with OBF). Con-
trolled by bi set/reset of PC4.
Used in Group A only
One 8-bit, bi-directional bus Por (Port A) and a 5-bit Input Operations
control Por (Port C)
Both inputs and outputs are latched STB - (Strobe Input). A "low" on this input loads data into the
npu latch.
The 5-bi control port (Port C) is used for control and
status for the 8-bit, bi-directional bus por (Port A) IBF - (Input Buffer Full F/F). A "high" on this output ndicates
that data has been loaded into the input latch.
B-Drectional Bus I/O Control Signaf Definition
(Figures 11, 12,13, 14) INTE 2 - (The INTE flip-flop associated wlh IBF). Controlled
by bi set/rese of PC4.
INTR - (Interrupt Reques). A high on ths output can be
used to interrupt the CPU for both input or output operations.
10
C.114
82C55A
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 DO
INTRA
PC2-PCO
1 =(NPUT
0 = OUTPUT
PORTE
-+ 1=INPUT
0 = OUTPUT
GROUP B MODE
-- O = MODE O
1 =MODE1
|/0
DATA FROM
CPUTO 82C55A
PRIPHERAL
BUS
NOTE: Any sequence where WR~ occurs before ACK and STB occurs before RD is permissible. (INTR - IBF MASK - STB RD *- OBF
MASK - ACK - WR)
11
C.115
82C55A
PA7-PAO
N)
PC7 >-BFA
PA7-PAO
\
PC7 > OBFA
CONTROL WORD CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 DO PC6 .ACKA D7 D6 D5 D4 03 D2 D1 DO PC6 4 ACKA
1 1 XXX
1 1 XXX 0 1 1/0
PC4 4 STBA
0 0 1/0
PC4
PA7-PAO PA7-PAO
vV vV
PC7 . OBFA PC7 * OBFA
CONTROL WORD CONTROL WORD
PC6 4 ACKA PC6 4 ACKA
D7 D6 D5 D4 D3 D2 D1 DO D7 D6 D5 D4 D3 D2 D1 DO
1 1 XXX 1 0
X
PC4 4
PC5 MBFA
STBA
1 1 XXX 1 1
X
PC4
PC5 * IBFA
STBA
N
PB7-PBO PB7-PBO
12
C.116
82C55A
Through a "Write Por C" command, only he Port C pins GROUP A GROUPB
programmed as outputs in a Mode O group can be written.
FIGURE 15. MODE 1 STATUS WORD FORMAT
No other pins can be affected by a "Write Port C" command,
or can the interrupt enable flags be accessed. To write o
any Port C output programmed as an oupu in Mode 1 group D7 D6 05 D4 03 D2 D1 DO
or to change an interrupt enable flag, the "Set/Reset Port C OBFA INTE1 IBFA 1NTE2 INTRA X X X
Bit" command mus be used.
GROUP A GROUP B
With a "Set/Reset Port Cea Bit" command, any Port C line
programmed as an outpu (ncluding IBF and OBF) can be (Defined by Mode O or Mode 1 Selection)
written, or an inerrupt enable flag can be either set or reset. FIGURE16. MODE2STATUS WORD FORMAT
Port C lines programmed as inputs, including ACK and STB
lines, associated wih Port C fare not affected by a Current Orive Capability
"Set/Reset Por C Bi" command. Writing ohe correspond-
ing Port C bit positions of he ACK and STB lines with he Any output on Port A, B or C can sink or source 2.5rnA. This
"Se Reset Port C Bi" command will affec the Group A and feaure allows he 82C55A to directly drive Darlington ype
Group B inerrupt enable fiags, as illustrated in Figure 17. drivers and high-voltage displays ha require such sink or
source current.
13
C.117
82C55A
INTERRUPT
REQUEST
HIGH SPEED
MODE1 J
(OUTPUT)
L HAMMER
82C55A * *
(OUTPUT) |
CARRlAGE SEN.
*
peo
INTERRUPT CONTROL LOGIC
REQUEST AND DRIVERS
14
C.118
82C55A
INTERRUPT
REQUEST ^I
PC3 PAO RO
PA1 R1
PB3 o o
PC1 DATA READY MODEO .
(INPUT) PB4 4 o o
PC2 ACK PB5 4 o o
PC6 BLANKING PB6 4 0 O
PC7 CANCEL WORD PB7 4 o o
INTERRUPT J
REQUEST "*
FIGURE 19. KEYBOARD AND DISPLAY INTERFACE FIGURE 20. KEYBOARD AND TERMINAL ADDRESS
INTERFACE
INTERRUPT
REQUEST +I
I
PCO STB DATA 32C55A
PC1
BIT < PC2 ROW STB
SET/RESET PC2 SAMPLE EN PC1 COLUMN STB
PC3 STB PCO CURSOR WV STB
FIGURE 21. DIGITAL TO ANALOG, ANALOG TO DIGITAL FIGURE 22. BASIC CRT CONTROLLER INTERFACE
15
C.119
B2C55A
INTERRUPT , INTERRUPT .
REQUEST ^ I REQUEST " * |
J
PC3 DO PC3 PAO RO
PA1 D1 PA1 R1
PA2 D2 PA2 R2
n_ FLOPPY DISK P- B LEVEL
PA3 PA3
j Ud CONTROLLER Kli PAPER
PA4 D4 AND ORIVE PA4 R4 TAPE
PA5 R5 READER
D5 MODE1 . PA5
MODE2 < PAG D6 (INPUT) PA6 R6
PA7 D7 PA7 R7
FIGURE 23. BASIC FLOPPY DISC INTERFACE FIGURE 24. MACHINE TOOL CONTROLLER INTERFACE
16
C.120
82C55A
Die; Characteristics
Gat e Count 1 000 fiates
CAUTON: Stresses above hose Usted n "Absolute Mximum Ratings" may cause pt rmanent damage lo the device. This s a stress onlyrating and opera/fon
ofthe devce at these orany other condttions above those indicated in t e aperatonal secltons ofthis spedfication s not imped,
NOTE:
1. 6 JA is measured with the component rnounted on an evaluaton PC bo ard in free air.
LIMITS
ICCSB Standby Power Supply Current - 10 ^A VCG = 5-5V- VIN = VCC or GND- Outpu Open
ICCOP Operating Power Supply Current - . 1 mA/MHz TA = +25C, V cc = 5.0V, Typical (See Note 3)
NOTES:
2. No nternal current limiting exists on Port Outputs. A resistor must be added extemally o limit he current.
3. ICCOP = 1mA/MHz of Peripheral Read/Write cycle time. {Example: I.Ojis I/O Read/Wrie cycle time ~ imA).
4. Tested as VOH ai -2.5mA.
Capacitance TA = 25C
17
C.121
82C55A
<\ Electrical Specificatons V cc = +5V 10%, GND = OV;TA = -55C to +125C (M82C55A) (M82C55A-5);
TA = -40C to -f 85C (I82C55A) {I82C55A-5);
TA = 0C o +70C (C82C55A) (C82C55A-5)
82C55A-5 82C55A
TEST
SYMBOL PARAMETER MIN MAX MIN MAX UNITS CONDITIONS
REAO TIMING
WRITE TIMING
OTHER TIMING
NOTE: Period of intial Reset pulse after power-on must be at least 50|isec. Subsequent Reset pulses rnay be SOOns minimum.
18
C.122
82C55A
Timing Waveforms
tRR (3)
RD
V
tlR(13) tHR(14)
INPUT
tAR(1) tRA (2)
es, AI, AO
-4 tWW (9) *.
WR
^ S.
7
tWD (111
i tDW
r 00) *
CS,A1,AO
<...
X
.tAW(7) - >
* J
1
OUTPUT
x-
, tWS(12) J
V
tST(16)
IBF (23)
tSlT
(26) tR!B(24)
4 M ,.
INTR tRIT
L (25)
RD
INPUT FROM
PERIPHERAL
19
C.123
82C55A
Timing Waveforms
OBF
OUTPUT
tWB (12)
DATA FROM
CPUT082CS5A
PERIPHERAL
BUS
20
C.124
82C55A
o
WR
HIGHIMPEDANCE-
WW(9)
FIGURE 30. WRITE TIMING FIGURE31. READ TIMING
Burn-ln Circuits
MD82C55A CERDIP MR82C55A CLCC
GND
NOTES: NOTES:
1. V CC = 5.5V0.5V 1. C1 =0.01jiF mnimum
2. VIH = 4.5V10% 2. All resstors are 47kO 5%
3. V|L = -0,2Vto0.4V 3. fO = 100kHz10%
4. GND = OV 4. f1 =fO + 2;f2 = f 1 * 2 ; . . . ; f
21
C.125
82C55A
Die Characterstics
DIEDIMENSIONS: GLASSIVATION:
95 x 100 x 191mils Type: SiO2
Thickness:8kA1kA
METALLIZATION:
Type: Silicon - Aluminum WORST CASE CURRENT DENSITY:
Thickness:l1k1k 0.78x10 5 A7cm2
RESET
PC2 PD3 PBO PB1 PB2 PB3 PB4 PB5 PB6 PB7
22
C.126
82C55A
D1 0.005 - 0.13 - 5
E 0.600 0.625 15.24 . 15.87 6
23
C.127
82C55A
MIN
VIEW "A" TYP.
NOTES:
1. Conrolling dimensin: INCH. Converted millimeterdimensions
are not necessarily exact.
2. Dimensions and olerancing per ANS Y14.5M-1982,
3. Dimensions D1 and E1 do not iriclude mold protrusions. Allow-
able mold protrusion is 0.010 inch (0.25mm) per sde. Dimen-
sions D1 and E1 include mold mismatch and are measured at
the extreme material condtion at he body partng une.
4. To be measured at seating plae [-C^j contact point.
5. Centerline to be determined where center leads exit plstic body.
6. "N" is the number of terminal positions.
24
C.128
82C55A
i
F40.6 MIL-STD-1835 GDIP1-T40 (D-S, CONFIGURATION A)
40 LEAD CERAMIC DUAL-IN-LINE FRT SEAL PACKAGE
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A . 0.225 - 5.72 -
b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
25
C.129
82C55A
J44.A MIL-STD-1835CQCC1-N44(C-5)
0.010 E H(D
44 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
-D-
INCHES MILLIMETERS
-D3-
SYMBOL MIN MAX MIN MAX NOTES
I * 45
~T A 0.064 0.120 1.63 3.05 6,7
A1 0.054 0.088 1.37 2.24 -
B 0.033 0.039 0.84 0.99 4
B1 0.022 0.028 0.56 0.71 2,4
B2 0.072 REF 1.83 REF -
B3 0.006 0.022 0.15 0.56 -
D 0.640 0.662 16.26 16.81 -
D1 0.500 BSC 12.70 BSC -
D2 0.250 BSC 6.35 BSC -
D3 - 0.662 - 16.81 2
] 0.010 E
E 0.640 0.662 16.26 16.81 -
PLANE1
e 0.050 BSC 1.27 BSC -
riTT T e1 0.015 - 0.38 - 2
h 0.040 REF 1.02 REF 5
i 0.020 REF 0.51 REF 5
L 0.045 0.055 1.14 1.40 -
L1 0.045 0.055 1.14 1,40 -
L2 0.075 0.095 1.90 2.41 -
L3 0.003 0.015 0.08 0.38 -
ND 11 11 3
NE 11 11 3
N 44 44 3
Rev. 05/18/94
NOTES:
1. Metallzed castellatons shall be connected to plae 1 terminis
and extend toward plae 2 across at least two layers of ceramic
or completely across all of he ceramic layers to make electrical
connection with the optional plae 2 terminis.
2. Unless otherwise specified, a mnimum clearance of 0.015 nch
(0.38mm) shall be maintained between all metallized feaures
(e.g., lid, castellations, terminis, thermal pads, etc.)
ftft 3. Symbol "N" is the mximum number of terminis. Symbols "ND"
M and "NE" are the number of terminis along the sides of length
"D" and "E", respectively.
4. The required plae 1 terminis and optional plae 2 terminis (f
used) shall be electrically conneced.
5. The crner shape (square, notch, radius, etc.) may vary at he
manufacturis option, from that shown on the drawing.
6. Chip carriers shall be consructed of a mnimum of two ceramic
layers.
7. Dimensin "A" controls the overall package hlckness. The mxi-
mum "A" dimensin s package height before beng solder dipped.
8. Dimensioning and tolerancing per ANS Y14.5M-1982.
9. Conrolling dimensin: INCH.
r
26