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A B C D E

MYALL2 Block Diagram Project Code PCB


CLK GEN. Intel Mobile CPU 91.4G901.001 06203-MP
IDT CV125 TV Out
4 3 4
14
Yonah 478
G792 Celeron M CRT
4~5
19 14

FSB 400/533/667 MHz


LCD CPU DC/DC
13 ISL6262 37 ~ 38
DDR II INPUTS OUTPUTS
SO-DIMM 1
11 ~ 12 RAM BUS Calistoga PEG Nvidia VCC_CORE
VRAMx4 DCBATOUT 0.844~1.3V
533/667 MHz
945PM / 940GML G72M-V 49 ~ 50 27A
DDR II 46 ~ 48 , 51 ~ 55
SO-DIMM 2
6 ~ 10
11 ~ 12
PWR SW SYSTEM DC/DC
MAX8744 35
DMI 100 MHz CP2211 25
3
PCMCIA INPUTS OUTPUTS
3

TI SLOT 27 3D3V_S5
PCI BUS DCBATOUT
PCI7412 5V_S5
Card APL5331-KAC
a. Line In Codec HDA Reader26 APL5912-KAC
b. Mic In ALC883 24 ~ 25
1394 26 APL5308-25AC 40
c. INT Mic 29 28
Intel INPUTS OUTPUTS

d. Line Out OP AMP 82801 GBM TV & Video-In 1D5V_S5 1D05V_S0


e. INT.SPKR G1421B Mini-PCI 30 1D8V_S3 1D5V_S0
29
29 ICH7-M 30 3D3V_S5 1D5V_S5
WIRELESS 30 3D3V_S0 2D5V_S0
MODEM APW7057-KC
TPS51100DGQ
MDC Card PCIE x 1 LAN TXFM RJ45 APL5331-KAC 41
2 21 2

RTL8111B 23 23 INPUTS OUTPUTS


22 ~ 23
5V_S5 3D3V_S5
PCIE x 1 LPC BUS 5V_S5 1D8V_S3
MINI CARD 5V_S5 0D9V
26
1D8V_S0 1D2V_S0
SATA DEBUG SIO KBC
CONN34 NS87381 32 KB3910 CHARGER
31 ISL6255 42
15 ~ 18
X BUS
INPUTS OUTPUTS

FIR Touch BT+


BIOS INT. KB CIR DCBATOUT
32 16.8V 3A
PCB Layer Stackup 34 Pad 33 33 33

1 L1: Signal 1 PATA USB 1

L2: VCC
Wistron Corporation

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L3: Signal 2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

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SATA HDD CDROM MINI USB USB Taipei Hsien 221, Taiwan, R.O.C.

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L4: Signal 3 CAMERA

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24 ~ 25 20 20 Title
BlueTooth 4 Port21

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L5: GND 13
21 BLOCK DIAGRAM

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L6: Signal 4 Size Document Number Rev

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MYALL2

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MP

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Date: Tuesday, April 11, 2006 Sheet 1 of 57
A B C D E
A B C D E
ICH7M Integrated Pull-up 954305D 27Mhz/LCDCLK Spread Calistoga Strapping Signals and
and Pull-down Resistors ICH7-M EDS 17837 1.5V1
and Frequency Selection Table Configuration EDS 17050 0.71
page 7
SS3 SS2 SS1 SS0
Byte9 bit6 bit5 bit4 Spread Amount% page 3 Pin Name Strap Description Configuration
EE_DIN, EE_DOUT, GNT[3:0], GPIO[25], bit 7 CFG[2:0] FSB Frequency Select
GNT[4]#/GPIO48, GNT[5]#/GPO17, PME#, 0 0 0 0 -0.50 Down 001 = FSB533
ICH7 internal 20K pull-ups 011 = FSB667
LAD[3:0]#/FHW[3:0]#, LAN_RXD[2:0] 0 0 0 1 -1.00 Down others = Reserved

4 LDRQ[0], LDRQ[1]/GPIO[41], 0 0 1 0 -1.50 Down CFG[4:3] Reserved 4


PWRBTN#, TP[3] 0 0 1 1 -2.00 Down CFG5 DMI x2 Select 0 = DMI x2
1 = DMI x4 (Default)
0 1 0 0 -0.75 Down CFG6 Reserved
DD[7], DDREQ ICH7 internal 11.5K pull-downs
0 1 0 1 -1.25 Down CFG7 0 = Reserved
CPU Strap 1 =Mobile CPU(Default)
ACZ_BIT_CLK, ACZ_RST#, ACZ_SDIN[2:0], ICH7 internal 20K pull-downs 0 1 1 0 -1.75 Down
Reserved
ACZ_SDOUT, ACZ_SYNC, DPRSLPVR/GPIO16, 0 1 1 1 -2.25 Down CFG8
EE_CS,SPI_ARB, SPI_CLK, SPKR, 1 0 0 0 +-0.25 Center 0 = Reverse Lanes,15->0,14->1 ect..
CFG9 PCI Express Graphics 1= Normal operation(Default):Lane
1 0 0 1 +-0.5 Center Lane Reversal Numbered in order
USB[7:0][P,N] ICH7 internal 15K pull-downs
1 0 1 0 +-0.75 Center
CFG[11:10] Reserved
SATALED# ICH7 internal 15K pull-up 1 0 1 1 +-1.0 Center
XOR/ALL Z test 00 = Reserved
1 1 0 0 +-0.25 Center CFG[13:12] straps 01 = XOR mode enabled
LAN_CLK ICH7 internal 100K pull-down 10 = All Z mode enabled
1 1 0 1 +-0.5 Center 11 = Normal Operation
(Default)
1 1 1 0 +-0.75 Center
CFG[15:14] Reserved Reserved
ICH7M IDE Integrated Series 1 1 1 1 +-1.0 Center
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled

3 Termination Resistors Global R-comp Disable


1 = Dynamic ODT Enabled (Default)
0 = All R-comp Disable 3
CFG17 (All R-comps) 1 = Normal Operation (Default)
DD[15:0], DIOW#, DIOR#, DREQ,
approximately 33 ohm
PCI Routing page 16
CFG18 VCC Select 0 = 1.05V (Default)
DDACK#, IORDY, DA[2:0], DCS1#, 1 = 1.5V
DCS3#, IDEIRQ
IDSEL INT -> PIRQ REQ/GNT CFG19 DMI Lane Reversal 0 = Normal operation (Default):lane
A->G, B->B, Numbered in order
1 =Reverse Lane,4->0,3->1 ect...
7412 22 C->F, D->G 0
A/C -> E 0 = Only SDVO or PCIE x1 is
ICH7M Functional Strap Definitions page 16
MiniPCI 21 B/D -> E 1 CFG20 SDVO/PCIE
Concurrent
operational (Default)
1 =SDVO and PCIE x1 are operating
simultaneously via the PEG port
Signal Usage/When Sampled Comment
SDVOCRTL SDVO Present 0 = No SDVO Card present
ACZ_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 _DATA (Default)
PCIE Port Config bit1, pulled low.When TP3 not pulled low at rising edge 1= SDVO Card present
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers:
offset 224h) NOTE: All strap signals are sampled with respect to the leading
edge of the Calistoga GMCH PWORK in signal.
ACZ_SYNC PCIE bit0, Sets bit0 of RPC.PC(Config Registers:Offset 224h)
Rising Edge of PWROK.
EE_CS Reserved This signal should not be pull high.
EE_DOUT Reserved This signal should not be pull low.
2 GNT2# Reserved This signal should not be pull low. 2
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for
GNT3# Swap Override. all cycles targeting FWH BIOS space).
Rising Edge of PWROK. Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.

GNT5#/ Boot BIOS Destination Controllable via Boot BIOS Destination bit
GPIO17#, Selection. (Config Registers:Offset 3410h:bit 11:10).
GNT4#/ Rising Edge of PWROK. GNT5# is MSB, 01-SPI, 10-PCI, 11-LPC.
GPIO48

DPRSLPVR Reserved This signal should not be pull high.


GPIO25 Reserved.
Rising Edge of RSMRST#. This signal should not be pull low.
INTVRMEN Integrated VccSus1_05 Enables integrated VccSus1_05 VRM when
VRM Enable/Disable. sampled high
Always sampled.
LINKALERT# Reserved Requires an external pull-up resistor.
REQ[4:1]# XOR Chain Selection.
Rising Edge of PWROK. TBD, Chapter 8.
1 1
SATALED# Reserved This signal should not be pull low.
SPKR No Reboot. If sampled high, the system is strapped to the Wistron Corporation
Rising Edge of PWROK. "No Reboot" mode(ICH7 will disable the TCO Timer 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
system reboot feature). The status is readable
via the NO REBOOT bit. Title

TP3 XOR Chain Entrance. This signal should not be pull low unless using
Reference
Rising Edge of PWROK. XOR Chain testing. Size Document Number Rev
MYALL2 MP
Date: Friday, March 24, 2006 Sheet 2 of 57
A B C D E

3D3V_S0
3D3V_S0 R448 R204 R437
0R0603-PAD 0R0603-PAD 0R0603-PAD
1 2 3D3V_CLKPLL_S0 3D3V_S0 1 2 3D3V_48MPWR_S0 3D3V_CLKGEN_S0 2 1

1
C647 C652 C626 C633 C636 C655 C654 C653 C637 C625 C632
SC1U6D3V2ZY-GP SC1U6D3V2ZY-GP
SCD1U16V2ZY-2GP SC4D7U10V5ZY-3GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

2
4 4

3D3V_S0
1

R426
10KR2J-3-GP

DREFSSCLK_1 4 1 RN67 DREFSSCLK 7


2

DREFSSCLK#_1 3 2 SRN33J-5-GP-U DREFSSCLK# 7


SS_SEL
H/L: 100/96MHz CLK_MCH_3GPLL_1 4 1 RN68 CLK_MCH_3GPLL 7
1

U41 CLK_MCH_3GPLL_1# 3 2 SRN33J-5-GP-U CLK_MCH_3GPLL# 7


R427 DY
10KR2J-3-GP 31 PCLK_KBC R4512 1 33R2J-2-GP PCLKCLK0 56 17 DREFSSCLK_1 CLK_PCIE_ICH_1 3 2 RN73 CLK_PCIE_ICH 16
PCI0 LVDS DREFSSCLK#_1 CLK_PCIE_ICH_1#
3 PCI1 LVDS# 18 4 1 SRN33J-5-GP-U CLK_PCIE_ICH# 16
25 PCLK_PCM R4412 1 22R2J-2-GP PCLKCLK2 4
2

R4322 33R2J-2-GP PCLKCLK3 PCI2 CLK_MCH_3GPLL_1 CLK_PCIE_LAN_1


32 PCLK_SIO 1 5 PCI3 SRC1 19 3 2 RN71 CLK_PCIE_LAN 22
34 PCLK_FWH R4382 1 22R2J-2-GP 20 CLK_MCH_3GPLL_1# CLK_PCIE_LAN_1# 4 1 SRN33J-5-GP-U CLK_PCIE_LAN# 22
R4342 33R2J-2-GP SS_SEL SRC1# CLK_PCIE_ICH_1
30 PCLK_MINI 1 9 PCIF1/SEL100/96# SRC2 22
16 CLK_ICHPCI R2052 1 33R2J-2-GP ITP_EN 8 23 CLK_PCIE_ICH_1# CLK_PCIE_SATA_1 4 1 RN69 CLK_PCIE_SATA 15
R4332 10KR2J-3-GP PCIF0/ITP_EN SRC2# CLK_PCIE_LAN_1 CLK_PCIE_SATA_1#
1 SRC3 24 3 2 SRN33J-5-GP-U CLK_PCIE_SATA# 15
16 PM_STPPCI# 55 25 CLK_PCIE_LAN_1#
PCI_STOP# SRC3# CLK_PCIE_SATA_1
H/L : CPU_ITP/SRC7 SRC4 26
27 CLK_PCIE_SATA_1#
SRC4#
PCLK_FWH & PCLK_PCM 11,18 SMBC_ICH 46 SCL SRC5 31
3 47 30 CLK_PCIE_MINI_12 3 2 RN78 CLK_PCIE_MINI2 26
3
need equal length 11,18 SMBD_ICH SDA SRC5#
33 CLK_PCIE_MINI_12 CLK_PCIE_MINI_12# 4 1 SRN33J-5-GP-U CLK_PCIE_MINI2# 26
RN66 SRN33J-5-GP-U SRC6 CLK_PCIE_MINI_12#
SRC6# 32
7 DREFCLK 1 4 DREFCLK_1 14 CLK_PCIE_PEG_1 3 2 RN77 G72 CLK_PCIE_PEG 46
DREFCLK#_1 DOT96 CLK_PCIE_PEG_1 CLK_PCIE_PEG_1#
7 DREFCLK# 2 3 15 DOT96# CPU2_ITP/SRC7 36 4 1 SRN33J-5-GP-U CLK_PCIE_PEG# 46 When use UMA RN9 DUMMY
C648 35 CLK_PCIE_PEG_1#
SC27P50V2JN-2-GP CPU2_ITP#/SRC7# CLK_CPU_BCLK_1 3 2 RN75 CLK_CPU_BCLK 4
1 2 GEN_XTAL_IN 50 44 CLK_CPU_BCLK_1 CLK_CPU_BCLK_1# 4 1 SRN33J-5-GP-U CLK_CPU_BCLK# 4
GEN_XTAL_OUT_R R444 2 XTAL_IN CPU0
1 0R0603-PAD GEN_XTAL_OUT 49 XTAL_OUT CPU0# 43 CLK_CPU_BCLK_1#
1

X4 41 CLK_MCH_BCLK_1 CLK_MCH_BCLK_1 3 2 RN76 CLK_MCH_BCLK 6


X-14D31818M-31GP 32 R4522 CPU1
CLK14_SIO 1 22R2J-2-GP CPU1# 40 CLK_MCH_BCLK_1# CLK_MCH_BCLK_1# 4 1 SRN33J-5-GP-U CLK_MCH_BCLK# 6
C640 82.30005.831 16 CLK_ICH14 R4532 1 22R2J-2-GP GEN_REF 52
SC27P50V2JN-2-GP R4502 REF
1 475R2F-L1-GP GEN_IREF 39 54 PM_STPCPU# 16
2

IREF CPU_STOP# CPU_SEL2


1 2 FSC/TEST_SEL 53 CPU_SEL2 4,7
16 CPU_SEL1 CPU_SEL1 4,7
FSB/TEST_MODE CLK48 R436 22R2J-2-GP 2
37 CLK_EN# 10 VTT_PWRGD#/PD USB48/FSA 12 1 CLK48_ICH 16
R435 R428 22R2J-2-GP 2 1 CLK48_CARDBUS 25
10KR2J-3-GP R429 2K2R2J-2-GP 2 1 CPU_SEL0 CPU_SEL0 4,7
3D3V_S0 2 1 2 34 3D3V_CLKGEN_S0
VSS_PCI VDD_SRC
6 VSS_PCI VDD_SRC 21

51 VSS_REF VDD_PCI 7
45 VSS_CPU VDD_PCI 1
38 VSSA
13 VSS48 VDD_REF 48 FSC FSB FSA CPU FSB
29 VSS_SRC VDD_CPU 42
37 3D3V_CLKPLL_S0 0 0 0 266M X
VDDA 3D3V_48MPWR_S0 0 0 1 133M 533M
VDD48 11
28 0 1 0 200M X
2 VDD_SRC 0 1 1 166M 667M 2
1 0 0 333M X
IDTCV125PAG-GP 71.00125.A0W 1 0 1 100M X
1 1 0 400M X
1 1 1 Reserved X
RN63
SRN49D9F-GP
DREFSSCLK# 1 4 1D05V_S0
DREFSSCLK 2 3

2
RN62
SRN49D9F-GP R573 DY R574 DY R575 DY
DREFCLK# 1 4 1K74R2F-GP 1K74R2F-GP 1K74R2F-GP
DREFCLK 2 3

1
CPU_SEL0 CPU_SEL1 CPU_SEL2
RN79 RN72

2
SRN49D9F-GP SRN49D9F-GP
CLK_CPU_BCLK 1 4 CLK_PCIE_LAN 1 4 R576 DY R577 DY R578 DY
CLK_CPU_BCLK# 2 3 CLK_PCIE_LAN# 2 3 1K74R2F-GP 1K74R2F-GP 1K74R2F-GP

1
RN80 RN65
PCLK_SIO EC50 1 2 SC10P50V2JN-4GP DY SRN49D9F-GP SRN49D9F-GP
CLK_MCH_BCLK 1 4 CLK_PCIE_SATA 2 3
CLK_ICH14 EC55 1 2 SC10P50V2JN-4GP DY CLK_MCH_BCLK# 2 3 CLK_PCIE_SATA# 1 4
PCLK_MINI EC46 1 2 SC10P50V2JN-4GP

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1 DY 1
RN81 G72 RN74

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PCLK_PCM EC51 1 2 SC10P50V2JN-4GP DY SRN49D9F-GP SRN49D9F-GP

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CLK_PCIE_PEG CLK_PCIE_ICH
1 4 1 4
Wistron Corporation

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PCLK_KBC EC53 1 2 SC10P50V2JN-4GP DY CLK_PCIE_PEG# 2 3 CLK_PCIE_ICH# 2 3
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

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CLK_ICHPCI EC45 1 2 SC10P50V2JN-4GP Taipei Hsien 221, Taiwan, R.O.C.

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DY
RN64 RN82

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CLK48_ICH EC47 1 2 SC10P50V2JN-4GP DY SRN49D9F-GP SRN49D9F-GP Title

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CLK_MCH_3GPLL 2 3 CLK_PCIE_MINI2 1 4 Clock Generator ICS954305D

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EMI CLK_MCH_3GPLL# 1 4 CLK_PCIE_MINI2# 2 3
Size Document Number Rev
MYALL2 MP
Date: Thursday, March 30, 2006 Sheet 3 of 57
A B C D E
A B C D E

H_DINV#[3..0]
H_DINV#[3..0] 6
H_DSTBN#[3..0]
H_DSTBN#[3..0] 6
TP24 TPAD30
U34A 1D05V_S0 H_DSTBP#[3..0]
H_DSTBP#[3..0] 6
H_A#[31..3] H_A#3 J4 H1
6 H_A#[31..3] A[3]# ADS# H_ADS# 6
4 H_A#4 L4 E2 H_D#[63..0] 4
A[4]# BNR# H_BNR# 6 H_D#[63..0] 6
H_A#5 M3 G5 H_BPRI# 6
A[5]# BPRI#

1
H_A#6 K5 A[6]#

ADDR GROUP 0
H_A#7 M1 H5 H_DEFER# 6 R101
H_A#8 A[7]# DEFER# 56R2J-4-GP
N2 A[8]# DRDY# F21 H_DRDY# 6
H_A#9 J1 E1 H_DBSY# 6
H_A#10 A[9]# DBSY#
N3

2
H_A#11 A[10]# Place testpoint on
P5 A[11]# BR0# F1 H_BREQ#0 6
H_A#12 P2 H_IERR# with a GND
A[12]#

CONTROL
H_A#13 L1 D20 H_IERR# 0.1" away
H_A#14 A[13]# IERR#
P4 A[14]# INIT# B3 H_INIT# 15
H_A#15 P1
H_A#16 A[15]#
R1 A[16]# LOCK# H4 H_LOCK# 6
L2 H_CPURST# 6 U34B
6 H_ADSTB#0 ADSTB[0]#
B1 H_RS#[2..0] 6 H_D#0 E22 AA23 H_D#32
6 H_REQ#[4..0] RESET# D[0]# D[32]#
H_REQ#0 K3 F3 H_RS#0 H_D#1 F24 AB24 H_D#33
H_REQ#1 H2 REQ[0]# RS[0]# H_RS#1 H_D#2 D[1]# D[33]# H_D#34
REQ[1]# RS[1]# F4 E26 D[2]# D[34]# V24
H_REQ#2 K2 G3 H_RS#2 H_D#3 H22 V26 H_D#35
H_REQ#3 J3 REQ[2]# RS[2]# H_D#4 D[3]# D[35]# H_D#36
REQ[3]# TRDY# G2 H_TRDY# 6 F23 D[4]# D[36]# W25

DATA GRP 0
H_REQ#4 L5 H_THERMDA H_D#5 H_D#37

DATA GRP 2
REQ[4]# G25 D[5]# D[37]# U23
G6 H_HIT# 6 H_D#6 E25 U25 H_D#38
HIT# D[6]# D[38]#

1
H_A#17 Y2 E4 H_HITM# 6 H_D#7 E23 U22 H_D#39
H_A#18 A[17]# HITM# C160 H_D#8 D[7]# D[39]# H_D#40
U5 A[18]# K24 D[8]# D[40]# AB25
H_A#19 R3 AD4 XDP_BPM#0 TP48 TPAD30 SC2200P50V2KX-2GP H_D#9 G24 W22 H_D#41

2
A[19]# BPM[0]# D[9]# D[41]#

ADDR GROUP 1
H_A#20 W6 AD3 XDP_BPM#1 TP49 TPAD30 H_THERMDC H_D#10 J24 Y23 H_D#42
H_A#21 A[20]# BPM[1]# XDP_BPM#2 TP43 TPAD30 H_D#11 D[10]# D[42]# H_D#43
U4 A[21]# BPM[2]# AD1 J23 D[11]# D[43]# AA26
H_A#22 Y5 AC4 XDP_BPM#3 TP42 TPAD30 H_D#12 H26 Y26 H_D#44
A[22]# BPM[3]# D[12]# D[44]#
XDP/ITP SIGNALS
H_A#23 U2 AC2 XDP_BPM#4 TP40 TPAD30 H_D#13 F26 Y22 H_D#45
H_A#24 A[23]# PRDY# XDP_BPM#5 TP41 TPAD30 1D05V_S0 H_D#14 D[13]# D[45]# H_D#46
R4 A[24]# PREQ# AC1 K22 D[14]# D[46]# AC26
3 H_A#25 T5 AC5 XDP_TCK TP47 TPAD30 H_D#15 H25 AA24 H_D#47 3
A[25]# TCK D[15]# D[47]#

2
H_A#26 T3 AA6 XDP_TDI TP35 TPAD30 H23 W24 H_DSTBN#2 6
A[26]# TDI 6 H_DSTBN#0 DSTBN[0]# DSTBN[2]#
H_A#27 W3 AB3 XDP_TDO TP39 TPAD30 R88 G22 Y25 H_DSTBP#2 6
A[27]# TDO 6 H_DSTBP#0 DSTBP[0]# DSTBP[2]#
H_A#28 W5 AB5 XDP_TMS TP38 TPAD30 56R2J-4-GP J26 V23 H_DINV#2 6
A[28]# TMS 6 H_DINV#0 DINV[0]# DINV[2]#
H_A#29 Y4 AB6 XDP_TRST# TP46 TPAD30
H_A#30 A[29]# TRST# XDP_DBRESET# TP10 TPAD30
W2 C20

1
H_A#31 A[30]# DBR# H_D#16 H_D#48
Y1 A[31]# N22 D[16]# D[48]# AC22
V4 D21 CPU_PROCHOT# 37 H_D#17 K25 AC23 H_D#49
THERM

6 H_ADSTB#1 ADSTB[1]# PROCHOT# D[17]# D[49]#


A24 H_THERMDA 19 H_D#18 P26 AB22 H_D#50
THERMDA H_D#19 D[18]# D[50]# H_D#51
15 H_A20M# A6 A20M# THERMDC A25 H_THERMDC 19 R23 D[19]# D[51]# AA21
15 H_FERR# A5 H_D#20 L25 AB21 H_D#52
FERR# H_D#21 D[20]# D[52]# H_D#53
15 H_IGNNE# C4 C7 PM_THRMTRIP-A# 7 L22 AC25

DATA GRP 1
IGNNE# THERMTRIP# D[21]# D[53]#

DATA GRP 3
H_D#22 L23 AD20 H_D#54
R96 0R0402-PAD H_D#23 D[22]# D[54]# H_D#55
15 H_STPCLK# D5 STPCLK# M23 D[23]# D[55]# AE22
15 H_INTR C6 1 2 PM_THRMTRIP-I# 19 H_D#24 P25 AF23 H_D#56
LINT0 D[24]# D[56]#
H CLK

B4 A22 PM_THRMTRIP# H_D#25 P22 AD24 H_D#57


15 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 3 D[25]# D[57]#
A3 A21 should connect to H_D#26 P23 AE21 H_D#58
15 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 3 D[26]# D[58]#
ICH7 and Calistoga H_D#27 T24 AD21 H_D#59
TPAD30 TP34 without T-ing H_D#28 D[27]# D[59]# H_D#60
AA1 RSVD[01] R24 D[28]# D[60]# AE25
TPAD30 TP31 AA4 T22 TP27 TPAD30 ( No stub) H_D#29 L26 AF25 H_D#61
TPAD30 TP33 RSVD[02] RSVD[12] 1D05V_S0 H_D#30 D[29]# D[61]# H_D#62
AB2 RSVD[03] T25 D[30]# D[62]# AF22
TPAD30 TP32 AA3 H_D#31 N24 AF26 H_D#63
RSVD[04] D[31]# D[63]#

1
TPAD30 TP26 TP17 TPAD30
RESERVED

M4 RSVD[05] RSVD[13] D2 6 H_DSTBN#1 M24 DSTBN[1]# DSTBN[3]# AD23 H_DSTBN#3 6


TPAD30 TP25 N5 F6 TP22 TPAD30 R188 N25 AE24 H_DSTBP#3 6
RSVD[06] RSVD[14] 1KR2F-3-GP 6 H_DSTBP#1 DSTBP[1]# DSTBP[3]#
TPAD30 TP28 T2 D3 M26 AC20 H_DINV#3 6
RSVD[07] RSVD[15] 6 H_DINV#1 DINV[1]# DINV[3]#
TPAD30 TP29 V3 C1
RSVD[08] RSVD[16] TP50 TPAD30 Layout Note: CPU_GTLREF0 COMP0 R164 1 27D4R2F-L1-GP
B2 AF1 AD26 R26 2

1 2
TPAD30 TP16 RSVD[09] RSVD[17] TP21 TPAD30 0.5" max length. GTLREF COMP[0] COMP1 R1721 54D9R2F-L1-GP
C3 RSVD[10] RSVD[18] D22 MISC COMP[1] U26 2

1
SC1KP16V2KX-GP
C23 TP20 TPAD30 U1 COMP2 R146 1 2 27D4R2F-L1-GP
2 TPAD30 TP13 RSVD[19] TP19 TPAD30 R189 C258 R381 COMP[2] 2
B25 RSVD[11] RSVD[20] C24 2 1TEST1 C26 TEST1 COMP[3] V1 COMP3 R1761 2 54D9R2F-L1-GP
2KR2F-3-GP 1KR2J-1-GP

2
BGA479-SKT6-GPU1 1 2TEST2 D25 E5 H_DPRSLP# 15,37
62.10079.001 R384 51R2F-2-GP TEST2 DPRSTP#
B5 H_DPSLP# 15

2
DPSLP#
2nd source: 62.10053.401 DPWR# D24 H_DPWR# 6
3,7 CPU_SEL0 B22 BSEL[0] PWRGOOD D6 H_PWRGD 15,19
3,7 CPU_SEL1 B23 BSEL[1] SLP# D7 H_CPUSLP# 6,15
3,7 CPU_SEL2 C21 BSEL[2] PSI# AE6 PSI# 37
BGA479-SKT6-GPU1
Layout Note:
1D05V_S0 Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .

XDP_TDI 1 2
R184 150R2F-1-GP
XDP_TMS 1 2
R186 DY 39D2R3F-2-GP
XDP_TDO R185 1 2 54D9R2F-L1-GP
DY
H_CPURST# R98 1 2 54D9R2F-L1-GP

3D3V_S0

1
XDP_DBRESET# 1 2 1
R90 150R2F-1-GP

XDP_TCK 1 2 Wistron Corporation


R200 27D4R2F-L1-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
XDP_TRST# R201 1 2 680R3F-GP Taipei Hsien 221, Taiwan, R.O.C.

All place within 2" to CPU Title

CPU (1 of 2)
Size Document Number Rev

MYALL2 MP
Date: Thursday, March 30, 2006 Sheet 4 of 57
A B C D E
A B C D E

VCC_CORE_S0
U34D
VCC_CORE_S0 A4 P6
VSS[001] VSS[082]
4 A8 VSS[002] VSS[083] P21 4
A11 VSS[003] VSS[084] P24
U34C A14 R2
VSS[004] VSS[085]
A7 VCC[001] VCC[068] AB20 A16 VSS[005] VSS[086] R5
A9 VCC[002] VCC[069] AB7 A19 VSS[006] VSS[087] R22
A10 VCC[003] VCC[070] AC7 A23 VSS[007] VSS[088] R25
A12 VCC[004] VCC[071] AC9 A26 VSS[008] VSS[089] T1
A13 VCC[005] VCC[072] AC12 B6 VSS[009] VSS[090] T4
A15 VCC[006] VCC[073] AC13 B8 VSS[010] VSS[091] T23
A17 VCC[007] VCC[074] AC15 B11 VSS[011] VSS[092] T26
A18 VCC[008] VCC[075] AC17 B13 VSS[012] VSS[093] U3
A20 VCC[009] VCC[076] AC18 B16 VSS[013] VSS[094] U6
B7 VCC[010] VCC[077] AD7 B19 VSS[014] VSS[095] U21
B9 VCC[011] VCC[078] AD9 B21 VSS[015] VSS[096] U24
B10 VCC[012] VCC[079] AD10 B24 VSS[016] VSS[097] V2
B12 VCC[013] VCC[080] AD12 C5 VSS[017] VSS[098] V5
B14 VCC[014] VCC[081] AD14 C8 VSS[018] VSS[099] V22
B15 VCC[015] VCC[082] AD15 C11 VSS[019] VSS[100] V25
B17 VCC[016] VCC[083] AD17 C14 VSS[020] VSS[101] W1
B18 VCC[017] VCC[084] AD18 C16 VSS[021] VSS[102] W4
B20 VCC[018] VCC[085] AE9 C19 VSS[022] VSS[103] W23
C9 VCC[019] VCC[086] AE10 C2 VSS[023] VSS[104] W26
C10 VCC[020] VCC[087] AE12 C22 VSS[024] VSS[105] Y3
C12 VCC[021] VCC[088] AE13 C25 VSS[025] VSS[106] Y6
C13 VCC[022] VCC[089] AE15 D1 VSS[026] VSS[107] Y21
C15 VCC[023] VCC[090] AE17 D4 VSS[027] VSS[108] Y24
C17 VCC[024] VCC[091] AE18 D8 VSS[028] VSS[109] AA2
C18 VCC[025] VCC[092] AE20 D11 VSS[029] VSS[110] AA5
D9 VCC[026] VCC[093] AF9 D13 VSS[030] VSS[111] AA8
3 D10 AF10 D16 AA11 3
VCC[027] VCC[094] VSS[031] VSS[112]
D12 VCC[028] VCC[095] AF12 D19 VSS[032] VSS[113] AA14
D14 VCC[029] VCC[096] AF14 D23 VSS[033] VSS[114] AA16
D15 VCC[030] VCC[097] AF15 D26 VSS[034] VSS[115] AA19
D17 AF17 Layout Note E3 AA22
VCC[031] VCC[098] VSS[035] VSS[116]
D18 VCC[032] VCC[099] AF18 E6 VSS[036] VSS[117] AA25
E7 AF20 1D05V_S0 E8 AB1
VCC[033] VCC[100] VSS[037] VSS[118]
E9 VCC[034] E11 VSS[038] VSS[119] AB4
E10 V6 CPU_V6 1 R170 2 E14 AB8
VCC[035] VCCP[01] 0R0402-PAD VSS[039] VSS[120]
E12 VCC[036] VCCP[02] G21 E16 VSS[040] VSS[121] AB11
E13 VCC[037] VCCP[03] J6 E19 VSS[041] VSS[122] AB13
E15 VCC[038] VCCP[04] K6 E21 VSS[042] VSS[123] AB16
1

E17 VCC[039] VCCP[05] M6 E24 VSS[043] VSS[124] AB19


E18 J21 C245 F5 AB23
VCC[040] VCCP[06] VSS[044] VSS[125]
E20 K21 F8 AB26
2

VCC[041] VCCP[07] SCD1U10V2KX-4GP VSS[045] VSS[126]


F7 VCC[042] VCCP[08] M21 F11 VSS[046] VSS[127] AC3
F9 VCC[043] VCCP[09] N21 F13 VSS[047] VSS[128] AC6
F10 VCC[044] VCCP[10] N6 F16 VSS[048] VSS[129] AC8
F12 VCC[045] VCCP[11] R21 F19 VSS[049] VSS[130] AC11
F14 VCC[046] VCCP[12] R6 F2 VSS[050] VSS[131] AC14
F15 VCC[047] VCCP[13] T21 F22 VSS[051] VSS[132] AC16
F17 VCC[048] VCCP[14] T6 F25 VSS[052] VSS[133] AC19
F18 V21 1D5V_VCCA_S0 1D5V_S0 G4 AC21
VCC[049] VCCP[15] 1D05V_S0 VSS[053] VSS[134]
F20 VCC[050] VCCP[16] W21 L26 G1 VSS[054] VSS[135] AC24
AA7 VCC[051] G23 VSS[055] VSS[136] AD2
AA9 VCC[052] VCCA B26 1 2 G26 VSS[056] VSS[137] AD5
AA10 HCB1608KF121T30-GP H3 AD8
VCC[053] VSS[057] VSS[138]
1

AA12 H_VID[6..0] C553 68.00230.041 H6 AD11


VCC[054] H_VID[6..0] 37 VSS[058] VSS[139]
AA13 AD6 H_VID0 C554 H21 AD13
VCC[055] VID[0] VSS[059] VSS[140]

1
2 H_VID1 SCD01U16V2KX-3GP SC4D7U6D3V3KX-GP C188 C216 C231 C209 C217 C233 C237 C243 2
AA15 AF5 H24 AD16
2

VCC[056] VID[1] H_VID2 VCC_CORE_S0 VSS[060] VSS[141]


AA17 VCC[057] VID[2] AE5 J2 VSS[061] VSS[142] AD19

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
AA18 AF4 H_VID3 J5 AD22
2

2
VCC[058] VID[3] H_VID4 VSS[062] VSS[143]
AA20 VCC[059] VID[4] AE3 J22 VSS[063] VSS[144] AD25
1

AB9 AF2 H_VID5 J25 AE1


VCC[060] VID[5] H_VID6 R198 VSS[064] VSS[145]
AC10 VCC[061] VID[6] AE2 K1 VSS[065] VSS[146] AE4
AB10 100R2F-L1-GP-U K4 AE8
VCC[062] VSS[066] VSS[147]
AB12 VCC[063] K23 VSS[067] VSS[148] AE11
AB14 AF7 VCC_SENSE 37 K26 AE14
2

VCC[064] VCCSENSE VSS[068] VSS[149]


AB15 VCC[065] L3 VSS[069] VSS[150] AE16
AB17 VCC[066] L6 VSS[070] VSS[151] AE19
AB18 VCC[067] VSSSENSE AE7 VSS_SENSE 37 L21 VSS[071] VSS[152] AE23
VCC_CORE_S0 L24 AE26
VSS[072] VSS[153]
1

BGA479-SKT6-GPU1 Layout Note: M2 AF3


R199 VSS[073] VSS[154]
M5 VSS[074] VSS[155] AF6
100R2F-L1-GP-U VCCSENSE and VSSSENSE lines DY M22 AF8
VSS[075] VSS[156]
1

1
should be of equal length. C184 C246 C183 C255 C239 C267 C145 M25 AF11
VSS[076] VSS[157]
SCD1U10V2KX-4GP

N1 AF13
2

VSS[077] VSS[158]
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP
N4 AF16
2

2
Layout Note: VSS[078] VSS[159]
N23 VSS[079] VSS[160] AF19
Provide a test point (with N26 AF21
no stub) to connect a VSS[080] VSS[161]
P3 VSS[081] VSS[162] AF24
differential probe
between VCCSENSE and BGA479-SKT6-GPU1
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
VCC_CORE_S0

om
1 1

l.c
ai
DY DY DY DY
Wistron Corporation

tm
1

1
C192 C189 C146 C268 C266 C147 C585 C269 C559 C148 C190 C191 C242 C241 C240

ho
SC10U10V5ZY-1GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP
Taipei Hsien 221, Taiwan, R.O.C.

f@
2

in
Title

xa
CPU (2 of 2)

he
Size Document Number Rev

MYALL2 MP
Date: Thursday, March 30, 2006 Sheet 5 of 57
A B C D E
A B C D E

H_XRCOMP

1
R416
24D9R2F-L-GP
H_D#[63..0] U39A H_A#[31..3]
4 H_D#[63..0] H_A#[31..3] 4
H_D#0 F1 H9 H_A#3

2
H_D#1 H_D#_0 H_A#_3 H_A#4
J1 H_D#_1 H_A#_4 C9
4 H_D#2 H1 E11 H_A#5 4
H_D#3 H_D#_2 H_A#_5 H_A#6
J6 H_D#_3 H_A#_6 G11
H_D#4 H3 F11 H_A#7
H_D#5 H_D#_4 H_A#_7 H_A#8
K2 H_D#_5 H_A#_8 G12
1D05V_S0 H_D#6 G1 F9 H_A#9
H_D#7 H_D#_6 H_A#_9 H_A#10
G2 H_D#_7 H_A#_10 H11
H_D#8 K9 J12 H_A#11
H_D#9 H_D#_8 H_A#_11 H_A#12
K1 H_D#_9 H_A#_12 G14

2
H_D#10 K7 D9 H_A#13
R415 H_D#11 H_D#_10 H_A#_13 H_A#14
J8 H_D#_11 H_A#_14 J14
54D9R2F-L1-GP H_D#12 H4 H13 H_A#15
H_D#13 H_D#_12 H_A#_15 H_A#16
J3 H_D#_13 H_A#_16 J15
H_D#14 K11 F14 H_A#17
1
H_D#15 H_D#_14 H_A#_17 H_A#18
G4 H_D#_15 H_A#_18 D12
H_XSCOMP H_D#16 T10 A11 H_A#19
H_D#17 H_D#_16 H_A#_19 H_A#20
W11 H_D#_17 H_A#_20 C11
H_D#18 T3 A12 H_A#21
H_D#19 H_D#_18 H_A#_21 H_A#22
U7 H_D#_19 H_A#_22 A13
1D05V_S0 H_D#20 U9 E13 H_A#23
H_D#21 H_D#_20 H_A#_23 H_A#24
U11 H_D#_21 H_A#_24 G13
H_D#22 T11 F12 H_A#25
H_D#_22 H_A#_25
1

H_D#23 W9 B12 H_A#26


R180 H_D#24 H_D#_23 H_A#_26 H_A#27 1D05V_S0
T1 H_D#_24 H_A#_27 B14
221R2F-2-GP H_D#25 T8 C12 H_A#28
H_D#26 H_D#_25 H_A#_28 H_A#29
T4 H_D#_26 H_A#_29 A14

1
H_D#27 W7 C14 H_A#30
2

H_XSWING H_D#28 H_D#_27 H_A#_30 H_A#31 R196


U5 H_D#_28 H_A#_31 D14
H_D#29 T9 100R2F-L1-GP-U
H_D#_29
1

H_D#30 W6 E8 H_ADS# 4
H_D#_30 H_ADS#
2

3 R183 H_D#31 T5 B9 H_ADSTB#0 4


3

2
100R2F-L1-GP-U C249 H_D#32 H_D#_31 H_ADSTB#_0
AB7 H_D#_32 H_ADSTB#_1 C13 H_ADSTB#1 4
SCD1U16V2ZY-2GP H_D#33 AA9 J13 H_VREF
1

H_D#34 H_D#_33 H_VREF_0


W4 C6 H_BNR# 4
2

H_D#_34 H_BNR#

1
HOST
H_D#35 W3 F6 H_BPRI# 4
H_D#_35 H_BPRI#

2
H_D#36 Y3 C7 H_BREQ#0 4 R192
H_D#37 H_D#_36 H_BREQ#0 C262 200R2F-L-GP
Y7 H_D#_37 H_CPURST# B7 H_CPURST# 4
H_D#38 W5 A7 SCD1U16V2ZY-2GP
H_DBSY# 4

1
H_D#39 H_D#_38 H_DBSY#
Y10 C3 H_DEFER# 4

2
H_D#40 H_D#_39 H_DEFER#
AB8 H_D#_40 H_DPWR# J9 H_DPWR# 4
H_D#41 W2 H8 H_DRDY# 4
H_YRCOMP H_D#42 H_D#_41 H_DRDY#
AA4 H_D#_42 H_VREF_1 K13
H_D#43 AA7 H_DINV#[3..0]
H_D#_43 H_DINV#[3..0] 4
H_D#44 AA2 J7 H_DINV#0
H_D#_44 H_DINV#_0
1

H_D#45 AA6 W8 H_DINV#1


R442 H_D#46 H_D#_45 H_DINV#_1 H_DINV#2
AA10 H_D#_46 H_DINV#_2 U3
24D9R2F-L-GP H_D#47 Y8 AB10 H_DINV#3
H_D#48 H_D#_47 H_DINV#_3 H_DSTBN#[3..0]
AA1 H_D#_48 H_DSTBN#[3..0] 4
H_D#49 AB4 K4 H_DSTBN#0
2

H_D#50 H_D#_49 H_DSTBN#_0 H_DSTBN#1


AC9 H_D#_50 H_DSTBN#_1 T7
H_D#51 AB11 Y5 H_DSTBN#2
H_D#52 H_D#_51 H_DSTBN#_2 H_DSTBN#3
AC11 H_D#_52 H_DSTBN#_3 AC4
H_D#53 AB3 H_DSTBP#[3..0]
H_D#_53 H_DSTBP#[3..0] 4
H_D#54 AC2 K3 H_DSTBP#0
1D05V_S0 H_D#55 H_D#_54 H_DSTBP#_0 H_DSTBP#1
AD1 H_D#_55 H_DSTBP#_1 T6
H_D#56 AD9 AA5 H_DSTBP#2
H_D#57 H_D#_56 H_DSTBP#_2 H_DSTBP#3
AC1 H_D#_57 H_DSTBP#_3 AC5
H_D#58 AD7 H_D#_58
2

H_D#59 AC6
2 R430 H_D#60 H_D#_59 2
AB5 H_D#_60 H_HIT# D3 H_HIT# 4
54D9R2F-L1-GP H_D#61 AD10 D4 H_HITM# 4
H_D#62 H_D#_61 H_HITM#
AD4 H_D#_62 H_LOCK# B3 H_LOCK# 4
H_D#63 AC8
1

H_D#_63
H_YSCOMP H_XRCOMP E1 H_REQ#[4..0] 4
H_XSCOMP H_XRCOMP H_REQ#0
E2 H_XSCOMP H_REQ#_0 D8
H_XSWING E4 G8 H_REQ#1
H_XSWING H_REQ#_1 H_REQ#2
H_REQ#_2 B8
1D05V_S0 H_YRCOMP Y1 F8 H_REQ#3
H_YSCOMP H_YRCOMP H_REQ#_3 H_REQ#4
U1 H_YSCOMP H_REQ#_4 A8
H_YSWING W1 H_RS#[2..0] 4
H_YSWING
1

B4 H_RS#0
R431 H_RS#_0 H_RS#1
3 CLK_MCH_BCLK AG2 H_CLKIN H_RS#_1 E6
221R2F-2-GP AG1 D6 H_RS#2
3 CLK_MCH_BCLK# H_CLKIN# H_RS#_2
E3 H_CPUSLP# 4,15
2

H_YSWING H_SLPCPU#
H_TRDY# E7 H_TRDY# 4
1

CALISTOGA KI.94501.006
2

R440
100R2F-L1-GP-U C627
SCD1U16V2ZY-2GP
1
2

1 Place them near to the chip ( < 0.5") 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GMCH (1 of 5)
Size Document Number Rev

MYALL2 MP
Date: Thursday, March 30, 2006 Sheet 6 of 57
A B C D E
A B C D E

U39B
RSVD_0 H32
11 M_CLK_DDR0 AY35 SM_CK_0 RSVD_1 T32
11 M_CLK_DDR1 AR1 SM_CK_1 RSVD_2 R32
11 M_CLK_DDR2 AW7 SM_CK_2 RSVD_3 F3
11 M_CLK_DDR3 AW40 SM_CK_3 RSVD_4 F7 for calistoga configuration

RSVD
AG11 R419
RSVD_5 U39C 24D9R2F-L-GP
11 M_CLK_DDR#0 AW35 SM_CK#_0 RSVD_6 AF11
11 M_CLK_DDR#1 AT1 H7 TP36 TPAD30 D32 D40 2 1 1D5V_PCIE_S0
SM_CK#_1 RSVD_7 BL_ON L_BKLTCTL EXP_A_COMPI
11 M_CLK_DDR#2 AY7 SM_CK#_2 RSVD_8 J19 31 BL_ON J30 L_BKLTEN EXP_A_COMPO D38
AY40 K30 LCTLA_CLK H30 PEG_RXN[15..0]
11 M_CLK_DDR#3 SM_CK#_3 RSVD_9 L_CLKCTLA PEG_RXN[15..0] 46
J29 LCTLB_DATA H29 F34 PEG_RXN0
RSVD_10 CLK_DDC_EDID L_CLKCTLB EXP_A_RXN_0 PEG_RXN1
11,12 M_CKE0 AU20 SM_CKE_0 RSVD_11 A41 13 CLK_DDC_EDID G26 L_DDC_CLK EXP_A_RXN_1 G38
4 11,12 M_CKE1 AT20 A35 13 DAT_DDC_EDID DAT_DDC_EDID G25 H34 PEG_RXN2 4
SM_CKE_1 RSVD_12 TPAD30 TP30 LIBG L_DDC_DATA EXP_A_RXN_2 PEG_RXN3
11,12 M_CKE2 BA29 SM_CKE_2 RSVD_13 A34 B38 L_IBG EXP_A_RXN_3 J38
11,12 M_CKE3 AY29 D28 TPAD30 TP37 L_LVBG C35 L34 PEG_RXN4
SM_CKE_3 RSVD_14 GMCH_LCDVDD_ON L_VBG EXP_A_RXN_4 PEG_RXN5
RSVD_15 D27 13 GMCH_LCDVDD_ON F32 L_VDDEN EXP_A_RXN_5 M38
11,12 M_CS0# AW13 C33 N34 PEG_RXN6
SM_CS#_0 L_VREFH EXP_A_RXN_6 PEG_RXN7
11,12 M_CS1# AW12 SM_CS#_1 C32 L_VREFL EXP_A_RXN_7 P38
PEG_RXN8

MUXING
11,12 M_CS2# AY21 SM_CS#_2 CFG_0 K16 CPU_SEL0 3,4 EXP_A_RXN_8 R34
11,12 M_CS3# AW21 K18 CPU_SEL1 3,4 13 GMCH_TXACLK- A33 T38 PEG_RXN9
SM_CS#_3 CFG_1 LA_CLK# EXP_A_RXN_9 PEG_RXN10
CFG_2 J18 CPU_SEL2 3,4 13 GMCH_TXACLK+ A32 LA_CLK EXP_A_RXN_10 V34
M_OCDCOMP0 AL20 F18 CFG3 13 GMCH_TXBCLK- E27 W38 PEG_RXN11
M_OCDCOMP1 SM_OCDCOMP_0 CFG_3 CFG4 LB_CLK# EXP_A_RXN_11 PEG_RXN12
AF10 SM_OCDCOMP_1 CFG_4 E15 13 GMCH_TXBCLK+ E26 LB_CLK EXP_A_RXN_12 Y34
1

F15 CFG5 AA38 PEG_RXN13


CFG_5 EXP_A_RXN_13

LVDS
R214DY R209 DY 11,12 M_ODT0 BA13 E18 CFG6 13 GMCH_TXAOUT0- C37 AB34 PEG_RXN14
40D2R2F-GP 40D2R2F-GP 11,12 M_ODT1 SM_ODT_0 CFG_6 CFG7 LA_DATA#_0 EXP_A_RXN_14 PEG_RXN15
BA12 SM_ODT_1 CFG_7 D19 13 GMCH_TXAOUT1- B35 LA_DATA#_1 EXP_A_RXN_15 AC38
AY20 D16 CFG8 A37 PEG_RXP[15..0]
11,12 M_ODT2 SM_ODT_2 CFG_8 13 GMCH_TXAOUT2- LA_DATA#_2 PEG_RXP[15..0] 46

CFG
11,12 M_ODT3 AU21 G16 CFG9 D34 PEG_RXP0
2

SM_ODT_3 CFG_9 CFG10 EXP_A_RXP_0 PEG_RXP1


E16 F38

DDR
CFG_10 EXP_A_RXP_1

GRAPHICS
M_RCOMPN AV9 D15 CFG11 G34 PEG_RXP2
DDR_VREF_S3 M_RCOMPP SM_RCOMP# CFG_11 CFG12 EXP_A_RXP_2 PEG_RXP3
AT9 SM_RCOMP CFG_12 G15 13 GMCH_TXAOUT0+ B37 LA_DATA_0 EXP_A_RXP_3 H38
K15 CFG13 13 GMCH_TXAOUT1+ B34 J34 PEG_RXP4
CFG_13 CFG14 LA_DATA_1 EXP_A_RXP_4 PEG_RXP5
AK1 SM_VREF_0 CFG_14 C15 13 GMCH_TXAOUT2+ A36 LA_DATA_2 EXP_A_RXP_5 L38
C649 AK41 H16 CFG15 M34 PEG_RXP6
SM_VREF_1 CFG_15 EXP_A_RXP_6
1

C298 G18 CFG16 N38 PEG_RXP7


CFG_16 EXP_A_RXP_7
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

H15 CFG17 13 GMCH_TXBOUT0- G30 P34 PEG_RXP8


CFG_17 CFG18 LB_DATA#_0 EXP_A_RXP_8 PEG_RXP9
3 CLK_MCH_3GPLL# AF33 J25 13 GMCH_TXBOUT1- D30 R38
2

G_CLKIN# CFG_18 CFG19 LB_DATA#_1 EXP_A_RXP_9 PEG_RXP10


3 CLK_MCH_3GPLL AG33 G_CLKIN CFG_19 K27 13 GMCH_TXBOUT2- F29 LB_DATA#_2 EXP_A_RXP_10 T34
DREFCLK# A27 J26 CFG20 V38 PEG_RXP11
3 DREFCLK# D_REFCLKIN# CFG_20 EXP_A_RXP_11

CLK
DREFCLK A26 W34 PEG_RXP12
3 DREFCLK DREFSSCLK# D_REFCLKIN EXP_A_RXP_12 PEG_RXP13
3 DREFSSCLK# C40 D_REFSSCLKIN# PM_BMBUSY# G28 PM_BMBUSY# 16 EXP_A_RXP_13 Y38
3 DREFSSCLK D41 F25 PM_EXTTS#0 13 GMCH_TXBOUT0+ F30 AA34 PEG_RXP14 3
3 DREFSSCLK D_REFSSCLKIN PM_EXTTS#_0 LB_DATA_0 EXP_A_RXP_14

PM
PM_EXTTS#_1 H26 PM_EXTTS#1 R2130R2J-2-GP DY 13 GMCH_TXBOUT1+ D29 LB_DATA_1 EXP_A_RXP_15 AB38 PEG_RXP15

PCI-EXPRESS
G6 F28 PEG_TXN[15..0]
PM_THRMTRIP# PM_THRMTRIP-A# 4 13 GMCH_TXBOUT2+ LB_DATA_2 PEG_TXN[15..0] 46
DMI_TXN0 AE35 AH33 1 2 VGATE_PWRGD 16,37 F36 GTXN0 1 2 C248SCD1U10V2KX-5GP PEG_TXN0
16 DMI_TXN0 DMI_TXN1 DMI_RXN_0 PWROK R215 0R2J-2-GP EXP_A_TXN_0 GTXN1 C610SCD1U10V2KX-5GP PEG_TXN1
16 DMI_TXN1 AF39 DMI_RXN_1 RSTIN# AH34 1 2 EXP_A_TXN_1 G40 1 2
DMI_TXN2 AG35 R212 1 2 PWROK 16,19 H36 GTXN2 1 2 C254SCD1U10V2KX-5GP PEG_TXN2
16 DMI_TXN2 DMI_TXN3 DMI_RXN_2 100R2J-2-GP EXP_A_TXN_2 GTXN3 C615SCD1U10V2KX-5GP PEG_TXN3
16 DMI_TXN3 AH39 DMI_RXN_3 PLT_RST1# 16,18,22,26,31,32,34,46,51 EXP_A_TXN_3 J40 1 2
MISC SDVO_CTRLCLK H28
H27
TP45 TPAD30
TP44 TPAD30
14 TV_DACA TV_DACA
TV_DACB
A16
C18
TV_DACA_OUT EXP_A_TXN_4 L36
M40
GTXN4
GTXN5
1
1
2
2
C259SCD1U10V2KX-5GP
C618SCD1U10V2KX-5GP
PEG_TXN4
PEG_TXN5
SDVO_CTRLDATA 14 TV_DACB TV_DACB_OUT EXP_A_TXN_5
DMI_TXP0 AC35 K28 MCH_ICH_SYNC# 16 14 TV_DACC TV_DACC A19 N36 GTXN6 1 2 C263SCD1U10V2KX-5GP PEG_TXN6
16 DMI_TXP0 DMI_RXP_0 LT_RESET# TV_DACC_OUT EXP_A_TXN_6

TV
DMI_TXP1 AE39 P40 GTXN7 1 2 C620SCD1U10V2KX-5GP PEG_TXN7
16 DMI_TXP1 DMI_TXP2 DMI_RXP_1 R389 4K99R2F-L-GP TV_IREF EXP_A_TXN_7 GTXN8 C272SCD1U10V2KX-5GP PEG_TXN8
16 DMI_TXP2 AF35 DMI_RXP_2 UMA 1 2 J20 TV_IREF EXP_A_TXN_8 R36 1 2
DMI_TXP3 AG39 D1 R385 0R2J-2-GP UMA 1 2 TV_IRTNA B16 T40 GTXN9 1 2 C622SCD1U10V2KX-5GP PEG_TXN9
16 DMI_TXP3 DMI_RXP_3 NC0 R106 0R2J-2-GP TV_IRTNB TV_IRTNA EXP_A_TXN_9 GTXN10 C278SCD1U10V2KX-5GP PEG_TXN10
NC1 C41 UMA 1 2 B18 TV_IRTNB EXP_A_TXN_10 V36 1 2
C1 R108 0R2J-2-GP UMA 1 2 TV_IRTNC B19 W40 GTXN11 1 2 C628SCD1U10V2KX-5GP PEG_TXN11
DMI_RXN0 NC2 TV_IRTNC EXP_A_TXN_11 GTXN12 C281SCD1U10V2KX-5GP PEG_TXN12
16 DMI_RXN0 AE37 DMI_TXN_0 NC3 BA41 EXP_A_TXN_12 Y36 1 2
DMI_RXN1 AF41 BA40 AA40 GTXN13 1 2 C631SCD1U10V2KX-5GP PEG_TXN13
16 DMI_RXN1 DMI_TXN_1 NC4 EXP_A_TXN_13
NC

DMI_RXN2 AG37 BA39 AB36 GTXN14 1 2 C286SCD1U10V2KX-5GP PEG_TXN14


16 DMI_RXN2 DMI_RXN3 DMI_TXN_2 NC5 EXP_A_TXN_14 GTXN15 C638SCD1U10V2KX-5GP PEG_TXN15
16 DMI_RXN3 AH41 DMI_TXN_3 NC6 BA3 EXP_A_TXN_15 AC40 1 2
BA2 PEG_TXP[15..0]
PEG_TXP[15..0] 46
DMI

NC7 GMCH_BLUE GTXP0 C251SCD1U10V2KX-5GP PEG_TXP0


NC8 BA1 14 GMCH_BLUE E23 CRT_BLUE EXP_A_TXP_0 D36 1 2
DMI_RXP0 AC37 B41 3D3V_S0 GMCH_BLUE# D23 F40 GTXP1 1 2 C608SCD1U10V2KX-5GP PEG_TXP1
16 DMI_RXP0 DMI_RXP1 DMI_TXP_0 NC9 RN10 DY GMCH_GREEN CRT_BLUE# EXP_A_TXP_1 GTXP2 C253SCD1U10V2KX-5GP PEG_TXP2
16 DMI_RXP1 AE41 DMI_TXP_1 NC10 B2 14 GMCH_GREEN C22 CRT_GREEN EXP_A_TXP_2 G36 1 2

VGA
DMI_RXP2 AF37 AY41 SRN10KJ-5-GP GMCH_GREEN# B22 H40 GTXP3 1 2 C612SCD1U10V2KX-5GP PEG_TXP3
3D3V_S0 16 DMI_RXP2 DMI_RXP3 DMI_TXP_2 NC11 GMCH_RED CRT_GREEN# EXP_A_TXP_3 GTXP4 C257SCD1U10V2KX-5GP PEG_TXP4
16 DMI_RXP3 AG41 DMI_TXP_3 NC12 AY1 4 1 14 GMCH_RED A21 CRT_RED EXP_A_TXP_4 J36 1 2
AW41 3 2 GMCH_RED# B21 L40 GTXP5 1 2 C617SCD1U10V2KX-5GP PEG_TXP5
NC13 CRT_RED# EXP_A_TXP_5 GTXP6 C261SCD1U10V2KX-5GP PEG_TXP6
NC14 AW1 EXP_A_TXP_6 M36 1 2
A40 N40 GTXP7 1 2 C619SCD1U10V2KX-5GP PEG_TXP7
NC15 GMCH_DDCCLK EXP_A_TXP_7 GTXP8 C271SCD1U10V2KX-5GP PEG_TXP8
RN17 A4 14 GMCH_DDCCLK C26 P36 1 2
2 PM_EXTTS#0 NC16 GMCH_DDCDATA CRT_DDC_CLK EXP_A_TXP_8 GTXP9 C621SCD1U10V2KX-5GP PEG_TXP9 2
1 4 NC17 A39 14 GMCH_DDCDATA C25 CRT_DDC_DATA EXP_A_TXP_9 R40 1 2
2 3 PM_EXTTS#1 A3 GMCH_HS G23 T36 GTXP10 1 2 C275SCD1U10V2KX-5GP PEG_TXP10
NC18 CRT_IREF CRT_HSYNC EXP_A_TXP_10 GTXP11 C624SCD1U10V2KX-5GP PEG_TXP11
J22 CRT_IREF EXP_A_TXP_11 V40 1 2
SRN10KJ-5-GP CALISTOGA KI.94501.006 R107 UMA GMCH_VS H23 W36 GTXP12 1 2 C279SCD1U10V2KX-5GP PEG_TXP12
1D8V_S3 3D3V_S0 0R2J-2-GP CRT_VSYNC EXP_A_TXP_12 GTXP13 C630SCD1U10V2KX-5GP PEG_TXP13
EXP_A_TXP_13 Y40 1 2
1 2 R163DUMMY-R2 CFG18 14 GMCH_HSYNC 1 2 GMCH_HS EXP_A_TXP_14 AA36 GTXP14 1 2 C283SCD1U10V2KX-5GP PEG_TXP14
1

R109 UMA AB40 GTXP15 1 2 C635SCD1U10V2KX-5GP PEG_TXP15


R216 CFG19 EXP_A_TXP_15
1 2 R161DUMMY-R2 0R2J-2-GP
80D6R2F-L-GP 1 2 GMCH_VS CALISTOGA KI.94501.006
14 GMCH_VSYNC
1 2 R162DUMMY-R2 CFG20
M_RCOMPN RN58 G72 RN18 UMA
2

1 2 R157DUMMY-R2 CFG3 SRN0J-6-GP SRN100KJ-6-GP


R152 GMCH_BLUE 2 3
M_RCOMPP 1 2 R178DUMMY-R2 CFG4 0R2J-2-GP G72 GMCH_GREEN 1 4 1D05V_S0 BL_ON 2 3 RN9 UMA
1

GMCH_RED# 1 2 GMCH_LCDVDD_ON 1 4 SRN10KJ-5-GP


R217 1 2 R187DUMMY-R2 CFG5 R408 G72 LCTLA_CLK 3 2
80D6R2F-L-GP R148 UMA R151 0R2J-2-GP LCTLB_DATA 4 1 3D3V_S0
1 2 R158DUMMY-R2 CFG6 150R2F-1-GP 0R2J-2-GP G72 GMCH_RED 1 2 R181 UMA
GMCH_BLUE 1 2 GMCH_GREEN# 1 2 1D05V_S0 R195 G72 1K5R2F-2-GP RN16 UMA
2

1 2 R156DUMMY-R2 CFG7 0R2J-2-GP LIBG 1 2 SRN10KJ-5-GP


R154 UMA R149 CRT_IREF 1 2 CLK_DDC_EDID 3 2
1 2 R166DUMMY-R2 CFG8 150R2F-1-GP 0R2J-2-GP G72 RN11 G72 DAT_DDC_EDID 4 1
GMCH_GREEN 1 2 GMCH_BLUE# 1 2 R409 G72 SRN0J-6-GP
1 2 R179DUMMY-R2 CFG9 0R2J-2-GP GMCH_VS 2 3
When High 1K Ohm R153 UMA R147 TV_DACC 1 2 GMCH_HS 1 4
1 2 R168DUMMY-R2 CFG10 150R2F-1-GP 0R2J-2-GP UMA
GMCH_RED 1 2 GMCH_RED# 1 2 RN59 G72
1 2 R167DUMMY-R2 CFG11 SRN0J-6-GP
1 CFG6: R413 UMA R155 TV_DACA 1 4 1D5V_S0 1
1 2 R193DUMMY-R2 CFG12 150R2F-1-GP 0R2J-2-GP UMA TV_DACB 2 3
0=Moby Dick ,1=Calistoga (default) TV_DACA 1 2 GMCH_GREEN# 1 2
2 R203DUMMY-R2 CFG13 RN49 G72
1
R400 UMA R150 SRN0J-6-GP Wistron Corporation
1 2 R165DUMMY-R2 CFG14 150R2F-1-GP 0R2J-2-GP UMA TV_IREF 1 4 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
TV_DACB 1 2 GMCH_BLUE# 1 2 TV_IRTNA 2 3 Taipei Hsien 221, Taiwan, R.O.C.
When Low choice 1 2 R202DUMMY-R2 CFG15
lower than 3.5K R398 UMA R191 RN8 G72 Title
2 R159DUMMY-R2 CFG16 150R2F-1-GP 255R2F-L-GP UMA SRN0J-6-GP
Ohm 1
TV_DACC 1 2 CRT_IREF 1 2 TV_IRTNB 1 4 GMCH (2 of 5)
1 2 R197DUMMY-R2 CFG17 TV_IRTNC 2 3 Size Document Number Rev

MYALL2 MP
Date: Thursday, March 30, 2006 Sheet 7 of 57

om
A B C D E

l.c
ai
tm
ho
f@
in
xa
he
A B C D E

4 4

M_B_DQ[63..0] U39E
11 M_B_DQ[63..0]
M_B_DQ0 AK39
M_B_DQ1 SB_DQ0
AJ37 SB_DQ1 SB_BS_0 AT24 M_B_BS#0 11,12
M_A_DQ[63..0] U39D M_B_DQ2 AP39 AV23
11 M_A_DQ[63..0] SB_DQ2 SB_BS_1 M_B_BS#1 11,12
M_A_DQ0 AJ35 AU12 M_A_BS#0 11,12 M_B_DQ3 AR41 AY28 M_B_BS#2 11,12
M_A_DQ1 SA_DQ0 SA_BS_0 M_B_DQ4 SB_DQ3 SB_BS_2
AJ34 SA_DQ1 SA_BS_1 AV14 M_A_BS#1 11,12 AJ38 SB_DQ4 M_B_CAS# 11,12
M_A_DQ2 AM31 BA20 M_B_DQ5 AK38 AR24 M_B_DM[7..0]
SA_DQ2 SA_BS_2 M_A_BS#2 11,12 SB_DQ5 SB_CAS# M_B_DM[7..0] 11
M_A_DQ3 AM33 M_A_CAS# 11,12 M_B_DQ6 AN41 AK36 M_B_DM0
M_A_DQ4 SA_DQ3 M_A_DM[7..0] M_B_DQ7 SB_DQ6 SB_DM_0 M_B_DM1
AJ36 SA_DQ4 SA_CAS# AY13 M_A_DM[7..0] 11 AP41 SB_DQ7 SB_DM_1 AR38
M_A_DQ5 AK35 AJ33 M_A_DM0 M_B_DQ8 AT40 AT36 M_B_DM2
M_A_DQ6 SA_DQ5 SA_DM_0 M_A_DM1 M_B_DQ9 SB_DQ8 SB_DM_2 M_B_DM3
AJ32 SA_DQ6 SA_DM_1 AM35 AV41 SB_DQ9 SB_DM_3 BA31
M_A_DQ7 AH31 AL26 M_A_DM2 M_B_DQ10 AU38 AL17 M_B_DM4
M_A_DQ8 SA_DQ7 SA_DM_2 M_A_DM3 M_B_DQ11 SB_DQ10 SB_DM_4 M_B_DM5
AN35 SA_DQ8 SA_DM_3 AN22 AV38 SB_DQ11 SB_DM_5 AH8
M_A_DQ9 AP33 AM14 M_A_DM4 M_B_DQ12 AP38 BA5 M_B_DM6
M_A_DQ10 SA_DQ9 SA_DM_4 M_A_DM5 M_B_DQ13 SB_DQ12 SB_DM_6 M_B_DM7
AR31 SA_DQ10 SA_DM_5 AL9 AR40 SB_DQ13 SB_DM_7 AN4
M_A_DQ11 AP31 AR3 M_A_DM6 M_B_DQ14 AW38 M_B_DQS[7..0]
SA_DQ11 SA_DM_6 SB_DQ14 M_B_DQS[7..0] 11
M_A_DQ12 AN38 AH4 M_A_DM7 M_B_DQ15 AY38 AM39 M_B_DQS0

B
M_A_DQ13 SA_DQ12 SA_DM_7 M_A_DQS[7..0] M_B_DQ16 SB_DQ15 SB_DQS_0 M_B_DQS1
AM36 SA_DQ13 M_A_DQS[7..0] 11 BA38 SB_DQ16 SB_DQS_1 AT39
M_A_DQ14 AM34 AK33 M_A_DQS0 M_B_DQ17 AV36 AU35 M_B_DQS2

A
M_A_DQ15 SA_DQ14 SA_DQS_0 M_A_DQS1 M_B_DQ18 SB_DQ17 SB_DQS_2 M_B_DQS3
AN33 SA_DQ15 SA_DQS_1 AT33 AR36 SB_DQ18 SB_DQS_3 AR29
M_A_DQ16 AK26 AN28 M_A_DQS2 M_B_DQ19 AP36 AR16 M_B_DQS4
M_A_DQ17 SA_DQ16 SA_DQS_2 M_A_DQS3 M_B_DQ20 SB_DQ19 SB_DQS_4 M_B_DQS5
AL27 AM22 BA36 AR10

MEMORY
3 M_A_DQ18 SA_DQ17 SA_DQS_3 M_A_DQS4 M_B_DQ21 SB_DQ20 SB_DQS_5 M_B_DQS6 3
AM26 SA_DQ18 SA_DQS_4 AN12 AU36 SB_DQ21 SB_DQS_6 AR7
M_A_DQ19 AN24
MEMORY AN8 M_A_DQS5 M_B_DQ22 AP35 AN5 M_B_DQS7 M_B_DQS#[7..0]
SA_DQ19 SA_DQS_5 SB_DQ22 SB_DQS_7 M_B_DQS#[7..0] 11
M_A_DQ20 AK28 AP3 M_A_DQS6 M_B_DQ23 AP34 AM40 M_B_DQS#0
M_A_DQ21 SA_DQ20 SA_DQS_6 M_A_DQS7 M_A_DQS#[7..0] M_B_DQ24 SB_DQ23 SB_DQS#_0 M_B_DQS#1
AL28 SA_DQ21 SA_DQS_7 AG5 M_A_DQS#[7..0] 11 AY33 SB_DQ24 SB_DQS#_1 AU39
M_A_DQ22 AM24 AK32 M_A_DQS#0 M_B_DQ25 BA33 AT35 M_B_DQS#2
M_A_DQ23 SA_DQ22 SA_DQS#_0 M_A_DQS#1 M_B_DQ26 SB_DQ25 SB_DQS#_2 M_B_DQS#3
AP26 SA_DQ23 SA_DQS#_1 AU33 AT31 SB_DQ26 SB_DQS#_3 AP29
M_A_DQ24 AP23 AN27 M_A_DQS#2 M_B_DQ27 AU29 AP16 M_B_DQS#4
M_A_DQ25 SA_DQ24 SA_DQS#_2 M_A_DQS#3 M_B_DQ28 SB_DQ27 SB_DQS#_4 M_B_DQS#5
AL22 SA_DQ25 SA_DQS#_3 AM21 AU31 SB_DQ28 SB_DQS#_5 AT10
M_A_DQ26 AP21 AM12 M_A_DQS#4 M_B_DQ29 AW31 AT7 M_B_DQS#6
M_A_DQ27 SA_DQ26 SA_DQS#_4 M_A_DQS#5 M_B_DQ30 SB_DQ29 SB_DQS#_6 M_B_DQS#7
AN20 SA_DQ27 SA_DQS#_5 AL8 AV29 SB_DQ30 SB_DQS#_7 AP5
M_A_DQ28 AL23 AN3 M_A_DQS#6 M_B_DQ31 AW29 M_B_A[13..0]
SA_DQ28 SA_DQS#_6 SB_DQ31 M_B_A[13..0] 11,12
M_A_DQ29 AP24 AH5 M_A_DQS#7 M_B_DQ32 AM19 AY23 M_B_A0
M_A_DQ30 SA_DQ29 SA_DQS#_7 M_A_A[13..0] M_B_DQ33 SB_DQ32 SB_MA_0 M_B_A1

SYSTEM
AP20 SA_DQ30 M_A_A[13..0] 11,12 AL19 SB_DQ33 SB_MA_1 AW24
M_A_DQ31 AT21 AY16 M_A_A0 M_B_DQ34 AP14 AY24 M_B_A2
M_A_DQ32 SA_DQ31 SA_MA_0 M_A_A1 M_B_DQ35 SB_DQ34 SB_MA_2 M_B_A3
SYSTEM

AR12 SA_DQ32 SA_MA_1 AU14 AN14 SB_DQ35 SB_MA_3 AR28


M_A_DQ33 AR14 AW16 M_A_A2 M_B_DQ36 AN17 AT27 M_B_A4
M_A_DQ34 SA_DQ33 SA_MA_2 M_A_A3 M_B_DQ37 SB_DQ36 SB_MA_4 M_B_A5
AP13 SA_DQ34 SA_MA_3 BA16 AM16 SB_DQ37 SB_MA_5 AT28
M_A_DQ35 AP12 BA17 M_A_A4 M_B_DQ38 AP15 AU27 M_B_A6
M_A_DQ36 SA_DQ35 SA_MA_4 M_A_A5 M_B_DQ39 SB_DQ38 SB_MA_6 M_B_A7
AT13 SA_DQ36 SA_MA_5 AU16 AL15 SB_DQ39 SB_MA_7 AV28
M_A_DQ37 AT12 AV17 M_A_A6 M_B_DQ40 AJ11 AV27 M_B_A8
M_A_DQ38 SA_DQ37 SA_MA_6 M_A_A7 M_B_DQ41 SB_DQ40 SB_MA_8 M_B_A9
AL14 SA_DQ38 SA_MA_7 AU17 AH10 SB_DQ41 SB_MA_9 AW27
M_A_DQ39 AL12 AW17 M_A_A8 M_B_DQ42 AJ9 AV24 M_B_A10
M_A_DQ40 SA_DQ39 SA_MA_8 M_A_A9 M_B_DQ43 SB_DQ42 SB_MA_10 M_B_A11
AK9 SA_DQ40 SA_MA_9 AT16 AN10 SB_DQ43 SB_MA_11 BA27
M_A_DQ41 AN7 AU13 M_A_A10 M_B_DQ44 AK13 AY27 M_B_A12
M_A_DQ42 SA_DQ41 SA_MA_10 M_A_A11 M_B_DQ45 SB_DQ44 SB_MA_12 M_B_A13
AK8 SA_DQ42 SA_MA_11 AT17 AH11 SB_DQ45 SB_MA_13 AR23

DDR
M_A_DQ43 AK7 AV20 M_A_A12 M_B_DQ46 AK10
M_A_DQ44 SA_DQ43 SA_MA_12 M_A_A13 M_B_DQ47 SB_DQ46
AP9 SA_DQ44 SA_MA_13 AV12 AJ8 SB_DQ47 SB_RAS# AU23 M_B_RAS# 11,12
DDR

M_A_DQ45 AN9 M_B_DQ48 BA10 AK16 SB_RCVENIN# TP52 TPAD30


M_A_DQ46 SA_DQ45 M_B_DQ49 SB_DQ48 SB_RCVENIN# SB_RCVENOUT# TP51 TPAD30
AT5 SA_DQ46 SA_RAS# AW14 M_A_RAS# 11,12 AW10 SB_DQ49 SB_RCVENOUT# AK18
2 M_A_DQ47 SA_RCVENIN# TP54 TPAD30 M_B_DQ50 2
AL5 SA_DQ47 SA_RCVENIN# AK23 BA4 SB_DQ50 SB_WE# AR27 M_B_WE# 11,12
M_A_DQ48 AY2 AK24 SA_RCVENOUT# TP53 TPAD30 M_B_DQ51 AW4
M_A_DQ49 SA_DQ48 SA_RCVENOUT# M_B_DQ52 SB_DQ51
AW2 SA_DQ49 SA_WE# AY14 M_A_WE# 11,12 AY10 SB_DQ52
M_A_DQ50 AP1 M_B_DQ53 AY9 Place Test PAD Near to Chip
M_A_DQ51 SA_DQ50 M_B_DQ54 SB_DQ53
AN2 SA_DQ51 AW5 SB_DQ54 ascould as possible
M_A_DQ52 AV2 Place Test PAD Near to Chip M_B_DQ55 AY5
M_A_DQ53 SA_DQ52 M_B_DQ56 SB_DQ55
AT3 SA_DQ53 as could as possible AV4 SB_DQ56
M_A_DQ54 AN1 M_B_DQ57 AR5
M_A_DQ55 SA_DQ54 M_B_DQ58 SB_DQ57
AL2 SA_DQ55 AK4 SB_DQ58
M_A_DQ56 AG7 M_B_DQ59 AK3
M_A_DQ57 SA_DQ56 M_B_DQ60 SB_DQ59
AF9 SA_DQ57 AT4 SB_DQ60
M_A_DQ58 AG4 M_B_DQ61 AK5
M_A_DQ59 SA_DQ58 M_B_DQ62 SB_DQ61
AF6 SA_DQ59 AJ5 SB_DQ62
M_A_DQ60 AG9 M_B_DQ63 AJ3
M_A_DQ61 SA_DQ60 SB_DQ63
AH6 SA_DQ61
M_A_DQ62 AF4 CALISTOGA KI.94501.006
M_A_DQ63 SA_DQ62
AF8 SA_DQ63
CALISTOGA KI.94501.006

1 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GMCH (3 of 5)
Size Document Number Rev

MYALL2 MP
Date: Thursday, March 30, 2006 Sheet 8 of 57
A B C D E
A B C D E

2D5V_S0 2D5V_S0

1
1
VCC_TXLVD R402

1
C588 R414 0R3-0-U-GP
C591 0R3-0-U-GP UMA
SC4D7U6D3V3KX-GP SCD1U10V2KX-4GP R190G72 UMA

2
0R2J-2-GP

2
1 2 U39H
H22 1D05V_S0
VCCSYNC

1
C260 UMA AC14
2D5V_3GBG_S0 2D5V_S0 SCD1U10V2KX-4GP VTT_0
C30 VCC_TXLVDS0 VTT_1 AB14
R403G72 B30 W14

2
R410 0R0603-PAD VCC_TXLVDS1 VTT_2
4 1 0R3-0-U-GP
2 VCC_TXLVD A30 VCC_TXLVDS2 VTT_3 V14 4

1
2 1 1D5V_PCIE_S0 T14
R211 0R0805-PAD VTT_4 C280 C274 C288
1 AJ41 VCC3G0 VTT_5 R14
1 2 AB41 P14 SCD1U10V2KX-4GP SC2D2U6D3V3MX-1-GP SC4D7U10V5ZY-3GP
1D5V_S0

2
C592 C291 VCC3G1 VTT_6
Y41 VCC3G2 VTT_7 N14

1
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
C297 C294 C289

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
V41 M14
2

VCC3G3 VTT_8
R41 VCC3G4 VTT_9 L14
R208 N41 AD13

2
0R0603-PAD 1D5V_3GPLL_S0 VCC3G5 VTT_10
L41 VCC3G6 VTT_11 AC13
1D5V_S0 2 1 AC33 VCCA_3GPLL VTT_12 AB13
2D5V_3GBG_S0 G41 AA13
VCCA_3GBG VTT_13

1
C285 H41 Y13
VSSA_3GBG VTT_14
VTT_15 W13
SC4D7U6D3V3KX-GP C284 VCCA_CRTDAC F21 V13

2
VCCA_CRTDAC0 VTT_16
E21 VCCA_CRTDAC1 VTT_17 U13
SCD1U10V2KX-4GP G21 T13
VSSA_CRTDAC VTT_18
VTT_19 R13
1D5V_DPLLA B26 N13
1D5V_DPLLB VCCA_DPLLA VTT_20
C39 VCCA_DPLLB VTT_21 M13
R613 UMA 1D5V_HPLL_S0 AF1 L13
0R3-0-U-GP VCCA_HPLL VTT_22
VTT_23 AB12
2D5V_S0 1 2 A38 VCCA_LVDS VTT_24 AA12
R182 2 1 0R2J-2-GP UMA B39 Y12
VSSA_LVDS VTT_25

1
1D5V_S0 C595UMA W12
R401 G72 SCD1U10V2KX-4GP R138G72 1D5V_MPLL_S0 AF2 VTT_26
VCCA_MPLL VTT_27 V12
0R2J-2-GP 0R2J-2-GP U12
L29

2
VTT_28
UMA 2 1 1 2 V_TVBG H20 VCCA_TVBG VTT_29 T12
1 2 1D5V_DPLLA G20 R12
HCB1608KF121T30-GP 1D5V_S0 VSSA_TVBG VTT_30
VTT_31 P12
1

3 68.00230.041 RN14 G72 N12 3


C596 C597 SRN0J-6-GP VTT_32
VTT_33 M12
SC10U10V5ZY-1GP SCD1U10V2KX-4GP 1 4 V_DACA E19 L12
2

VCCA_TVDACA0 VTT_34
L30 2 3 F19 VCCA_TVDACA1 VTT_35 R11
UMA V_DACB C20 P11
1D5V_DPLLB VCCA_TVDACB0 VTT_36
1 2 D20 VCCA_TVDACB1 VTT_37 N11
HCB1608KF121T30-GP R1341 2 0R2J-2-GP G72 V_DACC E20 M11
VCCA_TVDACC0
POWER VTT_38
1

68.00230.041 F20 R10


C599 C598 1D5V_S0 VCCA_TVDACC1 VTT_39
VTT_40 P10
SC10U10V5ZY-1GP SCD1U10V2KX-4GP AH1 N10
2

R404 G72 VCCD_HMPLL0 VTT_41


L38 AH2 VCCD_HMPLL1 VTT_42 M10
0R3-0-U-GP P9
1D5V_HPLL_S0 VTT_43
1 2 2 1 A28 VCCD_LVDS0 VTT_44 N9
HCB1608KF121T30-GP 2 1 R405 0R3-0-U-GP UMA B28 M9
VCCD_LVDS1 VTT_45
1

68.00230.041 C28 R8
C644 C643 R177 0R0603-PAD VCCD_LVDS2 VTT_46
VTT_47 P8
1D5V_S0 2 1 1D5V_TVDAC_S0 D21 N8
2

VCCD_TVDAC VTT_48
L34 VTT_49 M8

1
C247 A23 P7
1D5V_MPLL_S0 SCD1U10V2KX-4GP VCC_HV0 VTT_50
1 2 B23 VCC_HV1 VTT_51 N7
HCB1608KF121T30-GP B25 M7

2
VCC_HV2 VTT_52
1

68.00230.041 SC10U10V5ZY-1GP SCD1U10V2KX-4GP R406 0R0603-PAD R6


C641 C639 VTT_53
3D3V_S0 2 1 H19 VCCD_QTVDAC VTT_54 P6
SC10U10V5ZY-1GP SCD1U10V2KX-4GP M6
2

VTT_55 VCCP_GMCH_CAP3
AK31 VCCAUX0 VTT_56 A6

1
C587 C593 AF31 R5
VCCAUX1 VTT_57 C600
AE31 VCCAUX2 VTT_58 P5
SC10U10V5ZY-1GP SCD1U10V2KX-4GP AC31 N5 SCD47U10V3ZY-GP
2

2
VCCAUX3 VTT_59
AL30 VCCAUX4 VTT_60 M5
2 2
AK30 VCCAUX5 VTT_61 P4
D9 UMA AJ30 N4
BAT54-4-GP R194 0R0603-PAD VCCAUX6 VTT_62
AH30 VCCAUX7 VTT_63 M4
1D5V_S0 1 1D5V_S0 2 1 1D5V_QTVDAC_S0 AG30 R3
VCCAUX8 VTT_64
AF30 VCCAUX9 VTT_65 P3
1

3 C256 AE30 N3
VCCAUX10 VTT_66
1

AD30 VCCAUX11 VTT_67 M3


2 R118 SCD1U10V2KX-4GP AC30 R2
2

10R2J-2-GP VCCAUX12 VTT_68


AG29 VCCAUX13 VTT_69 P2
UMA AF29 VCCAUX14 VTT_70 M2
AE29 D2 VCCP_GMCH_CAP2
2

L14 UMA 2D5V_CRTDAC R133 UMA VCCA_CRTDAC R132 G72 VCCAUX15 VTT_71 VCCP_GMCH_CAP1
AD29 VCCAUX16 VTT_72 AB1

1
HCB1608KF121T30-GP 0R5J-6-GP 0R3-0-U-GP AC29 R1
VCCAUX17 VTT_73 C634 C250
2D5V_S0 1 2 2 1 1 2 1D5V_S0 AG28 VCCAUX18 VTT_74 P1
68.00230.041 AF28 N1 SCD47U10V3ZY-GP SCD22U16V3ZY-GP

2
VCCAUX19 VTT_75
1

C252 AE28 M1
VCCAUX20 VTT_76
AH22 VCCAUX21
SCD1U10V2KX-4GP AJ21
2

VCCAUX22
AH21 VCCAUX23
AJ20 VCCAUX24
D10 UMA R130 UMA AH20
BAT54-4-GP 0R3-0-U-GP VCCAUX25
AH19 VCCAUX26
1D5V_S0 1 2 1 V_DACA P19
1D5V_S0 VCCAUX27
P16 VCCAUX28
3 3D3V_TVDAC R131 UMA AH15 VCCAUX29
1

0R3-0-U-GP P15
R119 V_DACB VCCAUX30
2 2 1 AH14 VCCAUX31
10R2J-2-GP AG14 VCCAUX32
1

1
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C228 C227 C290 C293 C296 C292

om
1 UMA AF14 VCCAUX33 1
AE14
2

l.c
L12 UMA R129 UMA SCD1U10V2KX-4GP SCD1U10V2KX-4GP VCCAUX34
Y14
2

VCCAUX35

ai
HCB1608KF121T30-GP 0R3-0-U-GP AF13
Wistron Corporation

tm
V_DACC VCCAUX36
3D3V_S0 1 2 2 1 AE13 VCCAUX37

ho
68.00230.041 AF12 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
R128 0R3-0-U-GP UMA VCCAUX38 Taipei Hsien 221, Taiwan, R.O.C.

f@
AE12 VCCAUX39
1

2 1 V_TVBG C226 AD12

in
VCCAUX40
1

C214 Title

xa
1

C229 SCD1U10V2KX-4GP
GMCH (4 of 5)
2

he
SC10U10V5ZY-1GP CALISTOGA KI.94501.006
2

Divide by Trace (Layout Rule approve) UMA SCD1U10V2KX-4GP Size Document Number Rev
2

MYALL2 MP
Date: Friday, March 24, 2006 Sheet 9 of 57
A B C D E
A B C D E
U39G
1D05V_S0 AA33 U39I
VCC_0 1D05V_S0
W33 VCC_1 AC41 VSS_0 VSS_97 AK34
P33 VCC_2 AA41 VSS_1 VSS_98 AG34
N33 U39F W41 AF34
VCC_3 VSS_2 VSS_99 U39J
L33 VCC_4 VCC_SM_0 AU41 AD27
VCC_NCTF0 T41 VSS_3 VSS_100 AE34
J33 VCC_5 VCC_SM_1 AT41 AC27
VCC_NCTF1 VSS_NCTF0 AE27 P41 VSS_4 VSS_101 AC34 AT23 VSS_180 VSS_273 J11
AA32 VCC_6 VCC_SM_2 AM41 AB27
VCC_NCTF2 VSS_NCTF1 AE26 M41 VSS_5 VSS_102 C34 AN23 VSS_181 VSS_274 D11
Y32 VCC_7 VCC_SM_3 AU40 AA27
VCC_NCTF3 VSS_NCTF2 AE25 J41 VSS_6 VSS_103 AW33 AM23 VSS_182 VSS_275 B11
W32 VCC_8 VCC_SM_4 BA34 Y27
VCC_NCTF4 VSS_NCTF3 AE24 F41 VSS_7 VSS_104 AV33 AH23 VSS_183 VSS_276 AV10
V32 VCC_9 VCC_SM_5 AY34 W27
VCC_NCTF5 VSS_NCTF4 AE23 AV40 VSS_8 VSS_105 AR33 AC23 VSS_184 VSS_277 AP10
P32 VCC_10 VCC_SM_6 AW34 V27
VCC_NCTF6 VSS_NCTF5 AE22 AP40 VSS_9 VSS_106 AE33 W23 VSS_185 VSS_278 AL10
N32 VCC_11 VCC_SM_7 AV34 U27
VCC_NCTF7 VSS_NCTF6 AE21 AN40 VSS_10 VSS_107 AB33 K23 VSS_186 VSS_279 AJ10
M32 VCC_12 VCC_SM_8 AU34 T27
VCC_NCTF8 VSS_NCTF7 AE20 AK40 VSS_11 VSS_108 Y33 J23 VSS_187 VSS_280 AG10
4 L32 VCC_13 VCC_SM_9 AT34 R27
VCC_NCTF9 VSS_NCTF8 AE19 AJ40 VSS_12 VSS_109 V33 F23 VSS_188 VSS_281 AC10 4
J32 VCC_14 VCC_SM_10 AR34 AD26
VCC_NCTF10 VSS_NCTF9 AE18 AH40 VSS_13 VSS_110 T33 C23 VSS_189 VSS_282 W10
AA31 VCC_15 VCC_SM_11 BA30 AC26
VCC_NCTF11 VSS_NCTF10 AC17 AG40 VSS_14 VSS_111 R33 AA22 VSS_190 VSS_283 U10
W31 VCC_16 VCC_SM_12 AY30 AB26
VCC_NCTF12 VSS_NCTF11 Y17 AF40 VSS_15 VSS_112 M33 K22 VSS_191 VSS_284 BA9
V31 VCC_17 VCC_SM_13 AW30 AA26
VCC_NCTF13 VSS_NCTF12 U17 AE40 VSS_16 VSS_113 H33 G22 VSS_192 VSS_285 AW9
T31 VCC_18 VCC_SM_14 AV30 Y26
VCC_NCTF14 B40 VSS_17 VSS_114 G33 F22 VSS_193 VSS_286 AR9
R31 VCC_19 VCC_SM_15 AU30 W26
VCC_NCTF15 AY39 VSS_18 VSS_115 F33 E22 VSS_194 VSS_287 AH9
P31 VCC_20 VCC_SM_16 AT30 V26
VCC_NCTF16 AW39 VSS_19 VSS_116 D33 D22 VSS_195 VSS_288 AB9
N31 VCC_21 VCC_SM_17 AR30 U26
VCC_NCTF17 AV39 VSS_20 VSS_117 B33 A22 VSS_196 VSS_289 Y9
M31 VCC_22 VCC_SM_18 AP30 T26
VCC_NCTF18 AR39 VSS_21 VSS_118 AH32 BA21 VSS_197 VSS_290 R9
AA30 VCC_23 VCC_SM_19 AN30 R26
VCC_NCTF19 VCCAUX_NCTF0 AG27 AN39 VSS_22 VSS_119 AG32 AV21 VSS_198 VSS_291 G9
Y30 VCC_24 VCC_SM_20 AM30 AD25
VCC_NCTF20 VCCAUX_NCTF1 AF27 1D5V_S0 AJ39 VSS_23 VSS_120 AF32 AR21 VSS_199 VSS_292 E9
W30 VCC_25 VCC_SM_21 AM29 AC25
VCC_NCTF21 VCCAUX_NCTF2 AG26 AC39 VSS_24 VSS_121 AE32 AN21 VSS_200 VSS_293 A9
V30 VCC_26 VCC_SM_22 AL29 AB25
VCC_NCTF22 VCCAUX_NCTF3 AF26 AB39 VSS_25 VSS_122 AC32 AL21 VSS_201 VSS_294 AG8
U30 VCC_27 VCC_SM_23 AK29 AA25
VCC_NCTF23 VCCAUX_NCTF4 AG25 AA39 VSS_26 VSS_123 AB32 AB21 VSS_202 VSS_295 AD8
T30 VCC_28 VCC_SM_24 AJ29 Y25
VCC_NCTF24 VCCAUX_NCTF5 AF25 Y39 VSS_27 VSS_124 G32 Y21 VSS_203 VSS_296 AA8
R30 VCC_29 VCC_SM_25 AH29 W25
VCC_NCTF25 VCCAUX_NCTF6 AG24 W39 VSS_28 VSS_125 B32 P21 VSS_204 VSS_297 U8
P30 VCC_30 VCC_SM_26 AJ28 V25
VCC_NCTF26 VCCAUX_NCTF7 AF24 V39 VSS_29 VSS_126 AY31 K21 VSS_205 VSS_298 K8
N30 VCC_31 VCC_SM_27 AH28 U25
VCC_NCTF27 VCCAUX_NCTF8 AG23 T39 VSS_30 VSS_127 AV31 J21 VSS_206 VSS_299 C8
M30 VCC_32 VCC_SM_28 AJ27 T25
VCC_NCTF28 VCCAUX_NCTF9 AF23 R39 VSS_31 VSS_128 AN31 H21 VSS_207 VSS_300 BA7
L30 VCC_33 VCC_SM_29 AH27 R25
VCC_NCTF29 VCCAUX_NCTF10 AG22 P39 VSS_32 VSS_129 AJ31 C21 VSS_208 VSS_301 AV7
AA29 BA26 AD24 VCCAUX_NCTF11 AF22 N39 AG31 AW20 AP7
Y29
W29
VCC_34
VCC_35
VCC_36
VCC_SM_30
VCC_SM_31
VCC_SM_32
AY26
AW26
VCC_NCTF30
AC24
VCC_NCTF31
AB24
VCC_NCTF32
VCCAUX_NCTF12 AG21
VCCAUX_NCTF13 AF21
M39
L39
VSS_33
VSS_34
VSS_35
VSS VSS_130
VSS_131
VSS_132
AB31
Y31
AR20
AM20
VSS_209
VSS_210
VSS_211 VSS
VSS_302
VSS_303
VSS_304
AL7
AJ7
V29 VCC_37 VCC_SM_33 AV26 AA24
VCC_NCTF33 VCCAUX_NCTF14 AG20 J39 VSS_36 VSS_133 AB30 AA20 VSS_212 VSS_305 AH7
U29 VCC_38 VCC_SM_34 AU26 Y24
VCC_NCTF34 VCCAUX_NCTF15 AF20 H39 VSS_37 VSS_134 E30 K20 VSS_213 VSS_306 AF7
R29 VCC_39 VCC_SM_35 AT26 W24
VCC_NCTF35 VCCAUX_NCTF16 AG19 G39 VSS_38 VSS_135 AT29 B20 VSS_214 VSS_307 AC7
P29 VCC_40 VCC_SM_36 AR26 V24
VCC_NCTF36 VCCAUX_NCTF17 AF19 F39 VSS_39 VSS_136 AN29 A20 VSS_215 VSS_308 R7
M29 VCC_41 VCC_SM_37 AJ26 U24
VCC_NCTF37 VCCAUX_NCTF18 R19 D39 VSS_40 VSS_137 AB29 AN19 VSS_216 VSS_309 G7
3 L29 AH26 T24 3
VCC_42 VCC_SM_38 VCC_NCTF38 VCCAUX_NCTF19 AG18 AT38 VSS_41 VSS_138 T29 AC19 VSS_217 VSS_310 D7
AB28 VCC_43 VCC_SM_39 AJ25 R24
VCC_NCTF39 VCCAUX_NCTF20 AF18 AM38 VSS_42 VSS_139 N29 W19 VSS_218 VSS_311 AG6
AA28 VCC_44 VCC_SM_40 AH25 AD23
VCC_NCTF40 VCCAUX_NCTF21 R18 AH38 VSS_43 VSS_140 K29 K19 VSS_219 VSS_312 AD6
Y28 VCC_45 VCC_SM_41 AJ24 V23
VCC_NCTF41 VCCAUX_NCTF22 AG17 AG38 VSS_44 VSS_141 G29 G19 VSS_220 VSS_313 AB6
V28 VCC_46 VCC_SM_42 AH24 U23
VCC_NCTF42 VCCAUX_NCTF23 AF17 AF38 VSS_45 VSS_142 E29 C19 VSS_221 VSS_314 Y6
U28 VCC_47 VCC_SM_43 BA23 T23
VCC_NCTF43 VCCAUX_NCTF24 AE17 AE38 VSS_46 VSS_143 C29 AH18 VSS_222 VSS_315 U6
T28 VCC_48 VCC_SM_44 AJ23 R23
VCC_NCTF44 VCCAUX_NCTF25 AD17 C38 VSS_47 VSS_144 B29 P18 VSS_223 VSS_316 N6
R28 VCC_49 VCC_SM_45 BA22 AD22
VCC_NCTF45 VCCAUX_NCTF26 AB17 AK37 VSS_48 VSS_145 A29 H18 VSS_224 VSS_317 K6
P28 VCC_50 VCC_SM_46 AY22 V22
VCC_NCTF46 VCCAUX_NCTF27 AA17 AH37 VSS_49 VSS_146 BA28 D18 VSS_225 VSS_318 H6
N28 VCC_51 VCC_SM_47 AW22 U22
VCC_NCTF47 VCCAUX_NCTF28 W17 AB37 VSS_50 VSS_147 AW28 A18 VSS_226 VSS_319 B6
M28 VCC_52 VCC_SM_48 AV22 T22
VCC_NCTF48 VCCAUX_NCTF29 V17 AA37 VSS_51 VSS_148 AU28 AY17 VSS_227 VSS_320 AV5
L28 VCC_53 VCC_SM_49 AU22 R22
VCC_NCTF49 VCCAUX_NCTF30 T17 Y37 VSS_52 VSS_149 AP28 AR17 VSS_228 VSS_321 AF5
P27 AT22 AD21 R17 W37 AM28 AP17 AD5
N27
M27
VCC_54
VCC_55
VCC_56
VCC_SM_50
VCC_SM_51
VCC_SM_52
AR22
AP22
VCC_NCTF50
V21
VCC_NCTF51
U21
VCC_NCTF52
VCCAUX_NCTF31
VCCAUX_NCTF32 AG16
VCCAUX_NCTF33 AF16
NCTF V37
T37
VSS_53
VSS_54
VSS_55
VSS_150
VSS_151
VSS_152
AD28
AC28
AM17
AK17
VSS_229
VSS_230
VSS_231
VSS_322
VSS_323
VSS_324
AY4
AR4
L27 VCC_57 VCC_SM_53 AK22 T21
VCC_NCTF53 VCCAUX_NCTF34 AE16 R37 VSS_56 VSS_153 W28 AV16 VSS_232 VSS_325 AP4
P26 VCC_58 VCC_SM_54 AJ22 R21
VCC_NCTF54 VCCAUX_NCTF35 AD16 P37 VSS_57 VSS_154 J28 AN16 VSS_233 VSS_326 AL4
N26 VCC_59 VCC_SM_55 AK21 AD20
VCC_NCTF55 VCCAUX_NCTF36 AC16 N37 VSS_58 VSS_155 E28 AL16 VSS_234 VSS_327 AJ4
L26 VCC_60 VCC_SM_56 AK20 V20
VCC_NCTF56 VCCAUX_NCTF37 AB16 M37 VSS_59 VSS_156 AP27 J16 VSS_235 VSS_328 Y4
N25 VCC_61 VCC_SM_57 BA19 U20
VCC_NCTF57 VCCAUX_NCTF38 AA16 L37 VSS_60 VSS_157 AM27 F16 VSS_236 VSS_329 U4
M25 VCC_62 VCC_SM_58 AY19 T20
VCC_NCTF58 VCCAUX_NCTF39 Y16 J37 VSS_61 VSS_158 AK27 C16 VSS_237 VSS_330 R4
L25 VCC_63 VCC_SM_59 AW19 R20
VCC_NCTF59 VCCAUX_NCTF40 W16 H37 VSS_62 VSS_159 J27 AN15 VSS_238 VSS_331 J4
P24 VCC_64 VCC_SM_60 AV19 AD19
VCC_NCTF60 VCCAUX_NCTF41 V16 G37 VSS_63 VSS_160 G27 AM15 VSS_239 VSS_332 F4
N24 VCC_65 VCC_SM_61 AU19 V19
VCC_NCTF61 VCCAUX_NCTF42 U16 F37 VSS_64 VSS_161 F27 AK15 VSS_240 VSS_333 C4
M24 VCC_66 VCC_SM_62 AT19 U19
VCC_NCTF62 VCCAUX_NCTF43 T16 D37 VSS_65 VSS_162 C27 N15 VSS_241 VSS_334 AY3
AB23 VCC_67 VCC_SM_63 AR19 T19
VCC_NCTF63 VCCAUX_NCTF44 R16 AY36 VSS_66 VSS_163 B27 M15 VSS_242 VSS_335 AW3
AA23 AP19 AD18 VCCAUX_NCTF45 AG15 AW36 AN26 L15 AV3

2
Y23
P23
VCC_68
VCC_69
VCC_70
VCC VCC_SM_64
VCC_SM_65
VCC_SM_66
AK19
AJ19
VCC_NCTF64
AC18
VCC_NCTF65
AB18
VCC_NCTF66
VCCAUX_NCTF46 AF15
VCCAUX_NCTF47 AE15
AN36
AH36
VSS_67
VSS_68
VSS_69
VSS_164
VSS_165
VSS_166
M26
K26
B15
A15
VSS_243
VSS_244
VSS_245
VSS_336
VSS_337
VSS_338
AL3
AH3
2
N23 VCC_71 VCC_SM_67 AJ18 AA18
VCC_NCTF67 VCCAUX_NCTF48 AD15 AG36 VSS_70 VSS_167 F26 BA14 VSS_246 VSS_339 AG3
M23 VCC_72 VCC_SM_68 AJ17 Y18
VCC_NCTF68 VCCAUX_NCTF49 AC15 AF36 VSS_71 VSS_168 D26 AT14 VSS_247 VSS_340 AF3
L23 VCC_73 VCC_SM_69 AH17 W18
VCC_NCTF69 VCCAUX_NCTF50 AB15 AE36 VSS_72 VSS_169 AK25 AK14 VSS_248 VSS_341 AD3
AC22 VCC_74 VCC_SM_70 AJ16 V18
VCC_NCTF70 VCCAUX_NCTF51 AA15 AC36 VSS_73 VSS_170 P25 AD14 VSS_249 VSS_342 AC3
AB22 VCC_75 VCC_SM_71 AH16 U18
VCC_NCTF71 VCCAUX_NCTF52 Y15 C36 VSS_74 VSS_171 K25 AA14 VSS_250 VSS_343 AA3
Y22 VCC_76 VCC_SM_72 BA15 T18
VCC_NCTF72 VCCAUX_NCTF53 W15 B36 VSS_75 VSS_172 H25 U14 VSS_251 VSS_344 G3
W22 VCC_77 VCC_SM_73 AY15 VCCAUX_NCTF54 V15 BA35 VSS_76 VSS_173 E25 K14 VSS_252 VSS_345 AT2
P22 VCC_78 VCC_SM_74 AW15 VCCAUX_NCTF55 U15 AV35 VSS_77 VSS_174 D25 H14 VSS_253 VSS_346 AR2
N22 VCC_79 VCC_SM_75 AV15 VCCAUX_NCTF56 T15 AR35 VSS_78 VSS_175 A25 E14 VSS_254 VSS_347 AP2
M22 VCC_80 VCC_SM_76 AU15 VCCAUX_NCTF57 R15 AH35 VSS_79 VSS_176 BA24 AV13 VSS_255 VSS_348 AK2
L22 VCC_81 VCC_SM_77 AT15 AB35 VSS_80 VSS_177 AU24 AR13 VSS_256 VSS_349 AJ2
AC21 AR15 CALISTOGA KI.94501.006 AA35 AL24 AN13 AD2
VCC_82 VCC_SM_78 VSS_81 VSS_178 VSS_257 VSS_350
AA21 VCC_83 VCC_SM_79 AJ15 Y35 VSS_82 VSS_179 AW23 AM13 VSS_258 VSS_351 AB2
W21 VCC_84 VCC_SM_80 AJ14 W35 VSS_83 AL13 VSS_259 VSS_352 Y2
N21 VCC_85 VCC_SM_81 AJ13 V35 VSS_84 AG13 VSS_260 VSS_353 U2
M21 VCC_86 VCC_SM_82 AH13 T35 VSS_85 P13 VSS_261 VSS_354 T2
L21 VCC_87 VCC_SM_83 AK12 R35 VSS_86 F13 VSS_262 VSS_355 N2
AC20 VCC_88 VCC_SM_84 AJ12 P35 VSS_87 D13 VSS_263 VSS_356 J2
1

AB20 VCC_89 VCC_SM_85 AH12 N35 VSS_88 B13 VSS_264 VSS_357 H2


Y20 AG12 C273 C276 C265 C287 C264 C270 C282 TC13 M35 AY12 F2
VCC_90 VCC_SM_86 SC10U10V5ZY-1GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP ST220U2VBM-3GP VSS_89 VSS_265 VSS_358
W20 AK11 L35 AC12 C2
2

VCC_91 VCC_SM_87 SC10U10V5ZY-1GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP VSS_90 VSS_266 VSS_359


P20 VCC_92 VCC_SM_88 BA8 J35 VSS_91 K12 VSS_267 VSS_360 AL1
N20 VCC_93 VCC_SM_89 AY8 H35 VSS_92 H12 VSS_268
M20 VCC_94 VCC_SM_90 AW8 Place these Caps close VCC_0 ~ VCC_110 G35 VSS_93 E12 VSS_269
L20 VCC_95 VCC_SM_91 AV8 F35 VSS_94 AD11 VSS_270
AB19 VCC_96 VCC_SM_92 AT8 D35 VSS_95 AA11 VSS_271
AA19 VCC_97 VCC_SM_93 AR8 AN34 VSS_96 Y11 VSS_272
Y19 AP8 1D8V_S3
VCC_98 VCC_SM_94 CALISTOGA KI.94501.006
1 N19 VCC_99 VCC_SM_95 BA6 1
M19 AY6 CALISTOGA KI.94501.006
VCC_100 VCC_SM_96
L19 VCC_101 VCC_SM_97 AW6
ST220U2VBM-3GP

Wistron Corporation
SC10U10V5ZY-1GP

N18 VCC_102 VCC_SM_98 AV6


1

1
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

M18 AT6 C680 C299 C679 C302 C303 C301 C304 C677 C295
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
VCC_103 VCC_SM_99
1

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


SCD1U10V2KX-4GP

L18 AR6 TC5 DY C678


VCC_104 VCC_SM_100 Taipei Hsien 221, Taiwan, R.O.C.
P17 AP6 DY
2

2
VCC_105 VCC_SM_101
N17 AN6
2

VCC_106 VCC_SM_102 Title


M17 VCC_107 VCC_SM_103 AL6
N16
M16
VCC_108
VCC_109
VCC_SM_104
VCC_SM_105
AK6
AJ6 GMCH (5 of 5)
L16 AV1 CALISTOGA Size Document Number Rev
VCC_110 VCC_SM_106 KI.94501.006
VCC_SM_107 AJ1
MYALL2 MP
Date: Friday, March 24, 2006 Sheet 10 of 57
A B C D E
A B C D E

DM2 DM1
8,12 M_A_A[13..0]
M_A_A0 102 108 M_A_RAS# 8,12
8,12 M_B_A[13..0] A0 /RAS
M_B_A0 102 108 M_B_RAS# 8,12 M_A_A1 101 109 M_A_WE# 8,12
M_B_A1 A0 RAS# M_A_A2 A1 /WE
101 A1 WE# 109 M_B_WE# 8,12 100 A2 /CAS 113 M_A_CAS# 8,12
M_B_A2 100 113 M_B_CAS# 8,12 M_A_A3 99
M_B_A3 A2 CAS# M_A_A4 A3
99 A3 98 A4 /CS0 110 M_CS0# 7,12
M_B_A4 98 110 M_CS2# 7,12 M_A_A5 97 115 M_CS1# 7,12
M_B_A5 A4 CS0# M_A_A6 A5 /CS1
97 A5 CS1# 115 M_CS3# 7,12 94 A6
M_B_A6 94 M_A_A7 92 79 M_CKE0 7,12
M_B_A7 A6 M_A_A8 A7 CKE0
92 A7 CKE0 79 M_CKE2 7,12 93 A8 CKE1 80 M_CKE1 7,12
M_B_A8 93 80 M_CKE3 7,12 M_A_A9 91
M_B_A9 A8 CKE1 M_A_A10 A9
91 A9 105 A10/AP CK0 30 M_CLK_DDR0 7
4 M_B_A10 105 30 M_CLK_DDR3 7 M_A_A11 90 32 M_CLK_DDR#0 7 4
M_B_A11 A10/AP CK0 M_A_A12 A11 /CK0
90 A11 CK0# 32 M_CLK_DDR#3 7 89 A12
M_B_A12 89 M_A_A13 116 164 M_CLK_DDR1 7
M_B_A13 A12 A13 CK1
116 A13 CK1 164 M_CLK_DDR2 7 86 A14 /CK1 166 M_CLK_DDR#1 7
86 A14 CK1# 166 M_CLK_DDR#2 7 84 A15 M_A_DM[7..0] 8
84 8,12 M_A_BS#2 85 10 M_A_DM0
A15 M_B_DM[7..0] 8 A16/BA2 DM0
8,12 M_B_BS#2 85 10 M_B_DM0 26 M_A_DM1
A16/BA2 DM0 M_B_DM1 DM1 M_A_DM2
DM1 26 8,12 M_A_BS#0 107 BA0 DM2 52
8,12 M_B_BS#0 107 52 M_B_DM2 8,12 M_A_BS#1 106 67 M_A_DM3
BA0 DM2 M_B_DM3 BA1 DM3 M_A_DM4
8,12 M_B_BS#1 106 BA1 DM3 67 DM4 130
130 M_B_DM4 M_A_DQ0 5 147 M_A_DM5
DM4 M_B_DM5 M_A_DQ1 DQ0 DM5 M_A_DM6
DM5 147 8 M_A_DQ[63..0] 7 DQ1 DM6 170
M_B_DQ0 5 170 M_B_DM6 M_A_DQ2 17 185 M_A_DM7
M_B_DQ1 DQ0 DM6 M_B_DM7 M_A_DQ3 DQ2 DM7
8 M_B_DQ[63..0] 7 DQ1 DM7 185 19 DQ3
M_B_DQ2 17 SRN33J-5-GP-U M_A_DQ4 4 195 SMBD_ICH_1
M_B_DQ3 DQ2 RN20 M_A_DQ5 DQ4 SDA SMBC_ICH_1
19 DQ3 6 DQ5 SCL 197
M_B_DQ4 4 195 SMBD_ICH_1 1 4 SMBD_ICH 3,18 M_A_DQ6 14
M_B_DQ5 DQ4 SDA SMBC_ICH_1 M_A_DQ7 DQ6
6 DQ5 SCL 197 2 3 SMBC_ICH 3,18 16 DQ7 VDDSPD 199 3D3V_S0
M_B_DQ6 14 M_A_DQ8 23
M_B_DQ7 DQ6 M_A_DQ9 DQ8
16 DQ7 VDDSPD 199 3D3V_S0 25 DQ9 SA0 198
M_B_DQ8 23 R251 M_A_DQ10 35 200
M_B_DQ9 DQ8 10KR2J-3-GP M_A_DQ11 DQ10 SA1
25 DQ9 SA0 198 37 DQ11
M_B_DQ10 35 200 1 2 3D3V_S0 M_A_DQ12 20 50
M_B_DQ11 DQ10 SA1 M_A_DQ13 DQ12 NC#50
37 DQ11 22 DQ13 NC#69 69
M_B_DQ12 20 50 M_A_DQ14 36 83
M_B_DQ13 DQ12 NC#50 M_A_DQ15 DQ14 NC#83
22 DQ13 NC#69 69 38 DQ15 NC#120 120
M_B_DQ14 36 83 M_A_DQ16 43 163
M_B_DQ15 DQ14 NC#83 M_A_DQ17 DQ16 NC#163/TEST
38 DQ15 NC#120 120 45 DQ17
M_B_DQ16 43 163 M_A_DQ18 55
M_B_DQ17 DQ16 NC#163/TEST M_A_DQ19 DQ18
45 DQ17 57 DQ19 VDD 81
M_B_DQ18 55 M_A_DQ20 44 82
M_B_DQ19 DQ18 M_A_DQ21 DQ20 VDD
57 DQ19 VDD 81 46 DQ21 VDD 87
M_B_DQ20 44 82 M_A_DQ22 56 88
M_B_DQ21 DQ20 VDD M_A_DQ23 DQ22 VDD
46 DQ21 VDD 87 58 DQ23 VDD 95
M_B_DQ22 56 88 M_A_DQ24 61 96
M_B_DQ23 DQ22 VDD M_A_DQ25 DQ24 VDD
3 58 DQ23 VDD 95 63 DQ25 VDD 103 3
M_B_DQ24 61 96 M_A_DQ26 73 104
M_B_DQ25 DQ24 VDD M_A_DQ27 DQ26 VDD
63 DQ25 VDD 103 75 DQ27 VDD 111
M_B_DQ26 73 104 M_A_DQ28 62 112
M_B_DQ27 DQ26 VDD M_A_DQ29 DQ28 VDD
75 DQ27 VDD 111 64 DQ29 VDD 117
M_B_DQ28 62 112 M_A_DQ30 74 118
DQ28 VDD DQ30 VDD 1D8V_S3
M_B_DQ29 64 117 M_A_DQ31 76
M_B_DQ30 DQ29 VDD M_A_DQ32 DQ31
74 DQ30 VDD 118 1D8V_S3 123 DQ32 VSS 3
M_B_DQ31 76 M_A_DQ33 125 8
M_B_DQ32 DQ31 M_A_DQ34 DQ33 VSS
123 DQ32 VSS 3 135 DQ34 VSS 9
M_B_DQ33 125 8 M_A_DQ35 137 12
M_B_DQ34 DQ33 VSS M_A_DQ36 DQ35 VSS
135 DQ34 VSS 9 124 DQ36 VSS 15
M_B_DQ35 137 12 M_A_DQ37 126 18
M_B_DQ36 DQ35 VSS M_A_DQ38 DQ37 VSS
124 DQ36 VSS 15 134 DQ38 VSS 21
M_B_DQ37 126 18 M_A_DQ39 136 24
M_B_DQ38 DQ37 VSS M_A_DQ40 DQ39 VSS
134 DQ38 VSS 21 141 DQ40 VSS 27
M_B_DQ39 136 24 M_A_DQ41 143 28
M_B_DQ40 DQ39 VSS M_A_DQ42 DQ41 VSS
141 DQ40 VSS 27 151 DQ42 VSS 33
M_B_DQ41 143 28 M_A_DQ43 153 34
M_B_DQ42 DQ41 VSS M_A_DQ44 DQ43 VSS
151 DQ42 VSS 33 140 DQ44 VSS 39
M_B_DQ43 153 34 M_A_DQ45 142 40
M_B_DQ44 DQ43 VSS M_A_DQ46 DQ45 VSS
140 DQ44 VSS 39 152 DQ46 VSS 41
M_B_DQ45 142 40 M_A_DQ47 154 42
M_B_DQ46 DQ45 VSS M_A_DQ48 DQ47 VSS
152 DQ46 VSS 41 157 DQ48 VSS 47
M_B_DQ47 154 42 M_A_DQ49 159 48
M_B_DQ48 DQ47 VSS M_A_DQ50 DQ49 VSS
157 DQ48 VSS 47 173 DQ50 VSS 53
M_B_DQ49 159 48 M_A_DQ51 175 54
M_B_DQ50 DQ49 VSS M_A_DQ52 DQ51 VSS
173 DQ50 VSS 53 158 DQ52 VSS 59
M_B_DQ51 175 54 M_A_DQ53 160 60
M_B_DQ52 DQ51 VSS M_A_DQ54 DQ53 VSS
158 DQ52 VSS 59 174 DQ54 VSS 65
M_B_DQ53 160 60 M_A_DQ55 176 66
M_B_DQ54 DQ53 VSS M_A_DQ56 DQ55 VSS
174 DQ54 VSS 65 179 DQ56 VSS 71
M_B_DQ55 176 66 M_A_DQ57 181 72
M_B_DQ56 DQ55 VSS M_A_DQ58 DQ57 VSS
179 DQ56 VSS 71 189 DQ58 VSS 77
M_B_DQ57 181 72 M_A_DQ59 191 78
M_B_DQ58 DQ57 VSS M_A_DQ60 DQ59 VSS
2 189 DQ58 VSS 77 180 DQ60 VSS 121 2
M_B_DQ59 191 78 M_A_DQ61 182 122
M_B_DQ60 DQ59 VSS M_A_DQ62 DQ61 VSS
180 DQ60 VSS 121 192 DQ62 VSS 127
M_B_DQ61 182 122 M_A_DQ63 194 128
M_B_DQ62 DQ61 VSS DQ63 VSS
192 DQ62 VSS 127 VSS 132
M_B_DQ63 194 128 M_A_DQS#0 11 133
DQ63 VSS M_A_DQS#1 /DQS0 VSS
VSS 132 8 M_A_DQS[7..0] 29 /DQS1 VSS 138
M_B_DQS#0 11 133 M_A_DQS#2 49 139
M_B_DQS#1 DQS0# VSS M_A_DQS#3 /DQS2 VSS
8 M_B_DQS#[7..0] 29 DQS1# VSS 138 68 /DQS3 VSS 144
M_B_DQS#2 49 139 M_A_DQS#4 129 145
M_B_DQS#3 DQS2# VSS M_A_DQS#5 /DQS4 VSS
68 DQS3# VSS 144 146 /DQS5 VSS 149
M_B_DQS#4 129 145 M_A_DQS#6 167 150
M_B_DQS#5 DQS4# VSS M_A_DQS#7 /DQS6 VSS
146 DQS5# VSS 149 186 /DQS7 VSS 155
M_B_DQS#6 167 150 156
M_B_DQS#7 DQS6# VSS M_A_DQS0 VSS
186 DQS7# VSS 155 13 DQS0 VSS 161
156 M_A_DQS1 31 162
VSS 8 M_A_DQS#[7..0] DQS1 VSS
M_B_DQS0 13 161 M_A_DQS2 51 165
M_B_DQS1 DQS0 VSS M_A_DQS3 DQS2 VSS
8 M_B_DQS[7..0] 31 DQS1 VSS 162 70 DQS3 VSS 168
M_B_DQS2 51 165 M_A_DQS4 131 171
M_B_DQS3 DQS2 VSS M_A_DQS5 DQS4 VSS
70 DQS3 VSS 168 148 DQS5 VSS 172
M_B_DQS4 131 171 M_A_DQS6 169 177
M_B_DQS5 DQS4 VSS M_A_DQS7 DQS6 VSS
148 DQS5 VSS 172 188 DQS7 VSS 178
M_B_DQS6 169 177 183
M_B_DQS7 DQS6 VSS VSS
188 DQS7 VSS 178 7,12 M_ODT0 114 ODT0 VSS 184
VSS 183 7,12 M_ODT1 119 ODT1 VSS 187
7,12 M_ODT2 114 OTD0 VSS 184 VSS 190
7,12 M_ODT3 119 OTD1 VSS 187 DDR_VREF_S3 1 VREF VSS 193
VSS 190 2 VSS VSS 196
1

DDR_VREF_S3 1 VREF VSS 193


2 196 C321 202 201
VSS VSS GND GND
1

SC4D7U6D3V3KX-GP
2

C380 202 201 BC1 DDR2-200P-2-GP


SC4D7U6D3V3KX-GP GND GND
62.10017.691
2

BC2 MH1 MH2 SCD1U16V2ZY-2GP


MH1 MH2

om
1 SCD1U16V2ZY-2GP High 5.2mm 1

l.c
DDR2-200P-23-GP
62.10017.A71

ai
tm
High 9.2mm

ho
Wistron Corporation

f@
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

in
Taipei Hsien 221, Taiwan, R.O.C.

xa
he
Title

DDR2 Socket
Size Document Number Rev

MYALL2 MP
Date: Thursday, March 30, 2006 Sheet 11 of 57
A B C D E
A B C D E

PARALLEL TERMINATION Decoupling Capacitor


Put decap near power(0.9V) and pull-up resistor
DDR_VREF_S0
Put decap near power(0.9V)
RN30 DDR_VREF_S0
8 1 M_CKE2 7,11
and pull-up resistor
4 7 2 M_B_BS#2 8,11 4
6 3 M_B_A12
5 4 M_B_A9

1
C356 C397 C324 C379 C323 C325 C352 C326 C378 C392 C322

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
SRN56J-2-GP

2
1 2 M_ODT1 7,11
1 R235 2 56R2J-4-GP M_ODT3 7,11
1 R249 2 56R2J-4-GP M_A_A9
1 R234 2 56R2J-4-GP M_B_A8
R248 56R2J-4-GP

RN31
8 1 M_B_A5 M_A_A[13..0]
M_A_A[13..0] 8,11
7 2 M_B_A3
6 3 M_B_A1 M_B_A[13..0]
M_B_A[13..0] 8,11
5 4 M_B_A10

1
C393 C394 C396 C395 C351 C376 C375 C377 C353 C355 C354

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
SRN56J-2-GP
RN35

2
8 1 M_B_A13
7 2 M_ODT2 7,11
6 3 M_CS2# 7,11
5 4 M_B_RAS# 8,11
SRN56J-2-GP

RN34
8 1 M_B_BS#1 8,11
3 M_B_A0 3
7
6
2
3 M_B_A2 1D8V_S3 Place these Caps near DM1
5 4 M_B_A4

SRN56J-2-GP

1
C730 C731 C732 C733 C734

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP
RN33
8 1 M_B_A6

2
7 2 M_B_A7
6 3 M_B_A11
5 4 M_CKE3 7,11
SRN56J-2-GP

RN32
8 1 M_B_BS#0 8,11
7 2 M_B_WE# 8,11
6 3 M_CS3# 7,11
5 4 M_B_CAS# 8,11

1
C385 C386 C387 C388

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
SRN56J-2-GP

2
RN28
8 1 M_A_A13
7 2 M_ODT0 7,11
6 3 M_CS0# 7,11
5 4 M_A_RAS# 8,11
SRN56J-2-GP
2 2

RN27
8 1 M_A_BS#1 8,11
7 2 M_A_A0
M_A_A2
6
5
3
4 M_A_A4 1D8V_S3 Place these Caps near DM2
SRN56J-2-GP

1
RN23 C768 C771 C769 C770 C767

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP
8 1 M_A_BS#0 8,11
7 2 M_A_WE# 8,11
2

2
6 3 M_A_CAS# 8,11
5 4 M_CS1# 7,11
SRN56J-2-GP

RN21
8 1 M_CKE0 7,11
7 2 M_A_BS#2 8,11
6 3 M_A_A12
1

5 4 M_A_A8 C337
1

1
SCD1U16V2ZY-2GP

C342 C338 C343


SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
SRN56J-2-GP
2

2
RN26
8 1 M_A_A6
7 2 M_A_A7
1 6 3 M_A_A11 1
5 4 M_CKE1 7,11
SRN56J-2-GP
Wistron Corporation
RN22 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
8 1 M_A_A5 Taipei Hsien 221, Taiwan, R.O.C.
7 2 M_A_A3
6 3 M_A_A1 Title
M_A_A10
5 4
DDR2 Termination Resistor
SRN56J-2-GP Size Document Number Rev

MYALL2 MP
Date: Thursday, March 30, 2006 Sheet 12 of 57
A B C D E
LCDVDD
LED D19 DY
BAV99PT-GP-U
2
5V_S0

26,30 WLAN_LED#
WLAN_LED#
R290 120R2F-GP
1 2 K
LED5 LED-YO-3-GP-U
A
R289 330R2J-3-GP LED6 LED-B-77-GP-U
3D3V_S0

Layout 40 mil 3D3V_S0 WLAN_LED# 3 BLT_LED#_1 1 2 K A 5V_S0


U18 31 BLT_LED#_1
1
R320 UMA 1 6 R286 120R2F-GP LED4 LED-OG-17-GP
1KR2J-1-GP OUT IN CHARGE_LED# Orange
2 GND GND 5 31 CHARGE_LED# 1 2 3
7 GMCH_LCDVDD_ON 1 2 LCDVDD_ON_1 3 4 D20 DY
ON/OFF# IN BAV99PT-GP-U R287 120R2F-GP 1 5V_S5

1
2 DC_BATFULL# 1 2 2
3D3V_S0 C468 C470 31 DC_BATFULL# Green
SC1U10V3ZY-6GP AAT4280IGU-1-T1GP SC1U10V3ZY-6GP BLT_LED#_1 3

2
C467

1
SCD1U16V2ZY-2GP 1
R315 G72 R291 120R2F-GP LED3 LED-OG-17-GP
10KR2J-3-GP STDBY_LED# 1 2 3 Orange
R318 G72 RN55 31 STDBY_LED#
UMA
0R2J-2-GP LCD_TXAOUT2+ 1 8 R288 120R2F-GP 1
2
LCD_TXAOUT2- GMCH_TXAOUT2+ 7 FRONT_PWRLED#
1 2 2 7 GMCH_TXAOUT2- 7 31 FRONT_PWRLED# 1 2 2
LCD_TXACLK+ 3 6 Green
D LCD_TXACLK- GMCH_TXACLK+ 7
4 5 GMCH_TXACLK- 7
3

SRN0J-7-GP

2
Q21 G72 RN51 G72
2N7002PT-U R317 DY 1 8
0R2J-2-GP LVDS_TXACLK- 48
51 NV_LCDVDD_ON# 1 2 7
G
LCD/INVERTER CONN 3
4
6
5
LVDS_TXACLK+
LVDS_TXAOUT2-
48
48
2

1
LVDS_TXAOUT2+ 48
S SRN0J-7-GP
RN54 UMA
LCD_TXAOUT0+ 1 8
LCD_TXAOUT0- GMCH_TXAOUT0+ 7 3D3V_S0
2 7 GMCH_TXAOUT0- 7
LCD_TXAOUT1+ 3 6
LCD_TXAOUT1- 4 5
GMCH_TXAOUT1+
GMCH_TXAOUT1-
7
7
LED BD CONN

4
3
SRN0J-7-GP RN61
C232
RN50 G72 SC1U16V3KX-2GP SRN10KJ-5-GP
1 8 LVDS_TXAOUT1- 48 1 2

1
2 7 LVDS_TXAOUT1+ 48
3 6 LEDBD1 5V_S0 R424

1
2
LVDS_TXAOUT0- 48 10KR2J-3-GP
4 5 LVDS_TXAOUT0+ 48 13 EC15
1
3D3V_S0 5V_S0 SRN0J-7-GP SCD1U16V2ZY-2GP 1 2

2
BRIGHTNESS BRIGHTNESS 31 RN56 UMA R417 220R2J-L2-GP 2 1 2 MEDIA_LED#
FPBACK FPBACK 31 LCD_TXBOUT0- 1 8 R420 220R2J-L2-GP 3 1 2
GMCH_TXBOUT0- 7 CAP_LED# 31

1
LCD_TXBOUT0+ 2 7 R421 220R2J-L2-GP 4 1 2
R652 D36 LCD_TXBOUT1- GMCH_TXBOUT0+ 7 R422 220R2J-L2-GP NUM_LED# 31
3 6 GMCH_TXBOUT1- 7 5 1 2 WLAN_LED# 26,30
2

LCD1 C7 C6 0R2J-2-GP 1N4148W-7-F-GP LCD_TXBOUT1+ 4 5 R423 220R2J-L2-GP 6 1 2


GMCH_TXBOUT1+ 7 BLT_LED#_2 31
47 45 DY 7 WIRELESS_BTN# 31
MH1 SC100P50V2JN-U SC100P50V2JN-U SRN0J-7-GP 8 BLT_BTN# 31
1

2
1 RN52 G72 9
1 8 LVDS_TXBOUT1+ 48 10 INT_MIC 29
2 DCBATOUT U84 C846 2 7 11
LVDS_TXBOUT1- 48

1
1

1
1
1
1
1
48 3 SC4D7U10V5ZY-3GP 3 6 12 C604 DY
LVDS_TXBOUT0+ 48 SC1000P50V3JN-GP
4 1 OUT IN 5 1 2 4 5 LVDS_TXBOUT0- 48 14
5 2 C607 DY

2
2

2
2
2
2
2
GND
1

6 C462 C460 3 4 WEBCAM_PW_SW 31 SRN0J-7-GP SC1000P50V3JN-GP


USB_6- SC4D7U10V5ZY-3GP SCD1U16V2ZY-2GP NC#3 ON/OFF# RN57 UMA ACES-CON12-GP C616 DY
7
8 USB_6+ LCD_TXBOUT2- 1 8 20.K0174.012 SC1000P50V3JN-GP
2

AAT4250IGV-T1-GP LCD_TXBOUT2+ GMCH_TXBOUT2- 7 C613 DY


49 9 2 7 GMCH_TXBOUT2+ 7
10 BRIGHTNESS LCD_TXBCLK- 3 6 SC1000P50V3JN-GP
FPBACK LCD_TXBCLK+ GMCH_TXBCLK- 7 C609 DY
11 4 5 GMCH_TXBCLK+ 7
12 SC1000P50V3JN-GP
13 SRN0J-7-GP 3D3V_S0 C606 DY
LCDVDD
14 RN53 G72 SC1000P50V3JN-GP CAP_LED# /
1

50 15 C469 DY C465 C5 DY 1 8 C601 DY


16 EDID_CLK 2 7
LVDS_TXBCLK+ 48 SC1000P50V3JN-GP NUM_LED# /
LVDS_TXBCLK- 48

1
2
17 EDID_DAT SC10U10V5ZY-1GP SCD1U25V3ZY-3GP SCD1U25V3ZY-3GP 3 6 IDE_LED# DY
2

LVDS_TXBOUT2+ 48
18 4 5
19
LVDS_TXBOUT2- 48 2D5V_S0 1000p near
SRN0J-7-GP SRN2K2J-1-GP
20 3D3V_S0 RN46
LEDBD1 BY EMI
21
51 22 LCD_TXACLK- Q24 UMA REQUEST

4
3
23 LCD_TXACLK+ FDN337N-1-GP
24 R326 0R0603-PAD
25 LCD_TXAOUT2- S D 1 2 EDID_CLK
LCD_TXAOUT2+ 7 CLK_DDC_EDID R325 0R3-0-U-GP
26 G72
27 51 G72_LCD_EDID_CLK 1 2
28 LCD_TXAOUT1- EVEN CHANNEL

G
29 LCD_TXAOUT1+ Q25 UMA
52 30 FDN337N-1-GP R327 0R0603-PAD
31 LCD_TXAOUT0- S D 1 2 EDID_DAT
LCD_TXAOUT0+ 7 DAT_DDC_EDID
32
33 R328 0R3-0-U-GP G72

1
34 LCD_TXBOUT0- 1 2 EC27DY EC26 DY
LCD_TXBOUT0+ 51 G72_LCD_EDID_DAT SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
35
53 36

2
37 LCD_TXBOUT1-
38 LCD_TXBOUT1+ ODD CHANNEL
39
40 LCD_TXBOUT2-
41 LCD_TXBOUT2+
54 42 D30
43 LCD_TXBCLK- 6 1 IDE_LED#
44 LCD_TXBCLK+ IDE_LED# 20
RN88 R425 0R0402-PAD

om
MH2
55 46 USB_6- 3 2 USBPN6 16 MEDIA_LED# 5 2 SATA_LED# IDE_LED# 1 2 ODD_LED#

l.c
USB_6+ SATA_LED# 15
4 1 USBPP6 16
Wistron Corporation

ai
tm
JAE-CON44-3-GP SRN0J-6-GP 4 3 ODD_LED# 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
ODD_LED# 20

ho
20.F0690.044 Taipei Hsien 221, Taiwan, R.O.C.
RB731U-1GP-U

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Title

in
LCD CONN & LED

xa
he
Size Document Number Rev

MYALL2 MP
Date: Tuesday, April 11, 2006 Sheet 13 of 57
A B C D E

Layout Note:
Place these resistors
CRT I/F & CONNECTOR
close to the CRT-out
connector
Ferrite bead impedance: 10 ohm@100MHz
L22

47 CRT_RED 1 G72 2 RED 1 2 CRT_R


R375 0R2J-2-GP FCB1608CF-GP
7 GMCH_RED 1 UMA 2
R376 0R2J-2-GP CRT1
L23
17
47 CRT_GREEN 1 G72 2 GREEN 1 2 CRT_G MH1
4 R373 0R2J-2-GP FCB1608CF-GP 6 4
7 GMCH_GREEN 1 UMA 2 11
R374 0R2J-2-GP CRT_R 1
L24
7
47 CRT_BLUE 1 G72 2 BLUE 1 2 CRT_B
R371 0R2J-2-GP FCB1608CF-GP DAT_DDC1_5

SC3P50V2CN-1-GP

SC3P50V2CN-1-GP

SC3P50V2CN-1-GP
12

1
1 UMA 2 C457 C452 C453 2 CRT_G
7 GMCH_BLUE

1
R372 0R2J-2-GP R294 R295 R296 C446 C447 C448 C441 8

SC3P50V2CN-1-GP

SC3P50V2CN-1-GP

SC3P50V2CN-1-GP
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP 13 CRT_HSYNC1

2
SC100P50V2JN-3GP CRT_B 3

1
DY DY DY 9 5V_CRT_S0 C438

2
CRT_VSYNC1 14
4 C440 SC18P50V2JN-1-GP

2
1
C439 10
15 CLK_DDC1_5 SCD01U16V2KX-3GP
SC18P50V2JN-1-GP 5
Layout Note:

1
MH2 C442
5V_S0
* Must be a ground return path between this ground and the ground on 16
SC100P50V2JN-3GP

2
the VGA connector.

1
VIDEO-15-21-U3-GP
Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT R646
10KR2J-3-GP
20.20334.015
CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.
R648

2
0R2J-GP
1 2
31 CRT_DEC
5V_S0
3 3
Hsync & Vsync level shift

2
R647 DY
5V_S0 0R2J-GP D24
CH751H-40PT

2
2D5V_S0 3D3V_S0 2D5V_S0 3D3V_S0

1
1
5V_CRT_S0 5V_CRT_S0
C459

1
2 SCD1U16V2ZY-2GP

1
2

1
2

3
4
R306 UMA R298 R299
0R2J-2-GP RN43 UMA SRN2K2J-1-GP 0R2J-2-GP 0R2J-2-GP RN41
SRN2K2J-1-GP RN44 UMA G72 SRN10KJ-5-GP
14

7 GMCH_HSYNC 1 2
1

R308 G72 G72

2
0R2J-2-GP
1 2 HSYNC_4 2 3 CRT_HSYNC1

4
3

4
3

2
1
47 HSYNC R313 UMA

G
0R2J-2-GP U16A
TSAHCT125PW-GP
14

1 2
7

7 GMCH_VSYNC
4

R311 G72 R305 1 2 0R2J-2-GP UMA S D DAT_DDC1_5


7 GMCH_DDCDATA
0R2J-2-GP
47 VSYNC 1 2VSYNC_4 5 6 CRT_VSYNC1
47 G72_CRT_EDID_DAT
R297 1 2 0R2J-2-GP G72
U16B Q19

G
TSAHCT125PW-GP R303 1 2 0R2J-2-GP G72 FDN337N-1-GP
47 G72_CRT_EDID_CLK
7

R304 1 2 0R2J-2-GP UMA S D CLK_DDC1_5


7 GMCH_DDCCLK

2 2
DDC_CLK & DATA level shift Q20
FDN337N-1-GP

C449 SC33P50V3JN-GP TVOUT


TV CONN R379 G72
0R2J-2-GP
1 2
L19 TVOUT TVOUT1
1 2 DACB 1 2 LUMA_1 4 2 5V_S0 5V_S0
47 G72_TV_LUMA IND-1D2UH-5-GP LUMA NC#2 D1 TVOUT
6 CRMA
1

R380 UMA C454 C443 7 1 BAV99PT-GP-U


0R2J-2-GP R300 COMP GND D21
TVOUT TVOUT GND 3 2 2
1 2 150R2F-1-GP SC150P-GP SC270P50V2JN-2GP 8
2

7 TV_DACB GND DACB CRT_R 3


TVOUT 5 NC#5 GND 9 3
2

MINDIN7-19-GP-U2 1 1
C451 SC33P50V3JN-GP TVOUT 22.10021.H61 TVOUT
1 2 BAV99PT-GP-U
R382 G72 D3 TVOUT
0R2J-2-GP L21 TVOUT BAV99PT-GP-U
1 2 DACC 1 2 CRMA_1 2 D22 2
47 G72_TV_CRMA IND-1D2UH-5-GP
1

R383 UMA C456 C445 DACC 3 CRT_G 3


0R2J-2-GP R302 TVOUT TVOUT
1 2 150R2F-1-GP SC150P-GP SC270P50V2JN-2GP 1 1
2

7 TV_DACC
TVOUT
D2 TVOUT BAV99PT-GP-U
2

1
BAV99PT-GP-U 1
C450 SC33P50V3JN-GP TVOUT 2 D23 2
1 2
R377 G72 DACA CRT_B 3
0R2J-2-GP L20 TVOUT
3
Wistron Corporation
1 2 DACA 1 2 COMP_1 1 1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
47 G72_TV_COMP IND-1D2UH-5-GP Taipei Hsien 221, Taiwan, R.O.C.
1

R378 UMA C455 C444 BAV99PT-GP-U


0R2J-2-GP R301 TVOUT TVOUT Title
1 2 150R2F-1-GP SC150P-GP SC270P50V2JN-2GP
CRT/TV Connector
2

7 TV_DACA
TVOUT
Size Document Number Rev
2

MYALL2 MP
Date: Thursday, March 30, 2006 Sheet 14 of 57
A B C D E
A B C D E

C722 SC4D7P50V2CN-1GP
1 2
4 4
1D05V_S0

1
3

4
R499 DY
X5 56R2J-4-GP

1
X-32D768KHZ-41GP
3D3V_AUX_S5 RTC_AUX_S5 82.30001.731 R520

2
D32 10MR2J-L-GP H_DPSLP#
2 1

1
1

2
C332
CH751H-40PT SC1U10V3ZY-6GP

2
C737 SC4D7P50V2CN-1GP LPC_LAD[3..0]
RTC circuitry 1 2
U65A LPC_LAD[3..0] 31,32,34
RCT_X1 AB1 AA6 LPC_LAD0
RTC1 RCT_X2AB2 RTXC1 LAD0 LPC_LAD1 Open R179 for Dothan A step
RTCX2 LAD1 AB5
4 D15 AC4 LPC_LAD2 Shunt for Dothan B step

LPC
RTC
BAT 1 LAD2 & all Yonah
1 2BAT_D2 1 R525 1 2 20KR2J-L2-GP RTC_RST# AA3 RTCRST# LAD3 Y6 LPC_LAD3
1KR2J-1-GP R233
2 R232 1 2 INTRUDER# Y5 AC3 LPC_LDRQ0# 32 10KR2J-3-GP
CH751H-40PT R526 1MR2J-1-GP INTVRMEN INTRUDER# LDRQ0#
3 W4 INTVRMEN LDRQ1#/GPIO23 AA5 1 2 3D3V_S0
2

1
5
C709 DY C739 W1 AB3 LPC_LFRAME# 31,32,34
ACES-CON3-GP SC1U10V3ZY-6GP 19 INTRUDER# EE_CS LFRAME# 1D05V_S0
SCD1U16V2ZY-2GP Y1
1

2
20.F0714.003 EE_SHCLK
Y2 EE_DOUT A20GATE AE22 KA20GATE_1 31
W3 AH28 H_A20M# 4 R502 DY
EE_DIN A20M#

1
2nd source: 20.D0198.103 0R2J-2-GP
3 V3 AG27 H_CPUSLP#_2 1 2 H_CPUSLP# 4,6 R500 3
LAN_CLK CPUSLP# 56R2J-4-GP
LAN_RSTYNC U3 AF24 H_DPRSLP#

LAN
CPU
LAN_RSTSYNC TP1/DPRSTP# H_DPRSLP# 4,37
AH25 H_DPSLP# 4

2
TP2/DPSLP#
U5 LAN_RXD0
V4 LAN_RXD1 FERR# AG26 H_FERR# 4
T5 LAN_RXD2
R527 AG24 H_PWRGD 4,19
22R2J-2-GP GPIO49/CPUPWRGD R498 DY 1D05V_S0
U7 LAN_TXD0
21 ACZ_BTCLK_MDC 2 1 V6 200R2F-L-GP
LAN_TXD1 H_PWRGD
V7 LAN_TXD2 IGNNE# AG22 H_IGNNE# 4 1 2
INIT3_3V# AG21 FWH_INIT# 34
28 ACZ_BITCLK 2 R528 1 ACZ_BIT_CLK U1 AF22 H_INIT# 4
ACZ_BIT_CLK INIT#

AC-97/AZALIA
21,28 ACZ_SYNC 22R2J-2-GP
1 2 ACZ_SYNC_R R6 AF25 H_INTR 4
LAN_RSTYNC R240 39R2J-L-GP ACZ_SYNC INTR 1D05V_S0
SATA2RXN 21,28 ACZ_RST# 1 2 ACZ_RST#_R R5 AG23 KBRCIN#_1 31
SATA2RXP R242 39R2J-L-GP ACZ_RST# RCIN#

1
28 ACZ_SDATAIN0 T2 ACZ_SDIN0 NMI AH24 H_NMI 4
1

21 ACZ_SDATAIN1 T3 AF23 H_SMI# 4 R501


R529 DY R495 R496 ACZ_SDIN1 SMI#
T1 ACZ_SDIN2 56R2J-4-GP
0R2J-2-GP 0R0402-PAD 0R0402-PAD TPAD30 TP83 AH22 H_STPCLK# 4
R241 ACZ_SDATAOUT_R STPCLK#
21,28 ACZ_SDATAOUT 1 2 T4

2
39R2J-L-GP ACZ_SDOUT H_THERMTRIP_R
AF26
2

THERMTRIP#
13 SATA_LED# AF18 SATALED#
AF3 AB15 Layout Note: R568 needs to placed
20 SATA_RXN0 SATA0RXN DD0 IDE_PDD0 20
AE3 AE14 within 2" of ICH7, R568 must be placed
20 SATA_RXP0 SATA0RXP DD1 IDE_PDD1 20
AG2 AG13 within 2" of R169 w/o stub.
20 SATA_TXN0 SATA0TXN DD2 IDE_PDD2 20
20 SATA_TXP0 AH2 SATA0TXP DD3 AF13 IDE_PDD3 20
2 2
DD4 AD14 IDE_PDD4 20
SATA2RXN AF7 AC13 IDE_PDD5 20
SATA2RXP AE7 SATA2RXN DD5
SATA2RXP DD6 AD12 IDE_PDD6 20
AG6 SATA2TXN DD7 AC12 IDE_PDD7 20
AH6 SATA2TXP DD8 AE12 IDE_PDD8 20
DD9 AF12 IDE_PDD9 20
AF1 AB13

SATA
3 CLK_PCIE_SATA# SATA_CLKN DD10 IDE_PDD10 20
3 CLK_PCIE_SATA AE1 SATA_CLKP DD11 AC14 IDE_PDD11 20
RTC_AUX_S5 Change to 24.9 1% ohm AF14
DD12 IDE_PDD12 20
when use SATA HD SATARBIAS AH10 AH13
SATARBIASN DD13 IDE_PDD13 20
1 R497
2 AG10 AH14 IDE_PDD14 20
SATARBIASP DD14
1

24D9R2F-L-GP AC15
DD15 IDE_PDD15 20
R238
300KR2J-GP
P.H. for internal VCCSUS1_05
20 IDE_PDIOR# AF15
AH15
DIOR# IDE DA0 AH17
AE17
IDE_PDA0 20
20 IDE_PDIOW# DIOW# DA1 IDE_PDA1 20
20 IDE_PDDACK# AF16 AF17 IDE_PDA2 20
2

DDACK# DA2
20 INT_IRQ14 AH16 IDEIRQ
INTVRMEN 20 IDE_PDIORDY AG16 AE16 IDE_PDCS1# 20
Place within 500 mils IORDY DCS1#
20 IDE_PDDREQ AE15 DDREQ DCS3# AD16 IDE_PDCS3# 20
of ICH7ball
1

ICH7-M-GP KI.80101.017
R239 DY
0R2J-2-GP INTVRMEN
2

Enable 1

Disable 0

om
1 1

l.c
ai
Wistron Corporation

tm
Placement Note:

ho
Diatance between the ICH-7 M and cap on the "P" signal 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
should be identical distance between the ICH-7 M and cap Taipei Hsien 221, Taiwan, R.O.C.

f@
on the "N" signal for same pair.

in
Title

xa
ICH7-M (1 of 4)

he
Size Document Number Rev

MYALL2 MP
Date: Thursday, March 30, 2006 Sheet 15 of 57
A B C D E
A B C D E

U65C RN84
24,25,30 PCI_AD[31..0]
U65B C22 AF19 SATA0_R0 SATA0_R2 1 8
18,26 SMB_CLK SMBCLK GPIO21/SATA0GP
PCI_AD0 E18 D7 PCI_REQ#0 B22 AH18 SATA0_R1 SATA0_R0 2 7

SMB
AD0 REQ0# PCI_REQ#0 25 18,26 SMB_DATA SMBDATA GPIO19/SATA1GP 3D3V_S0

SATA
PCI_AD1 PCI_GNT#0 SMB_LINK_ALERT# A26 SATA0_R2 SATA0_R3 3

GPIO
PCI_AD2
C18
A16
AD1 PCI GNT0# E7
C16 PCI_REQ#1
PCI_GNT#0 25
SMLINK0 B25
LINKALERT# GPIO36/SATA2GP AH19
AE19 SATA0_R3 SATA0_R1 4
6
5
AD2 REQ1# PCI_REQ#1 30 SMLINK0 GPIO37/SATA3GP
PCI_AD3 F18 D16 PCI_GNT#1 PCI_GNT#1 30 SMLINK1 A25 SRN10KJ-4-GP
PCI_AD4 AD3 GNT1# PCI_REQ#2 SMLINK1
E16 AD4 REQ2# C17 CLK14 AC1 CLK_ICH14 3

Clocks
PCI_AD5 A18 D17 PCI_GNT#2 TP58 TPAD30 PM_RI# A28 B2 CLK48_ICH 3
PCI_AD6 AD5 GNT2# PCI_REQ#3 RI# CLK48
E17 AD6 REQ3# E13
PCI_AD7 A17 F13 PCI_GNT#3 TP60 TPAD30 28 ACZ_SPKR A19 C20 PM_SUS_CLK 18
PCI_AD8 AD7 GNT3# PCI_REQ#4 SPKR SUSCLK
A15 AD8 REQ4#/GPIO22 A13 31,32 PM_SUS_STAT# A27 SUS_STAT#
4 PCI_AD9 C14 A14 PCI_GNT#4 TP90 TPAD30 DBRESET# A22 B24 PM_SLP_S3# 18,31,35,40,41,45,56 4
PCI_AD10 AD9 GNT4#/GPIO48 PCI_REQ#5 SYS_RST# SLP_S3#
E14 AD10 GPIO1/REQ5# C8 SLP_S4# D23 PM_SLP_S4# 31,41
PCI_AD11 D14 D8 PCI_GNT#5 TP59 TPAD30 7 PM_BMBUSY# AB18 F22
PCI_AD12 AD11 GPIO17/GNT5# GPIO0/BM_BUSY# SLP_S5# TP57 TPAD30
B12 AD12
PCI_AD13 C13 B15 PCI_C/BE#0 24,30 SMB_ALERT# B23 AA4 PWROK 7,19 R223
PCI_AD14 AD13 C/BE0# GPIO11/SMBALERT# PWROK 100R2J-2-GP
G15 C12 PCI_C/BE#1 24,30

Power MGT
PCI_AD15 AD14 C/BE1# PM_DPRSLPVR_R
G13 AD15 C/BE2# D12 PCI_C/BE#2 24,30 3 PM_STPPCI# AC20 GPIO18/STPPCI# GPIO16/DPRSLPVR AC22 2 1 PM_DPRSLPVR 37
PCI_AD16 E12 C15 PCI_C/BE#3 24,30 3 PM_STPCPU# AF21 1 2 R224 DY

GPIO
PCI_AD17 AD16 C/BE3# GPIO20/STPCPU# PM_BATLOW#_R 100KR2J-1-GP
C11 C21

SYS
PCI_AD18 AD17 TP0/BATLOW#
D11 A7 PCI_IRDY# 25,30 A21 D33
PCI_AD19 AD18 IRDY# GPIO26 PWRBTN#_ICH BAS16-1-GP
A11 AD19 PAR E10 PCI_PAR 24,30 PWRBTN# C23 1 PM_PWRBTN# 31
PCI_AD20 A10 B18 1 R544
2 PCIRST1# 25,27,30 B21 R547
PCI_AD21 AD20 PCIRST# 47R2J-2-GP PSW_CLR# GPIO27 10KR2J-3-GP
F11 AD21 DEVSEL# A12 PCI_DEVSEL# 25,30 34 PSW_CLR# E23 GPIO28 3
PCI_AD22 F10 C9 PCI_PERR# 25,30 C19 1 2
PCI_AD23 AD22 PERR# LAN_RST#
E9 AD23 PLOCK# E11 PCI_LOCK# 25,30,31,32 PM_CLKRUN# AG18 GPIO32/CLKRUN# 2
PCI_AD24 D9 B10 PCI_SERR# 25,30 Y4 RSMRST#_SB
PCI_AD25 AD24 SERR# RSMRST#
B9 AD25 STOP# F15 PCI_STOP# 25,30 AC19 GPIO33/AZ_DOCK_EN#
PCI_AD26 A8 F14 PCI_TRDY# 25,30 U2 E20 ECSWI# 31
PCI_AD27 AD26 TRDY# GPIO34/AZ_DOCK_RST# GPIO9
A6 AD27 FRAME# F16 PCI_FRAME# 25,30 GPIO10 A20
PCI_AD28 C7 ICH7_WAKE# F20 F19 ICH7_GPI12
PCI_AD29 AD28 WAKE# GPIO12
B6 AD29 PLTRST# C26 PLT_RST1# 7,18,22,26,31,32,34,46,51 25,30,31,32 INT_SERIRQ AH21 SERIRQ GPIO13 E19
PCI_AD30 E6 A9 CLK_ICHPCI 3 19 THRM# AF20 R4
PCI_AD31 AD30 PCICLK THRM# GPIO14
D6 AD31 PME# B19 ICH_PME#_1
1 2 ICH_PME# 22 GPIO15 E22
R545 0R0402-PAD 7,37 VGATE_PWRGD AD22 R3
VRMPWRGD GPIO24
INT_PIRQA# A3
Interrupt I/F G8 INT_PIRQE# AC21
GPIO25 D20
AD21
PIRQA# GPIO2/PIRQE# INT_PIRQE# 30 31 KBC_SLP_WAKE GPIO6 GPIO35
INT_PIRQB# INT_PIRQF#
25 INT_PIRQB#
INT_PIRQC#
B4
C5
PIRQB# GPIO3/PIRQF# F7
F8 INT_PIRQG#
INT_PIRQF# 25 31 ECSCI#_1 AC18
E21
GPIO7 GPIO GPIO38 AD20
AE20
PIRQC# GPIO4/PIRQG# INT_PIRQG# 25 31 ECSMI# GPIO8 GPIO39
INT_PIRQD# B5 G7 INT_PIRQH#
3 PIRQD# GPIO5/PIRQH# ICH7-M-GP KI.80101.017 3

AE5
MISC AE9 U65D
RSVD[1] RSVD[6]
AD5 RSVD[2] RSVD[7] AG8 22 PCIE_RXN1 F26 PERn1 DMI0RXN V26 DMI_RXN0 7
AG4 RSVD[3] RSVD[8] AH8 22 PCIE_RXP1 F25 PERp1 DMI0RXP V25 DMI_RXP0 7

Direct Media Interface


AH4 F21 C758 SCD1U10V2KX-5GP 2 1 E28 U28 Layout Note:
RSVD[4] RSVD[9] 22 PCIE_TXN1 PETn1 DMI0TXN DMI_TXN0 7
AD9 AH20 C759 SCD1U10V2KX-5GP 2 1 E27 U27 PCIE AC coupling caps
RSVD[5] MCH_SYNC# MCH_ICH_SYNC# 7 22 PCIE_TXP1 PETp1 DMI0TXP DMI_TXP0 7
need to be within 250 mils of the driver.
ICH7-M-GP KI.80101.017 H26 Y26 DMI_RXN1 7
PERn2 DMI1RXN
H25 PERp2 DMI1RXP Y25 DMI_RXP1 7
G28 PETn2 DMI1TXN W28 DMI_TXN1 7
G27 PETp2 DMI1TXP W27 DMI_TXP1 7

PCI-Express
RP2 26 PCIE_RXN3 K26 AB26 DMI_RXN2 7
INT_PIRQF# PERn3 DMI2RXN
1 10 3D3V_S0 26 PCIE_RXP3 K25 PERp3 DMI2RXP AB25 DMI_RXP2 7
INT_PIRQC# 2 9 PCI_REQ#0 26 PCIE_TXN3 C750 SCD1U10V2KX-5GP 2 1 J28 AA28 DMI_TXN2 7
PCI_PERR# INT_PIRQH# C755 SCD1U10V2KX-5GP 2 PETn3 DMI2TXN
3 8 RP4 3D3V_S5 26 PCIE_TXP3 1 J27 AA27 DMI_TXP2 7
INT_PIRQG# PCI_REQ#5 ICH7_GPI12 PETp3 DMI2TXP
4 7 1 10
5 6 PCI_IRDY# PM_BATLOW#_R 2 9 ICH7_WAKE# M26 AD25 DMI_RXN3 7
3D3V_S0 PERn4 DMI3RXN 1D5V_S0
DBRESET# 3 8 PSW_CLR# M25 AD24 DMI_RXP3 7
SMB_LINK_ALERT# 4 SMB_ALERT# PERp4 DMI3RXP
SRN8K2J-2-GP 7 L28 AC28 DMI_TXN3 7
PM_RI# PETn4 DMI3TXN Place within 500 mils of ICH
RP3 3D3V_S5 5 6 L27 AC27 DMI_TXP3 7
PETp4 DMI3TXP

1
MCH_ICH_SYNC# 1 10 3D3V_S0
PCI_REQ#4 2 9 PCI_STOP# SRN10KJ-L3-GP P26 AE28 CLK_PCIE_ICH# 3 R250
PCI_TRDY# PCI_REQ#1 PERn5 DMI_CLKN 24D9R2F-L-GP
3 8 RP1 3D3V_S5 P25 AE27 CLK_PCIE_ICH 3
INT_SERIRQ PCI_REQ#2 USB_OC#2 PERp5 DMI_CLKP
4 7 1 10 N28 PETn5
5 6 PCI_FRAME# USB_OC#6 2 9 USB_OC#4 N27 C25
3D3V_S0

2
USB_OC#7 USB_OC#0 PETp5 DMI_ZCOMP DMI_IRCOMP_R
3 8 DMI_IRCOMP D25
SRN8K2J-2-GP USB_OC#1 4 7 USB_OC#3 T25
2 USB_OC#5 PERn6 2
RP5 3D3V_S5 5 6 T24 F1 USBPN0 21
PCI_DEVSEL# PERp6 USBP0N
1 10 3D3V_S0 R28 PETn6 USBP0P F2 USBPP0 21
PCI_LOCK# 2 9 PCI_SERR# SRN10KJ-L3-GP R27 G4 USBPN1 26 USB
PCI_REQ#3 INT_PIRQD# PETp6 USBP1N
3 8 USBP1P G3 USBPP1 26
INT_PIRQE# 4 7 INT_PIRQB# R2 H1 USBPN2 21 Pair Device
INT_PIRQA# 3D3V_S5 SPI_CLK USBP2N
3D3V_S0 5 6 P6 SPI_CS# USBP2P H2 USBPP2 21
TPAD30 TP84 SPI_ARB P1 J4 0 USB2

SPI
SPI_ARB USBP3N USBPN3 21
SRN8K2J-2-GP J3 USBPP3 21
RN38 SRN100KJ-6-GP USBP3P
P5 SPI_MOSI USBP4N K1 1 MINIC1
ECSWI# 3 2 P2 K2

USB
ECSMI# SPI_MISO USBP4P
3D3V_S0
4 1 USBP5N L4 USBPN5 21 2 USB3
USB_OC#0 D3 L5 USBPP5 21
USB_OC#1 OC0# USBP5P
C4 OC1# USBP6N M1 USBPN6 13 3 USB4
PM_CLKRUN# 1 2 21 USB_OC#2 USB_OC#2 D5 M2 USBPP6 13
R222 8K2R2J-3-GP USB_OC#3 OC2# USBP6P
21 USB_OC#3 D4 OC3# USBP7N N4 USBPN7 21 4 NC
ACZ_SPKR 2 R546
1 RN86 USB_OC#4 E5 N3 USBPP7 21
1KR2J-1-GP SMLINK0 USB_OC#5 OC4# USBP7P
3 2 21 USB_OC#5 C3 OC5#/GPIO29 5 USB1
ECSCI#_1 1 R229
2 SMLINK1 4 1 USB_OC#6 A2 D2 USB_RBIAS_PN
10KR2J-3-GP USB_OC#7 OC6#/GPIO30 USBRBIAS#
B3 OC7#/GPIO31 USBRBIAS D1 6 CAMERA
R231 10KR2J-3-GP SRN10KJ-5-GP

1
PWROK 3D3V_S5 ICH7-M-GP KI.80101.017
2 1 7 BLUETOOTH
R542
22D6R2F-L1-GP
1

R227 DY D14

2
4K7R2J-2-GP BAT54PT-GP
1 RSMRST#_SB
Default:H
2

1 31 RSMRST#_KBC 3 1
GNT5# GNT4#
1

2
LPC H H R236
10KR2J-3-GP Wistron Corporation
PCI H L 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2

SPI L H
Title

ICH7-M (2 of 4)
Size Document Number Rev

MYALL2 MP
Date: Thursday, March 30, 2006 Sheet 16 of 57
A B C D E
A B C D E

Layout Note:
Place near pin AA19 1D05V_S0

U65F

1
G10 L11 C348 C339 C344 C346 C357 C340
V5REF[1] Vcc1_05[1]

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC10U10V5ZY-1GP
Vcc1_05[2] L12
4 V5REF_S0 AD17 L14 4

2
V5REF[2] Vcc1_05[3]
Vcc1_05[4] L16
1D5V_S0 V5REF_S5 F6 L17
R237 0R0603-PAD V5REF_Sus Vcc1_05[5]
Vcc1_05[6] L18
1 2 1D5V_ICH7 AA22 M11
Vcc1_5_B[1] Vcc1_05[7]
AA23 Vcc1_5_B[2] Vcc1_05[8] M18

1
C740 C335 C362 C347 C736 C365 C382 C341

CORE
AB22 Vcc1_5_B[3] Vcc1_05[9] P11

1
SC10U10V5ZY-1GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC10U10V5ZY-1GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
AB23 P18 C331 C330 C360
Vcc1_5_B[4] Vcc1_05[10]

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
AC23 T11

2
Vcc1_5_B[5] Vcc1_05[11]

SCD1U10V2KX-4GP
AC24 T18

2
Vcc1_5_B[6] Vcc1_05[12]
AC25 Vcc1_5_B[7] Vcc1_05[13] U11 DY
AC26 Vcc1_5_B[8] Vcc1_05[14] U18
AD26 Vcc1_5_B[9] Vcc1_05[15] V11
AD27 Vcc1_5_B[10] Vcc1_05[16] V12
AD28 Vcc1_5_B[11] Vcc1_05[17] V14
*Within a given well, 5VREF needs to be up before the D26 Vcc1_5_B[12] Vcc1_05[18] V16
corresponding 3.3V rail D27 Vcc1_5_B[13] Vcc1_05[19] V17
D28 V18 3D3V_S5
Vcc1_5_B[14] VCC PAUX Vcc1_05[20]
E24 Vcc1_5_B[15]
E25 Vcc1_5_B[16] VccSus3_3/VccLAN3_3[1] V5
E26 Vcc1_5_B[17] VccSus3_3/VccLAN3_3[2] V1

1
3D3V_S0 5V_S0 F23 W2
Vcc1_5_B[18] VccSus3_3/VccLAN3_3[3] 3D3V_S0 C345 C333
F24 Vcc1_5_B[19] VccSus3_3/VccLAN3_3[4] W7
G22 SCD1U10V2KX-4GP SCD1U10V2KX-4GP

2
Vcc1_5_B[20]
2

G23 U6 3D3V_S5
D16 R228 Vcc1_5_B[21] Vcc3_3/VccHDA
H22 Vcc1_5_B[22]
CH751H-40PT 100R2J-2-GP H23 R7
Vcc1_5_B[23] VccSus3_3/VccSusHDA 1D05V_S0
J22 Vcc1_5_B[24]
J23 AE23
1

3 V5REF_S0 Vcc1_5_B[25] V_CPU_IO[1] 3


K22 Vcc1_5_B[26] V_CPU_IO[2] AE26
K23 AH26 3D3V_S0 C358 C314 C359

VCCA3GP
Vcc1_5_B[27] V_CPU_IO[3]
1

1
L22 Vcc1_5_B[28]

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC4D7U10V5ZY-3GP
C367 L23 AA7
Vcc1_5_B[29] Vcc3_3[3]

1
SCD1U16V2ZY-2GP M22 AB12 C327 C320
2

2
Vcc1_5_B[30] Vcc3_3[4]

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
M23 Vcc1_5_B[31] Vcc3_3[5] AB20
N22 AC16

2
Vcc1_5_B[32] Vcc3_3[6]
N23 Vcc1_5_B[33] Vcc3_3[7] AD13

IDE
Layout Note: 3D3V_S5 5V_S5 P22 AD18
Place near ICH7 Vcc1_5_B[34] Vcc3_3[8]
P23 Vcc1_5_B[35] Vcc3_3[9] AG12
R22 AG15 Layout Note: