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Engineering Science and Technology, an International Journal 19 (2016) 11601165

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Engineering Science and Technology,


an International Journal Press: Karabuk University, Press Unit
ISSN (Printed) : 1302-0056
ISSN (Online) : 2215-0986
ISSN (E-Mail) : 1308-2043

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Full Length Article

Design of Multiplier-less FIR lters with Simultaneously Variable


Bandwidth and Fractional Delay
Aravind Illa, Nisha Haridas *, Elizabeth Elias
Department of Electronics and Communication Engineering, National Institute of Technology Calicut, Kerala, India

A R T I C L E I N F O A B S T R A C T

Article history: Low complexity and recongurability are the key features in emerging communication applications in
Received 1 October 2015 order to support multi-standards and operation modes. To obtain these features, an ecient implemen-
Received in revised form tation of nite impulse response (FIR) lter, with Variable Bandwidth and Fractional Delay, is proposed
28 December 2015
in this paper. The reduction in the implementation complexity is achieved by converting the continu-
Accepted 28 December 2015
Available online 15 March 2016
ous lter coecients to signed power of two (SPT) space. This may lead to performance degradation.
Hence, in this paper, Articial Bee Colony (ABC) optimization is deployed for nding the near optimal
solution in the discrete space.
Keywords:
Variable bandwidth lter 2016 Karabuk University. Publishing services by Elsevier B.V. This is an open access article under the CC
Variable fractional delay lter BY-NC-ND license (http://creativecommons.org/ licenses/by-nc-nd/4.0/).
ABC optimization
Farrow structures
Multiplier-less

1. Introduction precision in the SPT space, by making use of the Canonic Sign Digit
(CSD) representation of the lter coecients. There are various
Applications such as spectrum sharing radios and emerging com- methods for minimizing coecient complexity in literature. Coef-
munication systems, which provide multi-modes, multi-standards cient complexity reduction includes reducing the coecient word
and multi-services, require variable bandwidth lters [13]. In order length and coecient representation using a limited number of
to support various operating modes variable fractional delay lters signed power-of-two (SPT) terms. Signed power-of-two represen-
are also considered. In the literature, design of some variable digital tation uses three-valued digits instead of binary digits, 0, 1 and 1.
lters are discussed in References 46. Canonic signed digit (CSD) is the special case of signed-digit power-
In this paper, the design method proposed in Reference 4 is con- of-two, with minimal number of non-zero digits. CSD has minimal
sidered. The overall lter structure is shown in Fig. 1. The impulse number of non-zeros. The multiplier components consume major
response is a two-dimensional polynomial in the bandwidth and power and area of a lter, and thus these are replaced by shifters
fractional delay parameters. In this structure, the overall transfer and adders. This may result in the performance degradation of the
function is a weighted linear combination of xed linear-phase FIR lter response. Hence, suitable optimization algorithms are needed
sublters cascaded with pre-designed farrow structure based vari- to improve the performances of the lter [710]. Since the search
able fractional delay. Variability is achieved by few adjustable space contains integers, the classical gradient-based optimization
parameters determined for the bandwidth and delay require- algorithms cannot be used [11]. In this paper, ABC optimization al-
ments. By utilizing the Farrow structures, the impulse response of gorithm is used because it is reported that ABC algorithms are
the lter based on polynomial realization supports the oine design especially useful for nding near optimal solutions in multi-
of xed FIR sublters and simple online update of variable multi- modal and multi-dimensional objective problems and can be tailor
pliers. Thus, updating is simple and is reported to have signicant made to suit the problem considered [7,9,12]. Multiplier-less design
savings in the number of multiplications and additions compared of FIR lter with variable bandwidth and variable delay with the
to the previous polynomial based realizations. coecients synthesized in the CSD form using modied meta-
A further reduction in complexity is proposed in this paper to heuristic algorithm is hitherto not reported in the literature.
represent the innite precision coecients of the lters by nite The paper is organized as follows. Section 2 gives an overview
of variable digital lters. Section 3 gives a brief introduction of CSD
representation and ABC algorithm. Section 4 gives the design of vari-
* Corresponding author. Tel.: +919895465581.
able digital lter using ABC optimization. The design example and
E-mail address: nisha_p120093ec@nitc.ac.in (N. Haridas). discussion on results are given in Section 5 and Section 6 respec-
Peer review under responsibility of Karabuk University. tively. Section 7 concludes the paper.

http://dx.doi.org/10.1016/j.jestch.2015.12.010
2215-0986/ 2016 Karabuk University. Publishing services by Elsevier B.V.
This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).
A. Illa et al./Engineering Science and Technology, an International Journal 19 (2016) 11601165 1161

Fig. 2. The realization of G(z, d) [4].

Fig. 1. The variable digital lter [4].

E (z , b , d ) = H (z , b , d ) D H (z , b , d ) (8)

2. Review of variable digital lters Hence, the design problem is reduced to the non-linear optimi-
zation problem, which has to minimize the complex error function
The desired frequency response of FIR lters with simultane- E (z , w , d ) in the region T = [0, b ] [b + , ] [4]. If the tar-
ously variable bandwidth and fractional delay, D H ( j T , b , d ) is given geted approximation error e is given, then the sublter orders NF
by Reference 4. It is based on Farrow structure [13], which is widely and NG are estimated as in Eq. (9) and then rounded to the nearest
used as variable fractional delay lters. Applications of this struc- even integers [4].
ture are detailed in Reference 14.
 F = 2 log10 (10 e ) , N
 G = 4 log10 (10 e )
2 2
N (9)
e j T (N H 2+d )
T [0, b ] 3 3( bu + )
D H ( j T , b , d ) = (1)
0, T [b + , ]
After nding an approximate order of sublters in F(z) and G(z)
Here, d and b are adjustable fractional delay and adjustable band- from Eq. (9), the number of sublters for each is to be deter-
width parameters, respectively, d [ 1 2 , 1 2] and b [bl , bu ], where mined. This is done by separately designing the VBW lter F(z, b)
bu, and bl respectively are the upper and lower bounds of the ad- and the VFD lter G(z, d) to approximate the functions in Eqs. (4)
justable bandwidth parameter b. For each pair of values of b and and (6) respectively with allowable error e. Finally, to nd the exact
d, the variable lter corresponds to a lowpass lter with a fraction- sublter order, at each combination of NF and NG close to the ap-
al delay of NH/2 + d in the passband, where NH is the order of the proximated values, VBW and VFD lters are designed using minimax
lter. This desired function can be approximated using a transfer algorithm. Johansson and Eghbali [4] designs the lter coecients
function H(z, b, d) in a cascade form [4] of order NH = NF + NG, given using minimax algorithm such that it approximates the ideal lter
by, response with minimum error. The proposed method optimizes error
as well as implementation complexity. This is achieved by con-
H (z , b , d ) = F (z , b )G (z , d ) (2) straining coecients to be in canonic signed digit (CSD) space. This
enables the lter to be implemented without multipliers and only
where, F(z, b) is a variable bandwidth lter given by Eq. (3), which using adders. Minimum possible number of adders, without com-
approximates the desired frequency response in Eq. (4), and promising the passband and stopband characteristics, is selected by
b 0 = (bl + bu ) 2 . Similarly, G(z, d) is a variable delay lter given by means of optimization (using an evolutionary algorithm Arti-
Eq. (5), which approximates the desired frequency response in Eq. cial Bee Colony algorithm (ABC)).
(6).
P 3. Overview of CSD and ABC algorithm
F (z , b ) = (b b 0 ) Fp (z )
p
(3)
p =0
The approximation of the innite precision multiplier coe-
cients of the variable digital lter into the SPT number
e jTN F 2
T [0, b ]
D F ( j T , b ) = (4) representations will give us great advantage in the reduction of the
0, T [b + , ] hardware complexity. In this paper, canonic signed digit represen-
tation is used. It is a special case of the signed power of two
K
representation system [7,15].
G (z , d ) = d k G k (z ) (5)
k =0
3.1. Canonic signed digit representation
DG ( j T , d ) = e jT (N G 2+d )
, T [0, bu ] (6)
The CSD representation uses a digit set that is ternary and each
where NF and NG are the orders of sub-lters Fp(z) and Gk(z) respec- digit may be either 1, 0, or +l. Adjacent CSD digits are never both
tively. The variable lter structure [4] is shown in Fig. 1 The lters non-zero, i.e., bi 1 bi = 0 . This property implies that for an n-bit
Fp(z) and Gk(z) are xed and are chosen to be linear phase FIR lters. number, there are at most n/2 non-zero digits. Any innite preci-
The lters G(z, d) are chosen to have farrow structure and the re- sion multiplier coecient c can be represented using the CSD format
alization is shown in Fig. 2. The transfer function of the variable as follows:
digital lter is given by
l
P c = bi 2R i (10)
H (z , b , d ) = Fp (z )G (z , d ) (b b 0 )
p
(7) i =1
p =0
where l is the word length of the CSD number and integer R rep-
The modulus of error between the desired and approximated resents a radix point in the range 0 < R < L. Besides, bi ( 1, 0, 1) .
transfer function is given by Hence, by CSD representation, multipliers can be replaced by shifters
1162 A. Illa et al./Engineering Science and Technology, an International Journal 19 (2016) 11601165

Table 1 coecients and Ab indicates the upper bound of A(X), then the ob-
A typical entry of the look-up-table. jective function is dened as follows
Index CSD representation Decimal equivalent Number of SPT terms
O ( X ) = 1E ( X ) + 2Z ( X ) (12)
7726 001000-10010-10-101 0.4715 6

where Z ( X ) = max (0, A ( X ) Ab ), 1 and 2 are the correspond-


ing weights for E(X) and Z(X) respectively. The weights of the
objective function in Eq. (12) are positive weighting coecients and
and adders. The number of partial product adders can be decided are selected considering the relative importance of each term in the
by the number of non-zero bits in the lter coecient represen- optimization problem, by means of trial and error to meet the re-
tation. Hence, reducing the number of non-zero bits in the lter quired lter specications and minimum number of non-zero
coecient representation will reduce the number of adders. CSD coecients. The various phases involved in the ABC algorithm to
is a unique representation for a given lter coecient, with minimum minimize the objective function, are given below [7]. An illustra-
number of non-zero bits. tion of the algorithm using ow chart is given in Fig. 3.

3.1.1. Encoding variables in the CSD space 4.1. Initialization of food source
In this paper, 16 bit CSD representation is considered to repre-
sent a decimal number, 14 bits are used for the fractional part and The CSD coecients of the xed sublters in the variable digital
2 bits are used for the integer part. A look-up-table with four elds lter are concatenated to generate the initial food source. Since all
is created, which contains index, CSD numbers, decimal equiva- the sublters Fp(z) and Gk(z) have linear phase, only half the number
lent and the number of non-zero SPT terms. A typical entry of the of coecients need to be considered. The other food sources are
look-up-table is shown in Table 1. generated by randomly perturbating the initial food source. In order
Since the sub-lters are linear phase lters, only half of the sym- to begin with a wider search space, the initial number of food sources
metrical coecients of the sub-lters of F(z, b) and G(z, d) are needed is selected to be an integer multiple of the number of employed bees.
to be used. Then obtain the corresponding signed indexes on the
look-up-table locations for the CSD equivalents of the extracted lter 4.2. Prioritized enlisting of food source
coecients. The signed indexes are concatenated together to form
an initial vector in the optimization problem. The tness values of the initial food sources are evaluated and
the food sources with a high tness value are passed on to the next
phase. The number of these prioritized food sources is taken as the
3.2. ABC optimization
same as the number of employed bees.
In Reference 16, the ABC algorithm is proved as an ecient op-
4.3. Employed bee phase
timization algorithm for nding out the potential solution for a
multidimensional, multi-modal optimization problem. The food
Employed bees search for a new food source within the neigh-
source represents the possible solution to the problem and the nectar
borhood position of the food source in the memory and evaluate
quantity determines its tness value. In ABC algorithm, the colony
their tness value. The new food source in the neighborhood of the
of articial bees contains three categories of bees: employed bees,
ith food source can be obtained by changing the randomly selected
onlooker bees and scout bees. Employed bees nd a food source
jth parameter value in the ith food source as in the equation given
within the neighborhood of the food source in their memory and
below
determine the nectar quality. If a food source with a higher nectar
amount is found, the employed bees memorize the new position x tij+1 = x tij + f ( x tij x tkj ) (13)
of the food source and forget the old food source position, else the
old food source position is retained. Employed bees share their in- where x tij is the jth parameter of the ith food source, x tij+1 is the jth
formation with the onlooker bees. An onlooker bee will wait in the parameter of the new food source at the neighborhood of the ith food
dance area for making the decision to choose a food source based source, is a random value in the range [1, 1], and j [1, 2, , D ]
on the nectar amount. The food source containing the high nectar and k [1, 2, , D ] are randomly chosen indexes. D is the dimen-
will have higher probability to get more number of onlooker bees. sion of the food source. is randomly selected in the range [1 1].
An employed bee whose food source has been abandoned becomes The random value taken in each iteration of the optimization al-
a scout and it will search randomly for a new food source. gorithm is used to decide a new set of possible solutions for the
ABC evolutionary algorithm. In order to prevent the new food source
4. Design of variable digital lter using ABC optimization from crossing the boundaries of the look-up-table, the steps given
below are to be followed.
The rounding-off of the innite precision coecients of the sub-
lters F(z, b) and G(z, d) with restricted SPT terms will degrade the if x tij+1 < v lb , then x tij+1 = v lb
performances [1719]. Hence, the main objective of the optimiza-
tion problem is to minimize the error of approximation, dened in if x tij+1 > v ub , then x tij+1 = v ub
the frequency domain as follows
where v lb and v ub are the lower and upper bounds, respectively,
E ( X ) = D H ( ) H c ( , X ) (11) of a parameter in a food source. If the new food source has higher
tness value than the old food source, then the old food source is
where Hc is response of the variable digital lter whose sub-lter replaced by the new food source in the memory.
coecients are in SPT terms and X represents an optimized vector
encoded in the CSD space. 4.4. Onlooker bee phase
In order to reduce the number of non-zero SPT terms in the CSD
space, an additional constraint has to be imposed on the objective Onlooker bees evaluate the tness value of the food source based
function. If A(X) represents the average number of nonzero SPT on the information shared by the employed bees and then they select
A. Illa et al./Engineering Science and Technology, an International Journal 19 (2016) 11601165 1163

Fig. 3. Flow diagram of ABC algorithm.

the food source based on probability. The food source that con- is followed by initially choosing an approximate order using Eq. (9).
tains high nectar amount will have higher probability to get more The nal values of P, K, NF and NG are arrived at by means of
number of onlooker bees than the food source with lower nectar minimax optimization techniques. For this example, these values
amount. The onlooker bees also modify the solution in their memory are found as, P = 4, K = 3, NF=26 and NG = 6. For comparison purpose,
similar to the procedure followed by the employed bees. the same specications given in example 1 in Reference 4 are chosen
here. Further b has 11 values evenly distributed between bl and bu
4.5. Scout bee phase and with 6 values of d evenly distributed between 0 and 1/2.
The parameters used in the ABC algorithm are 50 number of em-
This phase helps to carry out the random search. If there is no ployed bees and 50 number of onlooker bees, perturbation rate is
improvement in the tness values after a xed number of itera- 0.001, dimension of food source is 80, with weights 1 = 1 and
tions, then that food source is abandoned. The scout bees will search 2 = 0.0035 . The running time for optimization is 1204 seconds ob-
randomly for a new food source. In this search process, the scout tained for 500 maximum iterations. The modulus of the frequency
bees memorize the food source having the best tness value among response and error for the lter with continuous coecients, CSD
the entire randomly selected food sources. rounded and ABC optimized coecients are shown in Figs. 4, 5 and
6 respectively.
4.6. Termination phase Figs. 46 illustrate the performance of the lter with and without
multipliers in its implementation. The lter is initially designed for
The phases from 4.1 to 4.5 are repeated until the approxima- the given specication for variable bandwidth and variable frac-
tion error becomes less than the tolerance value specied or up to tional delay using Farrow based sublters by means of a simple
a predetermined number of iterations. After the termination, the minimax optimization. This results in continuous coecient im-
solution vector having the best tness value is taken and the CSD plementation of the structure, which requires multipliers for its
digits are decoded to obtain the optimum lter coecients. realization. The frequency response of such a lter across all de-
When the ternary encoding is used, dimension of the optimi- signed bandwidths is shown in Fig. 4. It is given in two parts: rst
zation problem is large. Also, restoration algorithms [12] are needed part being the magnitude response, showing stopband attenua-
to bring the non-canonical bit strings resulting from various op- tion clearly, and second is the zoomed version of the passband region,
erations into the CSD format. From the practical point of view, the showing the passband ripple to be 0.008 dB. The lter coecients
traditional approach to generate the CSD representation uses look- are thus designed and then rounded off to the nearest CSD repre-
up table. sentation using a 16-bit predesigned CSD look up table. A sample
entry is shown in Table 1. This representation is a special case of
5. Design example signed power of two and removes multipliers from the implemen-
tation. But the rounding off of the coecients degrades the lter
In this design example the specications are as follows: response as shown in Fig. 5, giving the passband ripple to be 0.015 dB.
bl = 0.22 , bu = 0.54 , = 0.12 , = 0.01. The method in Section 2 The proposed lter is designed by optimizing the CSD rounded
1164 A. Illa et al./Engineering Science and Technology, an International Journal 19 (2016) 11601165

Fig. 4. Modulus of the frequency response and error of the lter with continuous
coecients. Fig. 5. Modulus of the frequency response and error of the lter with CSD rounded
coecients.

Table 2
Performance and computational details of sub-lter xed coecients.
However, it is important to reduce hardware complexity without
Continuous CSD rounded ABC degradation in the lter response. Thus, using optimization tech-
coecient optimization nique, it is ensured that all the lters with variable bandwidths and
Max. passband ripple (dB) 0.0768 0.1605 0.08459 fractional delay can be recongured from the structure with the same
Min. stopband attenuation (dB) 41.0352 34.9840 40.5988 performance as that using continuous coecients, but with lower
No. of xed multipliers 120
number of LUTs. By deploying optimization techniques, the per-
No. of xed adders 210 210 210
No. of adders due to SPT terms 234 351 formances can be improved. Here, conventional gradient-based
Total adders 210 444 561 optimization cannot be used because the search space contains in-
tegers. Meta-heuristic Algorithms are reported to be good choices

coecients to have minimum non-zero terms as well as optimum


characteristics using ABC algorithm. The frequency response for this
is shown in Fig. 6, which has a passband ripple of 0.008 dB and is
achieved without multipliers in the design as seen in Table 2.
The performance and computational details of the xed sub-
lter coecients of F(z, b) and G(z, d) are given in Table 2.
Additionally 19 variable multipliers and 19 adders are required to
implement the structure in Figs. 1 and 2.
All simulations were done using MATLAB 7.10.0 on Intel Core2
Duo CPU operating at 3 GHz.

6. Result analysis

It can be observed from Fig. 4 that the results are very similar
to the results in Reference 4, where the lters are reported to result
in the least complexity when compared to earlier published results.
A 64% multiplications and 67% additions savings had been re-
ported in Reference 4 when compared to the previous polynomial
based realization [6].
In this paper, the coecients are represented in the CSD space. Fig. 6. Modulus of the frequency response and error of the lter with ABC opti-
But this is seen to degrade the performances as seen in Fig. 5. But mized coecients.
it has only adders and shifters, and no multipliers. This would have
reduced overall complexity, as suggested by their LUT utilization.

Table 3
Implementation complexity comparison of proposed method with References 4
and 6.

Design in Design in Proposed


Reference 4 Reference 6 method

Total multipliers 120 330 NIL


Total adders 210 630 561
Total LUTs 11 640 21 540 4488
Fig. 7. Group delay in passband for the lter with ABC optimized coecients.
A. Illa et al./Engineering Science and Technology, an International Journal 19 (2016) 11601165 1165

in such cases [9]. In this paper, the articial bee colony algorithm chip area. Multipliers are costly in terms of hardware implemen-
is used. This makes the performances very similar to the perfor- tation area. The current design is fully devoid of multipliers. This
mances in Reference 4 with continuous coecients as seen in Fig. 6 design is recongurable and has low delay due to the Farrow
and Table 3. There are 11 adjustable bandwidth parameters, b, evenly structure based design as in Reference 4. In addition to this, having
distributed between bl and bu. The group delay in the passband for lower hardware implementation complexity (signicantly lower
the lter with ABC optimized coecients is shown in Fig. 7. Since number of LUTs) makes the design ideal for real time applica-
in this paper, the same number of Farrow sublters and order of tions. Hence, in those applications such as systems that support
each sublter are employed in the multiplier-less realization of the different wireless communication standards and different modes,
example in Reference 4, the group delay remains the same as in Ref- this design leads to lower complexity and added recongurability.
erence 4. This value is reported in Reference 4 to be smaller than
when the technique in Reference 6 is used. It can also be seen that
d has 6 values evenly distributed between 0 and 1/2. This results References
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