In this experiment, we are expected to construct a half adder, full adder and a 4-bit adders.
Half adder is created with AND and OR gates and XOR and AND gates. Then we create a symbol for
half adder. After that, we have designed full adder by using AND and OR gates and two half adders
and OR gate. When we created a full adder which includes half adders, we have made another
symbol for full adder. For final part, we have designed a 4-bit adders with using 4 full adders and we
have assigned 9 inputs and 5 outputs respectively. Our equipments during this experiments were
Xilinx ISE Developlment Tool, Basys2 FPGA Development Board and Digilent Adept.

full adders and 4-bit parallel adders. we have made truth tables.Conclusion: To have a clear summation. . and how one adder contains another one inside of it. Before we start designing symbols for each of these. While designing the truth tables. how we are connected to each other. we have seen and experienced the internal structures of half adders. we have seen the internal structures. Half adder can be considered as the simplest part of the device while the 4-bit parallel adder is the most complicated. since it contains full adders.

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