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Islamic University of Gaza Computer Architecture ECOM 3310

Faculty of Engineering Instructor: Dr.wesam ashour
Computer Department T.A: Eng. Doaa KH. Abu Jabal

Quiz (5)
Question (1):

Part a. For the instructions beq and lw, fill out the table of control signals below. Use an X to indicate that a
control signal is a “don’t care”— that it it doesn’t matter whether the signal is 1 or 0.

Solution

insn RegDst Jump Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite

beq X 0 1 0 X 01 0 0 0

lw 0 0 0 1 1 00 0 1 1

Part B. Consider the single-cycle MIPS implementation we studied in Chapter 5. List the value of the control
signals associated with the following instruction:

sw $t0,0($t1).

RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch Jump

Answer:

RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch Jump

x 1 x 0 0 1 0 0

This instruction is described in Chapter 3.wesam ashour Computer Department T. Add any necessary datapaths and control signals to the multicycle data path if needed . Doaa KH. Solution: add a "bne" signal to the control and connect it as follows: Part (B): We wish to add the instruction addi (add immediate) to the multicycle datapath described in Chapter 5.Islamic University of Gaza Computer Architecture ECOM 3310 Faculty of Engineering Instructor: Dr. Abu Jabal Question (2): Part (A): We wish to add the instruction bne (branch if not equal) which is described in chapter 3 to the single-cycle datapath described in Chapter 5. and show the necessary modifications to the finite state machine . only do the following state sequence: Normal FETCH Normal DECODE ALUSrcA=1 ALUSrcB=10 ALUOp =00 RegWrite MemtoReg=0 RegDst =0 The illustrated instruction format will insure reading while decoding Total number of cycles will be 4. Add any necessary datapaths and control signals to the single-cycle datapath of the Figure attached. .A: Eng. Solution No changes are needed to data path. Please explicitly state how many cycles it takes to execute the instruction on your finite state machine.