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TRC103 868-960 MHz RF Transceiver

• Multi-channel • Programmable • Low current

TRC103 868-960 MHz Transceiver

Complies with Directive 2002/95/EC (RoHS) Product Overview
TRC103 is a highly integrated single chip, multi-channel, low power RF transceiver. It is an ideal fit for low cost, high volume, two way short-range wireless applications for use in the unlicensed 868-870 MHz (ETSI) and 902-928 MHz (FCC) frequency bands. The TRC103 is FCC & ETSI certifiable. All critical RF and baseband functions are completely integrated in the chip, thus minimizing external component count and simplifying and speeding design-ins. Use of a low cost, generic 12.8 MHz crystal and a low-cost microcontroller is all that is needed to create a complete link. The TRC103 also incorporates different sleep modes to reduce overall current consumption and extend battery life. Its small size with low power consumption makes it ideal for various short range radio applications.

Key Features
• • • • • • • • • • • • • • • • • • Modulation: OOK/FSK (Frequency Hopping Spread Spectrum capability) Frequency range: 868-960 MHz High sensitivity: -108 dBm High data rate: Up to 100 kbps Ultra Low current consumption (RX current ~3.5mA) +13 dBm TX Output Power Operating supply voltage: 2.1 to 3.6V Low sleep current (0.2uA) Programmable 32-bit Sync Byte Integrated PLL, IF, Baseband Circuitry Integrated Data and Clock Recovery Programmable Output RF Power Internal Valid Data Recognition Transmit/Receive FIFO Programmable 64-byte Tx/Rx FIFO depth Protocol Mode Packet Protocol Address Recognition Packet Handling Features: • Variable Packet Length • Packet Filtering • Packet Formatting Standard SPI Interface TTL/CMOS Compatible I/O pins Programmable CLK Output Freq Low cost, generic 12.8 MHz Xtal reference Integrated RSSI Integrated Crystal Oscillator External Processor Interrupt pins Programmable Data Rate External Wake-up Events Integrated packet CRC Integrated Data Whitening Integrated Manchester Encoding/Decoding Interrupt Signal Mapping Function

• • • • •

Support for Multiple Channels Power-saving sleep mode Very low external component count Small size plastic package: 32-pin QFN Standard 13 inch reel, 3K pieces.

Popular applications
• • • • • • • • • • • • Active RFID tags Automated Meter reading Home & Industrial Automation Security systems Two way Remote keyless entry Automobile Immobilizers Sports & Performance monitoring Wireless Toys Medical equipment Low power two way telemetry systems Wireless mesh sensors Wireless modules

• • • • • • • • • • • • •

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Page 1 of 43 TRC101 - 4/8/08

Table of Contents
1.0 TRC103 Pin Configuration ........................................................................................ 4 2.0 Pin Descriptions ........................................................................................................ 4 3.0 Functional Description............................................................................................... 5 4.0 Architecture ............................................................................................................... 5 4.1 RF Port................................................................................................................. 6 4.2 Transmitter ........................................................................................................... 7 4.3 Receiver ............................................................................................................... 8 4.4 Crystal Oscillator .................................................................................................. 9 4.5 Frequency Synthesizer....................................................................................... 10 4.6 PLL Loop Filter................................................................................................... 10 5.0 Operating Modes..................................................................................................... 11 5.1 Receiver in Continuous Mode ............................................................................ 12 5.1.1 Continuous Mode Data/Clock Recovery..................................................... 13 5.1.2 Continuous Mode Sync Pattern Recognition.............................................. 14 5.1.3 RSSI........................................................................................................... 14 5.2 Receiver in Buffered Mode................................................................................. 15 5.3 Transmitter Modes (Buffered and Continuous) .................................................. 17 6.0 Interrupt IRQx Mapping ........................................................................................... 18 7.0 External Clock Output ............................................................................................. 19 8.0 Packet Processing Features ................................................................................... 19 8.1 Fixed Length Packet Mode................................................................................. 19 8.2 Variable Length Packet Mode ............................................................................ 20 8.3 TX/RX Packet Payload Processing .................................................................... 20 8.4 Packet Filtering .................................................................................................. 22 8.5 CRC ................................................................................................................... 22 8.6 Data Whitening................................................................................................... 22 8.7 Manchester Coding ............................................................................................ 23 9.0 Serial SPI Control Interface..................................................................................... 23 9.1 Data transmission and reception via SPI_DATA interface ................................. 25 10.0 Register Memory Map ........................................................................................... 27 10.1 Main Configuration Registers ........................................................................... 28 MCFG00.............................................................................................................. 28 MCFG01.............................................................................................................. 28 MCFG02.............................................................................................................. 28 MCFG03.............................................................................................................. 29 MCFG04.............................................................................................................. 29 MCFG05.............................................................................................................. 29 MCFG06.............................................................................................................. 29 MCFG07.............................................................................................................. 29 MCFG08.............................................................................................................. 29 MCFG09.............................................................................................................. 29 MCFG0A ............................................................................................................. 30 MCFG0B ............................................................................................................. 30 RF Monolithics, Inc.
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MCFG0C ............................................................................................................. 30 10.2 IRQx Configuration Registers........................................................................... 31 IRQCFG0D.......................................................................................................... 31 IRQCFG0E.......................................................................................................... 32 IRQCFG0F .......................................................................................................... 32 10.3 Receiver Configuration Registers..................................................................... 33 RXCFG10............................................................................................................ 33 RXCFG11............................................................................................................ 33 RXCFG12............................................................................................................ 34 RXCFG13............................................................................................................ 34 RXCFG14............................................................................................................ 34 RXCFG15............................................................................................................ 35 10.4 Sync Pattern Configuration Registers .............................................................. 36 SYNCFG16 ......................................................................................................... 36 SYNCFG17 ......................................................................................................... 36 SYNCFG18 ......................................................................................................... 36 SYNCFG19 ......................................................................................................... 36 10.5 Transmitter Configuration Register.................................................................. 36 TXCFG1A............................................................................................................. 36 10.6 Oscillator Configuration Register..................................................................... 37 OSCFG1B ............................................................................................................ 37 10.7 Packet Handler Configuration Registers .......................................................... 37 PKTCFG1C ......................................................................................................... 37 PKTCFG1D ......................................................................................................... 37 PKTCFG1E ......................................................................................................... 38 10.8 Page Configuration Registers .......................................................................... 38 PGCFG1F ........................................................................................................... 38 11.0 Electrical Ratings .................................................................................................. 39 11.1 DC Electrical Characteristics............................................................................ 39 11.2 AC Electrical Characteristics ............................................................................ 40 12.0 Package Dimensions ............................................................................................ 42

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1.0 Pin Configuration

2.0 Pin Descriptions PIN TYPE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PAD O I/O I/O I/O I/O

NAME
GND GND VDD_VCO TANK_TANK_+ PLL_PLL-+ GND GND XTAL XTAL GND NC nSS_CONFIG nSS_DATA MISO MOSI SCK CLKOUT DATA IRQ0 IRQ1/DCLK PLL_LOCK GND GND VDD VDD_ANALOG VDD_DIG VDD_PA GND RFRF+ GROUND

DESCRIPTION
CONNECT TO GND CONNECT TO GND REGULATED SUPPLY FOR VCO VCO TANK VCO TANK PLL LOOP FILTER PLL LOOP FILTER CONNECT TO GND CONNECT TO GND CRYSTAL CONNECTION CRYSTAL CONNECTION CONNECT TO GND NO CONNECT - FLOAT IN NORMAL OPERATION SLAVE SELECT FOR SPI CONFIGURATION DATA SLAVE SELECT FOR SPI TX/RX DATA SERIAL DATA OUT SERIAL DATA IN SERIAL SPI CLOCK IN OUTPUT CLOCK SIGNAL TRANSMIT/RECEIVE DATA INTERRUPT OUTPUT INTERRUPT OUTPUT/RECOVERED DATA CLOCK (CONT MODE) PLL LOCKED INDICATOR CONNECT TO GND CONNECT TO GND MAIN 3.3V SUPPLY VOLTAGE REGULATED SUPPLY FOR ANALOG CIRCUITRY REGULATED SUPPLY FOR DIGITAL CIRCUITRY REGULATED SUPPLY FOR RF POWER AMP CONNECT TO GND RF I/O RF I/O GROUND PAD ON PKG BOTTOM Email: support@rfm.com

I I

I I O I I O I/O O O O

I O O O I/O I/O I

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3.0 Functional Description
The TRC103 is a single chip transceiver operating in the 868-870 and 902-928 MHz license-free ISM (Industry, Scientific and Medical) frequency bands, as well as the 950-960 MHz band. It allows two modulation schemes to be used: FSK and OOK. Its highly integrated architecture allows for minimum external components while maintaining design flexibility. All major RF communication parameters are programmable and most of them can be dynamically set. The TRC103 is optimized for very low power consumption (3.5 mA in full receiver mode). It complies with European (ETSI EN 300-220-1) and North American (FCC part 15) regulatory standards. Advanced digital features like FIFO and packet handling modes allow the load of the external MCU to be significantly reduced.

4.0 Architecture

Figure 1. Internal Architecture The receiver is based on a super-heterodyne structure. It is composed of the following blocks: • an LNA providing RF gain and selectivity, • the first mixer down-converting the signal to an intermediate frequency equal to 1/9th of the carrier frequency (about 100 MHz for 915 MHz signals), • an IF amplifier with programmable gain, • the second mixers down-converting the IF signal to I and Q signals at a very low frequency (zeroIF for FSK, low-IF for OOK), • a filtering-amplification chain performing the channel filtering and the amplification limiting of the signals for the demodulator; this chain also includes an RSSI function; the main channel filter is a 3rd order Butterworth low-pass filter,

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• the digital demodulator providing the FSK demodulated bit stream by processing the I and Q signals; an additional circuitry provides the clock allowing the output bit stream to be properly sampled; the bit stream from the OOK signal is obtained by processing the data from the RSSI. The transmitter is based on the same double-conversion architecture using the same intermediate frequencies. The main blocks are the following: • a waveform generator providing the I and Q base-band signals; this block includes a DDS, A/D converters and low-pass filters, • the first image rejection mixers up-converting the base-band signals to the IF at 1/9th of the carrier frequency, • the second image rejection mixers up-converting the IF signal to the definite RF frequency, • The power amplifier driving the antenna. The frequency synthesizer is based on an integer-N PLL having a variable step whose average is about 12.5 kHz. Two programmable frequency dividers in the feedback loop of the PLL and one programmable divider for the reference signal allow the LO frequency to be adjusted. The reference frequency is generated by a crystal oscillator working at 12.8 MHz. Regulators are implemented on-chip to provide stabilized supply voltages to the sensitive blocks and to allow the chip to be used with batteries with voltages from 2.1 V to 3.6 V. Most of the blocks are supplied at a voltage below 1.6 V. The control of the circuit is performed by a top-level digital block. This block includes the configuration registers storing all the settings of the circuit which can be accessed by an external micro-controller via a serial interface.

TRC103 Typical Application Circuit

Figure 2. Recommended Application Circuit

4.1 RF Port
The receiver and the transmitter share the same RF pins. Figure 3 below shows the implementation of the common front-end. In transmit mode, the PA and the PA regulator are on; the voltage on VDD_PA pin is the nominal voltage of the regulator, about 1.8 V. The external inductances L1 and L2 are used for the PA. In receive mode, both PA and PA regulator are off, and VDD_PA is tied to ground. The external

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inductances L1 and L2 are used for biasing and matching the LNA, which is implemented as a common gate amplifier.

Figure 3. Internal RF Port Structure

4.2 Transmitter
The TRC103 is set to transmit mode when MCFG00_Chip_mode[7..5] is set to “100”. In continuous mode the transmitted data is sent directly to the modulator. The external micro-controller is provided with a clock by the TRC103 to generate this data; using this clock to send the data synchronously is mandatory in FSK configuration and optional in OOK configuration. In buffered mode the data is first written into the 64 byte FIFO via the SPI interface; data from the FIFO is then used by the modulator. At the front end of the transmitter, I and Q signals are generated by the base-band circuit which contains a digital waveform generator, two D/A converters and two anti-aliasing low-pass filters. The I and Q signals are two quadrature sine signals whose frequency is the selected frequency deviation. In FSK mode, the phase shift between I and Q is switched between 90° and -90° according to the input data. The modulation is then performed at this stage, since the information contained in the phase shift will be converted into a frequency shift when the I and Q signals are combined in the first mixers. In OOK mode, the phase shift is kept constant whatever the data. The combination of the I and Q signals in the first mixers will then create a fixed frequency signal at a low intermediate frequency which is equal to the selected frequency deviation. After D/A conversion, both I and Q signals are filtered by the anti-aliasing filter whose bandwidth can be programmed with the register TXCFG1A_TXInterpfilt[7..4]. Behind the filters, a set of four mixers combines the I and Q signals and converts them into two I and Q signals at the second intermediate frequency which is equal to 1/8 of the LO frequency, which in turn is equal to 8/9 of the RF frequency. These two new I and Q signals are then combined and up-converted to the desired RF frequency by two quadrature mixers fed by the LO signals. The signal is then amplified by a preamplifier and the last Power Amplifier stage. The OOK modulation is performed by switching on and off the PA stage and the PA regulator. The rise and fall times of the OOK signal can be adjusted via the register MCFG0C_PA_ramp[4..3], which controls the charge and discharge time of the regulator. Figure 4 below shows the time constants depending on the content of MCFG0C_PA_ramp[4..3]. Table 1 below gives typical values of the rise and fall times as defined in Figure 4 when the capacitance connected to the output of the regulator is 0.047uF. Table 1. Rise/Fall times of PA MCFG0C_PA_ramp[4..3] 00 01 10 11 TPA (usec) 3 8.5 15 23 Rise/fall (usec) 2.5/2 5/3 10/6 20/10

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VDD_PA (V)

Figure 4. OOK PA_ramp waveform

4.3 Receiver
The TRC103 is set to receive mode when MCFG00_Chip_mode[7..5] is set to “011”. The receiver is based on a double conversion architecture. The front-end is composed of an LNA and a mixer whose gains are constant. The mixer down-converts the RF signal to an intermediate frequency which is equal to 1/8 of the LO frequency, which in turn is equal to 8/9 of the RF frequency. Just behind this first mixer there is an IF amplifier whose gain is variable and can be programmed from -13.5 dB to 0 dB in 4.5 dB steps with the MCFG01_IF_Gain[1..0] register. After the IF amplifier, the signal is down-converted into two I and Q base-band signals by two quadrature mixers which are fed by reference signals at 1/8 the LO frequency. These I and Q signals are then filtered and amplified before demodulation. The first filter is a second order passive RC filter whose bandwidth can be programmed to 16 values with the register RXCFG10_LP_filt[7..4]. The second filter is a third order Butterworth active filter which acts as a low-pass filter for zero-IF configuration or as a (pass-band) complex polyphase filter for low-IF configuration. The zero-IF configuration must be used for FSK modulation. For selecting this last configuration, the bit RXCFG12_PolyFilt_En has to be set low. The bandwidth of the filter can be programmed to 16 values with the register RXCFG10_BW_Filt[3..0]. The low-IF configuration must be used for OOK modulation. This configuration is enabled when the bit RXCFG12_PolyFilt_En is set high. The center frequency of the polyphase filter can be programmed to 16 values with the register RXCFG11_PolyFilt[7..4]. The bandwidth of the filter can be programmed with the register RXCFG10_BW_Filt[3..0]. In OOK mode, the value of the low-IF is equal to the deviation frequency defined in register MCFG02_Freq_dev[7..0]. Besides the channel filtering, the function of the polyphase filter is also to reject the image. Figure 5 below shows the two configurations of the active filter, where f0 is the center frequency given by RXCFG11_PolyFilt[7..4], and fC is the bandwidth of the filter whose offset referenced to f0 is given by RXCFG10_BW_Filt[3..0].

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Figure 5. Baseband Filter Configurations After filtering, the I and Q signals are amplified by a chain of 11 amplifiers having 6 dB of gain each. The outputs of these amplifiers as well as their intermediate 3dB nodes are used to evaluate the signal strength (RSSI). A last limiter is located behind the 11 amplifiers of the I and Q chains and the signals at the output of these limiters are used by the FSK demodulator, whereas the RSSI output is used by the OOK demodulator. The global bandwidth of the whole base-band chain is given by the bandwidths of the passive filter, the Butterworth filter, the amplifier chain and the limiter. The maximum achievable global bandwidth when the bandwidths of the first three blocks are programmed at their upper limit is about 350 kHz.

4.4 Crystal Oscillator
The crystal for the reference frequency of the TRC103 should have the following typical characteristics: Table 2. Crystal Parameters Name Fs CL Rm Cm C0 Dfs(0) Dfs(DT)) Dfs(Dt) Description Nominal frequency Load capacitance for Fs Motional resistance Motional capacitance Shunt capacitance Calibration tolerance at 25 °C Stability over temperature range (-40 °C to 85 °C) Aging tolerance in first 5 years Min value 13.5 pF 5 fF 1 pF Typ value 12.8 MHz (fundamental) 15 pF <±20 ppm <±2ppm/yr Max value 16.5 pF 50Ω 20 fF 7 pF (1)

(1) Note: the tolerances have to be in accordance with the accuracy requested on all the frequency parameters. The relative error of the crystal will directly add to the relative error on the carrier frequency, the bit rate and the frequency deviation.

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4.5 Frequency Synthesizer
The Frequency Synthesizer generates the local oscillator (LO) signal for the receiver section as well as the transmitter section. The core of the synthesizer is implemented with an integer-N PLL architecture. The frequency is programmable via the three divider ratios R, P and S. R is the ratio of the frequency divider in the reference frequency path, whereas P and S are the dividers in the feedback loop of the PLL. The frequency synthesizer includes a crystal oscillator which provides the frequency reference for the PLL. The main equations giving the relations between the reference, LO and RF (carrier) frequencies are given below:

fLO is the LO frequency, which is also the frequency at which the VCO is running; fxtal is the crystal frequency; fcomp is the comparison frequency which is also the reference frequency at the input of the phase-frequency detector; fRF is the RF (carrier) frequency. fLO is the frequency used for the first down-conversion of the receiver and the second up-conversion of the transmitter. The intermediate frequency used for the second down-conversion of the receiver and the first up-conversion of the transmitter is equal to 1/8 of fLO. As an example, with a crystal frequency of 12.8MHz and an RF frequency of 869 MHz, fLO is 772 MHz and the first IF of the receiver is 96.6 MHz. There are two sets of divider ratio registers;SynthR1[7..0], SynthP1[7..0], SynthS1[7..0], and SynthR2[7..0], SynthP2[7..0], SynthS2[7..0]. The MCFG00_RF_Frequency bit is used to select which set of registers to use as the current frequency setting. For frequency hopping applications, this reduces the programming and synthesizer settling time when changing frequencies. While the data is being transmitted, the next frequency is programmed and ready. When the current transaction is complete, the MCFG00_RF_Frequency bit is complemented and the frequency shifts to the next freq according to the contents of the divider ratio registers. This process is repeated for each frequency hop.

4.6 PLL Loop Filter
The loop filter for the frequency synthesizer is shown in Figure 6 below.

Table 3. PLL Loop Filter Component Values Name C8 C9 R1 All Bands 680 pF 0.01 uF 6.8kΩ Tolerance ±10% ±10% ±5%

Figure 6. PLL Loop Filter Typical recommended component values for the frequency synthesizer loop filter are provided in Table 3 above. The loop filter settings are not dependent on the frequency band, so they can be universally used on all designs.

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5.0 Operating modes
The TRC103 has 5 possible working modes. The actual mode is given by the value of MCFG00_Chip_mode[7..5], which is a 3-bit word in the configuration register. Table 4 below summarizes the working modes. Table 4. TRC103 working Modes MCFG00_Chip_mode[7..5] 000 001 010 011 100 MODE Sleep mode Standby mode Synth mode Receive mode Transmit mode Enabled blocks None Crystal oscillator Crystal and Frequency synthesizer Frequency synthesizer and receiver Frequency synthesizer and transmitter

Table 5 below gives the status of the digital pads for the different chip modes and settings. Table 5. I/O status for chip modes
PIN Func NSS_CONFIG* NSS_DATA IRQ0 IRQ1 DATA CLKOUT SDO SDI SCK SLEEP MODE I I TRI TRI TRI TRI O** I I STANDBY MODE I I O O TRI O O** I I SYNTH MODE I I O O TRI O O** I I RX MODE I I O O O O O** I I TX MODE I I O O I O O** I I
I=INPUT, O=OUTPUT, TRI=HIGH IMPEDANCE *NSS_CONFIG HAS PRIORITY OVER NSS_DATA **If NSS_CONFIG=’0’ or NSS_DATA=’0’

The TRC103 transmitter and receiver sections have three modes of operation (registers MCFG01_Mode and MCFG01_Packet_Hdl_en): - Continuous mode: each bit transmitted or received is accessed directly at the DATA input/output pin. - Buffered mode: a 64-byte FIFO is used to store each data byte transmitted or received; this data is written to/read from the FIFO via the SPI bus. - Packet Handling mode: besides the use of the FIFO, the circuit builds the complete packet in transmit mode and extracts the useful data from the packet in receive mode; this packet includes a preamble, a recognition pattern (or “sync word”), an address and the data; on request, the circuit can also perform additional operations like CRC and data whitening. The Buffered and Packet Handling modes allow processor overhead to be significantly reduced. The DATA pin is bi-directional and is used in both transmit and receive modes. In receive mode, DATA represents the demodulated received data. In transmit mode the input data is applied to this pin. The actual length of the FIFO can be modified and set to 16, 32, 48 or 64 bytes through the MCFG05_Fifo_depth[7..6] register. In the next sections describing the FIFO behaviour, the explanations are given with an assumption of 64 bytes, but the principle is the same for all the four possible FIFO sizes. The status of the FIFO can be monitored via interrupts which are described in section 6.0. Besides the straightforward nFIFOEMPY and FIFOFULL interrupts, additional configurable interrupts Fifo_Int_Tx and Fifo_Int_Rx are also available.

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A low to high transition occurs on Fifo_Int_Rx when the number of bytes in the FIFO (#byte) is greater than or equal to the threshold set by MCFG05_FIFO_thresh[5..0] (#byte ≥ FIFO_thresh). A low to high transition occurs on Fifo_Int_Tx when the number of bytes in the FIFO (#byte) is less than or equal to the threshold set by MCFG05_FIFO_thresh[5..0] (#byte ≤ FIFO_thresh).

5.1 Receiver in Continuous Mode

Fig 7. Receiver in Continuous Mode The receiver works in continuous mode when the MCFG01_Mode[5] bit is set ‘low’. In this mode, the receiver has two output signals indicating recovered clock, DCLK and recovered NRZ bit DATA. DCLK is connected to output pin IRQ1 and DATA is connected to pin DATA configured in output mode. The Data/Clock Recovery controls the recovered clock signal, DCLK. If the Data/Clock Recovery is enabled by setting the bit RXCFG12_DCLK_Dis to “0” (default value), the clock recovered from the incoming data stream appears at DCLK. If the Data/Clock Recovery is disabled, the DCLK output is held low and the demodulator output appears at DATA. The function of the Data/Clock Recovery is to remove glitches from the data stream and to provide a synchronous clock at DCLK. The output DATA is valid at the rising edge of DCLK as shown in Figure 7. The demodulator section comprises FSK demodulator, OOK demodulator, Data/Clock Recovery, and Pattern Recognition blocks. If FSK is selected, the demodulation is performed by analyzing the phase between the I and Q limited signals at the output of the base-band channels. If OOK is selected, the demodulation is performed by comparing the RSSI output value (stored in RXCFG14_RSSI (7..0) register) to the threshold which can be either a fixed value or a time-variant value depending on the past history of the RSSI output. Table 6 gives the three main possible procedures, which can be selected via the register MCFG01_RX_OOK(4..3).

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Mode
Fixed Threshold Peak Average

Table 6. OOK Detection Modes MCFG01_RX_OOK(4..3) Description
00 01 10 RSSI output is compared with a fixed threshold stored in MCFG04_OOK_thresh(7..0) RSSI output is compared with a threshold which is at a fixed offset below the maximum RSSI. RSSI output is compared with the average of the last RSSI values.

If the end-user application requires direct access to the output of the demodulator, then the RXCFG12_DCLK_Dis bit is set high disabling the clock recovery. In this case the demodulator output is directly connected to the DATA pin and the IRQ1 pin (DCLK) is set to low. In FSK mode, for proper operation of the demodulator the modulation index β of the input signal should meet the following condition:

2∆f β= BR
where ∆f is the frequency deviation and BR is the data rate in bits per second (bps).

≥ 2,

5.1.1 Continuous Mode Data/Clock Recovery
The raw output signal from the demodulator may contain jitter and glitches. The Data/Clock Recovery converts the data output of the demodulator into a glitch-free bit-stream DATA and generates a synchronized clock DCLK to be used for sampling the DATA output (see below). DCLK is available on pin IRQ1 when the chip operates in continuous mode.

Figure 8. Data/Clock Recovery Timing To ensure the correct operation of the Data/Clock Recovery, the following conditions have to be satisfied: -A preamble of 24 bits is required for synchronization -The preamble must be a sequence of ‘0’ and ‘1’ sent alternatively -The bit stream must have at least one transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ every 8 bits during data transmission -The bit rate accuracy must be better than 2 %. The Data/Clock Recovery is enabled by default. It is controlled by RXCFG12_DCLK_Dis. If the Data/Clock Recovery is disabled the output of the demodulator is directed to DATA and the DCLK output (IRQ1 Pin in continuous mode) is set to ‘0’. The received bit rate is defined by the value of the MCFG03_Bit_Rate(6..0) configuration register, and is calculated as follows: Fxtal Bit Rate = , 0 ≤ D ≤ 127 64 (D+1) where fXTAL is the crystal frequency, and D is the value stored in MCFG03_Bit_Rate(6..0). As an example, with a 12.8 MHz crystal, the bit rate is 25 kb/s when D = 7.

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5.1.2 Continuous Mode Sync Pattern Recognition
In receive mode this feature is activated by setting the RXCFG12_Recog bit to ‘1’. The demodulated signal is compared with a pattern stored in the SYNCFG registers. The PATTERN signal (mapped to output pin IRQ0) is driven by the output of this comparator and is synchronized by DCLK. It is set to high when a matching condition is detected, otherwise set to low. PATTERN output is updated at the rising edge of DCLK. The number of bits used for comparison is defined in the RXCFG12_Pat_sz[4..3] register PATTERN and the number of tolerated errors for the pattern recognition is defined in the RXCFG12_Ptol[2..1] register. Figure 9 illustrates the pattern matching process.
SYNC_PAT0 [7..0]

Figure 9. Pattern Matching Process* *Pattern matching is enabled ONLY if the Data/Clock Recovery is enabled

5.1.3 RSSI
The signal strength is measured in the amplifier chain behind the second mixer. This amplifier chain is composed of 11 amplifiers having a gain of 6 dB and an intermediate output at 3 dB. By monitoring the two outputs of each limiter, an estimation of the signal strength with a resolution of 3 dB and a dynamic range of 63dB is obtained. This estimation is performed 16 times over a period of the I and Q signals, and these 16 samples are averaged to obtain a final RSSI value with a 0.5 dB step. The period of the I and Q signal is the inverse of the deviation frequency, which is the low-IF frequency in OOK mode. The RSSI block can also be used in interrupt mode by setting the bit IRQCFG0E_RSSI_Int to “1”. WhenRXCFG14_RSSI[7..0] is equal or greater than a predefined value stored in IRQCFG0F_RSSI_thld [7..0], the bit IRQCFG0E_SIG_DETECT (which can be read) goes high and an interrupt signal RSSI_IRQ is generated on pin IRQ0 if IRQCFG0D_RX_IRQ0[7..6] is set to “01” (see Table 7). The interrupt is cleared by writing a ‘1’ to the bit IRQCFG0E_SIG_DETECT. If the bit RSSI_IRQ remains high, the process starts again. Figure 10 shows the timing diagram of RSSI in interrupt mode.

RSSI_Int RSSI SIG DETECT

RSSI_IRQ

Figure 10. Receiver in Buffered Mode

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Figure 11. Receiver in Buffered Mode The receiver works in buffered mode when the MCFG01_Mode[5] bit is set ‘high’. In this mode, the output of the Data/Clock Recovery, i.e. the demodulated and resynchronized signal and the clock signal DCLK are not sent directly to the output pins DATA and IRQ1 (DCLK). These signals are used to store the demodulated signal by packet of 8 bits in a 64 bytes FIFO. Figure 11 shows the receiver chain in this mode. The FSK and OOK demodulators, Data/Clock Recovery and pattern matching block work as described in section 5.1.1 but they are used with two additional blocks, FIFO and SPI. When the chip is in receive mode and the MCFG01_Mode [5] bit is set ‘high’, then all the blocks described above are enabled. In a normal communication frame the data stream comprises a 24 bit preamble, a pattern and the data. Upon receipt of the right pattern, the receiver recognizes the start of a frame, strips off the preamble and pattern, then transmits the data to the microcontroller. This automated data recovery reduces the overhead for the host controller. The IRQCFG0E_Start_Fill bit determines how the FIFO is filled. If IRQCFG0E_Start_Fill is low, data only fills the FIFO subject to a correct pattern match. Data is shifted into the pattern recognition block which continuously compares the received data with the contents of the SYNCFG registers. If a match occurs a start sequence is detected, and the internal output of the pattern matching block is asserted for one bit length and the IRQCFG0E_Start_Det bit is also asserted. This internal signal may be mapped to the IRQ0 output using interrupt signal mapping. Once a pattern match has occurred, the pattern recognition block will remain inactive until IRQCFG0E_Start_Det is reasserted. If IRQCFG0E_Start_Fill is high, FIFO filling is initiated by asserting IRQCFG0E_Start_Det. Once 64 bytes have been written to the FIFO the IRQCFG0D_FIFOFULL signal is asserted. Data should then normally be read out. If no action is taken the FIFO will overflow and subsequent data will be lost. If this occurs the IRQCFG0D_FIFO_OVR bit is set high. The IRQCFG0D_FIFOFULL signal can be mapped to pin IRQ1 as an interrupt for a microcontroller if IRQCFG0D_RX_IRQ1[5..4] is set to “01”.

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To recover from an overflow situation a “1” must be written to IRQCFG0D_FIFO_OVR; this clears the contents of the FIFO, resets all FIFO status flags and re-initiates pattern matching. Pattern matching can also be re-initiated during a FIFO filling sequence by writing a “1” to IRQCFG0E_Start_Det.

nFIFOEMPY

Figure 12. FIFO Fill Process The FIFO filling process is shown in detail in Figure 12. As the first byte is written into the FIFO the signal IRQCFG0D_nFIFOEMPY goes high indicating that at least one byte is present. The microcontroller can then read the contents of the FIFO via the SPI interface. Once all data have been read from the FIFO then IRQCFG0D_nFIFOEMPY goes low. Once the last bit of the 64th byte has been written into the FIFO then the signal IRQCFG0D_FIFOFULL is asserted; data should be read before the next byte is received. This is described in Figure 13. The IRQCFG0D_nFIFOEMPY signal can be used as an interrupt signal for a microcontroller by mapping to pin IRQ0 if IRQCFG0D_RX_IRQ0[7..6] is set to “10”. Alternatively, the WRITE_BYTE signal may also be used as an interrupt if IRQCFG0D_RX_IRQ0[7..6] is set to “01”. Figure 13. FIFO Fill Complete Demodulation in buffered mode occurs in the same way as in continuous mode. Received data is directly

nFIFOEMPY

FIFO_OVR

read from the FIFO and the DATA and DCLK pins are not used. The Data/Clock Recovery in buffered mode is automatically enabled (DCLK is not externally available). The pattern recognition block in buffered mode is automatically enabled. The PATTERN signal may be mapped to pin IRQ0. Please refer to section 6.0 for further mapping details. The Received Signal Strength Indication in buffered mode operates the same way as in continuous mode, however, RSSI_IRQ may be mapped to IRQ1 instead of to IRQ0 in continuous mode.

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5.3 Transmitter Modes (Continuous or Buffered)
The transmitter works in continuous mode if the MCFG01_Mode [5] bit is ‘low’. The bit clock (DCLK) to be used for sending the data is available on pin IRQ1. The data is sampled at the rising edge of this clock and must then be changed on the falling edge. DCLK must be used in FSK mode, but is optional in OOK mode. The transmitter works in buffered mode if MCFG01_Mode [5] bit is high. Data to be transmitted is written to the 64-byte FIFO via the SPI interface. The data is loaded into a shift register which passes the data bit by bit to the modulator. FIFO operation in transmit mode is similar to receive mode; transmission either starts immediately after data is written into the FIFO or when the FIFO is full, determined by the IRQCFG0E_Start_Full bit setting. If the transmit FIFO is full, the interrupt signal IRQCFG0D_FIFOFULL is asserted on pin IRQ1. If data is written into the FIFO while it is full, the flag IRQCFG0D_FIFO_OVR will be set to “1” and the previous FIFO contents will be overwritten. The IRQCFG0D_FIFO_OVR flag is cleared by writing a “1” to it. At the same time this clears the contents of the FIFO. Once the last data in the FIFO is loaded into the shift register, the flag IRQCFG0D_nFIFOEMPY is set high on pin IRQ0. If new data is not written in the FIFO and the last bit of the shift register has been transferred to the modulator, the IRQCFG0E_TX_STOP bit goes high and the data seen by the modulator is the last bit sent. If the transmitter is switched off (e.g. entry into another mode), the transmission will stop immediately even if there is still unsent data in the shift register. In transmit mode the two interrupt signals are IRQ0 and IRQ1. IRQ1 is mapped to IRQCFG0D_FIFOFULL signal indicating that the transmission FIFO is full when IRQCFG0D_TX_IRQ1 is set to “0” and to IRQCFG0E_TX_STOP when IRQCFG0D_TX_IRQ1 is set to “1”. IRQ0 is mapped to the IRQCFG0D_nFIFOEMPY signal; this signal is used to indicate that the transmission FIFO is empty and must be refilled with data to continue data transmission.

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6.0 Interrupt IRQx Mapping
In receiver mode, two lines are dedicated to interrupt information. The interrupt pins are IRQ0 and IRQ1 and have each 4 selectable sources. The two following tables summarize the interrupt mapping in continuous and buffered modes (MCFG01_Packet_Hdl_en = ‘0’). Table 7. IRQCFG0D_RX_IRQ0
00 01 10 11 00 01 10 11 Mode 1 1 1 1 0 0 0 0 IRQ0 Output Output Output Output Output Output Output Output IRQ0 Int Source None Mapped to Write_byte

Mapped to IRQCFG0D_nFIFOEMPY
Mapped to Pattern Mapped to Pattern Mapped to RSSI_IRQ Mapped to Pattern Mapped to Pattern

Table 8. IRQCFG0D_RX_IRQ1
00 01 10 11 00 01 10 11 Mode 1 1 1 1 0 0 0 0 IRQ1 Output Output Output Output Output Output Output Output IRQ1 Int Source None Mapped to IRQCFG0D_FIFOFULL Mapped to RSSI_IRQ Mapped to FIFO_Int_Rx DCLK Output DCLK Output DCLK Output DCLK Output

The tables below give the description of the interrupts available in receive mode when the packet handler is enabled. Table 9. IRQCFG0D_RX_IRQ0
00 01 10 11 IRQ0 Output Output Output Output IRQ0 Int Source Data_Rdy Write_byte

IRQCFG0D_nFIFOEMPY
Pattern or ADDRS_match (if PKTCFG1E_ADDRS_cmp enabled)

Table 10. IRQCFG0D_RX_IRQ1
00 01 10 11 IRQ1 Output Output Output Output IRQ1 Int Source CRC successful

IRQCFG0D_FIFOFULL
RSSI_IRQ FIFO_Int_Rx

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The tables below give the description of the interrupts available in transmit mode. Table 11. IRQCFG0E_Start_Full
0 1 IRQ0 Output Output IRQ0 Int Source FIFO_Int_Tx

IRQCFG0D_nFIFOEMPY

Table 12. IRQCFG0D_TX_IRQ1
0 1 IRQ1 Output Output IRQ1 Int Source FIFOFULL

IRQCFG0E_TX_STOP

7.0 External Clock Output
The reference frequency can be used as a reference clock for the external microcontroller on the CLKOUT pin. The OSCFG1B_Clkout_En bit controls the CLKOUT pin. When this bit is set high, CLKOUT is enabled, otherwise it is disabled. The output frequency at CLKOUT is defined by the value of the OSCFG1B_Clk_freq[6..2] parameter which gives the frequency divider ratio applied on the reference frequency. This clock signal is disabled in Sleep Mode. Refer to section 10.6 for programming detail.

8.0 Packet Processing Features
On request, the circuit provides on chip Rx and Tx packet handling features. These features ease the development of packet oriented wireless communication protocols and free the MCU resources for other tasks. The options include enabling protocols based on fixed and variable packet lengths, data whitening, CRC checksum calculations, and received packet filtering. All the programmable parameters of the packet handler are accessible through the PKTCFG configuration registers of the device. The packet handling mode is enabled when the register bit MCFG01_Packet_Hdl_En is set high. The packet handler supports two types of packet formats: fixed length packets and variable length packets, selectable by the PKTCFG1E_Pkt_mode bit. The maximum size of the packet/payload is limited by the size of the FIFO selected. Since the size of the FIFO can be configured as 16, 32, 48 or 64 bytes, the size of the maximum payload allowed in each case is equal to the FIFO size selected.

8.1 Fixed Length Packet Mode
Fixed length packet mode is selected by setting bit PKTCFG1E_Pkt_mode to ‘0’. In this mode the length of the packet is set by the PKTCFG1C_Pkt_len[6..0] register and is limited by the size of the FIFO which has been selected. The length stored in this register is the length of the payload which includes the message and the optional address byte. A fixed length packet shown in Figure 14 is made up of the following fields: 1. Preamble. 2. Sync word. 3. Optional Address byte. 4. Message data. 5. Optional 2-byte CRC checksum.

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Figure 14. Fixed Length Packets

8.2 Variable Length Packet Mode
Variable length packet mode is selected by setting bit PKTCFG1E_Pkt_mode to ‘1’. The packet format shown in Figure 15 is programmable and is made up of the following fields: 1. Preamble. 2. Sync word. 3. Length byte 4. Optional Address byte. 5. Message data. 6. Optional 2-byte CRC checksum.

Figure 15. Variable Length Packets In variable length packet mode the length of the packet or payload is given by the first byte written in the FIFO for transmission. The length byte itself is not included while calculating the payload length. The PKTCFG1C_Pkt_len[6..0] parameter is used to set the maximum packet length allowed in the receiver. All the received packets having lengths greater than this maximum are discarded.

8.3 TX/RX Packet Payload Processing
The packet handler constructs the packets using the payload in the FIFO when the circuit is in Tx mode. In the Rx mode it processes the packets and extracts the user payload. The processing in both Tx and Rx modes will now be discussed.

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In Tx mode the packet handler builds a packet by adding the following fields to the payload stored in the RX/TX FIFO: 1. A programmable number of preamble bytes (1 to 4). 2. A programmable number of sync bytes (1 to 4). 3. Optional CRC checksum calculation over complete payload field (message + optional length byte + optional address byte) and appending the 2 byte CRC to the packet. 4. Optional whitening of the data. The payload stored in the FIFO may contain the following two optional fields: 1. Length byte from user if the variable packet length mode is selected. 2. Optional Address byte from user. The way the real transmission in the air is initiated depends on the sequence defined by the user and the value of the IRQCFG0E_Start_Full bit. If the FIFO is filled when the transmit mode is enabled, and if IRQCFG0E_Start_Full is “1”, the modulator waits until the first byte is written into the FIFO, then it starts sending the preamble followed by the sync word and user payload. If IRQCFG0E_Start_Full is ‘0’ in the same conditions, the modulator waits until the number of bytes written in the FIFO is equal to the number defined in the register MCFG05_FIFO_thresh[5..0]. The data to be sent can also be written in the FIFO during standby mode. In this case, the data is automatically transmitted when the transmit mode is enabled and the transmitter has reached its steady state. If CRC is enabled the CRC checksum is calculated over the payload and optional fields. This 2-byte checksum is sent after the payload. If whitening is enabled, then all the data except the preamble and sync is whitened before transmission. Note that the length byte in the FIFO determines the length of the packet to be sent and PKTCFG1C_Pkt_len[6..0] parameter is not used in Tx. In Rx mode the packet handler retrieves the payload by performing the following steps: 1. Preamble detection. 2. Sync word detection. 3. Optional address byte check. 4. Error detection through CRC. When the Rx mode is enabled the demodulator detects the preamble followed by the sync word. If fixed length packet format is enabled then the number of bytes received as the payload are given by the PKTCFG1C_Pkt_len[6..0] parameter. In variable length mode the first byte received after the sync word is interpreted as the length of the received packet. The internal length counter is initialized to this received length. The PKTCFG1C_Pkt_len[6..0] register is set to a value which is greater than the maximum expected length of the received packet. If the received length is greater than the maximum length stored in PKTCFG1C_Pkt_len[6..0] register the packet is discarded otherwise the complete packet is received. If the address check is enabled, then the second byte received in the variable length mode and the first byte in the fixed length mode is the address byte. If the address matches to the one in the PKTCFG1D_Node_addrs[7..0] field, reception of the data continues, otherwise it’s stopped. The CRC check is performed if PKTCFG1E_CRC_En = 1 and the result is available in the PKTCFG1E_CRC_stat bit along with an interrupt on IRQ1 indicating that the CRC was successful. An interrupt (Data_rdy) is also generated on IRQ0 as soon as the payload is available in the FIFO. The payload available in the FIFO can also be read in standby mode by setting PGCFG1F_RnW_FIFO = 1. If the CRC fails, the Data_rdy interrupt is not generated and the FIFO is cleared. This function can be overridden by setting PGCFG1F_CRCclr_auto = 1, forcing the availability of Data_rdy interrupt and the payload in the FIFO even if the CRC fails.

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8.4 Packet filtering
The received packets can be filtered based on two different criteria: length based filtering and address based filtering. In the variable length packet format, the PKTCFG1C_Pkt_len[6..0] stores the maximum packet length permitted. If the received packet length is greater than this maximum, then the packet is discarded. Address based filtering is enabled by setting parameter PKTCFG1E_Addrs_cmp[2..1] to any value other than “00”, i.e. either “01”, “10” or “11”. These settings enable the following three distinct options: PKTCFG1E_Addrs_cmp[2..1] =” 01”: This activates the address based filtering function of the packet handler and the received address byte is compared with the address in the PKTCFG1D_Node_addrs[7..0] register. If both the address bytes are the same, then the received packet is for the current destination and is stored in FIFO, otherwise it is discarded. An interrupt (Addrs_match) is generated on IRQ1 if the address comparison was successful. PKTCFG1E_Addrs_cmp[2..1] = “10”: In this case the received address is compared to both the PKTCFG1D_Node_addrs[7..0] register and a constant 0x00. If the received address byte matches any of these, the packet is accepted. An interrupt (Addrs_match) is generated on IRQ1 if the address comparison was successful. PKTCFG1E_Addrs_cmp[2..1] = “11”: The packet is accepted if the received address byte matches the PKTCFG1D_Node_addrs[7..0] register or either of the constants 0x00 or 0xFF. An interrupt (Addrs_match) is generated on IRQ1 if the address comparison was successful.

8.5 Cyclic Redundancy Check
The CRC check is enabled by setting bit PKTCFG1E_CRC_En = 1. A two byte CRC checksum is calculated on the payload part of the packet and appended to the end of the transmitted message. On the receiver side the checksum is calculated on the received payload and compared with the two checksum bytes received. The result of the comparison is stored in the PKTCFG1E_CRC_stat bit and an interrupt is generated on IRQ0. The CRC is based on the CCITT polynomial as shown in Figure 16. The implementation also detects errors due to leading and trailing zeros.

Figure 16. CCITT Polynomial and Circuit Implementation

8.6 Data whitening
The payload to be transmitted may contain long sequences of 1’s and 0’, which introduces a DC bias in the transmitted signal. The radio signal thus produced has a non uniform power distribution over the occupied channel bandwidth. It also introduces data dependences in the normal operation of the demodulator. Thus it’s useful if the transmitted data is random and with negligible DC bias. Balanced data can be obtained by using Manchester encoding, which ensures that there are no more than two consecutive 1’s or 0’s. However this reduces the effective bit-rate of the system because it doubles the amount of data to be transmitted thus halving the effective bit-rate.

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Another technique called whitening or scrambling is widely used for randomizing the user data before radio transmission. The data is whitened using a random sequence on the Tx side and de-whitened on the Rx side using the same sequence. The packet handler provides a mechanism for whitening of the packet payload. A 9-bit LFSR is used to generate a random sequence. The payload and 2-byte CRC checksum is then XOR’d with this random sequence as shown in Figure 17. The data is de-whitened on the receiver side by XORing with the same random sequence. The whitening/de-whitening process is enabled by setting bit PKTCFG1E_White_En = ‘1’.

LFSR Polynomial = X9 + X5 + 1

X

8

X

7

X

6

X

5

X

4

X

3

X

2

X

1

X

0

TRANSMIT DATA

DATA WHITENED

Figure 17. Data Whitening Polynomial and Circuit Implementation

8.7 Manchester Coding
Manchester encoding is enabled by setting bit PKTCFG1C_Man_en = 1 and can only be used in packet handling mode (MCFG01_Packet_Hdl_En = 1). Figure 18 illustrates Manchester Encoding. The NRZ data is converted to Manchester code by coding ‘1’ as ‘10’ and ‘0’ as ‘01’. In this case, the maximum chip rate is the maximum bit rate given in the electrical specifications in section 11.2; the actual bit rate is half the chip rate.

Figure 18. Manchester Encoding On the transmitter side, Manchester encoding is applied only to the payload and CRC checksum parts of the packet. The receiver decodes the payload and checksum before performing other tasks in packet processing.

9.0 Serial SPI Control Interface
The TRC103 has several operating modes, configuration parameters and internal status registers. All these operating modes, status information and configuration parameters are stored in a series of internal Configuration and Status Registers that may be accessed by the microcontroller via the serial SPI_CONFIG interface. The TRC103 contains two SPI-compatible serial interfaces, one to send and read the chip configuration, the other to send and receive data in buffered mode. Both interfaces are configured in slave mode and share the same pins SDO (Master In Slave Out), SDI (Master Out Slave In), SCK (Serial Clock). Two additional pins are required to select the SPI interface: nSS_CONFIG to change or read the transceiver

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configuration, and nSS_DATA to send or read data. Figure 19 shows a typical connection between a microcontroller with an integrated SPI interface and the TRC103’s SPI bus.

Figure 19. Microcontroller/TRC103 SPI Connection A byte transmission can be seen as a rotate operation between the value stored in an 8 bit shift register of the master device (the microcontroller for instance) and the value stored in an 8 bit shift register of the selected slave device (the transceiver). The SCK line is used to synchronize both SPI interfaces. Data is transferred full-duplex from master to slave through the SDI line and from slave to master through the SDO line. The most significant bit is always sent first. In both SPI interfaces the rising SCK edge is used to sample the received bit, and the falling SCK edge shifts the data inside the shift register. The nSS_CONFIG or nSS_DATA signal is controlled by the master device and should remain low during the byte transmission. The transmission is synchronized by these nSS_CONFIG or nSS_DATA signals. While the nSS_CONFIG or nSS_DATA is high, the counters controlling transmission are reset. Reception starts with the first clock cycle after the falling edge of nSS_CONFIG or nSS_DATA; if either signal goes high during a byte transmission the counters are reset and the byte has to be retransmitted. The SPI_CONFIG interface is selected if nSS_CONFIG is ‘low’ even if the circuit is in buffered mode and nSS_DATA is ‘low’ (SPI_CONFIG has priority). To configure the transceiver two bytes are required; the first byte contains a start bit (equal to ‘0’), R/W information (‘1’ = read, ‘0’ = write), 5 bits for the address of the register and finally a stop bit (equal to ‘0’). The second byte contains the data to be sent in write mode or the new address to read from in read mode. Figure 20 shows the timing diagram for a single byte write sequence to the TRC103 via the SPI_CONFIG.

SCK

SDI

SDO

nSS_CONFIG

Figure 20. Single Byte Configuration Write

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nSS_CONFIG must remain low during the transmission of the two bytes (address and data); if it goes high after the first byte, then the next byte will be considered as an address byte. When writing more than one register successively, nSS_CONFIG does not need to have a high to low transition between two write sequences. The bytes are alternatively considered as an address byte followed by a data byte. The read sequence via the SPI_CONFIG interface is similar to the write one. The microcontroller sends the address first during a first SPI communication and then reads the data during a second SPI communication. Figure 21 shows the timing diagram for a single byte read sequence from the TRC103 via the SPI.

SCK

SDI

SDO

nSS_CONFIG

Figure 21. Single Byte Configuration Read It is important to note that the SDI input is not useful during the second SPI communication. Figure 22 shows the timing diagram for a multiple byte read sequence from the TRC103 via the SPI.

SCK

SDI

SDO

nSS_CONFIG

Figure 22. Configuration Read of two registers.

9.1 Data transmission and reception via SPI_DATA interface.
When the transceiver is used in buffered mode, the data is stored in a 16 byte FIFO whose contents are transferred to or from the micro-controller via the SPI_DATA interface. Two interrupts IRQ0 and IRQ1 are used to manage the transfer procedure. When the transceiver is put in buffered mode, the SPI_DATA interface is selected if nSS_DATA is low and nSS_CONFIG is high. The operations with SPI_DATA interface are similar to those with SPI_CONFIG except that there is only a data byte (no address byte is required).

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Figure 23 shows the timing diagram for a multiple byte write sequence to the TRC103 during Transmit mode.

SCK

SDI

SDO

nSS_DATA

Figure 23. 2-byte write into Transmit FIFO. Figure 24 shows the timing diagram for a multiple byte read sequence from the TRC103 during Receive mode.

SCK

SDI

SDO

nSS_DATA

Figure 24. 2-byte Read in Receive Buffered Mode

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10.0 Register Memory Map
0x01F 0x1C 0x1B 0x1A PGCFG1F PKTCFG1E PKTCFG1D PKTCFG1C OSCFG1B TXCFG1A SYNCFG19 SYNCFG18 SYNCFG17 SYNCFG16 RXCFG15 RXCFG14 RXCFG13 RXCFG12 RXCFG11 RXCFG10 IRQCFG0F IRQCFG0E IRQCFG0D MCFG0C MCFG0B MCFG0A MCFG09 MCFG08 MCFG07 MCFG06 MCFG05 MCFG04 MCFG03 MCFG02 MCFG01 MCFG00

Register names are based on the function name and address location for easy reference.

0x016

0x010 0x00D

0x000

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10.1 Main Configuration Registers (MCFG) - *bold is default power-up setting 0x00 – MCFG00 [default 28h]
Name Chip_Mode(7..5) Bits 7,6,5 R/W r/w Description Transceiver Mode: 000 -> Sleep Mode 001 -> Stand-by Mode* 010 -> Freq Synth Mode 011 -> Receive Mode 100 -> Transmit Mode 101 -> Not Used 110 -> Not Used 111 -> Not Used Frequency Band: 00 -> 902-915 MHz 01 -> 915-928 MHz* 10 -> 950-960 MHz (868-870 MHz w/ other VCO tank) 11 -> Not Used VCO Trim: “00”* Selection between two RF frequencies as defined by SynthRx, SynthPx, and SynthSx registers: 0 -> frequency 1* 1 -> frequency 2

Band (4..3)

4,3

r/w

Trim_Band(2..1) RF_Frequency

2,1 0

r/w r/w

0x01 – MCFG01 [default 88h]
Name FSK_OOK(7..6) Bits 7,6 R/W r/w Description TX/RX Modulation: 00 -> Reset 01 -> OOK 10 -> FSK* 11 -> Not Used Enable Mode: 0 -> Continuous Mode* 1 -> Buffered Mode RX OOK Threshold Mode: 00 -> Fixed Threshold 01 -> Peak Mode* 10 -> AVG Mode 11 -> Not Used Enable Packet Handling: 0 -> Disabled*;Mode selected by Mode bit above 1 -> Enabled Gain (AGC) on IF chain in IF amplifier: 00 -> Max Gain (0 dB)* 01 -> -4.5 dB 10 -> -9 dB 11 -> -13.5 dB

Mode RX_OOK(4..3)

5 4,3

r/w r/w

Packet_Hdl_En IF_Gain(1..0)

2 1,0

r/w r/w

0x02 – MCFG02 [default 03h]
Name Freq_Dev(7..0) Bits 7..0 R/W r/w Description Frequency Deviation: Δf = f XTAL(MHz) , 0 ≤ R ≤ 255, where R is the register value. 32·(R+1) *R = 3 => Δf = 100kHz (default)

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0x03 – MCFG03 [default 07h]
Name XX Bit_Rate(6..0) Bits 7 6..0 R/W r/w , 0 ≤ D ≤ 127, where D is the register value. XTAL(MHz) 64·(D+1) *D = 7 => BR = 25kbps NRZ Description Not Used Bit Rate = f

0x04 – MCFG04 [default 01h]
Name OOK_Thresh(7..0) Bits 7..0 R/W r/w Description OOK fixed threshold or min threshold in peak mode. By default at 6 dB. 00000000 -> 0 dB 00000001 -> 0.5 dB 00001100 -> 6 dB* 11111111 -> 127 dB
· · · ·

0x05 – MCFG05 [default 0Fh]
Name FIFO_depth(7..6) Bits 7,6 R/W r/w Description Configures the size of the FIFO: 00 -> 16 bytes* 01 -> 32 bytes 10 -> 48 bytes 11 -> 64 bytes Number of bytes to be written in the FIFO to activate the FIFO_Int_Tx and FIFO_Int_Rx interrupts. # bytes = B + 1, where B is the register value. B = 15 => # bytes = 16*

FIFO_thresh(5..0)

5..0

r/w

0x06 – MCFG06 [default 77h]
Name SynthR1 Bits 7..0 R/W r/w Description RF Frequency 1, X counter *R1 = 77h (“01110111”) for 915 MHz

0x07 – MCFG07 [default 64h]
Name SynthP1(7..0) Bits 7..0 R/W r/w Description RF Frequency 1, Y counter *P1 = 64h (“01100100”) for 915 MHz

0x08 – MCFG08 [default 32h]
Name SynthS1(7..0) Bits 7..0 R/W r/w Description RF Frequency 1, Z counter *S1 = 32h (“00110010”) for 915 MHz

0x09– MCFG09 [default 74h]
Name SynthR2(7..0) Bits 7..0 R/W r/w Description RF Frequency 2, X counter *R2 = 74h (“01110100”) for 920 MHz
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0x0A – MCFG0A [default 62h]
Name SynthP2(7..0) Bits 7..0 R/W r/w Description RF Frequency 2, X counter *P2 = 62h (“01100010”) for 920 MHz

0x0B – MCFG0B [default 32h]
Name SynthS2(7..0) Bits 7..0 R/W r/w Description RF Frequency 2, Z counter *S2 = 32h (“00110010”) for 920 MHz

0x0C – MCFG0C [default 18h]
Name XX PA_ramp(4..3) Bits 7,6,5 4,3 R/W r/w Description Not Used Rise/Fall time control of Power Amp in OOK mode: 00 -> 3 usec 01 -> 8.5 usec 10 -> 15 usec 11 -> 23 usec* Not Used

XX

2,1,0

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10.2 Interrupt Configuration Registers (IRQCFG) 0x0D – IRQCFG0D [default 00h]
Name RX_IRQ0(7..6) Bits 7,6 R/W r/w Description IRQ0 source in receive mode. 1- If in Continuous Mode (MCFG01_Mode = ‘0’) and Packet Handler disabled (MCFG01_Packet_Hdl_En = ‘0’): 00 -> IRQ0 mapped to pattern signal* 01 -> IRQ0 mapped to RSSI_IRQ 10,11 -> IRQ0 mapped to pattern signal 2- If in Buffered Mode (MCFG01_Mode = ‘1’): 00 -> IRQ0 set to ‘0’* 01 -> IRQ0 mapped to Write_byte signal 10 -> IRQ0 mapped to nFIFOEMPY signal 11 -> IRQ0 mapped to pattern signal 3- If Packet Handler Enabled (MCFG01_Packet_Hdl_En = ‘1’): 00 -> IRQ0 mapped to Data_Rdy signal* 01 -> IRQ0 mapped to Write_byte signal 10 -> IRQ0 mapped to nFIFOEMPY signal 11 -> IRQ0 mapped to pattern or Addrs_match (if addr compare enabled) signal. IRQ1 source in receive mode. 1- If in Continuous Mode (MCFG01_Mode = ‘0’) and Packet Handler disabled (MCFG01_Packet_Hdl_En = ‘0’): 00 -> IRQ1 mapped to DCLK signal* 01,10,11 -> IRQ0 mapped to DCLK signal 2- If in Buffered Mode (MCFG01_Mode = ‘1’): 00 -> IRQ1 set to ‘0’* 01 -> IRQ1 mapped to FIFOFULL signal 10 -> IRQ1 mapped to RSSI_IRQ signal 11 -> IRQ1 mapped to FIFO_Int_Rx signal 3- If Packet Handler Enabled (MCFG01_Packet_Hdl_En = ‘1’): 00 -> IRQ1 mapped to CRC_OK signal* 01 -> IRQ1 mapped to FIFOFULL signal 10 -> IRQ1 mapped to RSSI_IRQ signal 11 -> IRQ1 mapped to FIFO_Int_Rx signal IRQ1 source in transmit mode. If in Continuous Mode (MCFG01_Mode = ‘0’) and Packet Handler disabled (MCFG01_Packet_Hdl_En = ‘0’):: 0 or 1 -> IRQ1 mapped to IRQ1/DCLK signal* 0 or 1 -> IRQ0 is set to ‘0’ If in Buffered Mode (MCFG01_Mode = ‘1’) or Packet Handler Enabled (MCFG01_Packet_Hdl_En = ‘1’): 0 -> IRQ1 mapped to FIFOFULL signal* 1 -> IRQ1 is mapped to IRQCFG0E_TX_STOP signal *Note: IRQ0 mapped as follows for Transmit mode: If in Buffered Mode (MCFG01_Mode = ‘1’): IRQ0 mapped to nFIFOEMPY signal* If Packet Handler Enabled (MCFG01_Packet_Hdl_En = ‘1’): IRQ0 mapped to FIFO_Int_Tx signal if IRQCFG0E_Start_Full=’0’ IRQ0 mapped to nFIFOEMPY signal if IRQCFG0E _Start_Full=’1’ FIFO FULL (IRQ source) FIFO Empty (IRQ source) FIFO overrun error: write a ‘1’ to clear FIFO
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RX_IRQ1(5..4)

5,4

r/w

TX_IRQ1

3

r/w

FIFOFULL nFIFOEMPY FIFO_OVR

2 1 0

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0x0E – IRQCFG0E [default 00h]
Name Start_Fill Start_Det Bits 7 6 R/W r/w r/w Description FIFO Fill mode selection: 0 -> FIFO starts filling when pattern is recognized* 1 -> FIFO fills as long as IRQCFG0E_Start_Det is ‘1’ Start of FIFO fill: *If Start_Fill = ‘0’, goes “High” when pattern recognized. Write a ‘1’ to reset the Sync Pattern Recognition. If Start_Fill = ‘1’: 0 -> Stop filling FIFO* 1 -> Start filling FIFO Transmission stopped (IRQ source) If in Buffered Mode (MCFG01_Mode = ‘1’): 0 -> Start transmit when FIFO is full* 1 -> Start transmit when IRQCFG0D_nFIFOEMPY = ‘1’ If Packet Handler Enabled (MCFG01_Packet_Hdl_En = ‘1’): 0 -> Start transmit when # bytes ≥ MCFG05_FIFO_thresh value* 1 -> Start transmit when IRQCFG0D_nFIFOEMPY = ‘1’ Enable IRQCFG0E_SIG_DETECT when IRQCFG0F_RSSI_thld is tripped: 0 -> Disable interrupt* 1 -> Enable interrupt Detects signal above IRQCFG0F_RSSI_thld. 0 -> Signal lower than threshold 1 -> Signal ≥ RSSI_thld level Must be cleared by writing a ‘1’. Not Used

TX_STOP Start_Full

5 4

r r/w

RSSI_Int SIG_DETECT

3 2

r/w r/w/c

XX

1,0

0x0F – IRQCFG0F [default 00h]
Name RSSI_thld(7..0) Bits 7..0 R/W r/w Description RSSI threshold level for interrupt. Default “00000000”*

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10.3 Receiver Configuration Registers (RXCFG) 0x10 – RXCFG10 [default A3h]
Name LP_filt(7..4) Bits 7,6,5,4 R/W r/w Description Bandwidth of the lowpass filter. 0000 -> 65 kHz 0001 -> 82 kHz 0010 -> 109 kHz 0011 -> 137 kHz 0100 -> 157 kHz 0101 -> 184 kHz 0110 -> 211 kHz 0111 -> 234 kHz 1000 -> 262 kHz 1001 -> 321 kHz 1010 -> 378 kHz* 1011 -> 414 kHz 1100 -> 458 kHz 1101 -> 514 kHz 1110 -> 676 kHz 1111 -> 987 kHz Cutoff frequency of the Butterworth low pass/polyphase filter. This frequency is centered about the center-frequency, fO, calculated from the contents of RXCFG11_Polyfilt.

BW_filt(3..0)

3,2,1,0

r/w

fC = fO + 200kHz · FXTAL(MHz) · 1+val(BW_filt[3..0])
BW_filt = “0011” => fC = 200 kHz*

12.8 (MHz) val(RFClkRef[7..0])+1

0x11 – RXCFG11 [default 38h]
Name Polyfilt(7..4) Bits 7,6,5,4 R/W r/w Description Center frequency of the polyphase filter:

fO = 200kHz · FXTAL(MHz) · 1+val(Polyfilt[7..4])
Polyfilt = “0011” => fO = 100 kHz* Power Amp Step regulation mode: 0 -> Regulation disabled 1 -> Regulation enabled* Not Used

12.8 (MHz) val(RFClkRef[7..0])+1

PA_reg XX

3 2,1,0

r/w

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0x12 – RXCFG12 [default 18h]
Name Polyfilt_En DCLK_Dis Recog Pat_sz(4..3) Bits 7 6 5 4,3 R/W r/w r/w r/w r/w Description Polyphase filter enable: 0 -> Polyphase filter disabled* 1 -> Polyphase filter enabled Data/Clock Recovery enable: 0 -> Enabled* 1 -> Disabled Sync Pattern Recognition enable: 0 -> Disabled* 1 -> Enabled Reference Pattern size: 00 -> 8 bits 01 -> 16 bits 10 -> 24 bits 11 -> 32 bits* Pattern error toleration limit: 00 -> 0 errors* 01 -> 1 error 10 -> 2 errors 11 -> 3 errors Not Used

Ptol(2..1)

2,1

r/w

XX

0

0x13 – RXCFG13 [default 07h]
Name RFClkRef(7..0) Bits 7..0 R/W r/w Description Reference clock counter/divider, F, for all digital circuitry: Fref = fxtal(MHz) / (F+1), 0 ≤ F ≤ 255, where F is the register value.

F = “00000111” => for 12.8 MHz xtal, Fref = 1. 6 MHz

0x14 – RXCFG14 [default 00h]
Name RSSI(7..0) Bits 7..0 R/W r Description RSSI Output

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0x15 – RXCFG15 [default 00h]
Name OOK_step(7..5) Bits 7,6,5 R/W r/w Description Reduction of max RSSI level in peak mode for OOK: 000 -> 0.5 dB* 001 -> 1.0 dB 010 -> 1.5 dB 011 -> 2.0 dB 100 -> 3.0 dB 101 -> 4.0 dB 110 -> 5.0 dB 111 -> 6.0 dB OOK peak mode update period: 000 -> once per chip period* 001 -> once per 2 chip periods 010 -> once per 4 chip periods 011 -> once per 8 chip periods 100 -> 2x per chip period 101 -> 4x per chip period 110 -> 8x per chip period 111 -> 16x per chip period OOK IIR filter coefficients in AVG mode. Each 2-s filter stage has two programmable sets of coefficients: 00 -> fc ≈ chip rate / 8.π (sets 1 and 1)* 01 -> fc ≈ chip rate / 8.π (sets 1 and 2) 10 -> fc ≈ chip rate / 32.π (sets 2 and 1) 11 -> fc ≈ chip rate / 32.π (sets 2 and 2)

OOK_length(4..2)

4,3,2

r/w

OOK_IIR_coeff(1..0)

1,0

r/w

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10.4 Sync Pattern Configuration Registers (SYNCFG) 0x16 – SYNCFG16 [default 00h]
Name Sync_Pat3(7..0) Bits 7..0 R/W r/w Description Sync recognition pattern Most Significant Byte. Default: “00000000”

0x17 – SYNCFG17 [default 00h]
Name Sync_Pat2(7..0) Bits 7..0 R/W r/w Description Sync recognition pattern Byte. Default: “00000000”

0x18 – SYNCFG18 [default 00h]
Name Sync_Pat1(7..0) Bits 7..0 R/W r/w Description Sync recognition pattern Byte. Default: “00000000”

0x19 – SYNCFG19 [default 00h]
Name Sync_Pat0(7..0) Bits 7..0 R/W r/w Description Sync recognition pattern Least Significant Byte. Default: “00000000”

10.5 Transmitter Configuration Registers (TXCFG) 0x1A – TXCFG1A [default 70h]
Name TxInterpfilt(7..4) Bits 7,6,5,4 R/W r/w Description Transmitter interpolation filter cutoff frequency: fc = 200kHz · FXTAL(MHz) · (1+val(TxInterpfilt[7..4]) val(RFClkRef[7..0])+1 12.8 (MHz) Default = “0111” => fc = 200 kHz* Transmitter output power (approx 3 dB steps): 000 -> Max* 001 -> -3 dB 010 -> -6 dB 011 -> -9 dB 100 -> -12 dB 101 -> -15 dB Others -> Not Used Not Used

Pout(3..1)

3,2,1

r/w

XX

0

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10.6 Oscillator Configuration Registers (OSCFG) 0x1B – OSCFG1B [default BCh]
Name Clkout_En Clk_Freq(6..2) Bits 7 6..2 R/W r/w r/w Description Buffered Clock Output Enable: 0 -> Disabled 1 -> Enabled* Buffered Clock Output Frequency on pin CLKOUT:

fclk = fxtal(MHz) / (2 * val(Clk_Freq[6..2]) fclk = fxtal if Clk_Freq = “00000”
XX 1,0 Default: “01111” => fclk = 427 kHz* Not Used

10.7 Packet Handler Configuration Registers (PKTCFG) 0x1C – PKTCFG1C [default 00h]
Name Man_En Pkt_len(6..0) Bits 7 6..0 R/W r/w r/w Description Manchester Encoding/Decoding enable: 0 -> Manchester Encoding/Decoding OFF* 1 -> Manchester Encoding/Decoding ON Packet Length: Packet size in fixed length mode and max packet size in variable length mode. Default: “0000000”*

0x1D – PKTCFG1D [default 00h]
Name Node_Addrs(7..0) Bits 7..0 R/W r/w Description Node address for use in filtering received packets in a network.

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0x1E – PKTCFG1E [default 41h]
Name Pkt_mode Preamb_len(6..5) Bits 7 6,5 R/W r/w r/w Description Packet Mode: 0 -> Fixed length packet mode* 1 -> Variable length packet mode Preamble Length: 00 -> 1 byte 01 -> 2 bytes 10 -> 3 bytes* 11 -> 4 bytes Data Whitening processing enable: 0 -> Whitening Processing OFF* 1 -> Whitening Processing ON Cyclic Redundancy Check processing enable: 0 -> CRC OFF* 1 -> CRC ON Address comparison for received packets: 00 -> No comparison* 01 -> Compare with ADDRS_cmp only 10 -> Compare with ADDRS_cmp & constant 0x00 11 -> Compare with ADDRS_cmp & constants 0x00 and 0xFF. CRC calc and check result: 0 -> CRC failed 1 -> CRC successful Write a ‘1’ to clear status

White_En CRC_En ADDRS_cmp(2..1)

4 3 2,1

r/w r/w r/w

CRC_stat

0

r/w/c

10.8 Page Configuration Register (PGCFG) 0x1F – PGCFG1F [default 00h]
Name CRCclr_auto RnW_FIFO XX PAGE(1..0) Bits 7 6 5,4,3,2 1,0 R/W r/w r/w Description Automatically clear FIFO (RX only) if CRC failed: 0 -> Clear FIFO if CRC failed* 1 -> DO NOT Clear FIFO Selects to read or write the FIFO while in standby mode: 0 -> Write FIFO* 1 -> Read FIFO Not Used Register Page: 00 -> Page 0 selected 01 -> Not Used 10 -> Not Used 11 -> Not Used

r/w

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11.0 Electrical Characteristics
Absolute Maximum Ratings SYMBOL PARAMETER VDD Supply Voltage Tstg Storage Temperature ESD JEDEC 22-A114 Class Rating RFIN Input Level Recommended Operating Range SYMBOL PARAMETER VDD Positive Supply Voltage Top Operating Temperature RFIN Input Level
NOTES: 1. Pins 3,4,5,27,28,29,31 Comply with Class 1A. 2. All other pins comply with Class2.

NOTES

MIN -0.3 -55

MAX 3.7 +125 0

1,2

UNITS V °C V dBm

NOTES

MIN 2.1 -40 -

MAX 3.6 +85 0

UNITS V °C dBm

11.1

DC Electrical Characteristics
SYM NOTES MIN TYP MAX UNITS

(Min/max values are valid over the recommended operating range Vdd = 2.1-3.6V. Typical conditions: To = 25°C; VDD = 3.3 V. The electrical specifications given below are valid for a crystal having the specifications given in Table 2.) PARAMETER

Test Condition

Sleep Mode Current Standby Mode Current Freq Synth Mode Current Receiver Mode Current Transmitter Mode Current Reset Threshold Digital input low level Digital input high level Digital input current low Digital input current high Digital output low level Digital output high level

IS ISB IFM IRX ITX
VPOR

Xtal Osc Running Synthesizer Running All blocks running Pout = +10 dBm Pout = +1 dBm

0.2 55 1.3 3.5 25 16 1.37
0.8*Vdd

1 80 1.7 4.0 30 21
0.2*Vdd

µA µA mA mA mA V V V µA µA V V

*

Vil Vih Iil Iih Vol Voh

-1 -1
0.9*Vdd

1 1
0.1*VDD

Vil = 0 V Vih = Vdd, Vdd = 3.3 V Iol = -1 mA Ioh = +1 mA

*Default mode, can be reduced to less than 3.0mA. Contact RFM.

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11.2 AC Electrical Characteristics
(Min/max values are valid over the recommended operating range Vdd = 2.1-3.6V. Typical conditions: To = 25°C; VDD = 3.3 V. The electrical specifications given below are valid for a crystal having the specifications given in Table 2.)

RECEIVER
PARAMETER RF Input Impedance RF Input power Receiver bandwidth Receiver Sensitivity SYM MIN TYP 150 MAX 0 400 -102 -106 dBc dBc dBc 100 32 0.5 ±3 70 -65 kbps kbps dB dB dB dBm UNITS Ohms dBm kHz dBm Blocking Immunity Co-channel rejection Adjacent channel rejection FSK bit rate OOK bit rate RSSI resolution RSSI accuracy RSSI dynamic range Local osc (Lo) emission -108 53 -12 42 Test Condition Differential Polyphase mode FSK: 10-3 BER, 25kbps, BW=100kHz, ∆f=50kHz OOK: 10-3 BER, 2kbps 1 MHz offset,unmodulated 600 kHz offset,same modulation as desired signal NRZ NRZ

50 -104

38 1.56 1.56

TRANSMITTER
PARAMETER RF Output Impedance RF Output power RF Output Power Range Reference Spur 2nd & 3rd Harmonic >3rd harmonic Phase noise FSK deviation -2 SYM MIN TYP 150 +13 +13 -46 -20 -25 -105 200 MAX UNITS Ohms dBm dBm dBc dBc dBc dBc/Hz kHz Test Condition Differential Not including SAW filter insertion loss Programmable No modulation No modulation No modulation 600 kHz offset Programmable

33

-112 50

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TIMING
PARAMETER TX to RX switch time RX to TX switch time Sleep to RX Sleep to TX Sleep to Standby Standby to Synth lock Standby to RX Standby to TX Freq hop time TX rise/fall time SYM MIN TYP 250 90 MAX UNITS us us ms ms ms us us us us us Test Condition Osc & Freq Synth running Osc & Freq Synth running SPI command to RX bit SPI command to TX bit Osc running Osc running Osc running 200 kHz hop Programmable

1.5 500 500 500 180

5 5 5

400 3

PLL Characteristics
PARAMETER Xtal Osc freq SYM MIN 10 TYP 12.8 180 200 250 280 320 12.5 15 1.5 0.5 MAX 15 UNITS MHz us us us us us kHz pF ms ms Test Condition 200 kHz step 1 MHz step 5 MHz step 10 MHz step 20 MHz step Variable, depending on freq From sleep mode Xtal osc running, 10kHz settle.

PLL lock time, 10kHz settle

Freq Synthesizer step Crystal Load Capacitance Xtal Oscillator start-up time Freq Synthesizer wake-up

13.5

16.5 5 0.8 870 928 960

Freq Range

868 902 950

MHz

SPI Timing
PARAMETER SCK for SPI_CONFIG SCK for SPI_DATA TSUDATA SPI_CONFIG TSU_SDI SPI_DATA TSU_SDI TSSCFG_L TSSDAT_L TSSCFG_H TSSDAT_H MIN 2 250 312 500 625 500 625 TYP MAX 2 1.6 UNITS MHz MHz us ns ns ns ns ns ns DESCRIPTION Max clock freq Max clock freq DATA hold and setup time SPI_CONFIG setup time SPI_DATA setup time nSS_CONFIG low to SCK rising edge. SCK falling edge to nSS_CONFIG high. nSS_DATA low to SCK rising edge. SCK falling edge to nSS_DATA high. nSS_CONFIG rising to falling edge nSS_DATA rising to falling edge

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12.0 Package Dimensions – 5x5 mm QFN-32
(all values in mm)

BOTTOM VIEW

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Revision History Rev 1.0 1.1 Date Description

11/6/2007 Initial Release -Added Sleep to Standby Max value of 5ms -Added Stability and Aging crystal parameters 2/29/2008 -Added TX cont mode DCLK usage statement -Update all TBD parameters

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