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Mixed signal interfacing

Hybrid System(Both Analog and


Digital)

Encoder Decoder
Digital
Analog Analog
Processing
input A/D D/A output
Unit
Converter Converter

Converts from analog input Converts from digital input


to digital output to analog output
ANALOG-TO-DIGITAL CONVERTER (ADC, A/D, or A to D)

a device that converts a continuous physical quantity (usually


voltage) to a digital number that represents the quantity's
amplitude.
The conversion involves quantization of the input, so it
necessarily introduces a small amount of error.
Instead of doing a single conversion, an ADC often performs
the conversions ("samples" the input) periodically.
The result is a sequence of digital values that have been
converted from a continuous-time and continuous-amplitude
analog signal to a discrete-time and discrete-amplitude digital
signal.
many microcontrollers include an analog-to-digital
converter (ADC) which converts an analog input value
to a binary value.
The analog input voltage range [GND,
r
Vref ] is parted into 2 classes, where r
is the number of bits used to represent
the digital value.
Each class corresponds to a digital
code word from 0 to 2 1
r
The analog value is mapped to the
representative of the class, in our case the
midpoint, by the transfer function.
We call r the resolution, or word
width in the literature.
Continued
U4
1 20
CS VCC
2 18
RD DB0(LSB)
3 17
Typical values for r are 8 or 10 bits, but you 4
WR
CLK IN
DB1
DB2
16
5 15
INTR DB3
8 14
A GND DB4
may also encounter 12 bit and more. 10
D GND DB5
13
9 12
VREF/2 DB6
19 11
CLK R DB7(MSB)
The LSB of the digital value represents the 6
VIN+
Vref 7
VIN-
smallest voltage difference that can be ADC0804
r
2 U6
distinguished reliably.
1 20
DVCC DB0
2 19
INT DB1
3 18
S/H DB2
4 17
RD DB3
5 16
CS DB4
6 15
AVCC DB5
7 14
VREF- DB6
8 13
VIN DB7
9 12
VREF+ DB8
10 11
GND DB9
ADC10061
mapping of the analog value into classes results in
information loss in the value domain.
Fluctuations of the analog value within a class go
unnoticed,
One way to achieve this is to make r larger, at the cost of a
larger word width. Alternatively, the granularity can be
improved by lowering Vref , at the cost of a smaller input
interval.
A certain minimum sampling period s
between two successive conversions,
resulting in an information loss in the
time domain.
The upper bound on the maximum
input frequency fmax that can be
sampled and reconstructed by an ADC
is given by Shannons sampling
theorem (Nyquist criterion):
Sample-and-hold devices

A number of problems exist with the previous sample and


hold circuit
load placed on the input of the circuit by charging the capacitor
during the sample phase
current flowing from the capacitor used in the conversion will
reduce the voltage stored on the capacitor

-
-
+
+
C

sample/hold
control line
Conversion Techniques

several different techniques A


for ADC.
The simplest one is the
flash converter.
Other Methods F
flash
counter ramp
successive approximation G

The idea : The input voltage


Vin is compared to several
reference voltages Vref ,i
where Fig Operating principle of
a flash converter
Converter Comparator Outputs Encoder Output
input
range (V) A B C D E F G
<1 0 0 0 0 0 0 0 000
>1-2 1 0 0 0 0 0 0 001
>2-3 1 1 0 0 0 0 0 010
>3-4 1 1 1 0 0 0 0 011
>4-5 1 1 1 1 0 0 0 100
>5-6 1 1 1 1 1 0 0 101
>6-7 1 1 1 1 1 1 0 110
>7 1 1 1 1 1 1 1 111
DAC

Two standard ways of building a digital-to-


analog converter:
1. Binary-weighted input
2. R/2R Ladder
Both methods use operational amplifiers with
negative feedback.
Binary-weighted-input DAC

In a binary-weighted-input DAC, the input current in each resistor is


proportional to the column weight in the binary numbering system. It
requires very accurate resistors and identical HIGH level voltages.

LSB 8R
D0 Rf
The MSB is represented by I0
+
4R
the largest current, so it has D1
If

the smallest resistor. To I1 Vou


2R
simplify analysis, assume all D2 I=0 t
+ Analog
current goes through Rf and R
I2
output
none into the op-amp. D3
MSB I3

Floyd, Digital Fundamentals, 10th 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights
ed Reserved
Binary-weighted-input DAC

A certain binary-weighted-input DAC has a binary


input of 1101. If a HIGH = +3.0 V and a LOW = 0 V,
what is Vout? 120 kW
R
+3.0 V f

60 kW 10 kW
0V

30 kW
+3.0 V Vou
+ t
15 kW
+3.0 V

I out ( I 0 I1 I 2 I 3 )
3.0 V 3.0 V 3.0 V
0 V 0.325 mA
120 k W 30 k W 15 kW
Vout = Iout Rf = (0.325 mA)(10 kW)3.25 V
=
Floyd, Digital Fundamentals, 10th 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights
ed Reserved