You are on page 1of 9

Sigma-Delta ADC Characterization Using Noise Transfer Function

Pole-Zero Tracking

Hochul Kim and Kye-shin Lee
Texas Instruments Inc. Dallas, TX

This work presents a new characterization method for
Σ∆ ADCs using noise transfer function pole zero tracking.
In this scheme, the ADC poles and zeros are extracted
from the measured FFT-plot. Furthermore, the pole-zero
behavior with respect to test conditions including supply
Figure 1 Block diagram of the 2nd order Σ∆ modulator
voltage, bias current and reference voltage can be
analyzed. As a result, the pole-zero sensitivity to each test
condition can be separately obtained. This can overcome In this paper, we propose a Σ∆ modulator characterization
the drawbacks of the conventional test method which method based on noise transfer function (NTF) pole-zero
mainly focuses on analyzing the FFT-plots and SNR value. location analysis. The locations of the NTF poles and zeros
are obtained from the measured FFT-plot using a novel
pole-zero searching scheme which gives consistent results
1. Introduction regardless of the number of output samples. Furthermore,
the pole-zero behavior with a certain test condition such as
Sigma-delta (Σ∆) ADC is a key component for recent supply voltage, bias current, and reference voltage can be
audio, instrumentation, data acquisition, bio-medical and obtained. From this information, the pole-zero sensitivity
telecom applications [1] – [3]. Especially, for system on a with respect to a specific test condition can be separately
chip (SOC) using a nanometer CMOS process that can shown. This is an advantage compared to the conventional
highly integrate RF/analog along with the digital test method which only shows the SNR versus test
processing circuits in the same chip, the characterization conditions. Furthermore, with the pole-zero sensitivity, it
and failure analysis of the Σ∆ modulator becomes is possible to easily figure out critical design or process
extremely important, since this mainly dominates the related parameters such as the noise, gain error, and
evaluation time of the entire system. So far, the Σ∆ matching accuracy. This can be possible due to the fact
modulator characterization has been performed by visually that the Σ∆ modulator non-idealities can be classified into
inspecting the FFT-plot which shows the noise spectrum NTF pole or zero affecting factors [7]. The following
of the modulator. In addition, the signal-to-noise ratio sections describe the NTF model, pole-zero searching
(SNR) and signal-to-(noise + distortion) ratio (SNDR) are scheme, and experimental results using a 2nd order single-
obtained from the FFT-plot [4], [5]. loop Σ∆ modulator.
However, the conventional test method has several
drawbacks. First of all, in case the SNR does not meet the 2. NTF Model of 2nd Order Σ∆ Modulator
budget, the root cause of the degradation cannot be The 2nd order Σ∆ modulator is widely used architecture
accurately seen from the FFT-plot, since the SNR of the
for Σ∆ ADCs due to simple circuit implementation and
modulator is affected both by the white (thermal) noise
good stability behavior[8]. In addition, high resolution can
and the shaped noise portion. This is especially
be achieved even with a moderate over-sampling rate by
problematic for wide-band Σ∆ modulators, where the in- using multi-bit quantizers. Figure 1 shows the general
band noise level is dominated by the quantization noise
block diagram of the single-loop 2nd order Σ∆ modulator.
rather than the thermal noise [3]. Secondly, analyzing the
The NTF of the Σ∆ modulator is given as [9]
device behavior by visually inspecting the FFT-plot cannot
give an absolute reference, since the noise level of the Y ( z ) ( z − 1) 2
FFT-plot varies with the number of samples [6]. In NTF ( z ) = = (1)
addition, overlaid FFT-plots can be used to solve this E(z) z2
problem. However, it is extremely difficult to analyze
where the two poles and two zeros are located at 0+j0
overlaid FFT-plots when the number of plots increases.
(origin) and 1+j0 of the z-plane. However, eq. (1) is an
ideal NTF which is valid only without the non-idealities
except the quantization error ε.

1-4244-1128-9/07/$25.00 © 2007 IEEE

which is unrealistic. In addition. θ = 0) frequency region of the NTF and poles affect the high frequency region of the NTF. a clear notch is observed in the NTF. respectively. Now. values. Pole-Zero Searching Scheme This section describes how the NTF poles and zeros are found from the measured FFT-plot. But when γ is close to 1. However. In addition. Figure 4 is a measured FFT-plot of a 2nd order Σ∆ modulator with 40MHz sampling rate. Overall. which the solid line is the 8th order poly-nominal curve fit of the FFT-plot obtained by using the MATLAB function ployval [10]. In reality when both pole and zero are present in the NTF. β = 0) Figure 5. the signal bandwidth. input tone. 3. That is line represents the scaled curve fit which is generated by multiplying scaling factor k to the original curve fit. [ z − (α + jβ ) ] ⋅ [ z − (α − jβ ) ] NTF ( z ) = (2) which makes the in-band noise power identical to the [ z − ( γ + jθ ) ] ⋅ [ z − (γ − jθ ) ] measured FFT-plot. In addition. effect of imaginary zero β is dominant when α is close to the ideal value (α=1). the peaking gets larger since the θ effect dominates. even poles can slightly affect the low frequency region of the NTF and vice versa. That is where α and β are the real and imaginary part of the zero. BW 2 while γ and θ are the real and imaginary part of the pole ∫ 0 N m ( f ) df respectively.003. the value of α and β was set to 1 and 0.2 INTERNATIONAL TEST CONFERENCE 2 . Figure 3 shows the NTF behavior with different pole values. In this case. In this case. the zeros affect the low Figure 2 NTF behaviors with zeros (γ = 0. we arbitrarily chose the value of α and β. which is mainly used for WCDMA applications. ∫ 0 N cf ( f ) df Another assumption used in the NTF model is that the real zero α and the real pole γ are all positive. θ. of the z-plane. as α moves further from the ideal value. the flat high frequency region is extended.9. As the value of γ increases from 0 to 0. The low frequency noise floor increases as α is decreased. When the value of real pole γ is close to 0.01). BW. This will make where Nm (f) and Ncf (f) are the noise spectrum of the the complex poles and zeros to locate in the right half side measured FFT-plot and curve fit. The dotted complex conjugate poles and zeros. is set to 1MHz. However. while β was set to 0. it will make a huge notch within the signal band. The FFT-plot is redrawn with the curve fits in Figure 3 NTF behaviors with poles (α = 1. the scaled curve fit can be an accurate approximation of the Figure 2 shows the NTF behavior with different zero measured FFT-plot NTF. The Paper 32. we re-define a more realistic NTF model with and harmonics are excluded from the curve fit. index (point-A) divides the noise spectrum into low both γ and θ were set to 0 in order to eliminate the pole frequency and high frequency regions. The proposed method is to first obtain a curve fit of the measured FFT-plot and finding the poles and zeros such that the error between the NTF and the curve fit is minimized. The value of α value was decreased from 1 to 0. To show how the zeros affect the Figure 6 shows the scaled curve fit where the frequency NTF. This requires solving a number of frequency versus noise power quadratic equations at specific frequency points. when α = 1 and β = γ = θ = 0. (2) is identical to the ideal NTF given in eq. the entire NTF shifts toward the low frequency region. the DC offset. respectively. makes a peak in the high frequency region of the NTF when the value of γ is close to 1. the notch disappears since the low frequency region of the NTF is dominated by the real zero. In this case.99. the pole index effect. The reason β value was selected close to be 0 is that (point-B) indicates the maximum point of the scaled curve even a small value (0. in k= BW 2 (3) eq. (1). As a result. The imaginary part of the pole. the NTF is mainly affected by γ.

and the zero index (point-C) is the mid-point between scaled curve fit and the NTF is compared. γ. Paper 32. Using γ and θ for each bin. The next step is to find the the optimum γ and θ that makes the minimum error are optimum α. involves solving a bi-quadratic equation for frequency bin Note that the poles mainly affect the high frequency region C. β. The real curve fit and NTF is further minimized by fine tuning the pole γ at each frequency bin between A and B is obtained complex zero β. As the result. Instead of directly solving the bi-quadratic equation for each frequency bin between A and B. a new equation is obtained by subtracting the bi-quadratic equation for a certain frequency bin with the bi-quadratic equation for point B. The error between the scaled the zeros are obtained with the bin at C (Figure 6). the complex pole θ for each bin between A and B is obtained by using the γ value obtained at that frequency bin. by plugging the frequency and magnitude of the scaled curve fit in eq. whereas real and positive number. This Figure 7 shows the proposed pole-zero extraction scheme. Figure 6 Concept of pole-zero searching with the scaled Furthermore. since the assumption of α is that it is a poles are obtained using bins between A and B. This approach is based on the fact that θ affects the high frequency slope and peaking behavior of the NTF. and θ value that minimize the error selected as the optimum value. the new equation will be a quadratic equation curve fit which can be more easily solved than the bi-quadratic equation. only the positive and real root is considered and zeros affect the low frequency region of the NTF. only the real roots of the bi-quadratic equation are considered as valid solutions. DC and the frequency index. the as a valid solution. because of the assumption that γ is a real number. Once the real poles are obtained. However. which yields a bi-quadratic equation.2 INTERNATIONAL TEST CONFERENCE 3 . A simplification can be made when finding θ. Figure 4 Measured FFT-plot Figure 7 Proposed pole-zero extraction scheme Figure 5 Measured FFT-plot with curve fits In addition. using the optimum γ and θ. real zero α at point-C. The next step is finding the between the NTF and scaled curve fit. the error between the fit. (4).

(8) will N CP ( e j ω Ts ) be a quadratic equation which is more simple to solve than the bi-quadratic equation. since this causes the Σ∆ modulator to become unstable. This approach is based on the fact that θ affects the high frequency slope and peaking b3 = b1 = 0 of the noise spectrum.594. Figure + (b 1i − b1n )θ + (b0 i − b0 n ) = 0 9 shows the scaled curved fit and complex pole noise spectrum NCP(ejωTs) with γ = 0. (7) and eq. a new equation is compared. That is jωTs Figure 9 NCP(e ) with γ = 0.594. a3 = a1 = − 4 cos ωTs ( 2 cos 2ωTs − 8 cos ωTs + 6 ) a0 = 1 − 2 N RP (e jωTs ) In addition. another bi-quadratic equation is obtained for θ for each frequency bin between A and B. Figure 8 shows the scaled curve fit and (b4 i − b4 n )θ 4 + (b3 i − b3 n )θ 3 + (b2 i − b2 n )θ 2 (8) real pole noise spectrum NRP(ejωTs) with γ = 0. That is the complex pole locate outside of the z-plane unit circle were excluded. b4θ + b3θ + b2θ + b1 θ + b0 = 0 4 3 2 (7) where bxi are the coefficients for specific frequency bin ωpi where which lies between A and B. since ( 2 cos 2ω T s − 8 cos ω T s + 6 ) − 2 b4 = 1 and b3 = b1 = 0 as shown in eq. In this case. (7). the value of θ obtained b0 = γ 4 + ( 4 cos ω T s ) ⋅ γ 3 + ( 2 cos 2ω T s + 4 ) ⋅ γ 2 from eq. (8) will make the high frequency slope and + ( 4 cos ω T s ) ⋅ γ + 1 peaking of complex pole noise spectrum NCP(ejωTs) a close approximation of the scaled curve fit. That is (e jωTs − 1) 2 N CP (e jωTs ) = (6) [ e jωTs − ( γ + jθ ) ] ⋅ [ e jωTs − (γ − jθ ) ] Similar to the real pole case. (4). It is shown that the NCP(ejωTs) matches the scaled curve fit with good accuracy in the high frequency region. the γ and θ values that make quadratic equation for point-B. the error between the For this case. is given by (e jωTs −1) 2 N RP (e jωTs ) = (4) (e jωTs − γ ) 2 where Ts is the sampling period. is obtained by solving eq.The real pole noise spectrum which is used to find the real pole γ. the imaginary pole noise spectrum is used.298. a simplification scheme is used when finding θ. is Instead of directly solving eq. However. only the real roots of eq. Finally.2 INTERNATIONAL TEST CONFERENCE 4 . scaled curve fit and NCP(ejωTs) replaced with γ and θ However. (5) are considered as a valid solution. γ = 0.594 are quadratic equation for the specific frequency bin from the the best solutions. Obviously. the best γ and θ will make the obtained for each frequency bin by subtracting the minimum error. The real pole γ for each frequency bin between point-A and B. the real pole γ obtained from eq. since the assumption of γ is a real number. obtained for each frequency bin between point-A and B. Paper 32.298 and θ = 0. Furthermore. which lead to a bi-quadratic equation given as a4γ 4 + a3γ 3 + a2γ 2 + a1γ + a0 = 0 (5) where a4 = 1 Figure 8 NRP(e jωTs ) with γ = 0. Therefore. and bxn are the coefficients b4 = 1 for frequency bin ωpn (point-B). (5) is used. In order to find the imaginary pole θ.298 and θ = 0.298 and θ = 0.298.

925. β is fine tuned to used for the complex pole value. zero location is at (0. Figure 11 shows the scaled curve fit and the final quadratic equation for the zero index (point-C) shown in NTF with the obtained α. because of the assumption that α is a real and positive number.925. respectively.298+j0. The Σ∆ modulator was fabricated using a nanometer CMOS technology. Figure 10 shows the scaled curve fit zero α is obtained by using the real zero noise spectrum and real zero noise spectrum NRZ(ejωTs) with α = 0.2 INTERNATIONAL TEST CONFERENCE 5 . The sampling clock − (4 cos ωTs + 4θ 2 cos ωTs ) ⋅ γ frequency was set to 40MHz with signal bandwidth of + (θ 4 + 2θ 2 cos 2ωTs +1) ] 1MHz.594) c4α 4 + c3α 3 + c2α 2 + c1α + c0 = 0 (10) and (0. The valid solution for this Once the best value of γ and θ are determined. However. and θ value. in which the signal Paper 32. Figure 12 Figure 6 will be solved to find α. jωTs Figure 10 NRZ(e ) with α = 0. only the positive real root of eq. Now. where the complex pole.925. which is due to where the best solution previously obtained for γ and θ are the imaginary zero β effect. γ. The optimum value for this case was β zero will increase the low frequency noise floor. (a) (b) Figure 12 (a) Final NTF pole-zero location (b) Detailed zero location In addition. selected as a valid solution. That is shows the z-plane pole-zero location of the final NTF. assuming the real minimize the error. = 0. Figure 13 shows the test setup. Experimental Results c3 = c1 = 0 2 A switched-capacitor (SC) 2nd order single-loop Σ∆ c0 = 1 − N RZ (e jωTs ) ⋅[ γ 4 − ( 4 cos ωTs ) ⋅ γ 3 modulator has been used to verify the proposed test + (2 cos ωTs + 2θ 2 + 4) ⋅ γ 2 scheme. whereas maintaining the high N RZ (e jωTs ) = (9) [ e jωTs − ( γ + jθ ) ] ⋅ [ e jωTs − (γ − jθ ) ] frequency behavior. where c4 = 1 4. Therefore.925+j0.003). the real case was α = 0.003. (10) is Figure 11 Final NTF. the bi. there is a slight discrepancy between the scaled curve fit and NRZ(ejωTs). As given as expected α increases the low frequency noise floor which makes NRZ(ejωTs) closely match the low frequency portion (e jωTs − α ) 2 of the scaled curve fit. β.

The complex pole β is not affected by the Figure 16 SNR and ∆ Z versus supply voltages supply voltage. However. In this test scheme. the real zero α is almost constant with supply voltage above 1. the data bits are sent to the PC through a USB cable. The digital output sequence was captured by the data capturing system. ∆ P ≡ distance between complex pole and (0 + j 0) ∆ Z ≡ distance between complex zero and (1 + j 0) Figure 15 SNR and ∆P versus supply voltages where ∆P and ∆z are the distance between the measured NTF (scaled curve fit) and the ideal NTF poles and zeros. bias current = 8µA. the real pole γ decreases while the complex pole θ slightly increases. the real pole γ significantly changes under low supply conditions (1. using MATLAB [10]. which is the FIFO board.7V. The bias current is swept using an external V-I converter. The default value of each test condition were supply voltage = 1. and VREF = 0.Figure 13 Test Setup generator made the fundamental tone for the Σ∆ ADC input with the common mode voltage (Vcm). in order to separately see how the poles and zeros affect the in band noise floor the following parameters are used. the NTF pole-zero dependency on each test condition variation can be easily obtained. In addition. In addition. the SNR for each case was observed to see the correlation between the in-band noise floor and the pole zero location. The FFT plot was generated with 65536 (64k) output samples for each Figure 14 Pole-zero locations with different supply voltages measurement. As the supply increases.2V to 2. The supply voltage was varied from 1. Figure 14 shows the z-domain pole-zero location with different supply voltages where the detailed zero location is shown in the bottom figure. In addition.4V. the pole-zero location was obtained from the measured FFT plots with different test conditions. However.6V. respectively. The supply voltage. With this approach. and an external power supply was used for sweeping the analog power supply and the reference voltage. and reference voltage (VREF) were the most important test conditions for the Σ∆ ADC. bias current.2 INTERNATIONAL TEST CONFERENCE 6 .2V and 1. Figure 15 shows the SNR and ∆P versus Paper 32.0V. The device sampling clock was externally provided.4V).

6V to 1. In addition. we use the pole- zero sensitivity to see the correlation between the NTF poles and zeros. respectively. the pole location does not drastically change. Figure 21 and 22 shows the SNR and pole-zero Figure 18 SNR and ∆P versus bias current. Overall. For the voltage. distance ∆P and ∆z. This indicates the SNR degradation is mainly due to the real zero effect Figure 17 shows the pole-zero location with different bias currents. the pole-zero distance ∆P and ∆Z are obtained. The complex zero β is not affected by VREF. this behavior is reversed as VREF exceeds 0. the result is shown for bias current up to 30µA. the real pole γ is not affected much by the bias current.7V. which makes the modulator unstable. However. the zero moves toward (1+j0) as VREF increases to 0. ∆z does not show much dependency on VREF with higher values (> 1V). under this bias current range.2 INTERNATIONAL TEST CONFERENCE 7 . however. In addition. and constantly increases beyond bias current of 10µA.3V.5V. The zero distance Figure 17 Pole-zero locations with different bias currents does not change with the variation of bias current up to 16µA. To summarize.5V and 0.3V.5V. using the proposed method. the imaginary part θ constantly increases as the bias current increases.9V. Figure 16 shows the SNR and ∆Z versus supply voltage. The pole distance ∆P is minimum value around bias current of 10µA. For VREF = 0. the NTF pole- zero behavior with different test conditions including supply voltage. the SNR is not affected by the variation of the supply voltage. ∆P does not show significant variation. since the bias current beyond this value forces the NTF poles and zeros to deviate from the ideal location. The zero movement is mainly due to the real zero α. In addition. From this information. Although ∆P consistently varies when the supply voltage is larger than 1. the NTF pole is located outside of the unit circle. The bias current was changed from 4µA to 30µA where the value between 4µA and 12µA was of particular interest. However. and reference voltage has been observed. As VREF is varied from 0.7V. The zero distance ∆Z drastically changes under low VREF value (< 1V). In this case. respectively. the complex pole θ is mainly affected by the bias current variation. Paper 32. similar to the ∆P case. That is Figure 19 SNR and ∆ Z versus bias current. bias current.93 whereas the complex pole θ does not show significant change. and gradually increases beyond this point. The SNR variation under low supply voltage is consistent with the ∆Z change. Therefore. Now. which mainly affects the SNR. beyond this voltage. However. Figure 18 and 19 show SNR with ∆P and SNR with ∆z. the SNR degradation under low bias conditions (< 16µA) is mainly caused by the NTF pole variation and SNR degradation under high current (> 16µA) is mainly affected by the zero variation. ∆P slightly increases as VREF exceeds 1. Figure 20 is the pole-zero location with reference voltage (VREF) which is varied between 0. the real zero is near 0.

78 11. the in-band noise level reduces as the resolution increases. for the high order case. which the accuracy might be an issue.2V 1.2V.7V 0. and process parameters using pole-zero sensitivity. Furthermore.95 5.87 3.24 7.8 VREF 0.56 Figure 20 Pole-zero location with different reference voltages 5. the proposed test scheme can be applied to higher order and higher resolution Σ∆ ADCs.5V 0. it is required to solve a number of (2N)-th order equations to find the NTF poles and zeros where N is the order of the modulator. 6. the number of roots will increase. Table 1 Pole-zero sensitivity with different test conditions Supply 1.9V (∆p /∆z) 4. and using the pole-zero behavior for characterizing the Σ∆ ADC.15 Bias 4µA 8 µA 10 µA 12 µA 16 µA (∆p /∆z) 9. Table 1 shows the pole-zero sensitivity with different test conditions. From this information. as the order increases.6V 0.4V to 1. the pole-zero behavior with respect to different test conditions are obtained. Limitations Basically.99 11. it is possible to figure out the critical design Figure 22 SNR and ∆ Z versus reference voltage.29 8.8V 2. Conclusions A new characterization method for Σ∆ modulators based on NTF pole-zero tracking is proposed.67 9.2 INTERNATIONAL TEST CONFERENCE 8 . and it will be more complicated to find the valid solution.42 7. This means the pole-zero variation will be less than the low resolution case. the proposed test method is novel in aspects of Figure 21 SNR and ∆P versus reference voltages finding the NTF poles and zeros from the measured FFT- plots. However.59 133.26 11. The proposed method finds the NTF poles and zeros from the measured FFT-plot using an iterative searching scheme. and vice versa.6V 1. limited analysis of Paper 32. the zero is more affected than the pole when the supply voltage decreases from 1. As a result. pole zero sensitivit y ≡ ( ∆ P / ∆ Z ) where larger value indicates that the poles are more affected than the zeros. since it does not focus on reducing the test time and test cost by simplifying the test procedure. For instance.79 9.8V 0.0V (∆p /∆z) 0. the NTF poles and zeros will not move much from the ideal location.4V 1. Overall. For high resolution Σ∆ ADCs. this can overcome the drawbacks of the conventional Σ∆ modulator test method such as noise level variation with number of FFT samples. Therefore. Overall. The proposed test scheme is different from BIST [5] and DFT [11].29 10.

and G.” IEEE J. “A wideband CMOS sigma-delta modulator with incremental data weighted averaging. 37. Instrum. R. pp. 525-528. [5] M. 1988. 352-363. [3] J.” ISSCC Dig. Delta-Sigma Data Converters-Theory. pp. and frequency response test of a sigma-delta ADC. Wiesbauer. Järvinen and K. 49.” IEEE Trans.. Temes. April 2002. [2] R. 11-17. [8] J. and difficult prediction of performance degradation with test conditions. Norsworthy. 37. 1-15. Solid State Circuits.-C. M. “Measuring harmonic distortion and noise floor of an A/D converter using spectral averaging . Jenq. 47. C. and H. Natick.2V dual-mode GSM/WCDMA Σ∆ modulator in 65nm CMOS. 8. I. Gaggl. 1997. Kuo. “A BIST scheme for a SNR. F. 77-81.-D. “Double interpolation for digital-to-analog conversions. pp. pp. I. 1996. Inversi. Candy and A.” ISSCC Dig. Roberts. Halonen. Circuits Syst. The Math Works Inc. Fetterman. R. pp.overlaid FFT-plots. design and performance evaluation. Commun. “A 14-bit 80kHz sigma-delta A/D converter: modeling. [11] C. 488- 489. 1995. Circuits Syst. “A 1.” IEEE Trans. Toner and G. vol. pp. April 1989. COM-34. and A. 1986. 2006. R. Norsworthy. New York: IEEE Press. 7.-T. [7] P. Yeng. vol. II. Jan. and H. pp. Solid State Circuits. Jan. [9] S. 123 – 128 Paper 32. 50. Meas. [6] Y. Huynh. [4] S. Post.-K. 82-83.” IEEE Trans. K.” IEEE Trans. “A power optimized 14-bit SC Σ∆ modulator for ADSL CO applications. 42. pp. W. References [1] T. Feb.-H. vol. pp. Ong and K. 2004. Papers. Papers. 24.. vol. “Behavioral modeling of switched- capacitor sigma-delta modulators. Design and Simulation. Jan.” IEEE VLSI Test Symposium. G. Malcovati et al. Chen. gain tracking.Tech. vol. March 2003. vol. [10] Simulink and Matlab Users Guides. Acknowledgements The authors would like to thank Russ Byrd and Joonsung Park for their comment and help in reviewing this paper. Chen.. N. 2002. Feb.” IEEE J. S. MA. 256-266.-R. Schreier.. vol.2 INTERNATIONAL TEST CONFERENCE 9 . “Self-testing second-order delta-sigma modulators using digital stimulus. vol. Dec.Tech.