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2292 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO.

10, OCTOBER 2012

A Simple Circuit Approach to Reduce Delay
Variations in Domino Logic Gates
Gaetano Palumbo, Fellow, IEEE, Melita Pennisi, Member, IEEE, and Massimo Alioto, Senior Member, IEEE

Abstract—In this paper, a simple approach to reduce delay
variations in domino logic gates is proposed. Previous analysis
by the same authors showed that delay variations in domino
logic are mainly due to the feedback loop implemented by the
keeper transistor and the output inverter gate. Accordingly, the
proposed strategy aims at reducing the loop gain associated with
this feedback loop, and hence its impact on delay variations. In
particular, a simple modified keeper is proposed to reduce the
loop gain while keeping the same silicon area, noise margin, and
nominal performance. The resulting delay variations associated
with keeper insertion are shown to be lowered by approximately
50%. The proposed approach is assessed by means of simulations
in 65-nm and 90-nm commercial CMOS technologies.
Index Terms—Intradie variations, process variations, timing
Fig. 1. Schematic of a Domino logic gate.
modeling, variability, VLSI.

the power supply and the dynamic node , when the latter has
to be kept high [10], [11].
I. INTRODUCTION
In nanometer technologies, intradie process variations deter-
mine large delay variations that are a timing overhead that limits
the performance improvements potentially offered by Domino

V ARIABILITY issues pose a major challenge in
nanometer integrated circuits (ICs) [1]–[3]. Indeed, espe-
cially in high-performance applications, the large delay/power
logic [15]–[23]. Since intradie process variations are expected
to rapidly increase in the next technology generations, and con-
sidering that they are very difficult to compensate with adaptive
deviations due to process and environmental variations make it schemes, they are regarded as the most critical source of vari-
difficult to meet the tight bounds imposed by performance and ability and a major limit to performance in nanometer technolo-
consumption requirements, thereby degrading the yield [4]–[9]. gies [21].
In performance-critical applications, Domino logic is widely Recently, the effect of process variations on the delay of dy-
employed since it has a lower delay at the cost of a reduced noise namic logic was investigated at the circuit level of abstraction
immunity, compared with static CMOS logic [10], [11]. The by the same authors [24]. The analysis showed that the delay
speed advantage of Domino logic is obtained thanks to the more variability of Domino logic gates is typically doubled compared
compact circuit topology (the pull-up network is much simpler to that of the static logic counterparts. In the same paper it was
than CMOS logic). This speed advantage becomes more pro- shown that [24]:
nounced when considering wide fan-in gates. As an example, — the variability of the delay at the dynamic node (i.e., from
fast OR gates and MUXes with wide fan-in are typically used the input to node in Fig. 1) is almost the same as the
to realize high-performance register files [12]–[14]. overall delay variability (i.e., from the input to node OUT
To counteract the noise immunity and signal integrity degra- in Fig. 1);
dation observed in Domino logic, the dynamic node is typi- — variations in the keeper transistor and the precharge tran-
cally connected to a “keeper” PMOS transistor ( in Fig. 1). sistor do not significantly contribute to the delay variability
During the evaluation phase, provides a static path between at the dynamic node .
Thus, the only remaining cause of variability increase compared
to static CMOS logic is the positive feedback loop that is imple-
Manuscript received February 18, 2011; revised September 05, 2011; ac-
mented by the keeper transistor and the output inverter in Fig. 1
cepted January 15, 2012. Date of publication May 04, 2012; date of current
version September 25, 2012. This paper was recommended by Associate Editor [24]. Furthermore, the delay variability degradation associated
S. Cotofana. with the feedback loop tends to get worse in more advanced
G. Palumbo and M. Pennisi are with the DIEES (Dipartimento di Ingegneria
technologies (see Section II for the details). Hence, it must be
Elettrica, Elettronica e dei Sistemi), Università di Catania, I-95125, Catania,
Italy (e-mail: gpalumbo@diees.unict.it; mpennisi@diees.unict.it). necessarily mitigated to avoid unmanageable delay variations in
M. Alioto is with the DII (Dipartimento di Ingegneria dell’Informazione), current and next technology generations.
Università di Siena, I-53100, Siena, Italy, and also with the EECS Department,
In regard to the trade-off between noise margin and perfor-
the University of Michigan, Ann Arbor, MI 48109 USA (e-mail: malioto@dii.
unisi.it; alioto@umich.edu). mance, a strong keeper improves the former but degrades the
Digital Object Identifier 10.1109/TCSI.2012.2189046 latter, due to the stronger current contention with pull-down

1549-8328/$31.00 © 2012 IEEE

and is minimum sized.5 [29] (i. hence various circuit solutions have been proposed to limit their impact [14]. On the other hand. a size smaller than PDN tran- adopted to reduce delay variations while keeping the same sistors) and the speed requirement. random dopant Fig. thereby increasing tally programmable strength.e. [4] and [2]. [25]–[28]. The scheme proposed in [28] compen- sates only fully correlated variations through a keeper with digi. The generic Domino logic gate in Fig. This is the well-known trade-off between of the dynamic node and its large overhead is justified only if noise immunity and speed in Domino logic. In particular. standard deviation node at the output of the PDN drives the static output inverter. the keeper is sized to achieve a of 0. and the stronger keeper obviously permits a better noise immunity.. Test circuit to evaluate delay variability for the traditional Domino. out. a simple uation transistor is chosen according to the trade-off between keeper topology that replaces the standard PMOS keeper is the clock load specification (i. Hence. a stronger keeper also opposes to transitions deviation estimate.: A SIMPLE CIRCUIT APPROACH TO REDUCE DELAY VARIATIONS IN DOMINO LOGIC GATES 2293 network. [3].g. Domino circuits. on the Role of the Positive Feedback Loop [25]. . layout-dependent variations). this work aims to reduce the delay The output inverter must be high skewed to minimize the sensitivity to process variations by reducing the loop gain. as delay. the noise margin is constantly kept to the targeted B. Two appen. the adoption of a range for will be considered in Section IV).. of determined by the PDN in Fig. 2. a detailed technology are reported in Appendix I to enable comparison analysis of delay variation in a Domino logic gate is carried between different technologies. The proposed keeper topology to reduce delay variations To correctly evaluate the delay variations. The dynamic respectively report the mean value . Analysis of the Impact of Intradie Variations and Discussion value without any temporary degradation. [8]. the NAND. On 1This number of runs ensures a lower than 4% inaccuracy in the standard the other hand. results equal to A. obtained with 2000 runs1 of Monte Carlo simu- pull-down network (PDN) inserted between the precharge tran. 1. ANALYSIS OF DELAY VARIATIONS IN DOMINO LOGIC imum-sized inverter ( quantifies the load indepen- dently of technology). which sistor and the evaluation transistor . in this paper a completely ranges from 0. subject to any process variation (so that the input rise time of dices are added to improve the readability of the paper. In these tables. When a transient noise is observed at node . More specifi- cally. in contrast to [14]. The approach in [27] proposes a replica bias technique that can counteract varia- tions that are fully correlated in both NMOS and PMOS transis- tors (i. and the resulting variability of the delay. Monte ulation setup is adopted.e. [4]. Also. [26]. rather than being purely a competitor.. which suffers from heavy loading the gate delay [3]. where the circuit under test is driven by a realistic input reported in Section IV to validate the proposed approach. and a NOR with fan-in equal to [2]. At the beginning of the evaluation phase (i. when goes the load capacitance is set to and .5 silicon area.e. although the latter is not clusions of the work are summarized in Section V. Rather. some results by using a 90-nm The paper is organized as follows. Assumptions and Constraints on the Transistor Sizes 410 aF in 65-nm technology. depends on the ratio between the saturation current of All the above approaches are based on the simple principle the keeper and that of the PDN. technique. To avoid an excessive delay that delay variations can be reduced by appropriately tuning the increase. [25] and [26] temporarily reduce the noise margin for a portion of the clock cycle. the circuit under test is not subject to significant variations). fluctuations) or variations that affect NMOS and PMOS tran- sistors in different ways. waveform generated by an equal gate. 2 Carlo simulations in 65-nm and 90-nm CMOS technology are is used. [16]. proposed technique can actually be complementary to such [3]. Also. The circuit under test is loaded by a capacitance that is set to some multiple of the input capacitance of a min- II. lations in 65-nm CMOS are summarized in Tables I–III. respectively) designed by using a 65-nm techniques. an inverter.. Interestingly. the size of the eval- loop implemented by the keeper [24].. typically with the PMOS transistor sized four times wider justified by the above considerations on the positive feedback than the NMOS [30]. Con. approaches in [14]. must be kept lower than unity. On the other hand. [32]. whereas it is ineffective against random variability components (e.PALUMBO et al.1 to 0.e.. delay and noise margin. thanks to the different principle and goal.1 (a wider With regard to the size of the keeper. the /60 nm. node is kept at the voltage by the keeper tran. In particular.e. [25]–[28] by simply replacing speed of Domino gates with different fan-in (i. in the proposed times larger than the equivalent width of the PDN [30]. the keeper saturation current is different principle is exploited to reduce delay variations in from 10% to 50% of the on current of the PDN). and is reasonably sized 1. the high). Moreover. which basically this approach is adopted in large structures like register files. keeper rejects it by bringing the voltage of back to [3]. CMOS technology. equivalent aspect ratio of the PDN is set to the realistic value sistor . a the PMOS keeper with the proposed structure. the proposed technique can be mixed with any of the Let us analyze the impact of the intradie variations on the alternative techniques in [14]. In particular. In Section II. 1 consists of an NMOS The results. the circuit shown in Fig. this trade-off becomes hard to manage in the presence of variations. Clearly. and typically keeper strength. an appropriate sim- is discussed in Section III along with design guidelines.

the feedback loop in Domino gates tends to reduce their speed improvement over high-skewed static inverter is sized by using the logical effort static logic. the delay variability decreases when increasing . the keeper insertion determines a mod- erate increase in the mean value of the gate delay. THE CASE WITHOUT KEEPER) responsible for an increase in the delay variations even when transistors in the loop (i. data in bold font and brackets refer to the percentage increase with respect to the case without keeper.2294 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS. the other is related to the presence DELAY STANDARD DEVIATION IN DOMINO LOGIC WITH/WITHOUT STANDARD of the positive feedback loop implemented by the keeper and KEEPER AND KEEPER IN FIG. 10.R. Thus. OCTOBER 2012 TABLE I TABLE III DELAY MEAN VALUE IN DOMINO LOGIC WITH/WITHOUT STANDARD KEEPER DELAY MEAN VALUE.e. In these tables. Fur- thermore. the delay variability also increases when considering a more advanced technology. as is confirmed by the comparison with results in 90-nm technology summarized in Appendix I. NO. II.T. with/without the feedback loop). this means that the speed degradation of Domino due to delay variations tends to grow faster than static CMOS logic (whose delay variations are basi- cally the same as Domino logic variations due to the only PDN. BRACKETS: PERCENTAGE INCREASE W. it is clear that the impact of the feedback loop on the delay variability is significant in sub-100 nm technologies. down-scaled technologies. On the other hand. As clarified by the authors in [24]. as shown in Table III. the mean value tends to in. due to the current contention with the pull-down network. due to the increase in the mean value (the standard deviation increases only slightly). II. where the mean value and the standard deviation of the delay are reported for the above considered logic gates with and without the keeper (i.. 1 is BRACKETS: PERCENTAGE INCREASE W. —IN the inverter gate. STANDARD DEVIATION AND VARIABILITY IN AND KEEPER IN FIG. the reduced variability in logic gates with higher fan-in is easily crease faster than the standard deviation when increasing the understood by considering that a larger number of stacked transistors permits to fan-in at a given load. compared to the case without keeper.e. let us analyze the results in Tables I. thereby making Domino logic less advantageous in approach for each load condition. 1. —IN DOMINO GATES WITH STANDARD KEEPER IN FIG. without the effect of keeper [24]). keeper and inverter transistors) are not subject to variations. From inspection of Tables I.R. 1 (65-nm TECHNOLOGY. 2In Table III. the delay variability tends to average out the transistor variations [18]. .2 From the above considerations. and also tends to increase in down-scaled technologies. the keeper insertion determines a strong increase in the delay stan- dard deviation . [21]. 4 (65-nm TECHNOLOGY. From Table I.. compared to the case without keeper. from Table II. In particular. 59. THE CASE WITHOUT KEEPER) ) decrease when increasing the fan-in. To quantitatively evaluate the impact of the feedback loop on the delay variations. In turn. As expected. 4 (65-nm TECHNOLOGY. the above delay varia- tions are due to two main factors: one is the process variability TABLE II within the PDN in Fig.T. VOL. the feedback loop in Fig. Hence.

the ously lower than one3 at the beginning of the evaluation phase effective transconductance of the keeper is immediately found (i.e. the Domino delay variability increase due to the presence of the keeper (i. whose simplified scheme is reported in Fig. The resulting small-signal voltage strength is shown in Fig.. . as the original keeper (i.. a circuit ap- proach to reduce the loop gain without impacting other param- eters of interest is discussed. when the delay becomes rather sensitive to process variations. being the circuit in Fig. when the voltage at node is ). the loop gain is positive but certainly lower than one at the beginning of the evaluation phase. The PDN the latter. where only is driven by the inverter output. In the following section. at the dynamic node can be written as . to be the keeper transconductance at the beginning of the evaluation phase is small as well. when as in the case of Domino logic without keeper. the magnitude of the loop gain can be reduced C. To this aim. Simplified schematic of a Domino logic gate. For the case of interest. Hence.PALUMBO et al. in Fig. since it is a crit- comes very sensitive to variations when . On the other hand. as desired. transistor works as an equivalent resistance From inspection of Fig. let us consider the closed-loop gain only if the loop gain reduction is obtained by keeping the same between the input voltage and the current . stead. Let us analyze the small-signal loop gain of the circuit in In the following. which be. whereas the keeper is A. which is Variations controlled by the output small-signal voltage .e. In particular. From a design perspective.e. lower-than-one and positive feedback loop gain in Domino gates increases the gain sensitivity to variations when . we have to 3 becomes rather high only around bias points where the voltage of size and so that they provide the same DC current node are close to the inverter logic threshold. At the same time. as the keeper operates in the linear region. and the current detail. we discuss an approach that aims at reducing Fig. the delay variability is reduced and becomes equal to that of static CMOS gates. noise margin as the gate with the original keeper. B.. Keeper Topology to Reduce the Impact of Process represented as a dependent current source . becomes rather sensitive to varia- tions when . Hence. In turn. the current determines the voltage drop at the dy- namic node and hence the delay at the same node. From basic circuit theory. In turn. the factor of . 3. 1. being signal transconductance while keeping the same the keeper transconductance. they have to set an equal . in open loop con. As no change is made in the strength. In by transistor parasitics). 1 feedback circuit with a loop gain has a closed-loop gain sen. or the impedance or the keeper transconductance . the feedback associated with the keeper transistor has a noninverting loop gain given by (2) (1) that represents a source degeneration for the transistor . Equivalently. Summarizing.: A SIMPLE CIRCUIT APPROACH TO REDUCE DELAY VARIATIONS IN DOMINO LOGIC GATES 2295 above. Circuit Analysis of the Positive Feedback Loop by reducing either the voltage gain of the inverter . Transistor Sizing Strategy compared to the case without keeper (i. the small-signal component of current can be written A simple approach to modify the keeper and reduce its small- as . In- hence . 4 does not have any penalty in terms of noise the impedance at the dynamic node (which is determined margin and speed. 3. a Apparently. the improved keeper is realized by splitting the original flowing through . 1. as discussed ical specification in Domino logic gates. Hence. where is the voltage gain of the inverter. naming the transconductance of . 1. A SIMPLE CIRCUIT APPROACH TO REDUCE DELAY Fig. VARIATIONS IN DOMINO LOGIC GATES From (1). without . 4. III. the transistor keeper transistor into two transistors and voltage at node decreases from the precharged value . 3 (including the evaluation transistor) is represented with an independent current source . [32]. compared to the standard keeper in Fig. feedback loop) can be lowered by reducing the loop gain. the above technique makes sense figuration).. which is obvi. (3) Due to the low value of and of the gain .e. for a given change in the input voltage. compared to the standard keeper topology in Fig. and hence the loop gain is reduced by a sitivity to variations equal to [31].

4 was also found to keep the as high as possible from (3). AND VALIDATION From the simulation results in Table II. Fig. as expected. In regard to the delay variability. in Fig. mobility. First. As the overall length is the same as the reported in Tables I–II. its (i. In the ation and variability with the proposed keeper (see Table IV) uncommon case where . which is in the low side of the typical ratio). . we have to set4 and reasons discussed in Appendix II. the increment in the simulations is reported in Table IV. transistor width is customarily set to the minimum value for the keeper in Fig.. which was found to be the same for both keepers. The variability resulting from these channel length of the original keeper. Domino logic gates were sim. The ported in Table VII of Appendix I). transistors and are sized with the nominal noise margin was confirmed to be consistently the and . IV. OCTOBER 2012 TABLE IV DELAY VARIABILITY IN DOMINO GATES WITH KEEPER IN FIG. 4. VOL. this condition is met range and leads to a noise margin ranging from 300 to 350 by setting the aspect ratio of and according to mV for all logic gates and the standard keeper in Fig. we considered Domino logic gates with assigned to 0. this ensures that ratio. 4 (65-nm TECHNOLOGY. 59. permits to reduce the loop gain while maintaining the same even when variations are accounted for. accounted for the variation in the threshold voltage. 1. This is especially true . (1) as low as possible. This means that the proposed . gate oxide thickness. the small dif- ulated according to the test circuit in Fig. even in the presence of variations. Monte Carlo simulations silicon area is negligible. allowed by the technology.1. 1 and the proposed keeper in Fig. expected from the considerations in Appendix II. which was sized according variability. thereby avoiding any penalty in terms of noise all comparisons presented in the following are fairly performed margin and performance. nificant speed penalty at nominal conditions. This sizing criterion combined with (4) keeper does not introduce any penalty in terms of noise margin. whose numerical values are width. since it is the series of two transistors with minimum the delay for the proposed keeper. and its layout is very out to evaluate the mean value and the standard deviation of simple. the delay standard devi- 4This clearly holds in practical cases where . as to the design strategy in Section III. Since these transistors are in series. we still have another degree of freedom in the percentage points (the small difference is due to the approxi- and sizes that can be used to keep the loop gain in mations that are customarily introduced in the transistor sizes). Thus.2296 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS. 4. the mean value of the To assess the reduction in the delay variations offered by the delay is basically the same for both the standard keeper in above discussed keeper topology. NO. ) Fig. DESIGN CONSIDERATIONS. or equivalently to keep Interestingly. it is easily found that we must set . 1). same for both types of keeper with a difference of just a few Now. in the gate with modified keeper. As expected from the considerations in Section III. source/drain resistance and channel di- mensions. for the tional to . 4 (again. It is worth noting that the considered keeper is very similar Monte Carlo simulations with 2000 samples were carried to the keeper based on a single transistor. conditions as in Section II for the 65-nm technology (results on This means that the proposed keeper does not introduce any sig- the most critical gates for the 90-nm CMOS technologies are re. a noise margin of 340 mV for the inverter (4) and 300 mV for the NAND3 gate were obtained with the appropriate sizes of the keeper in Fig. Table III) for all logic gates. As an example. the keeper in Fig. 4 that leads to Since the keeper usually has a rather small driving capability. whereas its length is and for the standard keeper greater than minimum. Keeper topology to reduce delay variations. SIMULATIONS. Since is propor. 2 and under the same ference is due to the usual approximations in transistor sizes).e. at same noise margin. and are consistently lower than those with the standard keeper (see in order to satisfy (4) and maximize . Also. as expected. 10. The same sizes were kept for same observation was confirmed to hold for the noise margin all transistors except for the keeper. same noise margin variability as the traditional keeper.

Domino logic on Figs. the delay standard deviation loaded with were found to be slowed of an -stage path approximately scales proportionally to down by 1 ps (4 ps) and 2 ps (8 ps) for and [4]. The results for both the standard and that the proposed keeper does not introduce any speed and the proposed keeper are shown for the output of each stage. Again. 7 shows the percentage standard . case with no keeper vs. Indeed. Similar results are re.r. This is because a stronger in Fig. For example. 1.. 6) versus V. crease due to the insertion of the keeper with respect to the case without keeper is plotted in Fig.r. 5. 5–6. they hold also for different values of . 6. the proposed keeper crease associated with the feedback loop. 65-nm technology): (a) inverter and NAND. a higher value of The improvement in delay standard deviation that is enabled leads to a higher delay because of the increased current con. This means keeper has a greater small-signal transconductance. As an example. 4 under the sizing strategy in loop gain increases and hence delay variations are more pro- Section III-B is effective in reducing the delay variability in.PALUMBO et al.1 to 0. the proposed keeper significantly reduces (by 35% adopted . In regardless of the adopted value of . case with no keeper vs. Percentage increase of delay standard deviation of standard/proposed keeper w. ( . (b) NOR. compared to the case without keeper. 1. regardless of the value of . the delay variation always increases for all logic gates suffer from significant increase higher delay variability.: A SIMPLE CIRCUIT APPROACH TO REDUCE DELAY VARIATIONS IN DOMINO LOGIC GATES 2297 Fig. More quantita- Although the above results were obtained assuming tively. CONCLUSIONS for . regardless of the expected. insertion. As a first comment As was recently shown by the same authors. Fig. 65-nm tech- nology): (a) inverter and NAND. ( .e. keeper that obtained with the standard keeper in Fig. the delay variability increase due to the insertion of the . simulations confirmed a sample 6-stage path. Percentage increase of delay standard deviation of standard/proposed keeper w. in low fan-in gates and in the case of low capacitive load. .5. its percentage in.. As deviation increase with respect to the case with no keeper in already observed for . As noise margin penalty at nominal conditions. [21]. higher ) is adopted. nounced (as clarified in Section III). proposed keeper was found again to be typically 50% lower than To show the influence of a different (i. 5 (Fig. hence the that the keeper topology in Fig. This is clear from the data in brackets in Table II. Fig.t. dard keeper. which shows that the delay variability increase due to the insertion of the proposed gates when a stronger keeper (i. compared to the case with . on average) the standard deviation increase due to the keeper In regard to the delay standard deviation.e. (b) NOR. This confirms strenght). the same Domino logic gates were also designed that the considerable advantages of the proposed keeper are kept and simulated with widely ranging from 0. regard to the mean value of the delay. keeper is almost half that obtained with the standard keeper regardless of the adopted keeper. by the proposed keeper is clearly maintained in practical circuits tention with the pull-down network. offers a considerable delay variability reduction over the stan- ported in Appendix I under a 90-nm technology.t. all the gates built with cascaded gates.

some results are reported for the most crit.1 for the and load. and 2. This is due to the pres- ence of the keeper transistor and the associated positive feed- back loop. STANDARD DEVIATION. 1 (90-nm TECHNOLOGY. hence the technology. Comparison on standard deviation delay be- obtained with 2000 runs of Monte Carlo simulations for a load tween traditional Domino gates and the proposed topology are capacitance equal to and . Extensive Monte Carlo simulations in commercial 65-nm and 90-nm CMOS showed that the proposed keeper topology halves the delay variability increase associated with the keeper inser- tion.. reduced delay variability is not obtained by penalizing the noise The equivalent aspect ratio of the PDN for all gates is set to margin.e. In this paper.8 /0.r. The resulting area overhead is also in- significant. the proposed keeper guarantees the the same simulation setup previously described for the 65-nm same nominal noise margin and its variability as well. The latter per- mits to minimize the loop gain (and hence delay variations) while keeping the same keeper strength. the proposed keeper is sized to achieve a of 0. AND VARIABILITY IN DOMINO GATES WITH STANDARD KEEPER IN FIG. to be and standard deviation and the variability of the delay . for which the input The transistor sizes of the proposed keeper to achieve an equiv- capacitance of a minimum-sized inverter was found alent aspect ratio of were found to be 520 aF. 59. A keeper topology to reduce the loop gain was introduced ) along with a detailed transistor sizing strategy.2298 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS. VOL. ) Fig. compared to the inverter. The noise margin for Domino logic with 90-nm APPENDIX I technology is around 350 mV for the inverter and linearly re- RESULTS ON A 90-nm TECHNOLOGY duces to 310 mV for the NAND3 gate.5 /0. and noise margin. and again the abso- havior (delay mean value) and silicon area as the Domino logic lute sizes for the NAND2 and NAND3 are multiplied by 2 and 3.1. this also means that the proposed keeper reduces by 50% the delay variability degradation of Domino logic with respect to static CMOS logic (i.t. which is very close to In this appendix. ical gates realized with a 90-nm technology. OCTOBER 2012 TABLE V DELAY MEAN VALUE. compared to static CMOS logic [24]. and by using summarized in Table VII. and hence the same noise margin and delay.1 terms of nominal performance. the realistic value . AND VARIABILITY IN DOMINO GATES WITH KEEPER IN FIG. Moreover. This delay variability increase becomes more critical moving toward more advanced technology generations. Since Domino logic without keeper essentially experiences the same delay variability as static CMOS logic. 10. tion. Also. Table V and Table VI summarize the mean . At the same time. is minimum sized and the keeper ability at each new technology generation. . TABLE VII rameter that is responsible for this delay variability degrada. ) TABLE VI DELAY MEAN VALUE. 4 (90-nm TECHNOLOGY. area. it partially fills the variability gap between the two logic styles). respectively. the high- is a useful tool to keep variations under control at no penalty in skew static inverter is sized with the NMOS equal to 0. 1 AND KEEPER IN FIG. the design examples that we presented above in 65-nm CMOS. with standard keeper. 4 (90-nm TECHNOLOGY. Due to the increasing importance of vari. NO. DELAY STANDARD DEVIATION IN DOMINO LOGIC WITH/WITHOUT STANDARD KEEPER IN FIG. STANDARD DEVIATION. Percentage increase of delay standard deviation of standard/proposed keeper w. the loop gain was found to be the critical pa. case with no keeper at the output of the various stages in the de- picted circuit. 7. the proposed keeper keeps the same dynamic be.

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. His primary research and energy scavenging. and high-performance MOS Current-Mode Logic: CML. Integration—The VLSI Journal. he is also Visiting Professor at University of Michigan. Professor.D. in noise immunity evaluation. respectively. Kabbani and A. which has the aim to also Guest Editor of the Special Issue “Ultra-low voltage circuits and systems” evaluate the Italian research in the above area for the period 2001–2003. Italy. in 1988 and 1993. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I. of Circuits. Italy. ICCD.” respectively. In 2003 of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II. and Computers.2300 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS. in 1997 and 2001. DIEES (Dipartimento di Ingegneria Elettrica Elet. ECL and SCL Digital Circuits). Catania. degree in electronics [30] I. Moreover. the ACM Transactions on Design Automation of Electronic Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART II. Then. Harris. current-mode approach. She received the Laurea degree in electronics Theory Appl. In 2002. and a textbook on electronic devices in the Chair of the “VLSI Systems and Applications” Technical Committee of 2005. e dei Sistemi) of the University of Catania as a sign. behavioral modeling of complex mixed-signal circuits. 1987. J. now investigating on next-generation ultra-low power circuits and wireless nodes. Pennisi. VOL. and 2005. ECL and SCL Digital Circuits (Springer. and design/modeling for variability-tolerant and low-leakage VLSI circuits. His primary research interests include ultra-low power VLSI circuits low power operation. timento Elettrico Elettronico e Sistemistico). in 1972. no. Logical Effort. APCCAD. Since 2011 he is a member of the Board of of the Special Issue “Advances in oscillator analysis and design” of the Journal Governors of the IEEE CAS Society. Associate and in the same year as an Assistant spectively. 2002. Sproull. Italy. circuit techniques for emerging thor of three books. She is coauthor of more than 15 pub- lications on international journals and conference proceedings. 2011–2012. In 2009–2011. He is coauthor of the book Model and Design of Bipolar and MOS current-mode digital circuits. electronics for digital systems. Designing Fast and automatic engineering from the University of CMOS Circuits. Editor of the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION cuits and Systems. 59. He is or was CIVR (Committee for Evaluation of Italian Research). In all these fields he is developing some the research and wireless nodes. Palumbo he served as an Associate Editor of the IEEE TRANSACTIONS ences (ISCAS. the 2008 to 2011 he served as an Associate Editor of the IEEE TRANSACTIONS ON Microelectronics Journal. 50. He received the Laurea de. [31] J. In the summer of 2007. In 2005 he was appointed Associate Pro- Since 1993 he has conducted courses on electronic fessor of Electronics. 2003. respectively. Systems. San Mateo. mostly IEEE Transactions) and conference proceedings. In 2011–2012. Jan. low-voltage circuits. From 2006 to 2007 he served as an Associate (VLSI) SYSTEMS. Circuits Syst. OCTOBER 2012 [29] A. 2000 he has been a full Professor in the same department. Al-Khalili. all by Kluwer Academic Publishers. New Since 2008. respectively. the Journal of Low Power Electronics. Switzerland. Feedback Ampilfiers: Theory and De. Sutherland. analysis of analog nonlinear circuits. MA: Kluwer Academic. Microelectronics (Second Edition). he was devices. Prof. vol. as well as he received the Darlington Award. for which he was also Distinguished journals (more than 150) and in conferences. adiabatic circuits.D. in 2004 and 2008. He has authored or coauthored 170 publications on interest has been analog circuits with particular emphasis on feedback circuits. He serves or has served as a Track Chair in a number of confer- Dr. 1980.” IEEE Trans. electronics. Millman and A. CMOS Current Amplifiers. error-aware activities in collaboration with STMicroelectronics of Catania. 2001. He received the Laurea degree in electronics engineering and the Ph. journals (60. 1999. Catania. He is the director of the Electronics Lab at University of Siena and Design. he is coauthor of Lecturer in 2009–2010 and member of the DLP Coordinating Committee in several patents. He serves as Associate from 2004 to 2005 for the topic “Analog Circuits and Filters” and “Digital Cir. ultra-low power circuits. subsequently becoming Associate Professor in 1998. I. engineering and the Ph. he joined the Department of Information gree in electrical engineering and a Ph.D. re. Massimo Alioto (M’01–SM’07) was born in Brescia. she has worked with the DIEES York: McGraw-Hill. Boston. in- tronica e dei Sistemi). 1. and Computers. (CML. ICM). From Systems. Italy. . In 1994 he joined the DEES (Dipar. Grabel. Fundam. degree in electrical engineering from the University Gaetano Palumbo (M’91–SM’98–F’07) was born in of Catania. Palumbo and S. 10. (Dipartimento di Ingegneria Elettrica Elettronica [32] G. in 1964. them are among the most downloaded TVLSI papers in 2007 (respectively his research has also embraced digital circuits with emphasis on bipolar and 10th and 13th). “A technique for dynamic CMOS Melita Pennisi (M’07) was born in Catania. Since error-aware VLSI design for wide energy scalability. He is the coau. Her primary research interests include the modeling and the optimized design of CMOS high-performance. B. as a Researcher. and D. He is the author of about 380 scientific papers on referred international the IEEE Circuits and Systems Society. building blocks focused on achieving optimum speed within the constraint of 2005). and basic a Visiting Professor at EPFL-Lausanne. ICECS. Researcher. 74–88. CA: Morgan Kaufmann. Systems. Two of compensation techniques. he held a Visiting Professor position at BWRC-UCBerkeley. as scientific-disciplinare area 09—industrial and information engineering of the well as the Journal of Low Power Electronics and Applications. Italy. and Model and Design of Bipolar and MOS Current-Mode Logic (site of Arezzo). at the University of Catania vestigating on active techniques for resiliency in near-threshold processors. degree from Engineering of the University of Siena as a Research the University of Catania. Alioto is a member of the HiPEAC Network of Excellence. the Journal of CIRCUITS AND SYSTEMS PART I. He is in 1999. and widely energy-scalable VLSI circuits. NO. near-threshold circuits for green computing. pp. Feedback Amplifiers: Theory technologies. In 2005 he was one of the 12 panelists in the Circuits. He was Technical Program ON CIRCUITS AND SYSTEMS PART I from June 1999 to the end of 2001 and Chair of the ICM 2010 and NEWCAS 2012 conferences.