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You are on page 1of 22

By,

C.Radhika (09VL03F)

N.M.Yeshoda (09VL28F)

Prajakta Panse (09VLF01)

Mr.RAMESH KINI.M

Associate Professor.

NATIONAL INSTITUTE OF TECHNOLOGY KARNATAKA, SURATHKAL

P.O SRINIVASNAGAR, MANGALORE-575025.

1

Acknowledgment

We would like to take this opportunity to express our deep sense of gratitude

to Mr.Ramesh Kini M.(Associate Professor, E & C, N.I.T.K, Surathkal), our

guide for his help through provoking discussion, invigorating suggestions ex-

tended to us with immense care, zeal to our work.

We offer our sincere thanks to Dr. Sumam David S.(Head of the Depart-

ment, E & C, N.I.T.K, Surathkal) for providing necessary facilities, valuable

suggestions and support through our study.

ing us throughout the course of the Project.

2

Abstract

the waveform of transmitted pulses. Transmitting a signal at high modula-

tion rate through a band-limited channel can create inter symbol interference.

Therefore the purpose of pulse shaping filter is to make the transmitted signal

suit better to the communication channel by limiting the effective bandwidth

of the transmission.

FIR filter, pulse shaping filter come with linear phase and inherent stability.

These properties of pulse shaping filter makes it apt for ASIC implementa-

tion. By increasing the order of the filter, smoothness in the intended task

can be achieved to a great level but at the cost of area.Through this project

an attempt is made to minimize area while keeping throughput to an ad-

missible value. The implementation of pulse shaping filter is done in digital

domain using 0.18 micron technology.

Test (BIST) is incorporated onto the chip. BIST is designed to test more

structures in parallel thereby reducing the testing duration while providing

good fault coverage.

Contents

1 Introduction 3

2 ASIC Implementation 6

2.1 Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Back End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Results 13

1

List of Figures

1.2 Block diagram of fir filter . . . . . . . . . . . . . . . . . . . . . 5

2.2 The architecture of FIR filter . . . . . . . . . . . . . . . . . . 8

2.3 Block diagram of control logic . . . . . . . . . . . . . . . . . . 9

2.4 Combinational Logic for selecting appropriate signal . . . . . . 9

3.1 Output of FIR filter for rectangular pulse of width= 2 clk cycle 13

3.2 Output of FIR in testing mode for boundary scanning . . . . . 14

3.3 Output of FIR in testing mode detecting B-S-A-0 . . . . . . . 14

3.4 Layout of Control Logic . . . . . . . . . . . . . . . . . . . . . 15

3.5 Layout of FIR logic . . . . . . . . . . . . . . . . . . . . . . . . 15

3.6 Layout of Top module of FIR filter . . . . . . . . . . . . . . . 16

3.7 Comparison of ideal and practical FIR filter’s frequency do-

main behavioral . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2

Chapter 1

Introduction

ronment must contend with the fact that constraining the bandwidth of the

transmitted signal necessarily increases the likelihood of a decoding error at

the receiver. Bandwidth limited systems often employ pulse-shaping tech-

niques that allow for bandwidth containment while minimizing the likelihood

of errors at the receiver.

Generally the digital transmission will be rectangular pulses, whose spec-

trum spans infinite frequency. In many data transmission applications, the

transmitted signal must be restricted to a certain bandwidth due to either

system design constraints or government regulation. In such instances, the

infinite bandwidth associated with a rectangular pulse is not acceptable. The

bandwidth of the rectangular pulse can be limited, however, by forcing it to

pass through a low-pass filter.The act of filtering the pulse not only causes its

shape to change from purely rectangular to a smooth contour without sharp

edges in first symbol period, but it is also spread out over the subsequent

symbol periods. This results into Inter symbol interference(ISI) making sys-

tem less reliable. Hence for doing this pulse shaping, special types of pulse

shaping filters are preferred rather than simple low pass filters.The pulse

shaping filter is a FIR filter, which inherits all properties of FIR filter. The

LTI model of FIR filter can be represented by the difference equation as

X

N −1

y[n] = h[k] ∗ x[n − k] (1.1)

k=0

3

y[n] : current output discrete sample

The impulse response of pulse shaping filters is short enough that very

little energy from one symbol smears into the next symbol.Thereby it does

not cause ISI. Figure 1.1 shows pulse shaping filter’s zero ISI property.

are:

• Raised-cosine filter

• Gaussian filter

complex form of raised cosine is the square root raised cosine filter, which

offer s better spectral efficiency. The impulse response of square root raised

cosine pulse shaping FIR filter is given as

RC(t) = (1.2)

π Ttc (1 − (4α Ttc )2 )

4

Where

α: roll-off factor

The roll off rate and chip duration decide the performance metric of

the FIR filter. With the typical α=0.22 and Tc=0.2674 microseconds filter

coefficients are even symmetric.

Pulse shaping filter is basically a FIR filter. Hardware realization of it can

be represented as basic Multiplier and Accumulator (MAC) unit as shown in

the Figure 1.2

.

As the order of the filter increases, the accuracy with which it smoothens

the wave contour becomes superior. But at the same time number of multi-

pliers and adders required increases linearly. Specially higher the number of

multipliers higher is the chip area and thus higher number of multipliers is a

threat to the popularity of pulse shaping filter.

In this project, implementation of the pulse shaping FIR filter is done

with an aim to reduce the chip area by limiting number of multipliers. In

order to make filter design fault tolerent BIST is incorporated in the chip.

BIST is a Design-for-Testability (DFT) technique, because it makes the elec-

trical testing of a chip easier, faster, more efficient,less costly and reduces

dependence on an external automated test equipment (ATE).In the project,

parallel testing of scan design and combinational design is done to reduce

number of clock cycles required for testing. The functionality of the system

is verified using XILINX and the backend design of the system is done using

CADENCE.

5

Chapter 2

ASIC Implementation

to extract filter coefficients with the filter specifications as shown in Table 2.1.

Symbol rate 3.84 Msymbols/sec

Cut-off frequency Cut-off frequency

Sampling frequency Interpolation factor ∗ symbol rate= 15.36MHz

Chip duration 0.2604 micro sec

Stop band attenuation(dB) -52

coefficients were quantized to integer form. After quantization, performance

of FIR filters was compared with non-quantized filter in time and frequency

domain. It has been observed that the acceptable performance in terms of

stop band attenuation and pass band ripple is obtained with the filter order

of 32. Hence the order of filter is chosen as 32 and coefficients have been

extracted. For further details refer Appendix.

After extracting filter coefficients, hardware was described in behavioral

VHDL using ISE simulator to ensure that the code is independent of any

target architecture, therefore can be synthesized using any libraries. The

simulated VHDL code was synthesized using Synopsys Design Micro vision

Analyzer (Design Compiler) using VTVT TSMC 180 standard cell digital

libraries. The Verilog netlist was imported into CADENCE Silicon Ensemble

6

where floor planning, place and route were carried out. The system design

is done in two stages namely front end and back end.

Pulse shaping FIR filter is basically a MAC unit with memory. The simplest

FIR filter implementation requires number of multipliers equal to the order

of the filter. Therefore with the order of 32, filter implementation requires 32

multipliers thereby consuming lot of chip area. So the design has been done

with the goal of area optimization maintaining acceptable speed of operation.

The property of even symmetry of the filter coefficients has been exploited

to achieve the goal as shown in the 2.1.

filter was designed and utilization of multipliers is done over two system

clock cycles. Input is presumed 8-bit unsigned number. Coefficients are

shifted by 7 bits to left (multiplication by 127d ) in order to achieve higher

precision. For filter coefficients signed-magnitude representation is used.

The system is broadly divided into three subunits namely,

• Control Logic

7

• Fir Logic

• Boundary Scanner

The architecture is shown in the figure 2.2. Cont logic performs the func-

tion of routing appropriate data sequence to fir logic. In addition to that

it has all components of BIST like test vector gen, test mode gen, reset gen

etc. The fir logic block contains main 16-tap FIR filter, adder and latch to

get final convolution sum. Boundary scanner unit is included as an add-on,

to test input and output pins.

The figure 2.3 shows components of cont logic. In cont logic, system clock

is divided using T-Flip-flop. This signal is used to control the data given to 16

bit FIR filter. AND-OR combinational logic is used as multiplexer to route

appropriate (Xout /Data) signal to dout pin. Output of the T-Flip-flop is

also given to the pin n.

Built in self unit (BIST) is integrated within cont logic to endow with

testability measures. Design is optimized to trim down area and time over-

head. Testing of combinational and sequential design is done separately and

simultaneously. Test mode can be enabled by setting Test/normal pin of

the input to high. Fault collapsing and fault dominance has been exploited

to find out minimum number of test vectors for approximately 95% fault

coverage.

combinational logic (figure 2.4) is used. From this circuit test vectors needed

to find out all faults are found. These test vectors are listed in table 2.2

8

Figure 2.3: Block diagram of control logic

This necessitates the use of 6 clock cycles for testing entire circuit. In

the test mode, address generator unit is activated to generate address for

extracting test vectors. Test vectors along with expected output are saved in

ROM. In each clock cycle one vector is retrieved and applied to combinational

logic and second test vector is given out as dout signal for testing sequential

logic. Output is compared with expected result using XOR gate. Output of

XOR gate is used as feedback to address generator. Thus as soon as fault is

detected test enable signal goes low disabling address generator. This puts

into practice an idea of fault dropping and reduced power consumption. At

the end of the test mode, whatever data stored in sequential circuit need

to be flushed out. Thus reset gen unit is used to generate monoshot when

test mode pin makes high to low transition. This signal is inturn given out

9

Table 2.2: Fault equivalence and summery of test vectors

(abcd)b output output

0101 a-sa1,c-sa1,e-sa1,fsa1,g-sa1 0 1

0011 c-sa0,d-sa0,f-sa0,g-sa0 1 0

1110 a-sa0,b-sa0,e-sa0 1 0

1010 b-sa1,d-sa1 0 1

Fir logic contains 16 bit FIR filter unit employing 32 registers of size 8

bit, 16 multipliers of 8∗8 and 32 adders/ subtracters. Additional pin ’n’ is

provided which is connected to single bit signal and can have value either

’0’ or ’1’. As per value on this pin traversing path for coefficient array is

selected. During first clock cycle ’n’ goes to ’0’ thereby outputs partial con-

volution sum. In second clock cycle ’n’ goes to ’1’ and outputs second partial

convolution sum. Latch is used at the output to hold first partial convolution

sum for one clock cycle. So at the end of second clock cycle adder adds up

both partial convolution sums to give final output. This output has been

latched again and fed to divider. Divider unit divides the result by 7 bit

while preserving sign of the output. So final output is 12 bit signal in signed-

magnitude with MSB representing sign.

in such a way that multiplexer is included for every alternate flip-flop in scan

chain. Thus in 4 clock cycles all vectors will be out. This output data of scan

chain is compared with test vector so as to detect any fault if present.This

signal is then ORed with input signal sd to generate SCAN OUT signal. At

the end of the test mode, reset signal goes high and clears all flip-flops in

scan chain thereby reducing 4 clock cycles.

In boundary scan mode, both internal modules are disconnected from

10

data input pins and input pins are directly connected to output pins to

verify I/O functionality.

The synthesis process begins by converting the vhdl description of the logic

into a netlist using generic library gates. The important input to the syn-

thesis tool is the timing constraint .tcl file. The timing constraints have

been described in the Synopsys Design Constraint format. Here the clock,

the latency of the clock, the input and output delays is provided as inputs.

Once the constraints have been set, the code is compiled with appropriate

mapping effort ensuring no area, delay constraints violation. Then the post

synthesized net list is generated. In addition to the actual synthesized gate

level net list, it also generates several constraint reports as

• Area

• Power

• Delay

***********************************************************

Report: area

Design: fir 32 ru

***********************************************************

Number of ports: 24

Number of nets: 189

Number of cells: 32

Number of references: 29

Combinational area: 509625.406250

Noncombinational area: 75118.203125

Total cell area: 584710.18750

This report gives the rough estimate of area (excluding routing area) re-

quired to do the back end design. Similarly the power analysis report gives

the amount of power dissipated, from which an estimate of driving current

can be obtained to decide the power ring metal width in the back end design.

11

*********************************************************

Report: power-analysis effort medium

Design: fir 32 ru

*********************************************************

Operating Conditions: nom pvt

Library: vtvt tsmc180

Power-specific unit information:

Voltage Units 1V

Capacitance Units 1.000000ff

Time Units 1ps

Dynamic Power Units 1mW (derived from V,C,T units)

Leakage Power Units 1mW

Cell Internal Power 5.4245 mW (66%)

Net Switching Power 2.7922 mW (34%)

Total Dynamic Power 8.2167 mW (100%)

Cell Leakage Power 1.2977 micro W

The post synthesized net list from Synopsys is used for back end layout

design. The tool used for placement and routing is SOC ENCOUNTER.

In layout design modular approach of coding is enforced to the fullest by

doing separate layout design for cont logic and fir logic. These designs have

been saved as .lefs and imported to top module. Table 2.3 gives summery of

backend performance metric got from SYNOPSYS AND CADENCE SOC.

Supply voltage 1.8V

Power Dissipation 8.2167mW

Core Area 1 sq.mm

Clock Frequency 125KHz

Gate Density 9K

12

Chapter 3

Results

The functionality of the 32 tap fir filter is verified using XILINX ISE Simu-

lator.The design is tested for different data vectors namely

• Delta input

• Step input

• Rectangular pulse

width equal to 2 clock cycles with filter coefficients.

Figure 3.1: Output of FIR filter for rectangular pulse of width= 2 clk cycle

This testing is done in two phases namely

• Boundary Scan

13

• Single stuck at faults and Scan chain in shift registers mode

Figure 3.2 shows result for boundary scanning. In this mode of testing,

whatever data fed at the input reflects at the output. In second phase of

testing, design is tested for single stuck at fault. Figure 3.3 shows result of

B-S-A-0.

OPSYS and netlist has been extracted. This netlist is imported to CA-

DENCE SOC ENCOUNTER for Backend design.

As the entire design is done in modular form, first banckend design of

cont logic and fir logic is done. Layout of cont logic is as shown in figure 3.4

while layout of fir logic is shown in the 3.5.

14

Figure 3.4: Layout of Control Logic

In the design of top module along with technology lef file, lef for these

two base modules are also imported.After importing lef files carefully place-

ment of the two blocks is done for optimum utilization of area. Layout top

module obtained is shown in the figure 3.6

result is compared by plotting Fast fourier transform (FFT) of ideal and

actual characteristics as shown in Figure 3.7

15

Figure 3.6: Layout of Top module of FIR filter

Figure 3.7: Comparison of ideal and practical FIR filter’s frequency domain

behavioral

16

Conclusion

The concept of even symmetric pulse shaping FIR filter was substantiated

through the project. It is an attempt to optimize the design for area by

minimizing the number of multipliers. On-chip testability is adjoined for

good fault coverage while keeping area and delay overhead optimum. The

precision of the filter is retained to an acceptable level.

17

Appendix

The filter coefficients after truncating the decimal part of the coefficients

obtained from MATLAB are

1 -1

2 1

3 0

4 -2

5 -1

6 3

7 1

8 -5

9 -6

10 3

11 12

12 2

13 -22

14 -22

15 28

16 100

The above 16 coefficients are symmetric w.r.t the zeroth sampling in-

stance.

18

Bibliography

tion Of Channel Filter For 3G Wireless TDD System”

Memory and Mixed-Signal VLSI Circuits” Boston, 2000.

19

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