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2.

4 CMOS Fabrication Steps 27

‡ 6WDUWZLWKDEODQNZDIHUFRPPRQO\NQRZQDVDVXEVWUDWHZKLFKLVOLJKWO\GRSHG

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‡ &RYHUWKHZDIHUZLWKDSURWHFWLYHOD\HURI6L22 (oxide) using the oxidation pro-
cess at 900–1200 °C with H2O (wet oxidation) or O2 (dry oxidation) in the oxida-
tion furnace.

6L2

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exposed to light.
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6L2

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‡ ([SRVHSKRWRUHVLVWWKURXJKWKHQZHOOPDVNDQGVWULSRIIWKHH[SRVHGSKRWRUHVLVW
using organic solvents. The n-well mask used to define the n-well in this step is
shown below.

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6L2

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‡ (WFKR[LGHZLWK+)ZKLFKRQO\DWWDFNVR[LGHZKHUHWKHUHVLVWKDVEHHQH[SRVHG
3KRWRUHVLVW
6L2

SVXEVWUDWH

and n–transistors requires MASK 2. The diffusion process occurs in all directions and dipper the diffusion more it spreads laterally. which is also known as active mask because it defines the thin oxide regions where gates are formed.28 2 MOS Fabrication Technology ‡ 5HPRYHWKHSKRWRUHVLVWZKLFKH[SRVHVWKHZDIHU 6L2 SVXEVWUDWH ‡ .PSODQWRUGLIIXVHn dopants into the exposed wafer using diffusion or ion im- plantation. 3RO\VLOLFRQ 7KLQJDWHR[LGH QZHOO SVXEVWUDWH 3RO\VLOLFRQ 3RO\VLOLFRQ 7KLQJDWHR[LGH QZHOO SVXEVWUDWH . QZHOO SVXEVWUDWH Step 2 The formation of thin oxide regions for the formation of p. 6L2 QZHOO ‡ 6WULSRII6L22 leaving behind the p-substrate along with the n-well. The ion implantation process allows shallower wells suitable for the fabrication of devices of smaller dimensions. This affects how closely two separate structures can be fabricated.