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Department of Electrical and Computer Engineering

**EECE 311 Electronic Circuits
**

Spring 2016

DESIGN PROJECT

**This project is to be done in groups of three students.
**

One project report should be submitted per group.

(version 2016031901)

Design Specifications

**You are to design an integrated circuit CMOS operational amplifier that has a
**

differential input and single-ended output, and that meets the following specifications:

**Process CMOS 0.35 micron
**

Supply voltage (VDD) 3V

(+/– VDD/2 =

+/– 1.5V)

Differential gain (Ad) ≥ 85 dB

Common-Mode Rejection Ratio (CMRR) ≥ 100 dB

Load resistor (RL) 1000 Ω

Offset Voltage < 0.25 mV

VOV for all MOSFETs ≥ 0.2 V

Input common-mode range (ICMR) ≥ 1.5 V

Peak-to-peak output voltage (Vo,p-p) ≥ 1.5 V

Supply power dissipation (PS) Minimize

Area (see Area Calculation below) Minimize

Ideal sources can only be used to generate the supply voltages. . you can apply a DC offset at the input to zero the output voltage. not bias currents. This differential DC offset at the input should not exceed 0.The design specifications should be met under a variation of the supply voltages of ±10% (10% higher or 10% lower than the nominal voltage). The input common-mode range is the range of common-mode DC input voltages vCM (applied to both vin+ and vin–) for which all MOSFETs are in saturation. There should be no offset voltage: Zero input voltages (at vin+ and vin–) should result in a zero output voltage. PMOS transistors.25 mV. and resistors. You should use a positive +VDD/2 supply and a negative –VDD/2 supply only. The available components are: NMOS transistors. However.

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4u to instantiate an NMOS and a PMOS transistor. Note that the resistance is given by R = Rsheet × number of squares = Rsheet × (L/W). The reason for using a sub-circuit is to allow λ to decrease with increasing transistor length. respectively (you have to use the prefix x instead of m) with a width of 1 um and a length of 0. W and L should be multiples of 0.4u x2 d g s b pmos params: W=1u L=0.4 µm and the minimum gate width W is 0. . Since the transistor output resistance ro is proportional to 1/λ. For the transistors. use: x1 d g s b nmos params: W=1u L=0. the output resistance increases with increasing L. where Rsheet is the sheet resistance and is equal to 300 Ohms/square. the minimum gate length L is 0. Area Calculation Calculate the area by adding up the gate areas (W×L) of all the transistors and the area of the resistors. Device Models The device models are encapsulated in PSPICE sub-circuits. the minimum W and L are 1 µm.6 µm.01 µm.4 um. For the resistors.

the device parameters at minimum L are: 2 –1 k’n = 150 μA/V . For the PMOS transistors.4u/{l})/exp(1)} .025*exp(0. The body terminal (b) of the NMOS transistors should be connected to the –VDD/2 supply.4u m0 d g s b pmos_internal w={w} l={l} . and λn = 0.The sub-circuit definitions are as follows: .ends .4u/{l})/exp(1)} .035*exp(0.025 V . Vtn = 0.7 V.7 + lambda={0.4u m0 d g s b nmos_internal w={w} l={l} .subckt nmos d g s b params: w=1u l=0. and |λp|= 0.model nmos_internal + nmos level=1 kp=150u vto=0. • Thursday April 28. Vtp = –0.8 + lambda={0. ICMR. CMRR.035 V . the device parameters at minimum L are: 2 –1 k’p = 80 μA/V . Ad.model pmos_internal + pmos level=1 kp=80u vto=-0. and offset) 20 points for how well the area is minimized 20 points for how well power is minimized 10 points for originality and creativity of the design Due Dates • Wednesday/Thursday March 23/24. . Grading 100 points total: 10 points for conciseness and clarity of the report 40 points for meeting the specifications (VOV.subckt pmos d g s b params: w=1u l=0. The body terminal (b) of the PMOS transistors should be connected to the +VDD/2 supply. 2016: Final report with results and SPICE files submitted electronically on Moodle by 11:55 pm. 2016: Group form signed and submitted in hard copy in class.8 V.ends For the NMOS transistors.

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